1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //---------------------------------------------------------------------------
36 // Data types used to define information about a single machine instruction
37 //---------------------------------------------------------------------------
39 typedef short MachineOpCode;
40 typedef unsigned InstrSchedClass;
42 //---------------------------------------------------------------------------
43 // struct TargetInstrDescriptor:
44 // Predefined information about each machine instruction.
45 // Designed to initialized statically.
48 const unsigned M_BRANCH_FLAG = 1 << 0;
49 const unsigned M_CALL_FLAG = 1 << 1;
50 const unsigned M_RET_FLAG = 1 << 2;
51 const unsigned M_BARRIER_FLAG = 1 << 3;
52 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
54 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
55 /// from memory. This should only be set on instructions that load a value from
56 /// memory and return it in their only virtual register definition.
57 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
59 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
60 /// modify memory. Instructions with this flag set are not necessarily simple
61 /// store instructions, they may store a modified value based on their operands,
62 /// or may not actually modify anything, for example.
63 const unsigned M_MAY_STORE_FLAG = 1 << 6;
65 const unsigned M_INDIRECT_FLAG = 1 << 7;
66 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
68 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
69 // changed into a 3-address instruction if the first two operands cannot be
70 // assigned to the same register. The target must implement the
71 // TargetInstrInfo::convertToThreeAddress method for this instruction.
72 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
74 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
75 // Z), which produces the same result if Y and Z are exchanged.
76 const unsigned M_COMMUTABLE = 1 << 10;
78 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
79 // block? Typically this is things like return and branch instructions.
80 // Various passes use this to insert code into the bottom of a basic block, but
81 // before control flow occurs.
82 const unsigned M_TERMINATOR_FLAG = 1 << 11;
84 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
85 // insertion support when the DAG scheduler is inserting it into a machine basic
87 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
89 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
90 // operands in addition to the minimum number operands specified.
91 const unsigned M_VARIABLE_OPS = 1 << 13;
93 // M_PREDICABLE - Set if this instruction has a predicate operand that
94 // controls execution. It may be set to 'always'.
95 const unsigned M_PREDICABLE = 1 << 14;
97 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
98 // at any time, e.g. constant generation, load from constant pool.
99 const unsigned M_REMATERIALIZIBLE = 1 << 15;
101 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
102 // (e.g. instructions with unique labels attached).
103 const unsigned M_NOT_DUPLICABLE = 1 << 16;
105 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
106 // ARM instructions which can set condition code if 's' bit is set.
107 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
109 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
110 // are not captured by any operands of the instruction or other flags, and when
111 // *all* instances of the instruction of that opcode have no side effects.
113 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
114 // both! If neither flag is set, then the instruction *always* has side effects.
115 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
117 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
118 // side effects. The virtual method "isReallySideEffectFree" is called to
119 // determine this. Load instructions are an example of where this is useful. In
120 // general, loads always have side effects. However, loads from constant pools
121 // don't. We let the specific back end make this determination.
123 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
124 // both! If neither flag is set, then the instruction *always* has side effects.
125 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
127 // Machine operand flags
128 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
129 // requires a callback to look up its register class.
130 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
132 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
133 /// predicate operand that controls an M_PREDICATED instruction.
134 const unsigned M_PREDICATE_OPERAND = 1 << 1;
136 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
138 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
141 // Operand constraints: only "tied_to" for now.
142 enum OperandConstraint {
143 TIED_TO = 0 // Must be allocated the same register as.
147 /// TargetOperandInfo - This holds information about one operand of a machine
148 /// instruction, indicating the register class for register operands, etc.
150 class TargetOperandInfo {
152 /// RegClass - This specifies the register class enumeration of the operand
153 /// if the operand is a register. If not, this contains 0.
154 unsigned short RegClass;
155 unsigned short Flags;
156 /// Lower 16 bits are used to specify which constraints are set. The higher 16
157 /// bits are used to specify the value of constraints (4 bits each).
158 unsigned int Constraints;
159 /// Currently no other information.
163 class TargetInstrDescriptor {
165 MachineOpCode Opcode; // The opcode.
166 unsigned short numOperands; // Num of args (may be more if variable_ops).
167 unsigned short numDefs; // Num of args that are definitions.
168 const char * Name; // Assembly language mnemonic for the opcode.
169 InstrSchedClass schedClass; // enum identifying instr sched class
170 unsigned Flags; // flags identifying machine instr class
171 unsigned TSFlags; // Target Specific Flag values
172 const unsigned *ImplicitUses; // Registers implicitly read by this instr
173 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
174 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
176 /// getOperandConstraint - Returns the value of the specific constraint if
177 /// it is set. Returns -1 if it is not set.
178 int getOperandConstraint(unsigned OpNum,
179 TOI::OperandConstraint Constraint) const {
180 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
181 "Invalid operand # of TargetInstrInfo");
182 if (OpNum < numOperands &&
183 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
184 unsigned Pos = 16 + Constraint * 4;
185 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
190 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
191 /// dest operand. Returns -1 if there isn't one.
192 int findTiedToSrcOperand(unsigned OpNum) const;
195 /// isSimpleLoad - Return true for instructions that are simple loads from
196 /// memory. This should only be set on instructions that load a value from
197 /// memory and return it in their only virtual register definition.
198 /// Instructions that return a value loaded from memory and then modified in
199 /// some way should not return true for this.
200 bool isSimpleLoad() const {
201 return Flags & M_SIMPLE_LOAD_FLAG;
207 //---------------------------------------------------------------------------
209 /// TargetInstrInfo - Interface to description of machine instructions
211 class TargetInstrInfo {
212 const TargetInstrDescriptor* desc; // raw array to allow static init'n
213 unsigned NumOpcodes; // number of entries in the desc array
214 unsigned numRealOpCodes; // number of non-dummy op codes
216 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
217 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
219 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
220 virtual ~TargetInstrInfo();
222 // Invariant opcodes: All instruction sets have these as their low opcodes.
231 unsigned getNumOpcodes() const { return NumOpcodes; }
233 /// get - Return the machine instruction descriptor that corresponds to the
234 /// specified instruction opcode.
236 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
237 assert((unsigned)Opcode < NumOpcodes);
241 const char *getName(MachineOpCode Opcode) const {
242 return get(Opcode).Name;
245 int getNumOperands(MachineOpCode Opcode) const {
246 return get(Opcode).numOperands;
249 int getNumDefs(MachineOpCode Opcode) const {
250 return get(Opcode).numDefs;
253 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
254 return get(Opcode).schedClass;
257 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
258 return get(Opcode).ImplicitUses;
261 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
262 return get(Opcode).ImplicitDefs;
267 // Query instruction class flags according to the machine-independent
268 // flags listed above.
270 bool isReturn(MachineOpCode Opcode) const {
271 return get(Opcode).Flags & M_RET_FLAG;
274 bool isCommutableInstr(MachineOpCode Opcode) const {
275 return get(Opcode).Flags & M_COMMUTABLE;
277 bool isTerminatorInstr(MachineOpCode Opcode) const {
278 return get(Opcode).Flags & M_TERMINATOR_FLAG;
281 bool isBranch(MachineOpCode Opcode) const {
282 return get(Opcode).Flags & M_BRANCH_FLAG;
285 bool isIndirectBranch(MachineOpCode Opcode) const {
286 return get(Opcode).Flags & M_INDIRECT_FLAG;
289 /// isBarrier - Returns true if the specified instruction stops control flow
290 /// from executing the instruction immediately following it. Examples include
291 /// unconditional branches and return instructions.
292 bool isBarrier(MachineOpCode Opcode) const {
293 return get(Opcode).Flags & M_BARRIER_FLAG;
296 bool isCall(MachineOpCode Opcode) const {
297 return get(Opcode).Flags & M_CALL_FLAG;
300 /// mayStore - Return true if this instruction could possibly modify memory.
301 /// Instructions with this flag set are not necessarily simple store
302 /// instructions, they may store a modified value based on their operands, or
303 /// may not actually modify anything, for example.
304 bool mayStore(MachineOpCode Opcode) const {
305 return get(Opcode).Flags & M_MAY_STORE_FLAG;
308 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
309 /// which must be filled by the code generator.
310 bool hasDelaySlot(MachineOpCode Opcode) const {
311 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
314 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
315 /// custom insertion support when the DAG scheduler is inserting it into a
316 /// machine basic block.
317 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
318 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
321 bool hasVariableOperands(MachineOpCode Opcode) const {
322 return get(Opcode).Flags & M_VARIABLE_OPS;
325 bool isPredicable(MachineOpCode Opcode) const {
326 return get(Opcode).Flags & M_PREDICABLE;
329 bool isNotDuplicable(MachineOpCode Opcode) const {
330 return get(Opcode).Flags & M_NOT_DUPLICABLE;
333 bool hasOptionalDef(MachineOpCode Opcode) const {
334 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
337 /// isTriviallyReMaterializable - Return true if the instruction is trivially
338 /// rematerializable, meaning it has no side effects and requires no operands
339 /// that aren't always available.
340 bool isTriviallyReMaterializable(MachineInstr *MI) const {
341 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
342 isReallyTriviallyReMaterializable(MI);
345 /// hasUnmodelledSideEffects - Returns true if the instruction has side
346 /// effects that are not captured by any operands of the instruction or other
348 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
349 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
350 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
351 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
352 return !isReallySideEffectFree(MI); // May have side effects
355 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
356 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
357 /// instruction itself is actually trivially rematerializable, considering
358 /// its operands. This is used for targets that have instructions that are
359 /// only trivially rematerializable for specific uses. This predicate must
360 /// return false if the instruction has any side effects other than
361 /// producing a value, or if it requres any address registers that are not
362 /// always available.
363 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
367 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
368 /// method is called to determine if the specific instance of this
369 /// instruction has side effects. This is useful in cases of instructions,
370 /// like loads, which generally always have side effects. A load from a
371 /// constant pool doesn't have side effects, though. So we need to
372 /// differentiate it from the general case.
373 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
377 /// getOperandConstraint - Returns the value of the specific constraint if
378 /// it is set. Returns -1 if it is not set.
379 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
380 TOI::OperandConstraint Constraint) const {
381 return get(Opcode).getOperandConstraint(OpNum, Constraint);
384 /// Return true if the instruction is a register to register move
385 /// and leave the source and dest operands in the passed parameters.
386 virtual bool isMoveInstr(const MachineInstr& MI,
388 unsigned& destReg) const {
392 /// isLoadFromStackSlot - If the specified machine instruction is a direct
393 /// load from a stack slot, return the virtual or physical register number of
394 /// the destination along with the FrameIndex of the loaded stack slot. If
395 /// not, return 0. This predicate must return 0 if the instruction has
396 /// any side effects other than loading from the stack slot.
397 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
401 /// isStoreToStackSlot - If the specified machine instruction is a direct
402 /// store to a stack slot, return the virtual or physical register number of
403 /// the source reg along with the FrameIndex of the loaded stack slot. If
404 /// not, return 0. This predicate must return 0 if the instruction has
405 /// any side effects other than storing to the stack slot.
406 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
410 /// convertToThreeAddress - This method must be implemented by targets that
411 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
412 /// may be able to convert a two-address instruction into one or more true
413 /// three-address instructions on demand. This allows the X86 target (for
414 /// example) to convert ADD and SHL instructions into LEA instructions if they
415 /// would require register copies due to two-addressness.
417 /// This method returns a null pointer if the transformation cannot be
418 /// performed, otherwise it returns the last new instruction.
420 virtual MachineInstr *
421 convertToThreeAddress(MachineFunction::iterator &MFI,
422 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
426 /// commuteInstruction - If a target has any instructions that are commutable,
427 /// but require converting to a different instruction or making non-trivial
428 /// changes to commute them, this method can overloaded to do this. The
429 /// default implementation of this method simply swaps the first two operands
430 /// of MI and returns it.
432 /// If a target wants to make more aggressive changes, they can construct and
433 /// return a new machine instruction. If an instruction cannot commute, it
434 /// can also return null.
436 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
438 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
439 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
440 /// implemented for a target). Upon success, this returns false and returns
441 /// with the following information in various cases:
443 /// 1. If this block ends with no branches (it just falls through to its succ)
444 /// just return false, leaving TBB/FBB null.
445 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
446 /// the destination block.
447 /// 3. If this block ends with an conditional branch and it falls through to
448 /// an successor block, it sets TBB to be the branch destination block and a
449 /// list of operands that evaluate the condition. These
450 /// operands can be passed to other TargetInstrInfo methods to create new
452 /// 4. If this block ends with an conditional branch and an unconditional
453 /// block, it returns the 'true' destination in TBB, the 'false' destination
454 /// in FBB, and a list of operands that evaluate the condition. These
455 /// operands can be passed to other TargetInstrInfo methods to create new
458 /// Note that RemoveBranch and InsertBranch must be implemented to support
459 /// cases where this method returns success.
461 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
462 MachineBasicBlock *&FBB,
463 std::vector<MachineOperand> &Cond) const {
467 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
468 /// this is only invoked in cases where AnalyzeBranch returns success. It
469 /// returns the number of instructions that were removed.
470 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
471 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
475 /// InsertBranch - Insert a branch into the end of the specified
476 /// MachineBasicBlock. This operands to this method are the same as those
477 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
478 /// returns success and when an unconditional branch (TBB is non-null, FBB is
479 /// null, Cond is empty) needs to be inserted. It returns the number of
480 /// instructions inserted.
481 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
482 MachineBasicBlock *FBB,
483 const std::vector<MachineOperand> &Cond) const {
484 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
488 /// copyRegToReg - Add a copy between a pair of registers
489 virtual void copyRegToReg(MachineBasicBlock &MBB,
490 MachineBasicBlock::iterator MI,
491 unsigned DestReg, unsigned SrcReg,
492 const TargetRegisterClass *DestRC,
493 const TargetRegisterClass *SrcRC) const {
494 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
497 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator MI,
499 unsigned SrcReg, bool isKill, int FrameIndex,
500 const TargetRegisterClass *RC) const {
501 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
504 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
505 SmallVectorImpl<MachineOperand> &Addr,
506 const TargetRegisterClass *RC,
507 SmallVectorImpl<MachineInstr*> &NewMIs) const {
508 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
511 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator MI,
513 unsigned DestReg, int FrameIndex,
514 const TargetRegisterClass *RC) const {
515 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
518 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
519 SmallVectorImpl<MachineOperand> &Addr,
520 const TargetRegisterClass *RC,
521 SmallVectorImpl<MachineInstr*> &NewMIs) const {
522 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
525 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
526 /// saved registers and returns true if it isn't possible / profitable to do
527 /// so by issuing a series of store instructions via
528 /// storeRegToStackSlot(). Returns false otherwise.
529 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
530 MachineBasicBlock::iterator MI,
531 const std::vector<CalleeSavedInfo> &CSI) const {
535 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
536 /// saved registers and returns true if it isn't possible / profitable to do
537 /// so by issuing a series of load instructions via loadRegToStackSlot().
538 /// Returns false otherwise.
539 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI,
541 const std::vector<CalleeSavedInfo> &CSI) const {
545 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
546 /// slot into the specified machine instruction for the specified operand(s).
547 /// If this is possible, a new instruction is returned with the specified
548 /// operand folded, otherwise NULL is returned. The client is responsible for
549 /// removing the old instruction and adding the new one in the instruction
551 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
552 SmallVectorImpl<unsigned> &Ops,
553 int FrameIndex) const {
557 /// foldMemoryOperand - Same as the previous version except it allows folding
558 /// of any load and store from / to any address, not just from a specific
560 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
561 SmallVectorImpl<unsigned> &Ops,
562 MachineInstr* LoadMI) const {
566 /// canFoldMemoryOperand - Returns true if the specified load / store is
567 /// folding is possible.
569 bool canFoldMemoryOperand(MachineInstr *MI,
570 SmallVectorImpl<unsigned> &Ops) const{
574 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
575 /// a store or a load and a store into two or more instruction. If this is
576 /// possible, returns true as well as the new instructions by reference.
577 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
578 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
579 SmallVectorImpl<MachineInstr*> &NewMIs) const{
583 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
584 SmallVectorImpl<SDNode*> &NewNodes) const {
588 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
589 /// instruction after load / store are unfolded from an instruction of the
590 /// specified opcode. It returns zero if the specified unfolding is not
592 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
593 bool UnfoldLoad, bool UnfoldStore) const {
597 /// BlockHasNoFallThrough - Return true if the specified block does not
598 /// fall-through into its successor block. This is primarily used when a
599 /// branch is unanalyzable. It is useful for things like unconditional
600 /// indirect branches (jump tables).
601 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
605 /// ReverseBranchCondition - Reverses the branch condition of the specified
606 /// condition list, returning false on success and true if it cannot be
608 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
612 /// insertNoop - Insert a noop into the instruction stream at the specified
614 virtual void insertNoop(MachineBasicBlock &MBB,
615 MachineBasicBlock::iterator MI) const {
616 assert(0 && "Target didn't implement insertNoop!");
620 /// isPredicated - Returns true if the instruction is already predicated.
622 virtual bool isPredicated(const MachineInstr *MI) const {
626 /// isUnpredicatedTerminator - Returns true if the instruction is a
627 /// terminator instruction that has not been predicated.
628 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
630 /// PredicateInstruction - Convert the instruction into a predicated
631 /// instruction. It returns true if the operation was successful.
633 bool PredicateInstruction(MachineInstr *MI,
634 const std::vector<MachineOperand> &Pred) const = 0;
636 /// SubsumesPredicate - Returns true if the first specified predicate
637 /// subsumes the second, e.g. GE subsumes GT.
639 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
640 const std::vector<MachineOperand> &Pred2) const {
644 /// DefinesPredicate - If the specified instruction defines any predicate
645 /// or condition code register(s) used for predication, returns true as well
646 /// as the definition predicate(s) by reference.
647 virtual bool DefinesPredicate(MachineInstr *MI,
648 std::vector<MachineOperand> &Pred) const {
652 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
654 virtual const TargetRegisterClass *getPointerRegClass() const {
655 assert(0 && "Target didn't implement getPointerRegClass!");
657 return 0; // Must return a value in order to compile with VS 2005
661 /// TargetInstrInfoImpl - This is the default implementation of
662 /// TargetInstrInfo, which just provides a couple of default implementations
663 /// for various methods. This separated out because it is implemented in
664 /// libcodegen, not in libtarget.
665 class TargetInstrInfoImpl : public TargetInstrInfo {
667 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
668 : TargetInstrInfo(desc, NumOpcodes) {}
670 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
671 virtual bool PredicateInstruction(MachineInstr *MI,
672 const std::vector<MachineOperand> &Pred) const;
676 } // End llvm namespace