1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/DataTypes.h"
13 class MachineInstrDescriptor;
20 class MachineCodeForInstruction;
22 //---------------------------------------------------------------------------
23 // Data types used to define information about a single machine instruction
24 //---------------------------------------------------------------------------
26 typedef int MachineOpCode;
27 typedef unsigned InstrSchedClass;
29 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
32 // Global variable holding an array of descriptors for machine instructions.
33 // The actual object needs to be created separately for each target machine.
34 // This variable is initialized and reset by class MachineInstrInfo.
36 // FIXME: This should be a property of the target so that more than one target
37 // at a time can be active...
39 extern const MachineInstrDescriptor *TargetInstrDescriptors;
42 //---------------------------------------------------------------------------
43 // struct MachineInstrDescriptor:
44 // Predefined information about each machine instruction.
45 // Designed to initialized statically.
47 // class MachineInstructionInfo
48 // Interface to description of machine instructions
50 //---------------------------------------------------------------------------
52 const unsigned M_NOP_FLAG = 1 << 0;
53 const unsigned M_BRANCH_FLAG = 1 << 1;
54 const unsigned M_CALL_FLAG = 1 << 2;
55 const unsigned M_RET_FLAG = 1 << 3;
56 const unsigned M_ARITH_FLAG = 1 << 4;
57 const unsigned M_CC_FLAG = 1 << 6;
58 const unsigned M_LOGICAL_FLAG = 1 << 6;
59 const unsigned M_INT_FLAG = 1 << 7;
60 const unsigned M_FLOAT_FLAG = 1 << 8;
61 const unsigned M_CONDL_FLAG = 1 << 9;
62 const unsigned M_LOAD_FLAG = 1 << 10;
63 const unsigned M_PREFETCH_FLAG = 1 << 11;
64 const unsigned M_STORE_FLAG = 1 << 12;
65 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
66 const unsigned M_PSEUDO_FLAG = 1 << 14;
69 struct MachineInstrDescriptor {
70 const char * Name; // Assembly language mnemonic for the opcode.
71 int numOperands; // Number of args; -1 if variable #args
72 int resultPos; // Position of the result; -1 if no result
73 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
74 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
75 // smallest -ve value is -(maxImmedConst+1).
76 unsigned numDelaySlots; // Number of delay slots after instruction
77 unsigned latency; // Latency in machine cycles
78 InstrSchedClass schedClass; // enum identifying instr sched class
79 unsigned iclass; // flags identifying machine instr class
83 class MachineInstrInfo {
84 const MachineInstrDescriptor* desc; // raw array to allow static init'n
85 unsigned descSize; // number of entries in the desc array
86 unsigned numRealOpCodes; // number of non-dummy op codes
88 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
89 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
91 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
92 unsigned numRealOpCodes);
93 virtual ~MachineInstrInfo();
95 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
96 unsigned getNumTotalOpCodes() const { return descSize; }
98 /// get - Return the machine instruction descriptor that corresponds to the
99 /// specified instruction opcode.
101 const MachineInstrDescriptor& get(MachineOpCode opCode) const {
102 assert(opCode >= 0 && opCode < (int)descSize);
106 const char *getName(MachineOpCode opCode) const {
107 return get(opCode).Name;
110 int getNumOperands(MachineOpCode opCode) const {
111 return get(opCode).numOperands;
114 int getResultPos(MachineOpCode opCode) const {
115 return get(opCode).resultPos;
118 unsigned getNumDelaySlots(MachineOpCode opCode) const {
119 return get(opCode).numDelaySlots;
122 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
123 return get(opCode).schedClass;
127 // Query instruction class flags according to the machine-independent
128 // flags listed above.
130 unsigned getIClass(MachineOpCode opCode) const {
131 return get(opCode).iclass;
133 bool isNop(MachineOpCode opCode) const {
134 return get(opCode).iclass & M_NOP_FLAG;
136 bool isBranch(MachineOpCode opCode) const {
137 return get(opCode).iclass & M_BRANCH_FLAG;
139 bool isCall(MachineOpCode opCode) const {
140 return get(opCode).iclass & M_CALL_FLAG;
142 bool isReturn(MachineOpCode opCode) const {
143 return get(opCode).iclass & M_RET_FLAG;
145 bool isControlFlow(MachineOpCode opCode) const {
146 return get(opCode).iclass & M_BRANCH_FLAG
147 || get(opCode).iclass & M_CALL_FLAG
148 || get(opCode).iclass & M_RET_FLAG;
150 bool isArith(MachineOpCode opCode) const {
151 return get(opCode).iclass & M_ARITH_FLAG;
153 bool isCCInstr(MachineOpCode opCode) const {
154 return get(opCode).iclass & M_CC_FLAG;
156 bool isLogical(MachineOpCode opCode) const {
157 return get(opCode).iclass & M_LOGICAL_FLAG;
159 bool isIntInstr(MachineOpCode opCode) const {
160 return get(opCode).iclass & M_INT_FLAG;
162 bool isFloatInstr(MachineOpCode opCode) const {
163 return get(opCode).iclass & M_FLOAT_FLAG;
165 bool isConditional(MachineOpCode opCode) const {
166 return get(opCode).iclass & M_CONDL_FLAG;
168 bool isLoad(MachineOpCode opCode) const {
169 return get(opCode).iclass & M_LOAD_FLAG;
171 bool isPrefetch(MachineOpCode opCode) const {
172 return get(opCode).iclass & M_PREFETCH_FLAG;
174 bool isLoadOrPrefetch(MachineOpCode opCode) const {
175 return get(opCode).iclass & M_LOAD_FLAG
176 || get(opCode).iclass & M_PREFETCH_FLAG;
178 bool isStore(MachineOpCode opCode) const {
179 return get(opCode).iclass & M_STORE_FLAG;
181 bool isMemoryAccess(MachineOpCode opCode) const {
182 return get(opCode).iclass & M_LOAD_FLAG
183 || get(opCode).iclass & M_PREFETCH_FLAG
184 || get(opCode).iclass & M_STORE_FLAG;
186 bool isDummyPhiInstr(const MachineOpCode opCode) const {
187 return get(opCode).iclass & M_DUMMY_PHI_FLAG;
189 bool isPseudoInstr(const MachineOpCode opCode) const {
190 return get(opCode).iclass & M_PSEUDO_FLAG;
193 // Check if an instruction can be issued before its operands are ready,
194 // or if a subsequent instruction that uses its result can be issued
195 // before the results are ready.
196 // Default to true since most instructions on many architectures allow this.
198 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
202 virtual bool hasResultInterlock(MachineOpCode opCode) const {
207 // Latencies for individual instructions and instruction pairs
209 virtual int minLatency(MachineOpCode opCode) const {
210 return get(opCode).latency;
213 virtual int maxLatency(MachineOpCode opCode) const {
214 return get(opCode).latency;
218 // Which operand holds an immediate constant? Returns -1 if none
220 virtual int getImmedConstantPos(MachineOpCode opCode) const {
221 return -1; // immediate position is machine specific, so say -1 == "none"
224 // Check if the specified constant fits in the immediate field
225 // of this machine instruction
227 virtual bool constantFitsInImmedField(MachineOpCode opCode,
228 int64_t intValue) const;
230 // Return the largest +ve constant that can be held in the IMMMED field
231 // of this machine instruction.
232 // isSignExtended is set to true if the value is sign-extended before use
233 // (this is true for all immediate fields in SPARC instructions).
234 // Return 0 if the instruction has no IMMED field.
236 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
237 bool &isSignExtended) const {
238 isSignExtended = get(opCode).immedIsSignExtended;
239 return get(opCode).maxImmedConst;
242 //-------------------------------------------------------------------------
243 // Queries about representation of LLVM quantities (e.g., constants)
244 //-------------------------------------------------------------------------
246 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
247 /// from memory into a register, i.e., cannot be set bitwise in register and
248 /// cannot use immediate fields of instructions. Note that this only makes
249 /// sense for primitive types.
251 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
253 // Test if this constant may not fit in the immediate field of the
254 // machine instructions (probably) generated for this instruction.
256 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
257 const Instruction* I) const {
258 return true; // safe but very conservative
261 //-------------------------------------------------------------------------
262 // Code generation support for creating individual machine instructions
263 //-------------------------------------------------------------------------
265 // Get certain common op codes for the current target. this and all the
266 // Create* methods below should be moved to a machine code generation class
268 virtual MachineOpCode getNOPOpCode() const = 0;
270 // Create an instruction sequence to put the constant `val' into
271 // the virtual register `dest'. `val' may be a Constant or a
272 // GlobalValue, viz., the constant address of a global variable or function.
273 // The generated instructions are returned in `mvec'.
274 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
275 // Symbolic constants or constants that must be accessed from memory
276 // are added to the constant pool via MachineFunction::get(F).
278 virtual void CreateCodeToLoadConst(const TargetMachine& target,
282 std::vector<MachineInstr*>& mvec,
283 MachineCodeForInstruction& mcfi) const=0;
285 // Create an instruction sequence to copy an integer value `val'
286 // to a floating point value `dest' by copying to memory and back.
287 // val must be an integral type. dest must be a Float or Double.
288 // The generated instructions are returned in `mvec'.
289 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
290 // Any stack space required is allocated via mcff.
292 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
296 std::vector<MachineInstr*>& mvec,
297 MachineCodeForInstruction& mcfi)const=0;
299 // Similarly, create an instruction sequence to copy an FP value
300 // `val' to an integer value `dest' by copying to memory and back.
301 // The generated instructions are returned in `mvec'.
302 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
303 // Any stack space required is allocated via mcff.
305 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
309 std::vector<MachineInstr*>& mvec,
310 MachineCodeForInstruction& mcfi)const=0;
312 // Create instruction(s) to copy src to dest, for arbitrary types
313 // The generated instructions are returned in `mvec'.
314 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
315 // Any stack space required is allocated via mcff.
317 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
321 std::vector<MachineInstr*>& mvec,
322 MachineCodeForInstruction& mcfi)const=0;
324 // Create instruction sequence to produce a sign-extended register value
325 // from an arbitrary sized value (sized in bits, not bytes).
326 // The generated instructions are appended to `mvec'.
327 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
328 // Any stack space required is allocated via mcff.
330 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
335 std::vector<MachineInstr*>& mvec,
336 MachineCodeForInstruction& mcfi) const=0;
338 // Create instruction sequence to produce a zero-extended register value
339 // from an arbitrary sized value (sized in bits, not bytes).
340 // The generated instructions are appended to `mvec'.
341 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
342 // Any stack space required is allocated via mcff.
344 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
348 unsigned srcSizeInBits,
349 std::vector<MachineInstr*>& mvec,
350 MachineCodeForInstruction& mcfi) const=0;