1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
25 class MachineMemOperand;
30 class TargetRegisterClass;
31 class TargetRegisterInfo;
33 template<class T> class SmallVectorImpl;
36 //---------------------------------------------------------------------------
38 /// TargetInstrInfo - Interface to description of machine instruction set
40 class TargetInstrInfo {
41 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
42 unsigned NumOpcodes; // Number of entries in the desc array
44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
48 virtual ~TargetInstrInfo();
50 unsigned getNumOpcodes() const { return NumOpcodes; }
52 /// get - Return the machine instruction descriptor that corresponds to the
53 /// specified instruction opcode.
55 const TargetInstrDesc &get(unsigned Opcode) const {
56 assert(Opcode < NumOpcodes && "Invalid opcode!");
57 return Descriptors[Opcode];
60 /// isTriviallyReMaterializable - Return true if the instruction is trivially
61 /// rematerializable, meaning it has no side effects and requires no operands
62 /// that aren't always available.
63 bool isTriviallyReMaterializable(const MachineInstr *MI,
64 AliasAnalysis *AA = 0) const {
65 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
66 (MI->getDesc().isRematerializable() &&
67 (isReallyTriviallyReMaterializable(MI, AA) ||
68 isReallyTriviallyReMaterializableGeneric(MI, AA)));
72 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
73 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
74 /// specify whether the instruction is actually trivially rematerializable,
75 /// taking into consideration its operands. This predicate must return false
76 /// if the instruction has any side effects other than producing a value, or
77 /// if it requres any address registers that are not always available.
78 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
79 AliasAnalysis *AA) const {
84 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
85 /// for which the M_REMATERIALIZABLE flag is set and the target hook
86 /// isReallyTriviallyReMaterializable returns false, this function does
87 /// target-independent tests to determine if the instruction is really
88 /// trivially rematerializable.
89 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
90 AliasAnalysis *AA) const;
93 /// isMoveInstr - Return true if the instruction is a register to register
94 /// move and return the source and dest operands and their sub-register
95 /// indices by reference.
96 virtual bool isMoveInstr(const MachineInstr& MI,
97 unsigned& SrcReg, unsigned& DstReg,
98 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
102 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
103 /// extension instruction. That is, it's like a copy where it's legal for the
104 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
105 /// true, then it's expected the pre-extension value is available as a subreg
106 /// of the result register. This also returns the sub-register index in
108 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
109 unsigned &SrcReg, unsigned &DstReg,
110 unsigned &SubIdx) const {
114 /// isIdentityCopy - Return true if the instruction is a copy (or
115 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
116 /// destination registers are the same.
117 bool isIdentityCopy(const MachineInstr &MI) const {
118 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
119 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
123 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
124 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
127 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
128 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
129 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
134 /// isLoadFromStackSlot - If the specified machine instruction is a direct
135 /// load from a stack slot, return the virtual or physical register number of
136 /// the destination along with the FrameIndex of the loaded stack slot. If
137 /// not, return 0. This predicate must return 0 if the instruction has
138 /// any side effects other than loading from the stack slot.
139 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
140 int &FrameIndex) const {
144 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
145 /// stack locations as well. This uses a heuristic so it isn't
146 /// reliable for correctness.
147 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
148 int &FrameIndex) const {
152 /// hasLoadFromStackSlot - If the specified machine instruction has
153 /// a load from a stack slot, return true along with the FrameIndex
154 /// of the loaded stack slot and the machine mem operand containing
155 /// the reference. If not, return false. Unlike
156 /// isLoadFromStackSlot, this returns true for any instructions that
157 /// loads from the stack. This is just a hint, as some cases may be
159 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
160 const MachineMemOperand *&MMO,
161 int &FrameIndex) const {
165 /// isStoreToStackSlot - If the specified machine instruction is a direct
166 /// store to a stack slot, return the virtual or physical register number of
167 /// the source reg along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than storing to the stack slot.
170 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const {
175 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
176 /// stack locations as well. This uses a heuristic so it isn't
177 /// reliable for correctness.
178 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
179 int &FrameIndex) const {
183 /// hasStoreToStackSlot - If the specified machine instruction has a
184 /// store to a stack slot, return true along with the FrameIndex of
185 /// the loaded stack slot and the machine mem operand containing the
186 /// reference. If not, return false. Unlike isStoreToStackSlot,
187 /// this returns true for any instructions that stores to the
188 /// stack. This is just a hint, as some cases may be missed.
189 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
190 const MachineMemOperand *&MMO,
191 int &FrameIndex) const {
195 /// reMaterialize - Re-issue the specified 'original' instruction at the
196 /// specific location targeting a new destination register.
197 /// The register in Orig->getOperand(0).getReg() will be substituted by
198 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
200 virtual void reMaterialize(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI,
202 unsigned DestReg, unsigned SubIdx,
203 const MachineInstr *Orig,
204 const TargetRegisterInfo &TRI) const = 0;
206 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
207 /// two-addrss instruction inserted by two-address pass.
208 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
210 const TargetRegisterInfo &TRI) const {
214 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
215 /// MachineFunction::CloneMachineInstr(), but the target may update operands
216 /// that are required to be unique.
218 /// The instruction must be duplicable as indicated by isNotDuplicable().
219 virtual MachineInstr *duplicate(MachineInstr *Orig,
220 MachineFunction &MF) const = 0;
222 /// convertToThreeAddress - This method must be implemented by targets that
223 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
224 /// may be able to convert a two-address instruction into one or more true
225 /// three-address instructions on demand. This allows the X86 target (for
226 /// example) to convert ADD and SHL instructions into LEA instructions if they
227 /// would require register copies due to two-addressness.
229 /// This method returns a null pointer if the transformation cannot be
230 /// performed, otherwise it returns the last new instruction.
232 virtual MachineInstr *
233 convertToThreeAddress(MachineFunction::iterator &MFI,
234 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
238 /// commuteInstruction - If a target has any instructions that are commutable,
239 /// but require converting to a different instruction or making non-trivial
240 /// changes to commute them, this method can overloaded to do this. The
241 /// default implementation of this method simply swaps the first two operands
242 /// of MI and returns it.
244 /// If a target wants to make more aggressive changes, they can construct and
245 /// return a new machine instruction. If an instruction cannot commute, it
246 /// can also return null.
248 /// If NewMI is true, then a new machine instruction must be created.
250 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
251 bool NewMI = false) const = 0;
253 /// findCommutedOpIndices - If specified MI is commutable, return the two
254 /// operand indices that would swap value. Return true if the instruction
255 /// is not in a form which this routine understands.
256 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
257 unsigned &SrcOpIdx2) const = 0;
259 /// produceSameValue - Return true if two machine instructions would produce
260 /// identical values. By default, this is only true when the two instructions
261 /// are deemed identical except for defs.
262 virtual bool produceSameValue(const MachineInstr *MI0,
263 const MachineInstr *MI1) const = 0;
265 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
266 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
267 /// implemented for a target). Upon success, this returns false and returns
268 /// with the following information in various cases:
270 /// 1. If this block ends with no branches (it just falls through to its succ)
271 /// just return false, leaving TBB/FBB null.
272 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
273 /// the destination block.
274 /// 3. If this block ends with a conditional branch and it falls through to a
275 /// successor block, it sets TBB to be the branch destination block and a
276 /// list of operands that evaluate the condition. These operands can be
277 /// passed to other TargetInstrInfo methods to create new branches.
278 /// 4. If this block ends with a conditional branch followed by an
279 /// unconditional branch, it returns the 'true' destination in TBB, the
280 /// 'false' destination in FBB, and a list of operands that evaluate the
281 /// condition. These operands can be passed to other TargetInstrInfo
282 /// methods to create new branches.
284 /// Note that RemoveBranch and InsertBranch must be implemented to support
285 /// cases where this method returns success.
287 /// If AllowModify is true, then this routine is allowed to modify the basic
288 /// block (e.g. delete instructions after the unconditional branch).
290 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
291 MachineBasicBlock *&FBB,
292 SmallVectorImpl<MachineOperand> &Cond,
293 bool AllowModify = false) const {
297 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
298 /// This is only invoked in cases where AnalyzeBranch returns success. It
299 /// returns the number of instructions that were removed.
300 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
301 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
305 /// InsertBranch - Insert branch code into the end of the specified
306 /// MachineBasicBlock. The operands to this method are the same as those
307 /// returned by AnalyzeBranch. This is only invoked in cases where
308 /// AnalyzeBranch returns success. It returns the number of instructions
311 /// It is also invoked by tail merging to add unconditional branches in
312 /// cases where AnalyzeBranch doesn't apply because there was no original
313 /// branch to analyze. At least this much must be implemented, else tail
314 /// merging needs to be disabled.
315 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
316 MachineBasicBlock *FBB,
317 const SmallVectorImpl<MachineOperand> &Cond) const {
318 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
322 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
323 /// returns false if the target does not how to copy between the specified
325 virtual bool copyRegToReg(MachineBasicBlock &MBB,
326 MachineBasicBlock::iterator MI,
327 unsigned DestReg, unsigned SrcReg,
328 const TargetRegisterClass *DestRC,
329 const TargetRegisterClass *SrcRC,
331 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
335 /// storeRegToStackSlot - Store the specified register of the given register
336 /// class to the specified stack frame index. The store instruction is to be
337 /// added to the given machine basic block before the specified machine
338 /// instruction. If isKill is true, the register operand is the last use and
339 /// must be marked kill.
340 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
341 MachineBasicBlock::iterator MI,
342 unsigned SrcReg, bool isKill, int FrameIndex,
343 const TargetRegisterClass *RC,
344 const TargetRegisterInfo *TRI) const {
345 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
348 /// loadRegFromStackSlot - Load the specified register of the given register
349 /// class from the specified stack frame index. The load instruction is to be
350 /// added to the given machine basic block before the specified machine
352 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
353 MachineBasicBlock::iterator MI,
354 unsigned DestReg, int FrameIndex,
355 const TargetRegisterClass *RC,
356 const TargetRegisterInfo *TRI) const {
357 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
360 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
361 /// saved registers and returns true if it isn't possible / profitable to do
362 /// so by issuing a series of store instructions via
363 /// storeRegToStackSlot(). Returns false otherwise.
364 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
365 MachineBasicBlock::iterator MI,
366 const std::vector<CalleeSavedInfo> &CSI,
367 const TargetRegisterInfo *TRI) const {
371 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
372 /// saved registers and returns true if it isn't possible / profitable to do
373 /// so by issuing a series of load instructions via loadRegToStackSlot().
374 /// Returns false otherwise.
375 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator MI,
377 const std::vector<CalleeSavedInfo> &CSI,
378 const TargetRegisterInfo *TRI) const {
382 /// emitFrameIndexDebugValue - Emit a target-dependent form of
383 /// DBG_VALUE encoding the address of a frame index. Addresses would
384 /// normally be lowered the same way as other addresses on the target,
385 /// e.g. in load instructions. For targets that do not support this
386 /// the debug info is simply lost.
387 /// If you add this for a target you should handle this DBG_VALUE in the
388 /// target-specific AsmPrinter code as well; you will probably get invalid
389 /// assembly output if you don't.
390 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
398 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
399 /// slot into the specified machine instruction for the specified operand(s).
400 /// If this is possible, a new instruction is returned with the specified
401 /// operand folded, otherwise NULL is returned. The client is responsible for
402 /// removing the old instruction and adding the new one in the instruction
404 MachineInstr* foldMemoryOperand(MachineFunction &MF,
406 const SmallVectorImpl<unsigned> &Ops,
407 int FrameIndex) const;
409 /// foldMemoryOperand - Same as the previous version except it allows folding
410 /// of any load and store from / to any address, not just from a specific
412 MachineInstr* foldMemoryOperand(MachineFunction &MF,
414 const SmallVectorImpl<unsigned> &Ops,
415 MachineInstr* LoadMI) const;
418 /// foldMemoryOperandImpl - Target-dependent implementation for
419 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
420 /// take care of adding a MachineMemOperand to the newly created instruction.
421 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
423 const SmallVectorImpl<unsigned> &Ops,
424 int FrameIndex) const {
428 /// foldMemoryOperandImpl - Target-dependent implementation for
429 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
430 /// take care of adding a MachineMemOperand to the newly created instruction.
431 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
433 const SmallVectorImpl<unsigned> &Ops,
434 MachineInstr* LoadMI) const {
439 /// canFoldMemoryOperand - Returns true for the specified load / store if
440 /// folding is possible.
442 bool canFoldMemoryOperand(const MachineInstr *MI,
443 const SmallVectorImpl<unsigned> &Ops) const {
447 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
448 /// a store or a load and a store into two or more instruction. If this is
449 /// possible, returns true as well as the new instructions by reference.
450 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
451 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
452 SmallVectorImpl<MachineInstr*> &NewMIs) const{
456 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
457 SmallVectorImpl<SDNode*> &NewNodes) const {
461 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
462 /// instruction after load / store are unfolded from an instruction of the
463 /// specified opcode. It returns zero if the specified unfolding is not
464 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
465 /// index of the operand which will hold the register holding the loaded
467 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
468 bool UnfoldLoad, bool UnfoldStore,
469 unsigned *LoadRegIndex = 0) const {
473 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
474 /// to determine if two loads are loading from the same base address. It
475 /// should only return true if the base pointers are the same and the
476 /// only differences between the two addresses are the offset. It also returns
477 /// the offsets by reference.
478 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
479 int64_t &Offset1, int64_t &Offset2) const {
483 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
484 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
485 /// be scheduled togther. On some targets if two loads are loading from
486 /// addresses in the same cache line, it's better if they are scheduled
487 /// together. This function takes two integers that represent the load offsets
488 /// from the common base address. It returns true if it decides it's desirable
489 /// to schedule the two loads together. "NumLoads" is the number of loads that
490 /// have already been scheduled after Load1.
491 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
492 int64_t Offset1, int64_t Offset2,
493 unsigned NumLoads) const {
497 /// ReverseBranchCondition - Reverses the branch condition of the specified
498 /// condition list, returning false on success and true if it cannot be
501 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
505 /// insertNoop - Insert a noop into the instruction stream at the specified
507 virtual void insertNoop(MachineBasicBlock &MBB,
508 MachineBasicBlock::iterator MI) const;
511 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
512 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
513 // Default to just using 'nop' string.
517 /// isPredicated - Returns true if the instruction is already predicated.
519 virtual bool isPredicated(const MachineInstr *MI) const {
523 /// isUnpredicatedTerminator - Returns true if the instruction is a
524 /// terminator instruction that has not been predicated.
525 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
527 /// PredicateInstruction - Convert the instruction into a predicated
528 /// instruction. It returns true if the operation was successful.
530 bool PredicateInstruction(MachineInstr *MI,
531 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
533 /// SubsumesPredicate - Returns true if the first specified predicate
534 /// subsumes the second, e.g. GE subsumes GT.
536 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
537 const SmallVectorImpl<MachineOperand> &Pred2) const {
541 /// DefinesPredicate - If the specified instruction defines any predicate
542 /// or condition code register(s) used for predication, returns true as well
543 /// as the definition predicate(s) by reference.
544 virtual bool DefinesPredicate(MachineInstr *MI,
545 std::vector<MachineOperand> &Pred) const {
549 /// isPredicable - Return true if the specified instruction can be predicated.
550 /// By default, this returns true for every instruction with a
551 /// PredicateOperand.
552 virtual bool isPredicable(MachineInstr *MI) const {
553 return MI->getDesc().isPredicable();
556 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
557 /// instruction that defines the specified register class.
558 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
562 /// GetInstSize - Returns the size of the specified Instruction.
564 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
565 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
569 /// GetFunctionSizeInBytes - Returns the size of the specified
572 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
574 /// Measure the specified inline asm to determine an approximation of its
576 virtual unsigned getInlineAsmLength(const char *Str,
577 const MCAsmInfo &MAI) const;
580 /// TargetInstrInfoImpl - This is the default implementation of
581 /// TargetInstrInfo, which just provides a couple of default implementations
582 /// for various methods. This separated out because it is implemented in
583 /// libcodegen, not in libtarget.
584 class TargetInstrInfoImpl : public TargetInstrInfo {
586 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
587 : TargetInstrInfo(desc, NumOpcodes) {}
589 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
590 bool NewMI = false) const;
591 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
592 unsigned &SrcOpIdx2) const;
593 virtual bool PredicateInstruction(MachineInstr *MI,
594 const SmallVectorImpl<MachineOperand> &Pred) const;
595 virtual void reMaterialize(MachineBasicBlock &MBB,
596 MachineBasicBlock::iterator MI,
597 unsigned DestReg, unsigned SubReg,
598 const MachineInstr *Orig,
599 const TargetRegisterInfo &TRI) const;
600 virtual MachineInstr *duplicate(MachineInstr *Orig,
601 MachineFunction &MF) const;
602 virtual bool produceSameValue(const MachineInstr *MI0,
603 const MachineInstr *MI1) const;
604 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
607 } // End llvm namespace