1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //---------------------------------------------------------------------------
36 // Data types used to define information about a single machine instruction
37 //---------------------------------------------------------------------------
39 typedef short MachineOpCode;
40 typedef unsigned InstrSchedClass;
42 //---------------------------------------------------------------------------
43 // struct TargetInstrDescriptor:
44 // Predefined information about each machine instruction.
45 // Designed to initialized statically.
48 const unsigned M_BRANCH_FLAG = 1 << 0;
49 const unsigned M_CALL_FLAG = 1 << 1;
50 const unsigned M_RET_FLAG = 1 << 2;
51 const unsigned M_BARRIER_FLAG = 1 << 3;
52 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
54 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
55 /// from memory. This should only be set on instructions that load a value from
56 /// memory and return it in their only virtual register definition.
57 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
59 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
60 /// modify memory. Instructions with this flag set are not necessarily simple
61 /// store instructions, they may store a modified value based on their operands,
62 /// or may not actually modify anything, for example.
63 const unsigned M_MAY_STORE_FLAG = 1 << 6;
65 const unsigned M_INDIRECT_FLAG = 1 << 7;
66 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
68 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
69 // changed into a 3-address instruction if the first two operands cannot be
70 // assigned to the same register. The target must implement the
71 // TargetInstrInfo::convertToThreeAddress method for this instruction.
72 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
74 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
75 // Z), which produces the same result if Y and Z are exchanged.
76 const unsigned M_COMMUTABLE = 1 << 10;
78 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
79 // block? Typically this is things like return and branch instructions.
80 // Various passes use this to insert code into the bottom of a basic block, but
81 // before control flow occurs.
82 const unsigned M_TERMINATOR_FLAG = 1 << 11;
84 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
85 // insertion support when the DAG scheduler is inserting it into a machine basic
87 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
89 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
90 // operands in addition to the minimum number operands specified.
91 const unsigned M_VARIABLE_OPS = 1 << 13;
93 // M_PREDICABLE - Set if this instruction has a predicate operand that
94 // controls execution. It may be set to 'always'.
95 const unsigned M_PREDICABLE = 1 << 14;
97 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
98 // at any time, e.g. constant generation, load from constant pool.
99 const unsigned M_REMATERIALIZIBLE = 1 << 15;
101 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
102 // (e.g. instructions with unique labels attached).
103 const unsigned M_NOT_DUPLICABLE = 1 << 16;
105 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
106 // ARM instructions which can set condition code if 's' bit is set.
107 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
109 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
110 // are not captured by any operands of the instruction or other flags, and when
111 // *all* instances of the instruction of that opcode have no side effects.
113 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
114 // both! If neither flag is set, then the instruction *always* has side effects.
115 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
117 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
118 // side effects. The virtual method "isReallySideEffectFree" is called to
119 // determine this. Load instructions are an example of where this is useful. In
120 // general, loads always have side effects. However, loads from constant pools
121 // don't. We let the specific back end make this determination.
123 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
124 // both! If neither flag is set, then the instruction *always* has side effects.
125 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
127 // Machine operand flags
128 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
129 // requires a callback to look up its register class.
130 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
132 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
133 /// predicate operand that controls an M_PREDICATED instruction.
134 const unsigned M_PREDICATE_OPERAND = 1 << 1;
136 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
138 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
141 // Operand constraints: only "tied_to" for now.
142 enum OperandConstraint {
143 TIED_TO = 0 // Must be allocated the same register as.
147 /// TargetOperandInfo - This holds information about one operand of a machine
148 /// instruction, indicating the register class for register operands, etc.
150 class TargetOperandInfo {
152 /// RegClass - This specifies the register class enumeration of the operand
153 /// if the operand is a register. If not, this contains 0.
154 unsigned short RegClass;
155 unsigned short Flags;
156 /// Lower 16 bits are used to specify which constraints are set. The higher 16
157 /// bits are used to specify the value of constraints (4 bits each).
158 unsigned int Constraints;
159 /// Currently no other information.
163 class TargetInstrDescriptor {
165 MachineOpCode Opcode; // The opcode.
166 unsigned short numOperands; // Num of args (may be more if variable_ops).
167 unsigned short numDefs; // Num of args that are definitions.
168 const char * Name; // Assembly language mnemonic for the opcode.
169 InstrSchedClass schedClass; // enum identifying instr sched class
170 unsigned Flags; // flags identifying machine instr class
171 unsigned TSFlags; // Target Specific Flag values
172 const unsigned *ImplicitUses; // Registers implicitly read by this instr
173 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
174 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
176 /// getOperandConstraint - Returns the value of the specific constraint if
177 /// it is set. Returns -1 if it is not set.
178 int getOperandConstraint(unsigned OpNum,
179 TOI::OperandConstraint Constraint) const {
180 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
181 "Invalid operand # of TargetInstrInfo");
182 if (OpNum < numOperands &&
183 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
184 unsigned Pos = 16 + Constraint * 4;
185 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
190 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
191 /// dest operand. Returns -1 if there isn't one.
192 int findTiedToSrcOperand(unsigned OpNum) const;
194 bool isCall() const {
195 return Flags & M_CALL_FLAG;
198 bool isBranch() const {
199 return Flags & M_BRANCH_FLAG;
202 bool isTerminator() const {
203 return Flags & M_TERMINATOR_FLAG;
206 bool isIndirectBranch() const {
207 return Flags & M_INDIRECT_FLAG;
210 bool isPredicable() const {
211 return Flags & M_PREDICABLE;
214 bool isNotDuplicable() const {
215 return Flags & M_NOT_DUPLICABLE;
220 /// isSimpleLoad - Return true for instructions that are simple loads from
221 /// memory. This should only be set on instructions that load a value from
222 /// memory and return it in their only virtual register definition.
223 /// Instructions that return a value loaded from memory and then modified in
224 /// some way should not return true for this.
225 bool isSimpleLoad() const {
226 return Flags & M_SIMPLE_LOAD_FLAG;
229 /// mayStore - Return true if this instruction could possibly modify memory.
230 /// Instructions with this flag set are not necessarily simple store
231 /// instructions, they may store a modified value based on their operands, or
232 /// may not actually modify anything, for example.
233 bool mayStore() const {
234 return Flags & M_MAY_STORE_FLAG;
237 /// isBarrier - Returns true if the specified instruction stops control flow
238 /// from executing the instruction immediately following it. Examples include
239 /// unconditional branches and return instructions.
240 bool isBarrier() const {
241 return Flags & M_BARRIER_FLAG;
244 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
245 /// which must be filled by the code generator.
246 bool hasDelaySlot() const {
247 return Flags & M_DELAY_SLOT_FLAG;
252 //---------------------------------------------------------------------------
254 /// TargetInstrInfo - Interface to description of machine instructions
256 class TargetInstrInfo {
257 const TargetInstrDescriptor* desc; // raw array to allow static init'n
258 unsigned NumOpcodes; // number of entries in the desc array
259 unsigned numRealOpCodes; // number of non-dummy op codes
261 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
262 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
264 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
265 virtual ~TargetInstrInfo();
267 // Invariant opcodes: All instruction sets have these as their low opcodes.
276 unsigned getNumOpcodes() const { return NumOpcodes; }
278 /// get - Return the machine instruction descriptor that corresponds to the
279 /// specified instruction opcode.
281 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
282 assert((unsigned)Opcode < NumOpcodes);
286 const char *getName(MachineOpCode Opcode) const {
287 return get(Opcode).Name;
290 int getNumOperands(MachineOpCode Opcode) const {
291 return get(Opcode).numOperands;
294 int getNumDefs(MachineOpCode Opcode) const {
295 return get(Opcode).numDefs;
298 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
299 return get(Opcode).schedClass;
302 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
303 return get(Opcode).ImplicitUses;
306 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
307 return get(Opcode).ImplicitDefs;
312 // Query instruction class flags according to the machine-independent
313 // flags listed above.
315 bool isReturn(MachineOpCode Opcode) const {
316 return get(Opcode).Flags & M_RET_FLAG;
319 bool isCommutableInstr(MachineOpCode Opcode) const {
320 return get(Opcode).Flags & M_COMMUTABLE;
323 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
324 /// custom insertion support when the DAG scheduler is inserting it into a
325 /// machine basic block.
326 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
327 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
330 bool hasVariableOperands(MachineOpCode Opcode) const {
331 return get(Opcode).Flags & M_VARIABLE_OPS;
334 bool hasOptionalDef(MachineOpCode Opcode) const {
335 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
338 /// isTriviallyReMaterializable - Return true if the instruction is trivially
339 /// rematerializable, meaning it has no side effects and requires no operands
340 /// that aren't always available.
341 bool isTriviallyReMaterializable(MachineInstr *MI) const {
342 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
343 isReallyTriviallyReMaterializable(MI);
346 /// hasUnmodelledSideEffects - Returns true if the instruction has side
347 /// effects that are not captured by any operands of the instruction or other
349 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
350 const TargetInstrDescriptor *TID = MI->getDesc();
351 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
352 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
353 return !isReallySideEffectFree(MI); // May have side effects
356 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
357 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
358 /// instruction itself is actually trivially rematerializable, considering
359 /// its operands. This is used for targets that have instructions that are
360 /// only trivially rematerializable for specific uses. This predicate must
361 /// return false if the instruction has any side effects other than
362 /// producing a value, or if it requres any address registers that are not
363 /// always available.
364 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
368 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
369 /// method is called to determine if the specific instance of this
370 /// instruction has side effects. This is useful in cases of instructions,
371 /// like loads, which generally always have side effects. A load from a
372 /// constant pool doesn't have side effects, though. So we need to
373 /// differentiate it from the general case.
374 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
378 /// getOperandConstraint - Returns the value of the specific constraint if
379 /// it is set. Returns -1 if it is not set.
380 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
381 TOI::OperandConstraint Constraint) const {
382 return get(Opcode).getOperandConstraint(OpNum, Constraint);
385 /// Return true if the instruction is a register to register move
386 /// and leave the source and dest operands in the passed parameters.
387 virtual bool isMoveInstr(const MachineInstr& MI,
389 unsigned& destReg) const {
393 /// isLoadFromStackSlot - If the specified machine instruction is a direct
394 /// load from a stack slot, return the virtual or physical register number of
395 /// the destination along with the FrameIndex of the loaded stack slot. If
396 /// not, return 0. This predicate must return 0 if the instruction has
397 /// any side effects other than loading from the stack slot.
398 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
402 /// isStoreToStackSlot - If the specified machine instruction is a direct
403 /// store to a stack slot, return the virtual or physical register number of
404 /// the source reg along with the FrameIndex of the loaded stack slot. If
405 /// not, return 0. This predicate must return 0 if the instruction has
406 /// any side effects other than storing to the stack slot.
407 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
411 /// convertToThreeAddress - This method must be implemented by targets that
412 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
413 /// may be able to convert a two-address instruction into one or more true
414 /// three-address instructions on demand. This allows the X86 target (for
415 /// example) to convert ADD and SHL instructions into LEA instructions if they
416 /// would require register copies due to two-addressness.
418 /// This method returns a null pointer if the transformation cannot be
419 /// performed, otherwise it returns the last new instruction.
421 virtual MachineInstr *
422 convertToThreeAddress(MachineFunction::iterator &MFI,
423 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
427 /// commuteInstruction - If a target has any instructions that are commutable,
428 /// but require converting to a different instruction or making non-trivial
429 /// changes to commute them, this method can overloaded to do this. The
430 /// default implementation of this method simply swaps the first two operands
431 /// of MI and returns it.
433 /// If a target wants to make more aggressive changes, they can construct and
434 /// return a new machine instruction. If an instruction cannot commute, it
435 /// can also return null.
437 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
439 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
440 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
441 /// implemented for a target). Upon success, this returns false and returns
442 /// with the following information in various cases:
444 /// 1. If this block ends with no branches (it just falls through to its succ)
445 /// just return false, leaving TBB/FBB null.
446 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
447 /// the destination block.
448 /// 3. If this block ends with an conditional branch and it falls through to
449 /// an successor block, it sets TBB to be the branch destination block and a
450 /// list of operands that evaluate the condition. These
451 /// operands can be passed to other TargetInstrInfo methods to create new
453 /// 4. If this block ends with an conditional branch and an unconditional
454 /// block, it returns the 'true' destination in TBB, the 'false' destination
455 /// in FBB, and a list of operands that evaluate the condition. These
456 /// operands can be passed to other TargetInstrInfo methods to create new
459 /// Note that RemoveBranch and InsertBranch must be implemented to support
460 /// cases where this method returns success.
462 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
463 MachineBasicBlock *&FBB,
464 std::vector<MachineOperand> &Cond) const {
468 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
469 /// this is only invoked in cases where AnalyzeBranch returns success. It
470 /// returns the number of instructions that were removed.
471 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
472 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
476 /// InsertBranch - Insert a branch into the end of the specified
477 /// MachineBasicBlock. This operands to this method are the same as those
478 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
479 /// returns success and when an unconditional branch (TBB is non-null, FBB is
480 /// null, Cond is empty) needs to be inserted. It returns the number of
481 /// instructions inserted.
482 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB,
484 const std::vector<MachineOperand> &Cond) const {
485 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
489 /// copyRegToReg - Add a copy between a pair of registers
490 virtual void copyRegToReg(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator MI,
492 unsigned DestReg, unsigned SrcReg,
493 const TargetRegisterClass *DestRC,
494 const TargetRegisterClass *SrcRC) const {
495 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
498 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator MI,
500 unsigned SrcReg, bool isKill, int FrameIndex,
501 const TargetRegisterClass *RC) const {
502 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
505 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
506 SmallVectorImpl<MachineOperand> &Addr,
507 const TargetRegisterClass *RC,
508 SmallVectorImpl<MachineInstr*> &NewMIs) const {
509 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
512 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator MI,
514 unsigned DestReg, int FrameIndex,
515 const TargetRegisterClass *RC) const {
516 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
519 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
520 SmallVectorImpl<MachineOperand> &Addr,
521 const TargetRegisterClass *RC,
522 SmallVectorImpl<MachineInstr*> &NewMIs) const {
523 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
526 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
527 /// saved registers and returns true if it isn't possible / profitable to do
528 /// so by issuing a series of store instructions via
529 /// storeRegToStackSlot(). Returns false otherwise.
530 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
531 MachineBasicBlock::iterator MI,
532 const std::vector<CalleeSavedInfo> &CSI) const {
536 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
537 /// saved registers and returns true if it isn't possible / profitable to do
538 /// so by issuing a series of load instructions via loadRegToStackSlot().
539 /// Returns false otherwise.
540 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
541 MachineBasicBlock::iterator MI,
542 const std::vector<CalleeSavedInfo> &CSI) const {
546 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
547 /// slot into the specified machine instruction for the specified operand(s).
548 /// If this is possible, a new instruction is returned with the specified
549 /// operand folded, otherwise NULL is returned. The client is responsible for
550 /// removing the old instruction and adding the new one in the instruction
552 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
553 SmallVectorImpl<unsigned> &Ops,
554 int FrameIndex) const {
558 /// foldMemoryOperand - Same as the previous version except it allows folding
559 /// of any load and store from / to any address, not just from a specific
561 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
562 SmallVectorImpl<unsigned> &Ops,
563 MachineInstr* LoadMI) const {
567 /// canFoldMemoryOperand - Returns true if the specified load / store is
568 /// folding is possible.
570 bool canFoldMemoryOperand(MachineInstr *MI,
571 SmallVectorImpl<unsigned> &Ops) const{
575 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
576 /// a store or a load and a store into two or more instruction. If this is
577 /// possible, returns true as well as the new instructions by reference.
578 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
579 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
580 SmallVectorImpl<MachineInstr*> &NewMIs) const{
584 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
585 SmallVectorImpl<SDNode*> &NewNodes) const {
589 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
590 /// instruction after load / store are unfolded from an instruction of the
591 /// specified opcode. It returns zero if the specified unfolding is not
593 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
594 bool UnfoldLoad, bool UnfoldStore) const {
598 /// BlockHasNoFallThrough - Return true if the specified block does not
599 /// fall-through into its successor block. This is primarily used when a
600 /// branch is unanalyzable. It is useful for things like unconditional
601 /// indirect branches (jump tables).
602 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
606 /// ReverseBranchCondition - Reverses the branch condition of the specified
607 /// condition list, returning false on success and true if it cannot be
609 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
613 /// insertNoop - Insert a noop into the instruction stream at the specified
615 virtual void insertNoop(MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator MI) const {
617 assert(0 && "Target didn't implement insertNoop!");
621 /// isPredicated - Returns true if the instruction is already predicated.
623 virtual bool isPredicated(const MachineInstr *MI) const {
627 /// isUnpredicatedTerminator - Returns true if the instruction is a
628 /// terminator instruction that has not been predicated.
629 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
631 /// PredicateInstruction - Convert the instruction into a predicated
632 /// instruction. It returns true if the operation was successful.
634 bool PredicateInstruction(MachineInstr *MI,
635 const std::vector<MachineOperand> &Pred) const = 0;
637 /// SubsumesPredicate - Returns true if the first specified predicate
638 /// subsumes the second, e.g. GE subsumes GT.
640 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
641 const std::vector<MachineOperand> &Pred2) const {
645 /// DefinesPredicate - If the specified instruction defines any predicate
646 /// or condition code register(s) used for predication, returns true as well
647 /// as the definition predicate(s) by reference.
648 virtual bool DefinesPredicate(MachineInstr *MI,
649 std::vector<MachineOperand> &Pred) const {
653 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
655 virtual const TargetRegisterClass *getPointerRegClass() const {
656 assert(0 && "Target didn't implement getPointerRegClass!");
658 return 0; // Must return a value in order to compile with VS 2005
662 /// TargetInstrInfoImpl - This is the default implementation of
663 /// TargetInstrInfo, which just provides a couple of default implementations
664 /// for various methods. This separated out because it is implemented in
665 /// libcodegen, not in libtarget.
666 class TargetInstrInfoImpl : public TargetInstrInfo {
668 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
669 : TargetInstrInfo(desc, NumOpcodes) {}
671 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
672 virtual bool PredicateInstruction(MachineInstr *MI,
673 const std::vector<MachineOperand> &Pred) const;
677 } // End llvm namespace