1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
30 //---------------------------------------------------------------------------
31 // Data types used to define information about a single machine instruction
32 //---------------------------------------------------------------------------
34 typedef short MachineOpCode;
35 typedef unsigned InstrSchedClass;
37 //---------------------------------------------------------------------------
38 // struct TargetInstrDescriptor:
39 // Predefined information about each machine instruction.
40 // Designed to initialized statically.
43 const unsigned M_BRANCH_FLAG = 1 << 0;
44 const unsigned M_CALL_FLAG = 1 << 1;
45 const unsigned M_RET_FLAG = 1 << 2;
46 const unsigned M_BARRIER_FLAG = 1 << 3;
47 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
48 const unsigned M_LOAD_FLAG = 1 << 5;
49 const unsigned M_STORE_FLAG = 1 << 6;
50 const unsigned M_INDIRECT_FLAG = 1 << 7;
51 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
53 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
54 // changed into a 3-address instruction if the first two operands cannot be
55 // assigned to the same register. The target must implement the
56 // TargetInstrInfo::convertToThreeAddress method for this instruction.
57 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
59 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
60 // Z), which produces the same result if Y and Z are exchanged.
61 const unsigned M_COMMUTABLE = 1 << 10;
63 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
64 // block? Typically this is things like return and branch instructions.
65 // Various passes use this to insert code into the bottom of a basic block, but
66 // before control flow occurs.
67 const unsigned M_TERMINATOR_FLAG = 1 << 11;
69 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
70 // insertion support when the DAG scheduler is inserting it into a machine basic
72 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
74 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
75 // operands in addition to the minimum number operands specified.
76 const unsigned M_VARIABLE_OPS = 1 << 13;
78 // M_PREDICABLE - Set if this instruction has a predicate operand that
79 // controls execution. It may be set to 'always'.
80 const unsigned M_PREDICABLE = 1 << 14;
82 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
83 // at any time, e.g. constant generation, load from constant pool.
84 const unsigned M_REMATERIALIZIBLE = 1 << 15;
86 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
87 // (e.g. instructions with unique labels attached).
88 const unsigned M_NOT_DUPLICABLE = 1 << 16;
90 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
91 // ARM instructions which can set condition code if 's' bit is set.
92 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
94 // M_MAY_HAVE_SIDE_EFFECTS - Set if this instruction *might* have side effects,
95 // e.g. load instructions. Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually
96 // exclusive. You can't set both! If neither flag is set, then the instruction
97 // *always* has side effects.
98 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 18;
100 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction *never* has side effects,
101 // e.g., xor on X86. Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually
102 // exclusive. You can't set both! If neither flag is set, then the instruction
103 // *always* has side effects.
104 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 19;
106 // Machine operand flags
107 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
108 // requires a callback to look up its register class.
109 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
111 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
112 /// predicate operand that controls an M_PREDICATED instruction.
113 const unsigned M_PREDICATE_OPERAND = 1 << 1;
115 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
117 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
120 // Operand constraints: only "tied_to" for now.
121 enum OperandConstraint {
122 TIED_TO = 0 // Must be allocated the same register as.
126 /// TargetOperandInfo - This holds information about one operand of a machine
127 /// instruction, indicating the register class for register operands, etc.
129 class TargetOperandInfo {
131 /// RegClass - This specifies the register class enumeration of the operand
132 /// if the operand is a register. If not, this contains 0.
133 unsigned short RegClass;
134 unsigned short Flags;
135 /// Lower 16 bits are used to specify which constraints are set. The higher 16
136 /// bits are used to specify the value of constraints (4 bits each).
137 unsigned int Constraints;
138 /// Currently no other information.
142 class TargetInstrDescriptor {
144 MachineOpCode Opcode; // The opcode.
145 unsigned short numOperands; // Num of args (may be more if variable_ops).
146 unsigned short numDefs; // Num of args that are definitions.
147 const char * Name; // Assembly language mnemonic for the opcode.
148 InstrSchedClass schedClass; // enum identifying instr sched class
149 unsigned Flags; // flags identifying machine instr class
150 unsigned TSFlags; // Target Specific Flag values
151 const unsigned *ImplicitUses; // Registers implicitly read by this instr
152 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
153 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
155 /// getOperandConstraint - Returns the value of the specific constraint if
156 /// it is set. Returns -1 if it is not set.
157 int getOperandConstraint(unsigned OpNum,
158 TOI::OperandConstraint Constraint) const {
159 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
160 "Invalid operand # of TargetInstrInfo");
161 if (OpNum < numOperands &&
162 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
163 unsigned Pos = 16 + Constraint * 4;
164 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
169 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
170 /// dest operand. Returns -1 if there isn't one.
171 int findTiedToSrcOperand(unsigned OpNum) const;
175 //---------------------------------------------------------------------------
177 /// TargetInstrInfo - Interface to description of machine instructions
179 class TargetInstrInfo {
180 const TargetInstrDescriptor* desc; // raw array to allow static init'n
181 unsigned NumOpcodes; // number of entries in the desc array
182 unsigned numRealOpCodes; // number of non-dummy op codes
184 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
185 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
187 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
188 virtual ~TargetInstrInfo();
190 // Invariant opcodes: All instruction sets have these as their low opcodes.
199 unsigned getNumOpcodes() const { return NumOpcodes; }
201 /// get - Return the machine instruction descriptor that corresponds to the
202 /// specified instruction opcode.
204 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
205 assert((unsigned)Opcode < NumOpcodes);
209 const char *getName(MachineOpCode Opcode) const {
210 return get(Opcode).Name;
213 int getNumOperands(MachineOpCode Opcode) const {
214 return get(Opcode).numOperands;
217 int getNumDefs(MachineOpCode Opcode) const {
218 return get(Opcode).numDefs;
221 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
222 return get(Opcode).schedClass;
225 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
226 return get(Opcode).ImplicitUses;
229 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
230 return get(Opcode).ImplicitDefs;
235 // Query instruction class flags according to the machine-independent
236 // flags listed above.
238 bool isReturn(MachineOpCode Opcode) const {
239 return get(Opcode).Flags & M_RET_FLAG;
242 bool isCommutableInstr(MachineOpCode Opcode) const {
243 return get(Opcode).Flags & M_COMMUTABLE;
245 bool isTerminatorInstr(MachineOpCode Opcode) const {
246 return get(Opcode).Flags & M_TERMINATOR_FLAG;
249 bool isBranch(MachineOpCode Opcode) const {
250 return get(Opcode).Flags & M_BRANCH_FLAG;
253 bool isIndirectBranch(MachineOpCode Opcode) const {
254 return get(Opcode).Flags & M_INDIRECT_FLAG;
257 /// isBarrier - Returns true if the specified instruction stops control flow
258 /// from executing the instruction immediately following it. Examples include
259 /// unconditional branches and return instructions.
260 bool isBarrier(MachineOpCode Opcode) const {
261 return get(Opcode).Flags & M_BARRIER_FLAG;
264 bool isCall(MachineOpCode Opcode) const {
265 return get(Opcode).Flags & M_CALL_FLAG;
267 bool isLoad(MachineOpCode Opcode) const {
268 return get(Opcode).Flags & M_LOAD_FLAG;
270 bool isStore(MachineOpCode Opcode) const {
271 return get(Opcode).Flags & M_STORE_FLAG;
274 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
275 /// which must be filled by the code generator.
276 bool hasDelaySlot(MachineOpCode Opcode) const {
277 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
280 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
281 /// custom insertion support when the DAG scheduler is inserting it into a
282 /// machine basic block.
283 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
284 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
287 bool hasVariableOperands(MachineOpCode Opcode) const {
288 return get(Opcode).Flags & M_VARIABLE_OPS;
291 bool isPredicable(MachineOpCode Opcode) const {
292 return get(Opcode).Flags & M_PREDICABLE;
295 bool isNotDuplicable(MachineOpCode Opcode) const {
296 return get(Opcode).Flags & M_NOT_DUPLICABLE;
299 bool hasOptionalDef(MachineOpCode Opcode) const {
300 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
303 /// isTriviallyReMaterializable - Return true if the instruction is trivially
304 /// rematerializable, meaning it has no side effects and requires no operands
305 /// that aren't always available.
306 bool isTriviallyReMaterializable(MachineInstr *MI) const {
307 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
308 isReallyTriviallyReMaterializable(MI);
312 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
313 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
314 /// instruction itself is actually trivially rematerializable, considering
315 /// its operands. This is used for targets that have instructions that are
316 /// only trivially rematerializable for specific uses. This predicate must
317 /// return false if the instruction has any side effects other than
318 /// producing a value, or if it requres any address registers that are not
319 /// always available.
320 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
325 /// getOperandConstraint - Returns the value of the specific constraint if
326 /// it is set. Returns -1 if it is not set.
327 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
328 TOI::OperandConstraint Constraint) const {
329 return get(Opcode).getOperandConstraint(OpNum, Constraint);
332 /// Return true if the instruction is a register to register move
333 /// and leave the source and dest operands in the passed parameters.
334 virtual bool isMoveInstr(const MachineInstr& MI,
336 unsigned& destReg) const {
340 /// isLoadFromStackSlot - If the specified machine instruction is a direct
341 /// load from a stack slot, return the virtual or physical register number of
342 /// the destination along with the FrameIndex of the loaded stack slot. If
343 /// not, return 0. This predicate must return 0 if the instruction has
344 /// any side effects other than loading from the stack slot.
345 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
349 /// isStoreToStackSlot - If the specified machine instruction is a direct
350 /// store to a stack slot, return the virtual or physical register number of
351 /// the source reg along with the FrameIndex of the loaded stack slot. If
352 /// not, return 0. This predicate must return 0 if the instruction has
353 /// any side effects other than storing to the stack slot.
354 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
358 /// convertToThreeAddress - This method must be implemented by targets that
359 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
360 /// may be able to convert a two-address instruction into one or more true
361 /// three-address instructions on demand. This allows the X86 target (for
362 /// example) to convert ADD and SHL instructions into LEA instructions if they
363 /// would require register copies due to two-addressness.
365 /// This method returns a null pointer if the transformation cannot be
366 /// performed, otherwise it returns the last new instruction.
368 virtual MachineInstr *
369 convertToThreeAddress(MachineFunction::iterator &MFI,
370 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
374 /// commuteInstruction - If a target has any instructions that are commutable,
375 /// but require converting to a different instruction or making non-trivial
376 /// changes to commute them, this method can overloaded to do this. The
377 /// default implementation of this method simply swaps the first two operands
378 /// of MI and returns it.
380 /// If a target wants to make more aggressive changes, they can construct and
381 /// return a new machine instruction. If an instruction cannot commute, it
382 /// can also return null.
384 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
386 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
387 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
388 /// implemented for a target). Upon success, this returns false and returns
389 /// with the following information in various cases:
391 /// 1. If this block ends with no branches (it just falls through to its succ)
392 /// just return false, leaving TBB/FBB null.
393 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
394 /// the destination block.
395 /// 3. If this block ends with an conditional branch and it falls through to
396 /// an successor block, it sets TBB to be the branch destination block and a
397 /// list of operands that evaluate the condition. These
398 /// operands can be passed to other TargetInstrInfo methods to create new
400 /// 4. If this block ends with an conditional branch and an unconditional
401 /// block, it returns the 'true' destination in TBB, the 'false' destination
402 /// in FBB, and a list of operands that evaluate the condition. These
403 /// operands can be passed to other TargetInstrInfo methods to create new
406 /// Note that RemoveBranch and InsertBranch must be implemented to support
407 /// cases where this method returns success.
409 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
410 MachineBasicBlock *&FBB,
411 std::vector<MachineOperand> &Cond) const {
415 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
416 /// this is only invoked in cases where AnalyzeBranch returns success. It
417 /// returns the number of instructions that were removed.
418 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
419 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
423 /// InsertBranch - Insert a branch into the end of the specified
424 /// MachineBasicBlock. This operands to this method are the same as those
425 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
426 /// returns success and when an unconditional branch (TBB is non-null, FBB is
427 /// null, Cond is empty) needs to be inserted. It returns the number of
428 /// instructions inserted.
429 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
430 MachineBasicBlock *FBB,
431 const std::vector<MachineOperand> &Cond) const {
432 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
436 /// BlockHasNoFallThrough - Return true if the specified block does not
437 /// fall-through into its successor block. This is primarily used when a
438 /// branch is unanalyzable. It is useful for things like unconditional
439 /// indirect branches (jump tables).
440 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
444 /// ReverseBranchCondition - Reverses the branch condition of the specified
445 /// condition list, returning false on success and true if it cannot be
447 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
451 /// insertNoop - Insert a noop into the instruction stream at the specified
453 virtual void insertNoop(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator MI) const {
455 assert(0 && "Target didn't implement insertNoop!");
459 /// isPredicated - Returns true if the instruction is already predicated.
461 virtual bool isPredicated(const MachineInstr *MI) const {
465 /// isUnpredicatedTerminator - Returns true if the instruction is a
466 /// terminator instruction that has not been predicated.
467 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
469 /// PredicateInstruction - Convert the instruction into a predicated
470 /// instruction. It returns true if the operation was successful.
472 bool PredicateInstruction(MachineInstr *MI,
473 const std::vector<MachineOperand> &Pred) const;
475 /// SubsumesPredicate - Returns true if the first specified predicate
476 /// subsumes the second, e.g. GE subsumes GT.
478 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
479 const std::vector<MachineOperand> &Pred2) const {
483 /// DefinesPredicate - If the specified instruction defines any predicate
484 /// or condition code register(s) used for predication, returns true as well
485 /// as the definition predicate(s) by reference.
486 virtual bool DefinesPredicate(MachineInstr *MI,
487 std::vector<MachineOperand> &Pred) const {
491 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
493 virtual const TargetRegisterClass *getPointerRegClass() const {
494 assert(0 && "Target didn't implement getPointerRegClass!");
496 return 0; // Must return a value in order to compile with VS 2005
500 } // End llvm namespace