1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
30 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
35 /// TargetInstrInfo - Interface to description of machine instruction set
37 class TargetInstrInfo {
38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
39 unsigned NumOpcodes; // Number of entries in the desc array
41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
45 virtual ~TargetInstrInfo();
47 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 /// KILL - This instruction is a noop that is used only to adjust the liveness
56 /// of registers. This can be useful when dealing with sub-registers.
59 /// EXTRACT_SUBREG - This instruction takes two operands: a register
60 /// that has subregisters, and a subregister index. It returns the
61 /// extracted subregister value. This is commonly used to implement
62 /// truncation operations on target architectures which support it.
65 /// INSERT_SUBREG - This instruction takes three operands: a register
66 /// that has subregisters, a register providing an insert value, and a
67 /// subregister index. It returns the value of the first register with
68 /// the value of the second register inserted. The first register is
69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
70 /// anyext operations on target architectures which support it.
73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
77 /// that the first operand is an immediate integer constant. This constant
78 /// is often zero, as is commonly used to implement zext operations on
79 /// target architectures which support it, such as with x86-64 (with
80 /// zext from i32 to i64 via implicit zero-extension).
83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
84 /// register-to-register copy into a specific register class. This is only
85 /// used between instruction selection and MachineInstr creation, before
86 /// virtual registers have been created for all the instructions, and it's
87 /// only needed in cases where the register classes implied by the
88 /// instructions are insufficient. The actual MachineInstrs to perform
89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
93 unsigned getNumOpcodes() const { return NumOpcodes; }
95 /// get - Return the machine instruction descriptor that corresponds to the
96 /// specified instruction opcode.
98 const TargetInstrDesc &get(unsigned Opcode) const {
99 assert(Opcode < NumOpcodes && "Invalid opcode!");
100 return Descriptors[Opcode];
103 /// isTriviallyReMaterializable - Return true if the instruction is trivially
104 /// rematerializable, meaning it has no side effects and requires no operands
105 /// that aren't always available.
106 bool isTriviallyReMaterializable(const MachineInstr *MI,
107 AliasAnalysis *AA = 0) const {
108 return MI->getOpcode() == IMPLICIT_DEF ||
109 (MI->getDesc().isRematerializable() &&
110 (isReallyTriviallyReMaterializable(MI) ||
111 isReallyTriviallyReMaterializableGeneric(MI, AA)));
115 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
116 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
117 /// specify whether the instruction is actually trivially rematerializable,
118 /// taking into consideration its operands. This predicate must return false
119 /// if the instruction has any side effects other than producing a value, or
120 /// if it requres any address registers that are not always available.
121 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
126 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
127 /// for which the M_REMATERIALIZABLE flag is set and the target hook
128 /// isReallyTriviallyReMaterializable returns false, this function does
129 /// target-independent tests to determine if the instruction is really
130 /// trivially rematerializable.
131 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
132 AliasAnalysis *AA) const;
135 /// Return true if the instruction is a register to register move and return
136 /// the source and dest operands and their sub-register indices by reference.
137 virtual bool isMoveInstr(const MachineInstr& MI,
138 unsigned& SrcReg, unsigned& DstReg,
139 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
143 /// isLoadFromStackSlot - If the specified machine instruction is a direct
144 /// load from a stack slot, return the virtual or physical register number of
145 /// the destination along with the FrameIndex of the loaded stack slot. If
146 /// not, return 0. This predicate must return 0 if the instruction has
147 /// any side effects other than loading from the stack slot.
148 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
149 int &FrameIndex) const {
153 /// isStoreToStackSlot - If the specified machine instruction is a direct
154 /// store to a stack slot, return the virtual or physical register number of
155 /// the source reg along with the FrameIndex of the loaded stack slot. If
156 /// not, return 0. This predicate must return 0 if the instruction has
157 /// any side effects other than storing to the stack slot.
158 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
159 int &FrameIndex) const {
163 /// reMaterialize - Re-issue the specified 'original' instruction at the
164 /// specific location targeting a new destination register.
165 virtual void reMaterialize(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator MI,
167 unsigned DestReg, unsigned SubIdx,
168 const MachineInstr *Orig) const = 0;
170 /// convertToThreeAddress - This method must be implemented by targets that
171 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
172 /// may be able to convert a two-address instruction into one or more true
173 /// three-address instructions on demand. This allows the X86 target (for
174 /// example) to convert ADD and SHL instructions into LEA instructions if they
175 /// would require register copies due to two-addressness.
177 /// This method returns a null pointer if the transformation cannot be
178 /// performed, otherwise it returns the last new instruction.
180 virtual MachineInstr *
181 convertToThreeAddress(MachineFunction::iterator &MFI,
182 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
186 /// commuteInstruction - If a target has any instructions that are commutable,
187 /// but require converting to a different instruction or making non-trivial
188 /// changes to commute them, this method can overloaded to do this. The
189 /// default implementation of this method simply swaps the first two operands
190 /// of MI and returns it.
192 /// If a target wants to make more aggressive changes, they can construct and
193 /// return a new machine instruction. If an instruction cannot commute, it
194 /// can also return null.
196 /// If NewMI is true, then a new machine instruction must be created.
198 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
199 bool NewMI = false) const = 0;
201 /// findCommutedOpIndices - If specified MI is commutable, return the two
202 /// operand indices that would swap value. Return true if the instruction
203 /// is not in a form which this routine understands.
204 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
205 unsigned &SrcOpIdx2) const = 0;
207 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
208 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
209 /// implemented for a target). Upon success, this returns false and returns
210 /// with the following information in various cases:
212 /// 1. If this block ends with no branches (it just falls through to its succ)
213 /// just return false, leaving TBB/FBB null.
214 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
215 /// the destination block.
216 /// 3. If this block ends with an conditional branch and it falls through to
217 /// a successor block, it sets TBB to be the branch destination block and
218 /// a list of operands that evaluate the condition. These
219 /// operands can be passed to other TargetInstrInfo methods to create new
221 /// 4. If this block ends with a conditional branch followed by an
222 /// unconditional branch, it returns the 'true' destination in TBB, the
223 /// 'false' destination in FBB, and a list of operands that evaluate the
224 /// condition. These operands can be passed to other TargetInstrInfo
225 /// methods to create new branches.
227 /// Note that RemoveBranch and InsertBranch must be implemented to support
228 /// cases where this method returns success.
230 /// If AllowModify is true, then this routine is allowed to modify the basic
231 /// block (e.g. delete instructions after the unconditional branch).
233 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
234 MachineBasicBlock *&FBB,
235 SmallVectorImpl<MachineOperand> &Cond,
236 bool AllowModify = false) const {
240 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
241 /// This is only invoked in cases where AnalyzeBranch returns success. It
242 /// returns the number of instructions that were removed.
243 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
244 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
248 /// InsertBranch - Insert branch code into the end of the specified
249 /// MachineBasicBlock. The operands to this method are the same as those
250 /// returned by AnalyzeBranch. This is only invoked in cases where
251 /// AnalyzeBranch returns success. It returns the number of instructions
254 /// It is also invoked by tail merging to add unconditional branches in
255 /// cases where AnalyzeBranch doesn't apply because there was no original
256 /// branch to analyze. At least this much must be implemented, else tail
257 /// merging needs to be disabled.
258 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
259 MachineBasicBlock *FBB,
260 const SmallVectorImpl<MachineOperand> &Cond) const {
261 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
265 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
266 /// returns false if the target does not how to copy between the specified
268 virtual bool copyRegToReg(MachineBasicBlock &MBB,
269 MachineBasicBlock::iterator MI,
270 unsigned DestReg, unsigned SrcReg,
271 const TargetRegisterClass *DestRC,
272 const TargetRegisterClass *SrcRC) const {
273 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
277 /// storeRegToStackSlot - Store the specified register of the given register
278 /// class to the specified stack frame index. The store instruction is to be
279 /// added to the given machine basic block before the specified machine
280 /// instruction. If isKill is true, the register operand is the last use and
281 /// must be marked kill.
282 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator MI,
284 unsigned SrcReg, bool isKill, int FrameIndex,
285 const TargetRegisterClass *RC) const {
286 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
289 /// loadRegFromStackSlot - Load the specified register of the given register
290 /// class from the specified stack frame index. The load instruction is to be
291 /// added to the given machine basic block before the specified machine
293 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
294 MachineBasicBlock::iterator MI,
295 unsigned DestReg, int FrameIndex,
296 const TargetRegisterClass *RC) const {
297 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
300 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
301 /// saved registers and returns true if it isn't possible / profitable to do
302 /// so by issuing a series of store instructions via
303 /// storeRegToStackSlot(). Returns false otherwise.
304 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
305 MachineBasicBlock::iterator MI,
306 const std::vector<CalleeSavedInfo> &CSI) const {
310 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
311 /// saved registers and returns true if it isn't possible / profitable to do
312 /// so by issuing a series of load instructions via loadRegToStackSlot().
313 /// Returns false otherwise.
314 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator MI,
316 const std::vector<CalleeSavedInfo> &CSI) const {
320 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
321 /// slot into the specified machine instruction for the specified operand(s).
322 /// If this is possible, a new instruction is returned with the specified
323 /// operand folded, otherwise NULL is returned. The client is responsible for
324 /// removing the old instruction and adding the new one in the instruction
326 MachineInstr* foldMemoryOperand(MachineFunction &MF,
328 const SmallVectorImpl<unsigned> &Ops,
329 int FrameIndex) const;
331 /// foldMemoryOperand - Same as the previous version except it allows folding
332 /// of any load and store from / to any address, not just from a specific
334 MachineInstr* foldMemoryOperand(MachineFunction &MF,
336 const SmallVectorImpl<unsigned> &Ops,
337 MachineInstr* LoadMI) const;
340 /// foldMemoryOperandImpl - Target-dependent implementation for
341 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
342 /// take care of adding a MachineMemOperand to the newly created instruction.
343 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
345 const SmallVectorImpl<unsigned> &Ops,
346 int FrameIndex) const {
350 /// foldMemoryOperandImpl - Target-dependent implementation for
351 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
352 /// take care of adding a MachineMemOperand to the newly created instruction.
353 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
355 const SmallVectorImpl<unsigned> &Ops,
356 MachineInstr* LoadMI) const {
361 /// canFoldMemoryOperand - Returns true for the specified load / store if
362 /// folding is possible.
364 bool canFoldMemoryOperand(const MachineInstr *MI,
365 const SmallVectorImpl<unsigned> &Ops) const {
369 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
370 /// a store or a load and a store into two or more instruction. If this is
371 /// possible, returns true as well as the new instructions by reference.
372 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
373 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
374 SmallVectorImpl<MachineInstr*> &NewMIs) const{
378 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
379 SmallVectorImpl<SDNode*> &NewNodes) const {
383 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
384 /// instruction after load / store are unfolded from an instruction of the
385 /// specified opcode. It returns zero if the specified unfolding is not
387 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
388 bool UnfoldLoad, bool UnfoldStore) const {
392 /// BlockHasNoFallThrough - Return true if the specified block does not
393 /// fall-through into its successor block. This is primarily used when a
394 /// branch is unanalyzable. It is useful for things like unconditional
395 /// indirect branches (jump tables).
396 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
400 /// ReverseBranchCondition - Reverses the branch condition of the specified
401 /// condition list, returning false on success and true if it cannot be
404 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
408 /// insertNoop - Insert a noop into the instruction stream at the specified
410 virtual void insertNoop(MachineBasicBlock &MBB,
411 MachineBasicBlock::iterator MI) const;
413 /// isPredicated - Returns true if the instruction is already predicated.
415 virtual bool isPredicated(const MachineInstr *MI) const {
419 /// isUnpredicatedTerminator - Returns true if the instruction is a
420 /// terminator instruction that has not been predicated.
421 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
423 /// PredicateInstruction - Convert the instruction into a predicated
424 /// instruction. It returns true if the operation was successful.
426 bool PredicateInstruction(MachineInstr *MI,
427 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
429 /// SubsumesPredicate - Returns true if the first specified predicate
430 /// subsumes the second, e.g. GE subsumes GT.
432 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
433 const SmallVectorImpl<MachineOperand> &Pred2) const {
437 /// DefinesPredicate - If the specified instruction defines any predicate
438 /// or condition code register(s) used for predication, returns true as well
439 /// as the definition predicate(s) by reference.
440 virtual bool DefinesPredicate(MachineInstr *MI,
441 std::vector<MachineOperand> &Pred) const {
445 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
446 /// instruction that defines the specified register class.
447 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
451 /// isDeadInstruction - Return true if the instruction is considered dead.
452 /// This allows some late codegen passes to delete them.
453 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0;
455 /// GetInstSize - Returns the size of the specified Instruction.
457 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
458 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
462 /// GetFunctionSizeInBytes - Returns the size of the specified
465 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
467 /// Measure the specified inline asm to determine an approximation of its
469 virtual unsigned getInlineAsmLength(const char *Str,
470 const MCAsmInfo &MAI) const;
473 /// TargetInstrInfoImpl - This is the default implementation of
474 /// TargetInstrInfo, which just provides a couple of default implementations
475 /// for various methods. This separated out because it is implemented in
476 /// libcodegen, not in libtarget.
477 class TargetInstrInfoImpl : public TargetInstrInfo {
479 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
480 : TargetInstrInfo(desc, NumOpcodes) {}
482 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
483 bool NewMI = false) const;
484 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
485 unsigned &SrcOpIdx2) const;
486 virtual bool PredicateInstruction(MachineInstr *MI,
487 const SmallVectorImpl<MachineOperand> &Pred) const;
488 virtual void reMaterialize(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator MI,
490 unsigned DestReg, unsigned SubReg,
491 const MachineInstr *Orig) const;
492 virtual bool isDeadInstruction(const MachineInstr *MI) const;
494 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
497 } // End llvm namespace