1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "Support/DataTypes.h"
30 class MachineCodeForInstruction;
32 //---------------------------------------------------------------------------
33 // Data types used to define information about a single machine instruction
34 //---------------------------------------------------------------------------
36 typedef short MachineOpCode;
37 typedef unsigned InstrSchedClass;
39 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
42 //---------------------------------------------------------------------------
43 // struct TargetInstrDescriptor:
44 // Predefined information about each machine instruction.
45 // Designed to initialized statically.
48 const unsigned M_NOP_FLAG = 1 << 0;
49 const unsigned M_BRANCH_FLAG = 1 << 1;
50 const unsigned M_CALL_FLAG = 1 << 2;
51 const unsigned M_RET_FLAG = 1 << 3;
52 const unsigned M_ARITH_FLAG = 1 << 4;
53 const unsigned M_CC_FLAG = 1 << 6;
54 const unsigned M_LOGICAL_FLAG = 1 << 6;
55 const unsigned M_INT_FLAG = 1 << 7;
56 const unsigned M_FLOAT_FLAG = 1 << 8;
57 const unsigned M_CONDL_FLAG = 1 << 9;
58 const unsigned M_LOAD_FLAG = 1 << 10;
59 const unsigned M_PREFETCH_FLAG = 1 << 11;
60 const unsigned M_STORE_FLAG = 1 << 12;
61 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
62 const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
63 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
64 const unsigned M_2_ADDR_FLAG = 1 << 15;
66 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
67 // block? Typically this is things like return and branch instructions.
68 // Various passes use this to insert code into the bottom of a basic block, but
69 // before control flow occurs.
70 const unsigned M_TERMINATOR_FLAG = 1 << 16;
72 struct TargetInstrDescriptor {
73 const char * Name; // Assembly language mnemonic for the opcode.
74 int numOperands; // Number of args; -1 if variable #args
75 int resultPos; // Position of the result; -1 if no result
76 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
77 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
78 // smallest -ve value is -(maxImmedConst+1).
79 unsigned numDelaySlots; // Number of delay slots after instruction
80 unsigned latency; // Latency in machine cycles
81 InstrSchedClass schedClass; // enum identifying instr sched class
82 unsigned Flags; // flags identifying machine instr class
83 unsigned TSFlags; // Target Specific Flag values
84 const unsigned *ImplicitUses; // Registers implicitly read by this instr
85 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
89 //---------------------------------------------------------------------------
91 /// TargetInstrInfo - Interface to description of machine instructions
93 class TargetInstrInfo {
94 const TargetInstrDescriptor* desc; // raw array to allow static init'n
95 unsigned descSize; // number of entries in the desc array
96 unsigned numRealOpCodes; // number of non-dummy op codes
98 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
99 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
101 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
102 unsigned numRealOpCodes);
103 virtual ~TargetInstrInfo();
105 // Invariant: All instruction sets use opcode #0 as the PHI instruction
108 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
109 unsigned getNumTotalOpCodes() const { return descSize; }
111 /// get - Return the machine instruction descriptor that corresponds to the
112 /// specified instruction opcode.
114 const TargetInstrDescriptor& get(MachineOpCode opCode) const {
115 assert(opCode >= 0 && opCode < (int)descSize);
119 const char *getName(MachineOpCode opCode) const {
120 return get(opCode).Name;
123 int getNumOperands(MachineOpCode opCode) const {
124 return get(opCode).numOperands;
127 int getResultPos(MachineOpCode opCode) const {
128 return get(opCode).resultPos;
131 unsigned getNumDelaySlots(MachineOpCode opCode) const {
132 return get(opCode).numDelaySlots;
135 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
136 return get(opCode).schedClass;
139 const unsigned *getImplicitUses(MachineOpCode opCode) const {
140 return get(opCode).ImplicitUses;
143 const unsigned *getImplicitDefs(MachineOpCode opCode) const {
144 return get(opCode).ImplicitDefs;
148 // Query instruction class flags according to the machine-independent
149 // flags listed above.
151 bool isNop(MachineOpCode opCode) const {
152 return get(opCode).Flags & M_NOP_FLAG;
154 bool isBranch(MachineOpCode opCode) const {
155 return get(opCode).Flags & M_BRANCH_FLAG;
157 bool isCall(MachineOpCode opCode) const {
158 return get(opCode).Flags & M_CALL_FLAG;
160 bool isReturn(MachineOpCode opCode) const {
161 return get(opCode).Flags & M_RET_FLAG;
163 bool isControlFlow(MachineOpCode opCode) const {
164 return get(opCode).Flags & M_BRANCH_FLAG
165 || get(opCode).Flags & M_CALL_FLAG
166 || get(opCode).Flags & M_RET_FLAG;
168 bool isArith(MachineOpCode opCode) const {
169 return get(opCode).Flags & M_ARITH_FLAG;
171 bool isCCInstr(MachineOpCode opCode) const {
172 return get(opCode).Flags & M_CC_FLAG;
174 bool isLogical(MachineOpCode opCode) const {
175 return get(opCode).Flags & M_LOGICAL_FLAG;
177 bool isIntInstr(MachineOpCode opCode) const {
178 return get(opCode).Flags & M_INT_FLAG;
180 bool isFloatInstr(MachineOpCode opCode) const {
181 return get(opCode).Flags & M_FLOAT_FLAG;
183 bool isConditional(MachineOpCode opCode) const {
184 return get(opCode).Flags & M_CONDL_FLAG;
186 bool isLoad(MachineOpCode opCode) const {
187 return get(opCode).Flags & M_LOAD_FLAG;
189 bool isPrefetch(MachineOpCode opCode) const {
190 return get(opCode).Flags & M_PREFETCH_FLAG;
192 bool isLoadOrPrefetch(MachineOpCode opCode) const {
193 return get(opCode).Flags & M_LOAD_FLAG
194 || get(opCode).Flags & M_PREFETCH_FLAG;
196 bool isStore(MachineOpCode opCode) const {
197 return get(opCode).Flags & M_STORE_FLAG;
199 bool isMemoryAccess(MachineOpCode opCode) const {
200 return get(opCode).Flags & M_LOAD_FLAG
201 || get(opCode).Flags & M_PREFETCH_FLAG
202 || get(opCode).Flags & M_STORE_FLAG;
204 bool isDummyPhiInstr(MachineOpCode opCode) const {
205 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
207 bool isPseudoInstr(MachineOpCode opCode) const {
208 return get(opCode).Flags & M_PSEUDO_FLAG;
210 bool isTwoAddrInstr(MachineOpCode opCode) const {
211 return get(opCode).Flags & M_2_ADDR_FLAG;
213 bool isTerminatorInstr(unsigned Opcode) const {
214 return get(Opcode).Flags & M_TERMINATOR_FLAG;
218 // Return true if the instruction is a register to register move and
219 // leave the source and dest operands in the passed parameters.
221 virtual bool isMoveInstr(const MachineInstr& MI,
223 unsigned& destReg) const {
227 // Check if an instruction can be issued before its operands are ready,
228 // or if a subsequent instruction that uses its result can be issued
229 // before the results are ready.
230 // Default to true since most instructions on many architectures allow this.
232 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
236 virtual bool hasResultInterlock(MachineOpCode opCode) const {
241 // Latencies for individual instructions and instruction pairs
243 virtual int minLatency(MachineOpCode opCode) const {
244 return get(opCode).latency;
247 virtual int maxLatency(MachineOpCode opCode) const {
248 return get(opCode).latency;
252 // Which operand holds an immediate constant? Returns -1 if none
254 virtual int getImmedConstantPos(MachineOpCode opCode) const {
255 return -1; // immediate position is machine specific, so say -1 == "none"
258 // Check if the specified constant fits in the immediate field
259 // of this machine instruction
261 virtual bool constantFitsInImmedField(MachineOpCode opCode,
262 int64_t intValue) const;
264 // Return the largest positive constant that can be held in the IMMED field
265 // of this machine instruction.
266 // isSignExtended is set to true if the value is sign-extended before use
267 // (this is true for all immediate fields in SPARC instructions).
268 // Return 0 if the instruction has no IMMED field.
270 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
271 bool &isSignExtended) const {
272 isSignExtended = get(opCode).immedIsSignExtended;
273 return get(opCode).maxImmedConst;
276 //-------------------------------------------------------------------------
277 // Queries about representation of LLVM quantities (e.g., constants)
278 //-------------------------------------------------------------------------
280 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
281 /// from memory into a register, i.e., cannot be set bitwise in register and
282 /// cannot use immediate fields of instructions. Note that this only makes
283 /// sense for primitive types.
285 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
287 // Test if this constant may not fit in the immediate field of the
288 // machine instructions (probably) generated for this instruction.
290 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
291 const Instruction* I) const {
292 return true; // safe but very conservative
296 /// createNOPinstr - returns the target's implementation of NOP, which is
297 /// usually a pseudo-instruction, implemented by a degenerate version of
298 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
300 virtual MachineInstr* createNOPinstr() const = 0;
302 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
303 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
304 /// more than one way to `do nothing' but only one canonical way to slack off.
306 virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
308 //-------------------------------------------------------------------------
309 // Code generation support for creating individual machine instructions
311 // WARNING: These methods are Sparc specific
313 //-------------------------------------------------------------------------
315 // Get certain common op codes for the current target. this and all the
316 // Create* methods below should be moved to a machine code generation class
318 virtual MachineOpCode getNOPOpCode() const { abort(); }
320 // Get the value of an integral constant in the form that must
321 // be put into the machine register. The specified constant is interpreted
322 // as (i.e., converted if necessary to) the specified destination type. The
323 // result is always returned as an uint64_t, since the representation of
324 // int64_t and uint64_t are identical. The argument can be any known const.
326 // isValidConstant is set to true if a valid constant was found.
328 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
330 const Type *destType,
331 bool &isValidConstant) const {
335 // Create an instruction sequence to put the constant `val' into
336 // the virtual register `dest'. `val' may be a Constant or a
337 // GlobalValue, viz., the constant address of a global variable or function.
338 // The generated instructions are returned in `mvec'.
339 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
340 // Symbolic constants or constants that must be accessed from memory
341 // are added to the constant pool via MachineFunction::get(F).
343 virtual void CreateCodeToLoadConst(const TargetMachine& target,
347 std::vector<MachineInstr*>& mvec,
348 MachineCodeForInstruction& mcfi) const {
352 // Create an instruction sequence to copy an integer value `val'
353 // to a floating point value `dest' by copying to memory and back.
354 // val must be an integral type. dest must be a Float or Double.
355 // The generated instructions are returned in `mvec'.
356 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
357 // Any stack space required is allocated via mcff.
359 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
363 std::vector<MachineInstr*>& mvec,
364 MachineCodeForInstruction& MI) const {
368 // Similarly, create an instruction sequence to copy an FP value
369 // `val' to an integer value `dest' by copying to memory and back.
370 // The generated instructions are returned in `mvec'.
371 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
372 // Any stack space required is allocated via mcff.
374 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
378 std::vector<MachineInstr*>& mvec,
379 MachineCodeForInstruction& MI) const {
383 // Create instruction(s) to copy src to dest, for arbitrary types
384 // The generated instructions are returned in `mvec'.
385 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
386 // Any stack space required is allocated via mcff.
388 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
392 std::vector<MachineInstr*>& mvec,
393 MachineCodeForInstruction& MI) const {
397 // Create instruction sequence to produce a sign-extended register value
398 // from an arbitrary sized value (sized in bits, not bytes).
399 // The generated instructions are appended to `mvec'.
400 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
401 // Any stack space required is allocated via mcff.
403 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
408 std::vector<MachineInstr*>& mvec,
409 MachineCodeForInstruction& MI) const {
413 // Create instruction sequence to produce a zero-extended register value
414 // from an arbitrary sized value (sized in bits, not bytes).
415 // The generated instructions are appended to `mvec'.
416 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
417 // Any stack space required is allocated via mcff.
419 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
423 unsigned srcSizeInBits,
424 std::vector<MachineInstr*>& mvec,
425 MachineCodeForInstruction& mcfi) const {
430 } // End llvm namespace