1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
23 class InstrItineraryData;
26 class MachineMemOperand;
30 class ScheduleHazardRecognizer;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
35 template<class T> class SmallVectorImpl;
38 //---------------------------------------------------------------------------
40 /// TargetInstrInfo - Interface to description of machine instruction set
42 class TargetInstrInfo {
43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
44 unsigned NumOpcodes; // Number of entries in the desc array
46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
50 virtual ~TargetInstrInfo();
52 unsigned getNumOpcodes() const { return NumOpcodes; }
54 /// get - Return the machine instruction descriptor that corresponds to the
55 /// specified instruction opcode.
57 const TargetInstrDesc &get(unsigned Opcode) const {
58 assert(Opcode < NumOpcodes && "Invalid opcode!");
59 return Descriptors[Opcode];
62 /// isTriviallyReMaterializable - Return true if the instruction is trivially
63 /// rematerializable, meaning it has no side effects and requires no operands
64 /// that aren't always available.
65 bool isTriviallyReMaterializable(const MachineInstr *MI,
66 AliasAnalysis *AA = 0) const {
67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
68 (MI->getDesc().isRematerializable() &&
69 (isReallyTriviallyReMaterializable(MI, AA) ||
70 isReallyTriviallyReMaterializableGeneric(MI, AA)));
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
76 /// specify whether the instruction is actually trivially rematerializable,
77 /// taking into consideration its operands. This predicate must return false
78 /// if the instruction has any side effects other than producing a value, or
79 /// if it requres any address registers that are not always available.
80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA) const {
86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
87 /// for which the M_REMATERIALIZABLE flag is set and the target hook
88 /// isReallyTriviallyReMaterializable returns false, this function does
89 /// target-independent tests to determine if the instruction is really
90 /// trivially rematerializable.
91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
92 AliasAnalysis *AA) const;
95 /// isMoveInstr - Return true if the instruction is a register to register
96 /// move and return the source and dest operands and their sub-register
97 /// indices by reference.
98 virtual bool isMoveInstr(const MachineInstr& MI,
99 unsigned& SrcReg, unsigned& DstReg,
100 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
104 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
105 /// extension instruction. That is, it's like a copy where it's legal for the
106 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
107 /// true, then it's expected the pre-extension value is available as a subreg
108 /// of the result register. This also returns the sub-register index in
110 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SubIdx) const {
116 /// isLoadFromStackSlot - If the specified machine instruction is a direct
117 /// load from a stack slot, return the virtual or physical register number of
118 /// the destination along with the FrameIndex of the loaded stack slot. If
119 /// not, return 0. This predicate must return 0 if the instruction has
120 /// any side effects other than loading from the stack slot.
121 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
122 int &FrameIndex) const {
126 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
127 /// stack locations as well. This uses a heuristic so it isn't
128 /// reliable for correctness.
129 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
130 int &FrameIndex) const {
134 /// hasLoadFromStackSlot - If the specified machine instruction has
135 /// a load from a stack slot, return true along with the FrameIndex
136 /// of the loaded stack slot and the machine mem operand containing
137 /// the reference. If not, return false. Unlike
138 /// isLoadFromStackSlot, this returns true for any instructions that
139 /// loads from the stack. This is just a hint, as some cases may be
141 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
142 const MachineMemOperand *&MMO,
143 int &FrameIndex) const {
147 /// isStoreToStackSlot - If the specified machine instruction is a direct
148 /// store to a stack slot, return the virtual or physical register number of
149 /// the source reg along with the FrameIndex of the loaded stack slot. If
150 /// not, return 0. This predicate must return 0 if the instruction has
151 /// any side effects other than storing to the stack slot.
152 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
153 int &FrameIndex) const {
157 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
158 /// stack locations as well. This uses a heuristic so it isn't
159 /// reliable for correctness.
160 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
161 int &FrameIndex) const {
165 /// hasStoreToStackSlot - If the specified machine instruction has a
166 /// store to a stack slot, return true along with the FrameIndex of
167 /// the loaded stack slot and the machine mem operand containing the
168 /// reference. If not, return false. Unlike isStoreToStackSlot,
169 /// this returns true for any instructions that stores to the
170 /// stack. This is just a hint, as some cases may be missed.
171 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
172 const MachineMemOperand *&MMO,
173 int &FrameIndex) const {
177 /// reMaterialize - Re-issue the specified 'original' instruction at the
178 /// specific location targeting a new destination register.
179 /// The register in Orig->getOperand(0).getReg() will be substituted by
180 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
182 virtual void reMaterialize(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator MI,
184 unsigned DestReg, unsigned SubIdx,
185 const MachineInstr *Orig,
186 const TargetRegisterInfo &TRI) const = 0;
188 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
189 /// two-addrss instruction inserted by two-address pass.
190 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
192 const TargetRegisterInfo &TRI) const {
196 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
197 /// MachineFunction::CloneMachineInstr(), but the target may update operands
198 /// that are required to be unique.
200 /// The instruction must be duplicable as indicated by isNotDuplicable().
201 virtual MachineInstr *duplicate(MachineInstr *Orig,
202 MachineFunction &MF) const = 0;
204 /// convertToThreeAddress - This method must be implemented by targets that
205 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
206 /// may be able to convert a two-address instruction into one or more true
207 /// three-address instructions on demand. This allows the X86 target (for
208 /// example) to convert ADD and SHL instructions into LEA instructions if they
209 /// would require register copies due to two-addressness.
211 /// This method returns a null pointer if the transformation cannot be
212 /// performed, otherwise it returns the last new instruction.
214 virtual MachineInstr *
215 convertToThreeAddress(MachineFunction::iterator &MFI,
216 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
220 /// commuteInstruction - If a target has any instructions that are
221 /// commutable but require converting to different instructions or making
222 /// non-trivial changes to commute them, this method can overloaded to do
223 /// that. The default implementation simply swaps the commutable operands.
224 /// If NewMI is false, MI is modified in place and returned; otherwise, a
225 /// new machine instruction is created and returned. Do not call this
226 /// method for a non-commutable instruction, but there may be some cases
227 /// where this method fails and returns null.
228 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
229 bool NewMI = false) const = 0;
231 /// findCommutedOpIndices - If specified MI is commutable, return the two
232 /// operand indices that would swap value. Return false if the instruction
233 /// is not in a form which this routine understands.
234 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
235 unsigned &SrcOpIdx2) const = 0;
237 /// produceSameValue - Return true if two machine instructions would produce
238 /// identical values. By default, this is only true when the two instructions
239 /// are deemed identical except for defs.
240 virtual bool produceSameValue(const MachineInstr *MI0,
241 const MachineInstr *MI1) const = 0;
243 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
244 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
245 /// implemented for a target). Upon success, this returns false and returns
246 /// with the following information in various cases:
248 /// 1. If this block ends with no branches (it just falls through to its succ)
249 /// just return false, leaving TBB/FBB null.
250 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
251 /// the destination block.
252 /// 3. If this block ends with a conditional branch and it falls through to a
253 /// successor block, it sets TBB to be the branch destination block and a
254 /// list of operands that evaluate the condition. These operands can be
255 /// passed to other TargetInstrInfo methods to create new branches.
256 /// 4. If this block ends with a conditional branch followed by an
257 /// unconditional branch, it returns the 'true' destination in TBB, the
258 /// 'false' destination in FBB, and a list of operands that evaluate the
259 /// condition. These operands can be passed to other TargetInstrInfo
260 /// methods to create new branches.
262 /// Note that RemoveBranch and InsertBranch must be implemented to support
263 /// cases where this method returns success.
265 /// If AllowModify is true, then this routine is allowed to modify the basic
266 /// block (e.g. delete instructions after the unconditional branch).
268 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
269 MachineBasicBlock *&FBB,
270 SmallVectorImpl<MachineOperand> &Cond,
271 bool AllowModify = false) const {
275 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
276 /// This is only invoked in cases where AnalyzeBranch returns success. It
277 /// returns the number of instructions that were removed.
278 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
279 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
283 /// InsertBranch - Insert branch code into the end of the specified
284 /// MachineBasicBlock. The operands to this method are the same as those
285 /// returned by AnalyzeBranch. This is only invoked in cases where
286 /// AnalyzeBranch returns success. It returns the number of instructions
289 /// It is also invoked by tail merging to add unconditional branches in
290 /// cases where AnalyzeBranch doesn't apply because there was no original
291 /// branch to analyze. At least this much must be implemented, else tail
292 /// merging needs to be disabled.
293 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
294 MachineBasicBlock *FBB,
295 const SmallVectorImpl<MachineOperand> &Cond,
297 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
301 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
302 /// after it, replacing it with an unconditional branch to NewDest. This is
303 /// used by the tail merging pass.
304 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
305 MachineBasicBlock *NewDest) const = 0;
307 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
308 /// block at the specified instruction (i.e. instruction would be the start
309 /// of a new basic block).
310 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MBBI) const {
315 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs"
316 /// of the specified basic block.
318 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
322 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
323 /// checks for the case where two basic blocks from true and false path
324 /// of a if-then-else (diamond) are predicated on mutally exclusive
327 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
328 MachineBasicBlock &FMBB, unsigned NumFInstrs) const {
332 /// isProfitableToDupForIfCvt - Return true if it's profitable for
333 /// if-converter to duplicate a specific number of instructions in the
334 /// specified MBB to enable if-conversion.
336 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs) const {
340 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
341 virtual void copyPhysReg(MachineBasicBlock &MBB,
342 MachineBasicBlock::iterator MI, DebugLoc DL,
343 unsigned DestReg, unsigned SrcReg,
344 bool KillSrc) const {
345 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
348 /// storeRegToStackSlot - Store the specified register of the given register
349 /// class to the specified stack frame index. The store instruction is to be
350 /// added to the given machine basic block before the specified machine
351 /// instruction. If isKill is true, the register operand is the last use and
352 /// must be marked kill.
353 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI,
355 unsigned SrcReg, bool isKill, int FrameIndex,
356 const TargetRegisterClass *RC,
357 const TargetRegisterInfo *TRI) const {
358 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
361 /// loadRegFromStackSlot - Load the specified register of the given register
362 /// class from the specified stack frame index. The load instruction is to be
363 /// added to the given machine basic block before the specified machine
365 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
366 MachineBasicBlock::iterator MI,
367 unsigned DestReg, int FrameIndex,
368 const TargetRegisterClass *RC,
369 const TargetRegisterInfo *TRI) const {
370 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
373 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
374 /// saved registers and returns true if it isn't possible / profitable to do
375 /// so by issuing a series of store instructions via
376 /// storeRegToStackSlot(). Returns false otherwise.
377 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator MI,
379 const std::vector<CalleeSavedInfo> &CSI,
380 const TargetRegisterInfo *TRI) const {
384 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
385 /// saved registers and returns true if it isn't possible / profitable to do
386 /// so by issuing a series of load instructions via loadRegToStackSlot().
387 /// Returns false otherwise.
388 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
389 MachineBasicBlock::iterator MI,
390 const std::vector<CalleeSavedInfo> &CSI,
391 const TargetRegisterInfo *TRI) const {
395 /// emitFrameIndexDebugValue - Emit a target-dependent form of
396 /// DBG_VALUE encoding the address of a frame index. Addresses would
397 /// normally be lowered the same way as other addresses on the target,
398 /// e.g. in load instructions. For targets that do not support this
399 /// the debug info is simply lost.
400 /// If you add this for a target you should handle this DBG_VALUE in the
401 /// target-specific AsmPrinter code as well; you will probably get invalid
402 /// assembly output if you don't.
403 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
411 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
412 /// slot into the specified machine instruction for the specified operand(s).
413 /// If this is possible, a new instruction is returned with the specified
414 /// operand folded, otherwise NULL is returned.
415 /// The new instruction is inserted before MI, and the client is responsible
416 /// for removing the old instruction.
417 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
418 const SmallVectorImpl<unsigned> &Ops,
419 int FrameIndex) const;
421 /// foldMemoryOperand - Same as the previous version except it allows folding
422 /// of any load and store from / to any address, not just from a specific
424 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
425 const SmallVectorImpl<unsigned> &Ops,
426 MachineInstr* LoadMI) const;
429 /// foldMemoryOperandImpl - Target-dependent implementation for
430 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
431 /// take care of adding a MachineMemOperand to the newly created instruction.
432 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
434 const SmallVectorImpl<unsigned> &Ops,
435 int FrameIndex) const {
439 /// foldMemoryOperandImpl - Target-dependent implementation for
440 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
441 /// take care of adding a MachineMemOperand to the newly created instruction.
442 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
444 const SmallVectorImpl<unsigned> &Ops,
445 MachineInstr* LoadMI) const {
450 /// canFoldMemoryOperand - Returns true for the specified load / store if
451 /// folding is possible.
453 bool canFoldMemoryOperand(const MachineInstr *MI,
454 const SmallVectorImpl<unsigned> &Ops) const =0;
456 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
457 /// a store or a load and a store into two or more instruction. If this is
458 /// possible, returns true as well as the new instructions by reference.
459 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
460 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
461 SmallVectorImpl<MachineInstr*> &NewMIs) const{
465 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
466 SmallVectorImpl<SDNode*> &NewNodes) const {
470 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
471 /// instruction after load / store are unfolded from an instruction of the
472 /// specified opcode. It returns zero if the specified unfolding is not
473 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
474 /// index of the operand which will hold the register holding the loaded
476 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
477 bool UnfoldLoad, bool UnfoldStore,
478 unsigned *LoadRegIndex = 0) const {
482 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
483 /// to determine if two loads are loading from the same base address. It
484 /// should only return true if the base pointers are the same and the
485 /// only differences between the two addresses are the offset. It also returns
486 /// the offsets by reference.
487 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
488 int64_t &Offset1, int64_t &Offset2) const {
492 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
493 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
494 /// be scheduled togther. On some targets if two loads are loading from
495 /// addresses in the same cache line, it's better if they are scheduled
496 /// together. This function takes two integers that represent the load offsets
497 /// from the common base address. It returns true if it decides it's desirable
498 /// to schedule the two loads together. "NumLoads" is the number of loads that
499 /// have already been scheduled after Load1.
500 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
501 int64_t Offset1, int64_t Offset2,
502 unsigned NumLoads) const {
506 /// ReverseBranchCondition - Reverses the branch condition of the specified
507 /// condition list, returning false on success and true if it cannot be
510 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
514 /// insertNoop - Insert a noop into the instruction stream at the specified
516 virtual void insertNoop(MachineBasicBlock &MBB,
517 MachineBasicBlock::iterator MI) const;
520 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
521 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
522 // Default to just using 'nop' string.
526 /// isPredicated - Returns true if the instruction is already predicated.
528 virtual bool isPredicated(const MachineInstr *MI) const {
532 /// isUnpredicatedTerminator - Returns true if the instruction is a
533 /// terminator instruction that has not been predicated.
534 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
536 /// PredicateInstruction - Convert the instruction into a predicated
537 /// instruction. It returns true if the operation was successful.
539 bool PredicateInstruction(MachineInstr *MI,
540 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
542 /// SubsumesPredicate - Returns true if the first specified predicate
543 /// subsumes the second, e.g. GE subsumes GT.
545 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
546 const SmallVectorImpl<MachineOperand> &Pred2) const {
550 /// DefinesPredicate - If the specified instruction defines any predicate
551 /// or condition code register(s) used for predication, returns true as well
552 /// as the definition predicate(s) by reference.
553 virtual bool DefinesPredicate(MachineInstr *MI,
554 std::vector<MachineOperand> &Pred) const {
558 /// isPredicable - Return true if the specified instruction can be predicated.
559 /// By default, this returns true for every instruction with a
560 /// PredicateOperand.
561 virtual bool isPredicable(MachineInstr *MI) const {
562 return MI->getDesc().isPredicable();
565 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
566 /// instruction that defines the specified register class.
567 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
571 /// isSchedulingBoundary - Test if the given instruction should be
572 /// considered a scheduling boundary. This primarily includes labels and
574 virtual bool isSchedulingBoundary(const MachineInstr *MI,
575 const MachineBasicBlock *MBB,
576 const MachineFunction &MF) const = 0;
578 /// GetInstSize - Returns the size of the specified Instruction.
580 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
581 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
585 /// GetFunctionSizeInBytes - Returns the size of the specified
588 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
590 /// Measure the specified inline asm to determine an approximation of its
592 virtual unsigned getInlineAsmLength(const char *Str,
593 const MCAsmInfo &MAI) const;
595 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer
596 /// to use for this target when scheduling the machine instructions after
597 /// register allocation.
598 virtual ScheduleHazardRecognizer*
599 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0;
602 /// TargetInstrInfoImpl - This is the default implementation of
603 /// TargetInstrInfo, which just provides a couple of default implementations
604 /// for various methods. This separated out because it is implemented in
605 /// libcodegen, not in libtarget.
606 class TargetInstrInfoImpl : public TargetInstrInfo {
608 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
609 : TargetInstrInfo(desc, NumOpcodes) {}
611 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
612 MachineBasicBlock *NewDest) const;
613 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
614 bool NewMI = false) const;
615 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
616 unsigned &SrcOpIdx2) const;
617 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
618 const SmallVectorImpl<unsigned> &Ops) const;
619 virtual bool PredicateInstruction(MachineInstr *MI,
620 const SmallVectorImpl<MachineOperand> &Pred) const;
621 virtual void reMaterialize(MachineBasicBlock &MBB,
622 MachineBasicBlock::iterator MI,
623 unsigned DestReg, unsigned SubReg,
624 const MachineInstr *Orig,
625 const TargetRegisterInfo &TRI) const;
626 virtual MachineInstr *duplicate(MachineInstr *Orig,
627 MachineFunction &MF) const;
628 virtual bool produceSameValue(const MachineInstr *MI0,
629 const MachineInstr *MI1) const;
630 virtual bool isSchedulingBoundary(const MachineInstr *MI,
631 const MachineBasicBlock *MBB,
632 const MachineFunction &MF) const;
633 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
635 virtual ScheduleHazardRecognizer *
636 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
639 } // End llvm namespace