1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //===----------------------------------------------------------------------===//
36 // Data types used to define information about a single machine instruction
37 //===----------------------------------------------------------------------===//
39 typedef short MachineOpCode;
41 //===----------------------------------------------------------------------===//
42 // struct TargetInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
47 const unsigned M_BRANCH_FLAG = 1 << 0;
48 const unsigned M_CALL_FLAG = 1 << 1;
49 const unsigned M_RET_FLAG = 1 << 2;
50 const unsigned M_BARRIER_FLAG = 1 << 3;
51 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
53 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
54 /// from memory. This should only be set on instructions that load a value from
55 /// memory and return it in their only virtual register definition.
56 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
58 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
59 /// modify memory. Instructions with this flag set are not necessarily simple
60 /// store instructions, they may store a modified value based on their operands,
61 /// or may not actually modify anything, for example.
62 const unsigned M_MAY_STORE_FLAG = 1 << 6;
64 const unsigned M_INDIRECT_FLAG = 1 << 7;
65 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
67 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
68 // changed into a 3-address instruction if the first two operands cannot be
69 // assigned to the same register. The target must implement the
70 // TargetInstrInfo::convertToThreeAddress method for this instruction.
71 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
73 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
74 // Z), which produces the same result if Y and Z are exchanged.
75 const unsigned M_COMMUTABLE = 1 << 10;
77 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
78 // block? Typically this is things like return and branch instructions.
79 // Various passes use this to insert code into the bottom of a basic block, but
80 // before control flow occurs.
81 const unsigned M_TERMINATOR_FLAG = 1 << 11;
83 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
84 // insertion support when the DAG scheduler is inserting it into a machine basic
86 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
88 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
89 // operands in addition to the minimum number operands specified.
90 const unsigned M_VARIABLE_OPS = 1 << 13;
92 // M_PREDICABLE - Set if this instruction has a predicate operand that
93 // controls execution. It may be set to 'always'.
94 const unsigned M_PREDICABLE = 1 << 14;
96 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
97 // at any time, e.g. constant generation, load from constant pool.
98 const unsigned M_REMATERIALIZIBLE = 1 << 15;
100 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
101 // (e.g. instructions with unique labels attached).
102 const unsigned M_NOT_DUPLICABLE = 1 << 16;
104 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
105 // ARM instructions which can set condition code if 's' bit is set.
106 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
108 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
109 // are not captured by any operands of the instruction or other flags, and when
110 // *all* instances of the instruction of that opcode have no side effects.
112 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
113 // both! If neither flag is set, then the instruction *always* has side effects.
114 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
116 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
117 // side effects. The virtual method "isReallySideEffectFree" is called to
118 // determine this. Load instructions are an example of where this is useful. In
119 // general, loads always have side effects. However, loads from constant pools
120 // don't. We let the specific back end make this determination.
122 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
123 // both! If neither flag is set, then the instruction *always* has side effects.
124 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
127 //===----------------------------------------------------------------------===//
128 // Machine operand flags
129 //===----------------------------------------------------------------------===//
132 // Operand constraints: only "tied_to" for now.
133 enum OperandConstraint {
134 TIED_TO = 0 // Must be allocated the same register as.
137 /// OperandFlags - These are flags set on operands, but should be considered
138 /// private, all access should go through the TargetOperandInfo accessors.
139 /// See the accessors for a description of what these are.
141 LookupPtrRegClass = 1 << 0,
147 /// TargetOperandInfo - This holds information about one operand of a machine
148 /// instruction, indicating the register class for register operands, etc.
150 class TargetOperandInfo {
152 /// RegClass - This specifies the register class enumeration of the operand
153 /// if the operand is a register. If not, this contains 0.
154 unsigned short RegClass;
155 unsigned short Flags;
156 /// Lower 16 bits are used to specify which constraints are set. The higher 16
157 /// bits are used to specify the value of constraints (4 bits each).
158 unsigned int Constraints;
159 /// Currently no other information.
161 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
162 /// requires a callback to look up its register class.
163 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
165 /// isPredicate - Set if this is one of the operands that made up of
166 /// the predicate operand that controls an M_PREDICATED instruction.
167 bool isPredicate() const { return Flags & TOI::Predicate; }
169 /// isOptionalDef - Set if this operand is a optional def.
171 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
175 class TargetInstrDescriptor {
177 unsigned short Opcode; // The opcode.
178 unsigned short numOperands; // Num of args (may be more if variable_ops).
179 unsigned short numDefs; // Num of args that are definitions.
180 const char * Name; // Assembly language mnemonic for the opcode.
181 unsigned SchedClass; // enum identifying instr sched class
182 unsigned Flags; // flags identifying machine instr class
183 unsigned TSFlags; // Target Specific Flag values
184 const unsigned *ImplicitUses; // Registers implicitly read by this instr
185 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
186 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
188 /// getOperandConstraint - Returns the value of the specific constraint if
189 /// it is set. Returns -1 if it is not set.
190 int getOperandConstraint(unsigned OpNum,
191 TOI::OperandConstraint Constraint) const {
192 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
193 "Invalid operand # of TargetInstrInfo");
194 if (OpNum < numOperands &&
195 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
196 unsigned Pos = 16 + Constraint * 4;
197 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
202 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
203 /// dest operand. Returns -1 if there isn't one.
204 int findTiedToSrcOperand(unsigned OpNum) const;
206 bool isCall() const {
207 return Flags & M_CALL_FLAG;
210 bool isBranch() const {
211 return Flags & M_BRANCH_FLAG;
214 bool isTerminator() const {
215 return Flags & M_TERMINATOR_FLAG;
218 bool isIndirectBranch() const {
219 return Flags & M_INDIRECT_FLAG;
222 bool isPredicable() const {
223 return Flags & M_PREDICABLE;
226 bool isNotDuplicable() const {
227 return Flags & M_NOT_DUPLICABLE;
232 /// isSimpleLoad - Return true for instructions that are simple loads from
233 /// memory. This should only be set on instructions that load a value from
234 /// memory and return it in their only virtual register definition.
235 /// Instructions that return a value loaded from memory and then modified in
236 /// some way should not return true for this.
237 bool isSimpleLoad() const {
238 return Flags & M_SIMPLE_LOAD_FLAG;
241 /// mayStore - Return true if this instruction could possibly modify memory.
242 /// Instructions with this flag set are not necessarily simple store
243 /// instructions, they may store a modified value based on their operands, or
244 /// may not actually modify anything, for example.
245 bool mayStore() const {
246 return Flags & M_MAY_STORE_FLAG;
249 /// isBarrier - Returns true if the specified instruction stops control flow
250 /// from executing the instruction immediately following it. Examples include
251 /// unconditional branches and return instructions.
252 bool isBarrier() const {
253 return Flags & M_BARRIER_FLAG;
256 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
257 /// which must be filled by the code generator.
258 bool hasDelaySlot() const {
259 return Flags & M_DELAY_SLOT_FLAG;
262 unsigned getSchedClass() const {
268 //---------------------------------------------------------------------------
270 /// TargetInstrInfo - Interface to description of machine instructions
272 class TargetInstrInfo {
273 const TargetInstrDescriptor* desc; // raw array to allow static init'n
274 unsigned NumOpcodes; // number of entries in the desc array
275 unsigned numRealOpCodes; // number of non-dummy op codes
277 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
278 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
280 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
281 virtual ~TargetInstrInfo();
283 // Invariant opcodes: All instruction sets have these as their low opcodes.
292 unsigned getNumOpcodes() const { return NumOpcodes; }
294 /// get - Return the machine instruction descriptor that corresponds to the
295 /// specified instruction opcode.
297 const TargetInstrDescriptor& get(unsigned Opcode) const {
298 assert(Opcode < NumOpcodes);
302 const char *getName(unsigned Opcode) const {
303 return get(Opcode).Name;
306 int getNumOperands(unsigned Opcode) const {
307 return get(Opcode).numOperands;
310 int getNumDefs(unsigned Opcode) const {
311 return get(Opcode).numDefs;
314 const unsigned *getImplicitUses(unsigned Opcode) const {
315 return get(Opcode).ImplicitUses;
318 const unsigned *getImplicitDefs(unsigned Opcode) const {
319 return get(Opcode).ImplicitDefs;
324 // Query instruction class flags according to the machine-independent
325 // flags listed above.
327 bool isReturn(unsigned Opcode) const {
328 return get(Opcode).Flags & M_RET_FLAG;
331 bool isCommutableInstr(unsigned Opcode) const {
332 return get(Opcode).Flags & M_COMMUTABLE;
335 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
336 /// custom insertion support when the DAG scheduler is inserting it into a
337 /// machine basic block.
338 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
339 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
342 bool hasVariableOperands(unsigned Opcode) const {
343 return get(Opcode).Flags & M_VARIABLE_OPS;
346 bool hasOptionalDef(unsigned Opcode) const {
347 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
350 /// isTriviallyReMaterializable - Return true if the instruction is trivially
351 /// rematerializable, meaning it has no side effects and requires no operands
352 /// that aren't always available.
353 bool isTriviallyReMaterializable(MachineInstr *MI) const {
354 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
355 isReallyTriviallyReMaterializable(MI);
358 /// hasUnmodelledSideEffects - Returns true if the instruction has side
359 /// effects that are not captured by any operands of the instruction or other
361 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
362 const TargetInstrDescriptor *TID = MI->getDesc();
363 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
364 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
365 return !isReallySideEffectFree(MI); // May have side effects
368 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
369 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
370 /// instruction itself is actually trivially rematerializable, considering
371 /// its operands. This is used for targets that have instructions that are
372 /// only trivially rematerializable for specific uses. This predicate must
373 /// return false if the instruction has any side effects other than
374 /// producing a value, or if it requres any address registers that are not
375 /// always available.
376 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
380 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
381 /// method is called to determine if the specific instance of this
382 /// instruction has side effects. This is useful in cases of instructions,
383 /// like loads, which generally always have side effects. A load from a
384 /// constant pool doesn't have side effects, though. So we need to
385 /// differentiate it from the general case.
386 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
390 /// getOperandConstraint - Returns the value of the specific constraint if
391 /// it is set. Returns -1 if it is not set.
392 int getOperandConstraint(unsigned Opcode, unsigned OpNum,
393 TOI::OperandConstraint Constraint) const {
394 return get(Opcode).getOperandConstraint(OpNum, Constraint);
397 /// Return true if the instruction is a register to register move
398 /// and leave the source and dest operands in the passed parameters.
399 virtual bool isMoveInstr(const MachineInstr& MI,
401 unsigned& destReg) const {
405 /// isLoadFromStackSlot - If the specified machine instruction is a direct
406 /// load from a stack slot, return the virtual or physical register number of
407 /// the destination along with the FrameIndex of the loaded stack slot. If
408 /// not, return 0. This predicate must return 0 if the instruction has
409 /// any side effects other than loading from the stack slot.
410 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
414 /// isStoreToStackSlot - If the specified machine instruction is a direct
415 /// store to a stack slot, return the virtual or physical register number of
416 /// the source reg along with the FrameIndex of the loaded stack slot. If
417 /// not, return 0. This predicate must return 0 if the instruction has
418 /// any side effects other than storing to the stack slot.
419 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
423 /// convertToThreeAddress - This method must be implemented by targets that
424 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
425 /// may be able to convert a two-address instruction into one or more true
426 /// three-address instructions on demand. This allows the X86 target (for
427 /// example) to convert ADD and SHL instructions into LEA instructions if they
428 /// would require register copies due to two-addressness.
430 /// This method returns a null pointer if the transformation cannot be
431 /// performed, otherwise it returns the last new instruction.
433 virtual MachineInstr *
434 convertToThreeAddress(MachineFunction::iterator &MFI,
435 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
439 /// commuteInstruction - If a target has any instructions that are commutable,
440 /// but require converting to a different instruction or making non-trivial
441 /// changes to commute them, this method can overloaded to do this. The
442 /// default implementation of this method simply swaps the first two operands
443 /// of MI and returns it.
445 /// If a target wants to make more aggressive changes, they can construct and
446 /// return a new machine instruction. If an instruction cannot commute, it
447 /// can also return null.
449 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
451 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
452 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
453 /// implemented for a target). Upon success, this returns false and returns
454 /// with the following information in various cases:
456 /// 1. If this block ends with no branches (it just falls through to its succ)
457 /// just return false, leaving TBB/FBB null.
458 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
459 /// the destination block.
460 /// 3. If this block ends with an conditional branch and it falls through to
461 /// an successor block, it sets TBB to be the branch destination block and a
462 /// list of operands that evaluate the condition. These
463 /// operands can be passed to other TargetInstrInfo methods to create new
465 /// 4. If this block ends with an conditional branch and an unconditional
466 /// block, it returns the 'true' destination in TBB, the 'false' destination
467 /// in FBB, and a list of operands that evaluate the condition. These
468 /// operands can be passed to other TargetInstrInfo methods to create new
471 /// Note that RemoveBranch and InsertBranch must be implemented to support
472 /// cases where this method returns success.
474 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
475 MachineBasicBlock *&FBB,
476 std::vector<MachineOperand> &Cond) const {
480 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
481 /// this is only invoked in cases where AnalyzeBranch returns success. It
482 /// returns the number of instructions that were removed.
483 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
484 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
488 /// InsertBranch - Insert a branch into the end of the specified
489 /// MachineBasicBlock. This operands to this method are the same as those
490 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
491 /// returns success and when an unconditional branch (TBB is non-null, FBB is
492 /// null, Cond is empty) needs to be inserted. It returns the number of
493 /// instructions inserted.
494 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
495 MachineBasicBlock *FBB,
496 const std::vector<MachineOperand> &Cond) const {
497 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
501 /// copyRegToReg - Add a copy between a pair of registers
502 virtual void copyRegToReg(MachineBasicBlock &MBB,
503 MachineBasicBlock::iterator MI,
504 unsigned DestReg, unsigned SrcReg,
505 const TargetRegisterClass *DestRC,
506 const TargetRegisterClass *SrcRC) const {
507 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
510 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
511 MachineBasicBlock::iterator MI,
512 unsigned SrcReg, bool isKill, int FrameIndex,
513 const TargetRegisterClass *RC) const {
514 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
517 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
518 SmallVectorImpl<MachineOperand> &Addr,
519 const TargetRegisterClass *RC,
520 SmallVectorImpl<MachineInstr*> &NewMIs) const {
521 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
524 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
525 MachineBasicBlock::iterator MI,
526 unsigned DestReg, int FrameIndex,
527 const TargetRegisterClass *RC) const {
528 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
531 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
532 SmallVectorImpl<MachineOperand> &Addr,
533 const TargetRegisterClass *RC,
534 SmallVectorImpl<MachineInstr*> &NewMIs) const {
535 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
538 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
539 /// saved registers and returns true if it isn't possible / profitable to do
540 /// so by issuing a series of store instructions via
541 /// storeRegToStackSlot(). Returns false otherwise.
542 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator MI,
544 const std::vector<CalleeSavedInfo> &CSI) const {
548 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
549 /// saved registers and returns true if it isn't possible / profitable to do
550 /// so by issuing a series of load instructions via loadRegToStackSlot().
551 /// Returns false otherwise.
552 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
553 MachineBasicBlock::iterator MI,
554 const std::vector<CalleeSavedInfo> &CSI) const {
558 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
559 /// slot into the specified machine instruction for the specified operand(s).
560 /// If this is possible, a new instruction is returned with the specified
561 /// operand folded, otherwise NULL is returned. The client is responsible for
562 /// removing the old instruction and adding the new one in the instruction
564 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
565 SmallVectorImpl<unsigned> &Ops,
566 int FrameIndex) const {
570 /// foldMemoryOperand - Same as the previous version except it allows folding
571 /// of any load and store from / to any address, not just from a specific
573 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
574 SmallVectorImpl<unsigned> &Ops,
575 MachineInstr* LoadMI) const {
579 /// canFoldMemoryOperand - Returns true if the specified load / store is
580 /// folding is possible.
582 bool canFoldMemoryOperand(MachineInstr *MI,
583 SmallVectorImpl<unsigned> &Ops) const{
587 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
588 /// a store or a load and a store into two or more instruction. If this is
589 /// possible, returns true as well as the new instructions by reference.
590 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
591 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
592 SmallVectorImpl<MachineInstr*> &NewMIs) const{
596 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
597 SmallVectorImpl<SDNode*> &NewNodes) const {
601 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
602 /// instruction after load / store are unfolded from an instruction of the
603 /// specified opcode. It returns zero if the specified unfolding is not
605 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
606 bool UnfoldLoad, bool UnfoldStore) const {
610 /// BlockHasNoFallThrough - Return true if the specified block does not
611 /// fall-through into its successor block. This is primarily used when a
612 /// branch is unanalyzable. It is useful for things like unconditional
613 /// indirect branches (jump tables).
614 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
618 /// ReverseBranchCondition - Reverses the branch condition of the specified
619 /// condition list, returning false on success and true if it cannot be
621 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
625 /// insertNoop - Insert a noop into the instruction stream at the specified
627 virtual void insertNoop(MachineBasicBlock &MBB,
628 MachineBasicBlock::iterator MI) const {
629 assert(0 && "Target didn't implement insertNoop!");
633 /// isPredicated - Returns true if the instruction is already predicated.
635 virtual bool isPredicated(const MachineInstr *MI) const {
639 /// isUnpredicatedTerminator - Returns true if the instruction is a
640 /// terminator instruction that has not been predicated.
641 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
643 /// PredicateInstruction - Convert the instruction into a predicated
644 /// instruction. It returns true if the operation was successful.
646 bool PredicateInstruction(MachineInstr *MI,
647 const std::vector<MachineOperand> &Pred) const = 0;
649 /// SubsumesPredicate - Returns true if the first specified predicate
650 /// subsumes the second, e.g. GE subsumes GT.
652 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
653 const std::vector<MachineOperand> &Pred2) const {
657 /// DefinesPredicate - If the specified instruction defines any predicate
658 /// or condition code register(s) used for predication, returns true as well
659 /// as the definition predicate(s) by reference.
660 virtual bool DefinesPredicate(MachineInstr *MI,
661 std::vector<MachineOperand> &Pred) const {
665 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
667 virtual const TargetRegisterClass *getPointerRegClass() const {
668 assert(0 && "Target didn't implement getPointerRegClass!");
670 return 0; // Must return a value in order to compile with VS 2005
674 /// TargetInstrInfoImpl - This is the default implementation of
675 /// TargetInstrInfo, which just provides a couple of default implementations
676 /// for various methods. This separated out because it is implemented in
677 /// libcodegen, not in libtarget.
678 class TargetInstrInfoImpl : public TargetInstrInfo {
680 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
681 : TargetInstrInfo(desc, NumOpcodes) {}
683 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
684 virtual bool PredicateInstruction(MachineInstr *MI,
685 const std::vector<MachineOperand> &Pred) const;
689 } // End llvm namespace