1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instruction set
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
59 unsigned getNumOpcodes() const { return NumOpcodes; }
61 /// get - Return the machine instruction descriptor that corresponds to the
62 /// specified instruction opcode.
64 const TargetInstrDesc &get(unsigned Opcode) const {
65 assert(Opcode < NumOpcodes && "Invalid opcode!");
66 return Descriptors[Opcode];
69 /// isTriviallyReMaterializable - Return true if the instruction is trivially
70 /// rematerializable, meaning it has no side effects and requires no operands
71 /// that aren't always available.
72 bool isTriviallyReMaterializable(const MachineInstr *MI) const {
73 return MI->getDesc().isRematerializable() &&
74 isReallyTriviallyReMaterializable(MI);
78 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
79 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
80 /// instruction itself is actually trivially rematerializable, considering
81 /// its operands. This is used for targets that have instructions that are
82 /// only trivially rematerializable for specific uses. This predicate must
83 /// return false if the instruction has any side effects other than
84 /// producing a value, or if it requres any address registers that are not
86 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
91 /// Return true if the instruction is a register to register move and return
92 /// the source and dest operands and their sub-register indices by reference.
93 virtual bool isMoveInstr(const MachineInstr& MI,
94 unsigned& SrcReg, unsigned& DstReg,
95 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
99 /// isLoadFromStackSlot - If the specified machine instruction is a direct
100 /// load from a stack slot, return the virtual or physical register number of
101 /// the destination along with the FrameIndex of the loaded stack slot. If
102 /// not, return 0. This predicate must return 0 if the instruction has
103 /// any side effects other than loading from the stack slot.
104 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
105 int &FrameIndex) const {
109 /// isStoreToStackSlot - If the specified machine instruction is a direct
110 /// store to a stack slot, return the virtual or physical register number of
111 /// the source reg along with the FrameIndex of the loaded stack slot. If
112 /// not, return 0. This predicate must return 0 if the instruction has
113 /// any side effects other than storing to the stack slot.
114 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
115 int &FrameIndex) const {
119 /// reMaterialize - Re-issue the specified 'original' instruction at the
120 /// specific location targeting a new destination register.
121 virtual void reMaterialize(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MI,
124 const MachineInstr *Orig) const = 0;
126 /// isInvariantLoad - Return true if the specified instruction (which is
127 /// marked mayLoad) is loading from a location whose value is invariant across
128 /// the function. For example, loading a value from the constant pool or from
129 /// from the argument area of a function if it does not change. This should
130 /// only return true of *all* loads the instruction does are invariant (if it
131 /// does multiple loads).
132 virtual bool isInvariantLoad(const MachineInstr *MI) const {
136 /// convertToThreeAddress - This method must be implemented by targets that
137 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
138 /// may be able to convert a two-address instruction into one or more true
139 /// three-address instructions on demand. This allows the X86 target (for
140 /// example) to convert ADD and SHL instructions into LEA instructions if they
141 /// would require register copies due to two-addressness.
143 /// This method returns a null pointer if the transformation cannot be
144 /// performed, otherwise it returns the last new instruction.
146 virtual MachineInstr *
147 convertToThreeAddress(MachineFunction::iterator &MFI,
148 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
152 /// commuteInstruction - If a target has any instructions that are commutable,
153 /// but require converting to a different instruction or making non-trivial
154 /// changes to commute them, this method can overloaded to do this. The
155 /// default implementation of this method simply swaps the first two operands
156 /// of MI and returns it.
158 /// If a target wants to make more aggressive changes, they can construct and
159 /// return a new machine instruction. If an instruction cannot commute, it
160 /// can also return null.
162 /// If NewMI is true, then a new machine instruction must be created.
164 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
165 bool NewMI = false) const = 0;
167 /// CommuteChangesDestination - Return true if commuting the specified
168 /// instruction will also changes the destination operand. Also return the
169 /// current operand index of the would be new destination register by
170 /// reference. This can happen when the commutable instruction is also a
171 /// two-address instruction.
172 virtual bool CommuteChangesDestination(MachineInstr *MI,
173 unsigned &OpIdx) const = 0;
175 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
176 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
177 /// implemented for a target). Upon success, this returns false and returns
178 /// with the following information in various cases:
180 /// 1. If this block ends with no branches (it just falls through to its succ)
181 /// just return false, leaving TBB/FBB null.
182 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
183 /// the destination block.
184 /// 3. If this block ends with an conditional branch and it falls through to
185 /// an successor block, it sets TBB to be the branch destination block and a
186 /// list of operands that evaluate the condition. These
187 /// operands can be passed to other TargetInstrInfo methods to create new
189 /// 4. If this block ends with an conditional branch and an unconditional
190 /// block, it returns the 'true' destination in TBB, the 'false' destination
191 /// in FBB, and a list of operands that evaluate the condition. These
192 /// operands can be passed to other TargetInstrInfo methods to create new
195 /// Note that RemoveBranch and InsertBranch must be implemented to support
196 /// cases where this method returns success.
198 /// If AllowModify is true, then this routine is allowed to modify the basic
199 /// block (e.g. delete instructions after the unconditional branch).
201 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify = false) const {
208 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
209 /// This is only invoked in cases where AnalyzeBranch returns success. It
210 /// returns the number of instructions that were removed.
211 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
212 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
216 /// InsertBranch - Insert a branch into the end of the specified
217 /// MachineBasicBlock. This operands to this method are the same as those
218 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
219 /// returns success and when an unconditional branch (TBB is non-null, FBB is
220 /// null, Cond is empty) needs to be inserted. It returns the number of
221 /// instructions inserted.
222 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
223 MachineBasicBlock *FBB,
224 const SmallVectorImpl<MachineOperand> &Cond) const {
225 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
229 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
230 /// returns false if the target does not how to copy between the specified
232 virtual bool copyRegToReg(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator MI,
234 unsigned DestReg, unsigned SrcReg,
235 const TargetRegisterClass *DestRC,
236 const TargetRegisterClass *SrcRC) const {
237 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
241 /// storeRegToStackSlot - Store the specified register of the given register
242 /// class to the specified stack frame index. The store instruction is to be
243 /// added to the given machine basic block before the specified machine
244 /// instruction. If isKill is true, the register operand is the last use and
245 /// must be marked kill.
246 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
247 MachineBasicBlock::iterator MI,
248 unsigned SrcReg, bool isKill, int FrameIndex,
249 const TargetRegisterClass *RC) const {
250 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
253 /// storeRegToAddr - Store the specified register of the given register class
254 /// to the specified address. The store instruction is to be added to the
255 /// given machine basic block before the specified machine instruction. If
256 /// isKill is true, the register operand is the last use and must be marked
258 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
259 SmallVectorImpl<MachineOperand> &Addr,
260 const TargetRegisterClass *RC,
261 SmallVectorImpl<MachineInstr*> &NewMIs) const {
262 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
265 /// loadRegFromStackSlot - Load the specified register of the given register
266 /// class from the specified stack frame index. The load instruction is to be
267 /// added to the given machine basic block before the specified machine
269 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 unsigned DestReg, int FrameIndex,
272 const TargetRegisterClass *RC) const {
273 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
276 /// loadRegFromAddr - Load the specified register of the given register class
277 /// class from the specified address. The load instruction is to be added to
278 /// the given machine basic block before the specified machine instruction.
279 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
280 SmallVectorImpl<MachineOperand> &Addr,
281 const TargetRegisterClass *RC,
282 SmallVectorImpl<MachineInstr*> &NewMIs) const {
283 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
286 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
287 /// saved registers and returns true if it isn't possible / profitable to do
288 /// so by issuing a series of store instructions via
289 /// storeRegToStackSlot(). Returns false otherwise.
290 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator MI,
292 const std::vector<CalleeSavedInfo> &CSI) const {
296 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
297 /// saved registers and returns true if it isn't possible / profitable to do
298 /// so by issuing a series of load instructions via loadRegToStackSlot().
299 /// Returns false otherwise.
300 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
301 MachineBasicBlock::iterator MI,
302 const std::vector<CalleeSavedInfo> &CSI) const {
306 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
307 /// slot into the specified machine instruction for the specified operand(s).
308 /// If this is possible, a new instruction is returned with the specified
309 /// operand folded, otherwise NULL is returned. The client is responsible for
310 /// removing the old instruction and adding the new one in the instruction
312 MachineInstr* foldMemoryOperand(MachineFunction &MF,
314 const SmallVectorImpl<unsigned> &Ops,
315 int FrameIndex) const;
317 /// foldMemoryOperand - Same as the previous version except it allows folding
318 /// of any load and store from / to any address, not just from a specific
320 MachineInstr* foldMemoryOperand(MachineFunction &MF,
322 const SmallVectorImpl<unsigned> &Ops,
323 MachineInstr* LoadMI) const;
326 /// foldMemoryOperandImpl - Target-dependent implementation for
327 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
328 /// take care of adding a MachineMemOperand to the newly created instruction.
329 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
331 const SmallVectorImpl<unsigned> &Ops,
332 int FrameIndex) const {
336 /// foldMemoryOperandImpl - Target-dependent implementation for
337 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
338 /// take care of adding a MachineMemOperand to the newly created instruction.
339 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
341 const SmallVectorImpl<unsigned> &Ops,
342 MachineInstr* LoadMI) const {
347 /// canFoldMemoryOperand - Returns true for the specified load / store if
348 /// folding is possible.
350 bool canFoldMemoryOperand(const MachineInstr *MI,
351 const SmallVectorImpl<unsigned> &Ops) const {
355 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
356 /// a store or a load and a store into two or more instruction. If this is
357 /// possible, returns true as well as the new instructions by reference.
358 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
359 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
360 SmallVectorImpl<MachineInstr*> &NewMIs) const{
364 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
365 SmallVectorImpl<SDNode*> &NewNodes) const {
369 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
370 /// instruction after load / store are unfolded from an instruction of the
371 /// specified opcode. It returns zero if the specified unfolding is not
373 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
374 bool UnfoldLoad, bool UnfoldStore) const {
378 /// BlockHasNoFallThrough - Return true if the specified block does not
379 /// fall-through into its successor block. This is primarily used when a
380 /// branch is unanalyzable. It is useful for things like unconditional
381 /// indirect branches (jump tables).
382 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
386 /// ReverseBranchCondition - Reverses the branch condition of the specified
387 /// condition list, returning false on success and true if it cannot be
390 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
394 /// insertNoop - Insert a noop into the instruction stream at the specified
396 virtual void insertNoop(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator MI) const {
398 assert(0 && "Target didn't implement insertNoop!");
402 /// isPredicated - Returns true if the instruction is already predicated.
404 virtual bool isPredicated(const MachineInstr *MI) const {
408 /// isUnpredicatedTerminator - Returns true if the instruction is a
409 /// terminator instruction that has not been predicated.
410 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
412 /// PredicateInstruction - Convert the instruction into a predicated
413 /// instruction. It returns true if the operation was successful.
415 bool PredicateInstruction(MachineInstr *MI,
416 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
418 /// SubsumesPredicate - Returns true if the first specified predicate
419 /// subsumes the second, e.g. GE subsumes GT.
421 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
422 const SmallVectorImpl<MachineOperand> &Pred2) const {
426 /// DefinesPredicate - If the specified instruction defines any predicate
427 /// or condition code register(s) used for predication, returns true as well
428 /// as the definition predicate(s) by reference.
429 virtual bool DefinesPredicate(MachineInstr *MI,
430 std::vector<MachineOperand> &Pred) const {
434 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
435 /// instruction that defines the specified register class.
436 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
440 /// GetInstSize - Returns the size of the specified Instruction.
442 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
443 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
447 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
449 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
452 /// TargetInstrInfoImpl - This is the default implementation of
453 /// TargetInstrInfo, which just provides a couple of default implementations
454 /// for various methods. This separated out because it is implemented in
455 /// libcodegen, not in libtarget.
456 class TargetInstrInfoImpl : public TargetInstrInfo {
458 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
459 : TargetInstrInfo(desc, NumOpcodes) {}
461 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
462 bool NewMI = false) const;
463 virtual bool CommuteChangesDestination(MachineInstr *MI,
464 unsigned &OpIdx) const;
465 virtual bool PredicateInstruction(MachineInstr *MI,
466 const SmallVectorImpl<MachineOperand> &Pred) const;
467 virtual void reMaterialize(MachineBasicBlock &MBB,
468 MachineBasicBlock::iterator MI,
470 const MachineInstr *Orig) const;
471 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
474 } // End llvm namespace