1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //===----------------------------------------------------------------------===//
36 // Machine Operand Flags and Description
37 //===----------------------------------------------------------------------===//
40 // Operand constraints: only "tied_to" for now.
41 enum OperandConstraint {
42 TIED_TO = 0 // Must be allocated the same register as.
45 /// OperandFlags - These are flags set on operands, but should be considered
46 /// private, all access should go through the TargetOperandInfo accessors.
47 /// See the accessors for a description of what these are.
49 LookupPtrRegClass = 1 << 0,
55 /// TargetOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
58 class TargetOperandInfo {
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If not, this contains 0.
62 unsigned short RegClass;
64 /// Lower 16 bits are used to specify which constraints are set. The higher 16
65 /// bits are used to specify the value of constraints (4 bits each).
66 unsigned int Constraints;
67 /// Currently no other information.
69 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
70 /// requires a callback to look up its register class.
71 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
73 /// isPredicate - Set if this is one of the operands that made up of
74 /// the predicate operand that controls an isPredicable() instruction.
75 bool isPredicate() const { return Flags & TOI::Predicate; }
77 /// isOptionalDef - Set if this operand is a optional def.
79 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
83 //===----------------------------------------------------------------------===//
84 // Machine Instruction Flags and Description
85 //===----------------------------------------------------------------------===//
87 const unsigned M_BRANCH_FLAG = 1 << 0;
88 const unsigned M_CALL_FLAG = 1 << 1;
89 const unsigned M_RET_FLAG = 1 << 2;
90 const unsigned M_BARRIER_FLAG = 1 << 3;
91 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
92 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
93 const unsigned M_MAY_STORE_FLAG = 1 << 6;
94 const unsigned M_INDIRECT_FLAG = 1 << 7;
95 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
96 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
97 const unsigned M_COMMUTABLE = 1 << 10;
98 const unsigned M_TERMINATOR_FLAG = 1 << 11;
99 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
100 const unsigned M_VARIADIC = 1 << 13;
101 const unsigned M_PREDICABLE = 1 << 14;
102 const unsigned M_REMATERIALIZIBLE = 1 << 15;
103 const unsigned M_NOT_DUPLICABLE = 1 << 16;
104 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
105 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
106 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
110 class TargetInstrDescriptor {
112 unsigned short Opcode; // The opcode number.
113 unsigned short NumOperands; // Num of args (may be more if variable_ops)
114 unsigned short NumDefs; // Num of args that are definitions.
115 unsigned short SchedClass; // enum identifying instr sched class
116 const char * Name; // Name of the instruction record in td file.
117 unsigned Flags; // flags identifying machine instr class
118 unsigned TSFlags; // Target Specific Flag values
119 const unsigned *ImplicitUses; // Registers implicitly read by this instr
120 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
121 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
123 /// getOperandConstraint - Returns the value of the specific constraint if
124 /// it is set. Returns -1 if it is not set.
125 int getOperandConstraint(unsigned OpNum,
126 TOI::OperandConstraint Constraint) const {
127 assert((OpNum < NumOperands || isVariadic()) &&
128 "Invalid operand # of TargetInstrInfo");
129 if (OpNum < NumOperands &&
130 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
131 unsigned Pos = 16 + Constraint * 4;
132 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
137 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
138 /// dest operand. Returns -1 if there isn't one.
139 int findTiedToSrcOperand(unsigned OpNum) const;
141 /// getName - Return the name of the record in the .td file for this
142 /// instruction, for example "ADD8ri".
143 const char *getName() const {
147 /// getNumOperands - Return the number of declared MachineOperands for this
148 /// MachineInstruction. Note that variadic (isVariadic() returns true)
149 /// instructions may have additional operands at the end of the list, and note
150 /// that the machine instruction may include implicit register def/uses as
152 unsigned getNumOperands() const {
156 /// getNumDefs - Return the number of MachineOperands that are register
157 /// definitions. Register definitions always occur at the start of the
158 /// machine operand list. This is the number of "outs" in the .td file.
159 unsigned getNumDefs() const {
163 /// isVariadic - Return true if this instruction can have a variable number of
164 /// operands. In this case, the variable operands will be after the normal
165 /// operands but before the implicit definitions and uses (if any are
167 bool isVariadic() const {
168 return Flags & M_VARIADIC;
171 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
172 /// ARM instructions which can set condition code if 's' bit is set.
173 bool hasOptionalDef() const {
174 return Flags & M_HAS_OPTIONAL_DEF;
177 /// getImplicitUses - Return a list of machine operands that are potentially
178 /// read by any instance of this machine instruction. For example, on X86,
179 /// the "adc" instruction adds two register operands and adds the carry bit in
180 /// from the flags register. In this case, the instruction is marked as
181 /// implicitly reading the flags. Likewise, the variable shift instruction on
182 /// X86 is marked as implicitly reading the 'CL' register, which it always
185 /// This method returns null if the instruction has no implicit uses.
186 const unsigned *getImplicitUses() const {
190 /// getImplicitDefs - Return a list of machine operands that are potentially
191 /// written by any instance of this machine instruction. For example, on X86,
192 /// many instructions implicitly set the flags register. In this case, they
193 /// are marked as setting the FLAGS. Likewise, many instructions always
194 /// deposit their result in a physical register. For example, the X86 divide
195 /// instruction always deposits the quotient and remainder in the EAX/EDX
196 /// registers. For that instruction, this will return a list containing the
197 /// EAX/EDX/EFLAGS registers.
199 /// This method returns null if the instruction has no implicit uses.
200 const unsigned *getImplicitDefs() const {
204 /// getSchedClass - Return the scheduling class for this instruction. The
205 /// scheduling class is an index into the InstrItineraryData table. This
206 /// returns zero if there is no known scheduling information for the
209 unsigned getSchedClass() const {
213 bool isReturn() const {
214 return Flags & M_RET_FLAG;
217 bool isCall() const {
218 return Flags & M_CALL_FLAG;
221 /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
222 /// which defines a register to an unspecified value. These basically
223 /// correspond to x = undef.
224 bool isImplicitDef() const {
225 return Flags & M_IMPLICIT_DEF_FLAG;
228 /// isBarrier - Returns true if the specified instruction stops control flow
229 /// from executing the instruction immediately following it. Examples include
230 /// unconditional branches and return instructions.
231 bool isBarrier() const {
232 return Flags & M_BARRIER_FLAG;
235 /// isTerminator - Returns true if this instruction part of the terminator for
236 /// a basic block. Typically this is things like return and branch
239 /// Various passes use this to insert code into the bottom of a basic block,
240 /// but before control flow occurs.
241 bool isTerminator() const {
242 return Flags & M_TERMINATOR_FLAG;
245 /// isBranch - Returns true if this is a conditional, unconditional, or
246 /// indirect branch. Predicates below can be used to discriminate between
247 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
248 /// get more information.
249 bool isBranch() const {
250 return Flags & M_BRANCH_FLAG;
253 /// isIndirectBranch - Return true if this is an indirect branch, such as a
254 /// branch through a register.
255 bool isIndirectBranch() const {
256 return Flags & M_INDIRECT_FLAG;
259 /// isConditionalBranch - Return true if this is a branch which may fall
260 /// through to the next instruction or may transfer control flow to some other
261 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
262 /// information about this branch.
263 bool isConditionalBranch() const {
264 return isBranch() & !isBarrier() & !isIndirectBranch();
267 /// isUnconditionalBranch - Return true if this is a branch which always
268 /// transfers control flow to some other block. The
269 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
270 /// about this branch.
271 bool isUnconditionalBranch() const {
272 return isBranch() & isBarrier() & !isIndirectBranch();
275 // isPredicable - Return true if this instruction has a predicate operand that
276 // controls execution. It may be set to 'always', or may be set to other
277 /// values. There are various methods in TargetInstrInfo that can be used to
278 /// control and modify the predicate in this instruction.
279 bool isPredicable() const {
280 return Flags & M_PREDICABLE;
283 /// isNotDuplicable - Return true if this instruction cannot be safely
284 /// duplicated. For example, if the instruction has a unique labels attached
285 /// to it, duplicating it would cause multiple definition errors.
286 bool isNotDuplicable() const {
287 return Flags & M_NOT_DUPLICABLE;
290 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
291 /// which must be filled by the code generator.
292 bool hasDelaySlot() const {
293 return Flags & M_DELAY_SLOT_FLAG;
296 /// isSimpleLoad - Return true for instructions that are simple loads from
297 /// memory. This should only be set on instructions that load a value from
298 /// memory and return it in their only virtual register definition.
299 /// Instructions that return a value loaded from memory and then modified in
300 /// some way should not return true for this.
301 bool isSimpleLoad() const {
302 return Flags & M_SIMPLE_LOAD_FLAG;
305 //===--------------------------------------------------------------------===//
306 // Side Effect Analysis
307 //===--------------------------------------------------------------------===//
309 /// mayStore - Return true if this instruction could possibly modify memory.
310 /// Instructions with this flag set are not necessarily simple store
311 /// instructions, they may store a modified value based on their operands, or
312 /// may not actually modify anything, for example.
313 bool mayStore() const {
314 return Flags & M_MAY_STORE_FLAG;
319 /// hasNoSideEffects - Return true if all instances of this instruction are
320 /// guaranteed to have no side effects other than:
321 /// 1. The register operands that are def/used by the MachineInstr.
322 /// 2. Registers that are implicitly def/used by the MachineInstr.
323 /// 3. Memory Accesses captured by mayLoad() or mayStore().
325 /// Examples of other side effects would be calling a function, modifying
326 /// 'invisible' machine state like a control register, etc.
328 /// If some instances of this instruction are side-effect free but others are
329 /// not, the hasConditionalSideEffects() property should return true, not this
332 /// Note that you should not call this method directly, instead, call the
333 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
334 /// of the machine instruction.
335 bool hasNoSideEffects() const {
336 return Flags & M_NEVER_HAS_SIDE_EFFECTS;
339 /// hasConditionalSideEffects - Return true if some instances of this
340 /// instruction are guaranteed to have no side effects other than those listed
341 /// for hasNoSideEffects(). To determine whether a specific machineinstr has
342 /// side effects, the TargetInstrInfo::isReallySideEffectFree virtual method
343 /// is invoked to decide.
345 /// Note that you should not call this method directly, instead, call the
346 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
347 /// of the machine instruction.
348 bool hasConditionalSideEffects() const {
349 return Flags & M_MAY_HAVE_SIDE_EFFECTS;
352 //===--------------------------------------------------------------------===//
353 // Flags that indicate whether an instruction can be modified by a method.
354 //===--------------------------------------------------------------------===//
356 /// isCommutableInstr - Return true if this may be a 2- or 3-address
357 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
358 /// result if Y and Z are exchanged. If this flag is set, then the
359 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
362 /// Note that this flag may be set on instructions that are only commutable
363 /// sometimes. In these cases, the call to commuteInstruction will fail.
364 /// Also note that some instructions require non-trivial modification to
366 bool isCommutableInstr() const {
367 return Flags & M_COMMUTABLE;
370 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
371 /// which can be changed into a 3-address instruction if needed. Doing this
372 /// transformation can be profitable in the register allocator, because it
373 /// means that the instruction can use a 2-address form if possible, but
374 /// degrade into a less efficient form if the source and dest register cannot
375 /// be assigned to the same register. For example, this allows the x86
376 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
377 /// is the same speed as the shift but has bigger code size.
379 /// If this returns true, then the target must implement the
380 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
381 /// is allowed to fail if the transformation isn't valid for this specific
382 /// instruction (e.g. shl reg, 4 on x86).
384 bool isConvertibleTo3Addr() const {
385 return Flags & M_CONVERTIBLE_TO_3_ADDR;
388 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
389 /// custom insertion support when the DAG scheduler is inserting it into a
390 /// machine basic block. If this is true for the instruction, it basically
391 /// means that it is a pseudo instruction used at SelectionDAG time that is
392 /// expanded out into magic code by the target when MachineInstrs are formed.
394 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
395 /// is used to insert this into the MachineBasicBlock.
396 bool usesCustomDAGSchedInsertionHook() const {
397 return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
400 /// isRematerializable - Returns true if this instruction is a candidate for
401 /// remat. This flag is deprecated, please don't use it anymore. If this
402 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
403 /// verify the instruction is really rematable.
404 bool isRematerializable() const {
405 return Flags & M_REMATERIALIZIBLE;
410 //---------------------------------------------------------------------------
412 /// TargetInstrInfo - Interface to description of machine instructions
414 class TargetInstrInfo {
415 const TargetInstrDescriptor* desc; // raw array to allow static init'n
416 unsigned NumOpcodes; // number of entries in the desc array
417 unsigned numRealOpCodes; // number of non-dummy op codes
419 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
420 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
422 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
423 virtual ~TargetInstrInfo();
425 // Invariant opcodes: All instruction sets have these as their low opcodes.
434 unsigned getNumOpcodes() const { return NumOpcodes; }
436 /// get - Return the machine instruction descriptor that corresponds to the
437 /// specified instruction opcode.
439 const TargetInstrDescriptor& get(unsigned Opcode) const {
440 assert(Opcode < NumOpcodes);
444 /// isTriviallyReMaterializable - Return true if the instruction is trivially
445 /// rematerializable, meaning it has no side effects and requires no operands
446 /// that aren't always available.
447 bool isTriviallyReMaterializable(MachineInstr *MI) const {
448 return MI->getDesc()->isRematerializable() &&
449 isReallyTriviallyReMaterializable(MI);
452 /// hasUnmodelledSideEffects - Returns true if the instruction has side
453 /// effects that are not captured by any operands of the instruction or other
455 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
456 const TargetInstrDescriptor *TID = MI->getDesc();
457 if (TID->hasNoSideEffects()) return false;
458 if (!TID->hasConditionalSideEffects()) return true;
459 return !isReallySideEffectFree(MI); // May have side effects
462 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
463 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
464 /// instruction itself is actually trivially rematerializable, considering
465 /// its operands. This is used for targets that have instructions that are
466 /// only trivially rematerializable for specific uses. This predicate must
467 /// return false if the instruction has any side effects other than
468 /// producing a value, or if it requres any address registers that are not
469 /// always available.
470 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
474 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
475 /// method is called to determine if the specific instance of this
476 /// instruction has side effects. This is useful in cases of instructions,
477 /// like loads, which generally always have side effects. A load from a
478 /// constant pool doesn't have side effects, though. So we need to
479 /// differentiate it from the general case.
480 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
484 /// getOperandConstraint - Returns the value of the specific constraint if
485 /// it is set. Returns -1 if it is not set.
486 int getOperandConstraint(unsigned Opcode, unsigned OpNum,
487 TOI::OperandConstraint Constraint) const {
488 return get(Opcode).getOperandConstraint(OpNum, Constraint);
491 /// Return true if the instruction is a register to register move
492 /// and leave the source and dest operands in the passed parameters.
493 virtual bool isMoveInstr(const MachineInstr& MI,
495 unsigned& destReg) const {
499 /// isLoadFromStackSlot - If the specified machine instruction is a direct
500 /// load from a stack slot, return the virtual or physical register number of
501 /// the destination along with the FrameIndex of the loaded stack slot. If
502 /// not, return 0. This predicate must return 0 if the instruction has
503 /// any side effects other than loading from the stack slot.
504 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
508 /// isStoreToStackSlot - If the specified machine instruction is a direct
509 /// store to a stack slot, return the virtual or physical register number of
510 /// the source reg along with the FrameIndex of the loaded stack slot. If
511 /// not, return 0. This predicate must return 0 if the instruction has
512 /// any side effects other than storing to the stack slot.
513 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
517 /// convertToThreeAddress - This method must be implemented by targets that
518 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
519 /// may be able to convert a two-address instruction into one or more true
520 /// three-address instructions on demand. This allows the X86 target (for
521 /// example) to convert ADD and SHL instructions into LEA instructions if they
522 /// would require register copies due to two-addressness.
524 /// This method returns a null pointer if the transformation cannot be
525 /// performed, otherwise it returns the last new instruction.
527 virtual MachineInstr *
528 convertToThreeAddress(MachineFunction::iterator &MFI,
529 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
533 /// commuteInstruction - If a target has any instructions that are commutable,
534 /// but require converting to a different instruction or making non-trivial
535 /// changes to commute them, this method can overloaded to do this. The
536 /// default implementation of this method simply swaps the first two operands
537 /// of MI and returns it.
539 /// If a target wants to make more aggressive changes, they can construct and
540 /// return a new machine instruction. If an instruction cannot commute, it
541 /// can also return null.
543 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
545 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
546 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
547 /// implemented for a target). Upon success, this returns false and returns
548 /// with the following information in various cases:
550 /// 1. If this block ends with no branches (it just falls through to its succ)
551 /// just return false, leaving TBB/FBB null.
552 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
553 /// the destination block.
554 /// 3. If this block ends with an conditional branch and it falls through to
555 /// an successor block, it sets TBB to be the branch destination block and a
556 /// list of operands that evaluate the condition. These
557 /// operands can be passed to other TargetInstrInfo methods to create new
559 /// 4. If this block ends with an conditional branch and an unconditional
560 /// block, it returns the 'true' destination in TBB, the 'false' destination
561 /// in FBB, and a list of operands that evaluate the condition. These
562 /// operands can be passed to other TargetInstrInfo methods to create new
565 /// Note that RemoveBranch and InsertBranch must be implemented to support
566 /// cases where this method returns success.
568 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
569 MachineBasicBlock *&FBB,
570 std::vector<MachineOperand> &Cond) const {
574 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
575 /// this is only invoked in cases where AnalyzeBranch returns success. It
576 /// returns the number of instructions that were removed.
577 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
578 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
582 /// InsertBranch - Insert a branch into the end of the specified
583 /// MachineBasicBlock. This operands to this method are the same as those
584 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
585 /// returns success and when an unconditional branch (TBB is non-null, FBB is
586 /// null, Cond is empty) needs to be inserted. It returns the number of
587 /// instructions inserted.
588 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
589 MachineBasicBlock *FBB,
590 const std::vector<MachineOperand> &Cond) const {
591 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
595 /// copyRegToReg - Add a copy between a pair of registers
596 virtual void copyRegToReg(MachineBasicBlock &MBB,
597 MachineBasicBlock::iterator MI,
598 unsigned DestReg, unsigned SrcReg,
599 const TargetRegisterClass *DestRC,
600 const TargetRegisterClass *SrcRC) const {
601 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
604 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
605 MachineBasicBlock::iterator MI,
606 unsigned SrcReg, bool isKill, int FrameIndex,
607 const TargetRegisterClass *RC) const {
608 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
611 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
612 SmallVectorImpl<MachineOperand> &Addr,
613 const TargetRegisterClass *RC,
614 SmallVectorImpl<MachineInstr*> &NewMIs) const {
615 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
618 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator MI,
620 unsigned DestReg, int FrameIndex,
621 const TargetRegisterClass *RC) const {
622 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
625 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
626 SmallVectorImpl<MachineOperand> &Addr,
627 const TargetRegisterClass *RC,
628 SmallVectorImpl<MachineInstr*> &NewMIs) const {
629 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
632 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
633 /// saved registers and returns true if it isn't possible / profitable to do
634 /// so by issuing a series of store instructions via
635 /// storeRegToStackSlot(). Returns false otherwise.
636 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
637 MachineBasicBlock::iterator MI,
638 const std::vector<CalleeSavedInfo> &CSI) const {
642 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
643 /// saved registers and returns true if it isn't possible / profitable to do
644 /// so by issuing a series of load instructions via loadRegToStackSlot().
645 /// Returns false otherwise.
646 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator MI,
648 const std::vector<CalleeSavedInfo> &CSI) const {
652 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
653 /// slot into the specified machine instruction for the specified operand(s).
654 /// If this is possible, a new instruction is returned with the specified
655 /// operand folded, otherwise NULL is returned. The client is responsible for
656 /// removing the old instruction and adding the new one in the instruction
658 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
659 SmallVectorImpl<unsigned> &Ops,
660 int FrameIndex) const {
664 /// foldMemoryOperand - Same as the previous version except it allows folding
665 /// of any load and store from / to any address, not just from a specific
667 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
668 SmallVectorImpl<unsigned> &Ops,
669 MachineInstr* LoadMI) const {
673 /// canFoldMemoryOperand - Returns true if the specified load / store is
674 /// folding is possible.
676 bool canFoldMemoryOperand(MachineInstr *MI,
677 SmallVectorImpl<unsigned> &Ops) const{
681 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
682 /// a store or a load and a store into two or more instruction. If this is
683 /// possible, returns true as well as the new instructions by reference.
684 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
685 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
686 SmallVectorImpl<MachineInstr*> &NewMIs) const{
690 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
691 SmallVectorImpl<SDNode*> &NewNodes) const {
695 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
696 /// instruction after load / store are unfolded from an instruction of the
697 /// specified opcode. It returns zero if the specified unfolding is not
699 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
700 bool UnfoldLoad, bool UnfoldStore) const {
704 /// BlockHasNoFallThrough - Return true if the specified block does not
705 /// fall-through into its successor block. This is primarily used when a
706 /// branch is unanalyzable. It is useful for things like unconditional
707 /// indirect branches (jump tables).
708 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
712 /// ReverseBranchCondition - Reverses the branch condition of the specified
713 /// condition list, returning false on success and true if it cannot be
715 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
719 /// insertNoop - Insert a noop into the instruction stream at the specified
721 virtual void insertNoop(MachineBasicBlock &MBB,
722 MachineBasicBlock::iterator MI) const {
723 assert(0 && "Target didn't implement insertNoop!");
727 /// isPredicated - Returns true if the instruction is already predicated.
729 virtual bool isPredicated(const MachineInstr *MI) const {
733 /// isUnpredicatedTerminator - Returns true if the instruction is a
734 /// terminator instruction that has not been predicated.
735 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
737 /// PredicateInstruction - Convert the instruction into a predicated
738 /// instruction. It returns true if the operation was successful.
740 bool PredicateInstruction(MachineInstr *MI,
741 const std::vector<MachineOperand> &Pred) const = 0;
743 /// SubsumesPredicate - Returns true if the first specified predicate
744 /// subsumes the second, e.g. GE subsumes GT.
746 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
747 const std::vector<MachineOperand> &Pred2) const {
751 /// DefinesPredicate - If the specified instruction defines any predicate
752 /// or condition code register(s) used for predication, returns true as well
753 /// as the definition predicate(s) by reference.
754 virtual bool DefinesPredicate(MachineInstr *MI,
755 std::vector<MachineOperand> &Pred) const {
759 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
761 virtual const TargetRegisterClass *getPointerRegClass() const {
762 assert(0 && "Target didn't implement getPointerRegClass!");
764 return 0; // Must return a value in order to compile with VS 2005
768 /// TargetInstrInfoImpl - This is the default implementation of
769 /// TargetInstrInfo, which just provides a couple of default implementations
770 /// for various methods. This separated out because it is implemented in
771 /// libcodegen, not in libtarget.
772 class TargetInstrInfoImpl : public TargetInstrInfo {
774 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
775 : TargetInstrInfo(desc, NumOpcodes) {}
777 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
778 virtual bool PredicateInstruction(MachineInstr *MI,
779 const std::vector<MachineOperand> &Pred) const;
783 } // End llvm namespace