1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/Support/DataTypes.h"
31 class MachineCodeForInstruction;
32 class TargetRegisterClass;
34 //---------------------------------------------------------------------------
35 // Data types used to define information about a single machine instruction
36 //---------------------------------------------------------------------------
38 typedef short MachineOpCode;
39 typedef unsigned InstrSchedClass;
41 //---------------------------------------------------------------------------
42 // struct TargetInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
47 const unsigned M_BRANCH_FLAG = 1 << 0;
48 const unsigned M_CALL_FLAG = 1 << 1;
49 const unsigned M_RET_FLAG = 1 << 2;
50 const unsigned M_BARRIER_FLAG = 1 << 3;
51 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
52 const unsigned M_LOAD_FLAG = 1 << 5;
53 const unsigned M_STORE_FLAG = 1 << 6;
55 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
56 const unsigned M_2_ADDR_FLAG = 1 << 7;
58 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
59 // changed into a 3-address instruction if the first two operands cannot be
60 // assigned to the same register. The target must implement the
61 // TargetInstrInfo::convertToThreeAddress method for this instruction.
62 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8;
64 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
65 // Z), which produces the same result if Y and Z are exchanged.
66 const unsigned M_COMMUTABLE = 1 << 9;
68 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
69 // block? Typically this is things like return and branch instructions.
70 // Various passes use this to insert code into the bottom of a basic block, but
71 // before control flow occurs.
72 const unsigned M_TERMINATOR_FLAG = 1 << 10;
74 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
75 // insertion support when the DAG scheduler is inserting it into a machine basic
77 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
79 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
80 // operands in addition to the minimum number operands specified.
81 const unsigned M_VARIABLE_OPS = 1 << 12;
83 // Machine operand flags
84 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
85 // requires a callback to look up its register class.
86 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
88 /// TargetOperandInfo - This holds information about one operand of a machine
89 /// instruction, indicating the register class for register operands, etc.
91 class TargetOperandInfo {
93 /// RegClass - This specifies the register class enumeration of the operand
94 /// if the operand is a register. If not, this contains 0.
95 unsigned short RegClass;
97 /// Lower 16 bits are used to specify which constraints are set. The higher 16
98 /// bits are used to specify the value of constraints (4 bits each).
99 unsigned int Constraints;
100 /// Currently no other information.
104 class TargetInstrDescriptor {
106 const char * Name; // Assembly language mnemonic for the opcode.
107 unsigned numOperands; // Num of args (may be more if variable_ops).
108 InstrSchedClass schedClass; // enum identifying instr sched class
109 unsigned Flags; // flags identifying machine instr class
110 unsigned TSFlags; // Target Specific Flag values
111 const unsigned *ImplicitUses; // Registers implicitly read by this instr
112 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
113 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
117 //---------------------------------------------------------------------------
119 /// TargetInstrInfo - Interface to description of machine instructions
121 class TargetInstrInfo {
122 const TargetInstrDescriptor* desc; // raw array to allow static init'n
123 unsigned NumOpcodes; // number of entries in the desc array
124 unsigned numRealOpCodes; // number of non-dummy op codes
126 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
127 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
129 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
130 virtual ~TargetInstrInfo();
132 // Invariant opcodes: All instruction sets have these as their low opcodes.
138 unsigned getNumOpcodes() const { return NumOpcodes; }
140 /// get - Return the machine instruction descriptor that corresponds to the
141 /// specified instruction opcode.
143 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
144 assert((unsigned)Opcode < NumOpcodes);
148 const char *getName(MachineOpCode Opcode) const {
149 return get(Opcode).Name;
152 int getNumOperands(MachineOpCode Opcode) const {
153 return get(Opcode).numOperands;
156 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
157 return get(Opcode).schedClass;
160 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
161 return get(Opcode).ImplicitUses;
164 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
165 return get(Opcode).ImplicitDefs;
170 // Query instruction class flags according to the machine-independent
171 // flags listed above.
173 bool isReturn(MachineOpCode Opcode) const {
174 return get(Opcode).Flags & M_RET_FLAG;
177 bool isTwoAddrInstr(MachineOpCode Opcode) const {
178 return get(Opcode).Flags & M_2_ADDR_FLAG;
180 bool isCommutableInstr(MachineOpCode Opcode) const {
181 return get(Opcode).Flags & M_COMMUTABLE;
183 bool isTerminatorInstr(unsigned Opcode) const {
184 return get(Opcode).Flags & M_TERMINATOR_FLAG;
187 bool isBranch(MachineOpCode Opcode) const {
188 return get(Opcode).Flags & M_BRANCH_FLAG;
191 /// isBarrier - Returns true if the specified instruction stops control flow
192 /// from executing the instruction immediately following it. Examples include
193 /// unconditional branches and return instructions.
194 bool isBarrier(MachineOpCode Opcode) const {
195 return get(Opcode).Flags & M_BARRIER_FLAG;
198 bool isCall(MachineOpCode Opcode) const {
199 return get(Opcode).Flags & M_CALL_FLAG;
201 bool isLoad(MachineOpCode Opcode) const {
202 return get(Opcode).Flags & M_LOAD_FLAG;
204 bool isStore(MachineOpCode Opcode) const {
205 return get(Opcode).Flags & M_STORE_FLAG;
208 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
209 /// which must be filled by the code generator.
210 bool hasDelaySlot(unsigned Opcode) const {
211 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
214 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
215 /// custom insertion support when the DAG scheduler is inserting it into a
216 /// machine basic block.
217 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
218 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
221 bool hasVariableOperands(MachineOpCode Opcode) const {
222 return get(Opcode).Flags & M_VARIABLE_OPS;
225 // Operand constraints: only "tied_to" for now.
226 enum OperandConstraint {
227 TIED_TO = 0 // Must be allocated the same register as.
230 /// getOperandConstraint - Returns the value of the specific constraint if
231 /// it is set. Returns -1 if it is not set.
232 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
233 OperandConstraint Constraint) const {
234 assert(OpNum < get(Opcode).numOperands &&
235 "Invalid operand # of TargetInstrInfo");
236 if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) {
237 unsigned Pos = 16 + Constraint * 4;
238 return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf;
243 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
244 /// dest operand. Returns -1 if there isn't one.
245 int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
247 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
248 /// instruction if it has one. This is used by codegen passes that update
249 /// DWARF line number info as they modify the code.
250 virtual unsigned getDWARF_LABELOpcode() const {
254 /// Return true if the instruction is a register to register move
255 /// and leave the source and dest operands in the passed parameters.
256 virtual bool isMoveInstr(const MachineInstr& MI,
258 unsigned& destReg) const {
262 /// isLoadFromStackSlot - If the specified machine instruction is a direct
263 /// load from a stack slot, return the virtual or physical register number of
264 /// the destination along with the FrameIndex of the loaded stack slot. If
265 /// not, return 0. This predicate must return 0 if the instruction has
266 /// any side effects other than loading from the stack slot.
267 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
271 /// isStoreToStackSlot - If the specified machine instruction is a direct
272 /// store to a stack slot, return the virtual or physical register number of
273 /// the source reg along with the FrameIndex of the loaded stack slot. If
274 /// not, return 0. This predicate must return 0 if the instruction has
275 /// any side effects other than storing to the stack slot.
276 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
280 /// convertToThreeAddress - This method must be implemented by targets that
281 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
282 /// may be able to convert a two-address instruction into a true
283 /// three-address instruction on demand. This allows the X86 target (for
284 /// example) to convert ADD and SHL instructions into LEA instructions if they
285 /// would require register copies due to two-addressness.
287 /// This method returns a null pointer if the transformation cannot be
288 /// performed, otherwise it returns the new instruction.
290 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
294 /// commuteInstruction - If a target has any instructions that are commutable,
295 /// but require converting to a different instruction or making non-trivial
296 /// changes to commute them, this method can overloaded to do this. The
297 /// default implementation of this method simply swaps the first two operands
298 /// of MI and returns it.
300 /// If a target wants to make more aggressive changes, they can construct and
301 /// return a new machine instruction. If an instruction cannot commute, it
302 /// can also return null.
304 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
306 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
307 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
308 /// implemented for a target). Upon success, this returns false and returns
309 /// with the following information in various cases:
311 /// 1. If this block ends with no branches (it just falls through to its succ)
312 /// just return false, leaving TBB/FBB null.
313 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
314 /// the destination block.
315 /// 3. If this block ends with an conditional branch, it returns the 'true'
316 /// destination in TBB, the 'false' destination in FBB, and a list of
317 /// operands that evaluate the condition. These operands can be passed to
318 /// other TargetInstrInfo methods to create new branches.
320 /// Note that RemoveBranch and InsertBranch must be implemented to support
321 /// cases where this method returns success.
323 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
324 MachineBasicBlock *&FBB,
325 std::vector<MachineOperand> &Cond) const {
329 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
330 /// this is only invoked in cases where AnalyzeBranch returns success.
331 virtual void RemoveBranch(MachineBasicBlock &MBB) const {
332 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
335 /// InsertBranch - Insert a branch into the end of the specified
336 /// MachineBasicBlock. This operands to this method are the same as those
337 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
338 /// returns success and when an unconditional branch (TBB is non-null, FBB is
339 /// null, Cond is empty) needs to be inserted.
340 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
341 MachineBasicBlock *FBB,
342 const std::vector<MachineOperand> &Cond) const {
343 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
346 /// BlockHasNoFallThrough - Return true if the specified block does not
347 /// fall-through into its successor block. This is primarily used when a
348 /// branch is unanalyzable. It is useful for things like unconditional
349 /// indirect branches (jump tables).
350 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
354 /// ReverseBranchCondition - Reverses the branch condition of the specified
355 /// condition list, returning false on success and true if it cannot be
357 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
361 /// insertNoop - Insert a noop into the instruction stream at the specified
363 virtual void insertNoop(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator MI) const {
365 assert(0 && "Target didn't implement insertNoop!");
369 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
371 virtual const TargetRegisterClass *getPointerRegClass() const {
372 assert(0 && "Target didn't implement getPointerRegClass!");
377 } // End llvm namespace