1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class InstrItineraryData;
25 class MachineMemOperand;
26 class MachineRegisterInfo;
30 class ScheduleHazardRecognizer;
33 class TargetRegisterClass;
34 class TargetRegisterInfo;
36 template<class T> class SmallVectorImpl;
39 //---------------------------------------------------------------------------
41 /// TargetInstrInfo - Interface to description of machine instruction set
43 class TargetInstrInfo : public MCInstrInfo {
44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes);
48 virtual ~TargetInstrInfo();
50 /// getRegClass - Givem a machine instruction descriptor, returns the register
51 /// class constraint for OpNum, or NULL.
52 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
54 const TargetRegisterInfo *TRI) const;
56 /// isTriviallyReMaterializable - Return true if the instruction is trivially
57 /// rematerializable, meaning it has no side effects and requires no operands
58 /// that aren't always available.
59 bool isTriviallyReMaterializable(const MachineInstr *MI,
60 AliasAnalysis *AA = 0) const {
61 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
62 (MI->getDesc().isRematerializable() &&
63 (isReallyTriviallyReMaterializable(MI, AA) ||
64 isReallyTriviallyReMaterializableGeneric(MI, AA)));
68 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
69 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
70 /// specify whether the instruction is actually trivially rematerializable,
71 /// taking into consideration its operands. This predicate must return false
72 /// if the instruction has any side effects other than producing a value, or
73 /// if it requres any address registers that are not always available.
74 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
75 AliasAnalysis *AA) const {
80 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
81 /// for which the M_REMATERIALIZABLE flag is set and the target hook
82 /// isReallyTriviallyReMaterializable returns false, this function does
83 /// target-independent tests to determine if the instruction is really
84 /// trivially rematerializable.
85 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
86 AliasAnalysis *AA) const;
89 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
90 /// extension instruction. That is, it's like a copy where it's legal for the
91 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
92 /// true, then it's expected the pre-extension value is available as a subreg
93 /// of the result register. This also returns the sub-register index in
95 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
96 unsigned &SrcReg, unsigned &DstReg,
97 unsigned &SubIdx) const {
101 /// isLoadFromStackSlot - If the specified machine instruction is a direct
102 /// load from a stack slot, return the virtual or physical register number of
103 /// the destination along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than loading from the stack slot.
106 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
107 int &FrameIndex) const {
111 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
112 /// stack locations as well. This uses a heuristic so it isn't
113 /// reliable for correctness.
114 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
115 int &FrameIndex) const {
119 /// hasLoadFromStackSlot - If the specified machine instruction has
120 /// a load from a stack slot, return true along with the FrameIndex
121 /// of the loaded stack slot and the machine mem operand containing
122 /// the reference. If not, return false. Unlike
123 /// isLoadFromStackSlot, this returns true for any instructions that
124 /// loads from the stack. This is just a hint, as some cases may be
126 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
127 const MachineMemOperand *&MMO,
128 int &FrameIndex) const {
132 /// isStoreToStackSlot - If the specified machine instruction is a direct
133 /// store to a stack slot, return the virtual or physical register number of
134 /// the source reg along with the FrameIndex of the loaded stack slot. If
135 /// not, return 0. This predicate must return 0 if the instruction has
136 /// any side effects other than storing to the stack slot.
137 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
138 int &FrameIndex) const {
142 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
143 /// stack locations as well. This uses a heuristic so it isn't
144 /// reliable for correctness.
145 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
146 int &FrameIndex) const {
150 /// hasStoreToStackSlot - If the specified machine instruction has a
151 /// store to a stack slot, return true along with the FrameIndex of
152 /// the loaded stack slot and the machine mem operand containing the
153 /// reference. If not, return false. Unlike isStoreToStackSlot,
154 /// this returns true for any instructions that stores to the
155 /// stack. This is just a hint, as some cases may be missed.
156 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
157 const MachineMemOperand *&MMO,
158 int &FrameIndex) const {
162 /// reMaterialize - Re-issue the specified 'original' instruction at the
163 /// specific location targeting a new destination register.
164 /// The register in Orig->getOperand(0).getReg() will be substituted by
165 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
167 virtual void reMaterialize(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator MI,
169 unsigned DestReg, unsigned SubIdx,
170 const MachineInstr *Orig,
171 const TargetRegisterInfo &TRI) const = 0;
173 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
174 /// two-addrss instruction inserted by two-address pass.
175 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
177 const TargetRegisterInfo &TRI) const {
181 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
182 /// MachineFunction::CloneMachineInstr(), but the target may update operands
183 /// that are required to be unique.
185 /// The instruction must be duplicable as indicated by isNotDuplicable().
186 virtual MachineInstr *duplicate(MachineInstr *Orig,
187 MachineFunction &MF) const = 0;
189 /// convertToThreeAddress - This method must be implemented by targets that
190 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
191 /// may be able to convert a two-address instruction into one or more true
192 /// three-address instructions on demand. This allows the X86 target (for
193 /// example) to convert ADD and SHL instructions into LEA instructions if they
194 /// would require register copies due to two-addressness.
196 /// This method returns a null pointer if the transformation cannot be
197 /// performed, otherwise it returns the last new instruction.
199 virtual MachineInstr *
200 convertToThreeAddress(MachineFunction::iterator &MFI,
201 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
205 /// commuteInstruction - If a target has any instructions that are
206 /// commutable but require converting to different instructions or making
207 /// non-trivial changes to commute them, this method can overloaded to do
208 /// that. The default implementation simply swaps the commutable operands.
209 /// If NewMI is false, MI is modified in place and returned; otherwise, a
210 /// new machine instruction is created and returned. Do not call this
211 /// method for a non-commutable instruction, but there may be some cases
212 /// where this method fails and returns null.
213 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
214 bool NewMI = false) const = 0;
216 /// findCommutedOpIndices - If specified MI is commutable, return the two
217 /// operand indices that would swap value. Return false if the instruction
218 /// is not in a form which this routine understands.
219 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
220 unsigned &SrcOpIdx2) const = 0;
222 /// produceSameValue - Return true if two machine instructions would produce
223 /// identical values. By default, this is only true when the two instructions
224 /// are deemed identical except for defs. If this function is called when the
225 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
226 /// aggressive checks.
227 virtual bool produceSameValue(const MachineInstr *MI0,
228 const MachineInstr *MI1,
229 const MachineRegisterInfo *MRI = 0) const = 0;
231 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
232 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
233 /// implemented for a target). Upon success, this returns false and returns
234 /// with the following information in various cases:
236 /// 1. If this block ends with no branches (it just falls through to its succ)
237 /// just return false, leaving TBB/FBB null.
238 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
239 /// the destination block.
240 /// 3. If this block ends with a conditional branch and it falls through to a
241 /// successor block, it sets TBB to be the branch destination block and a
242 /// list of operands that evaluate the condition. These operands can be
243 /// passed to other TargetInstrInfo methods to create new branches.
244 /// 4. If this block ends with a conditional branch followed by an
245 /// unconditional branch, it returns the 'true' destination in TBB, the
246 /// 'false' destination in FBB, and a list of operands that evaluate the
247 /// condition. These operands can be passed to other TargetInstrInfo
248 /// methods to create new branches.
250 /// Note that RemoveBranch and InsertBranch must be implemented to support
251 /// cases where this method returns success.
253 /// If AllowModify is true, then this routine is allowed to modify the basic
254 /// block (e.g. delete instructions after the unconditional branch).
256 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
257 MachineBasicBlock *&FBB,
258 SmallVectorImpl<MachineOperand> &Cond,
259 bool AllowModify = false) const {
263 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
264 /// This is only invoked in cases where AnalyzeBranch returns success. It
265 /// returns the number of instructions that were removed.
266 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
267 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
271 /// InsertBranch - Insert branch code into the end of the specified
272 /// MachineBasicBlock. The operands to this method are the same as those
273 /// returned by AnalyzeBranch. This is only invoked in cases where
274 /// AnalyzeBranch returns success. It returns the number of instructions
277 /// It is also invoked by tail merging to add unconditional branches in
278 /// cases where AnalyzeBranch doesn't apply because there was no original
279 /// branch to analyze. At least this much must be implemented, else tail
280 /// merging needs to be disabled.
281 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
282 MachineBasicBlock *FBB,
283 const SmallVectorImpl<MachineOperand> &Cond,
285 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
289 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
290 /// after it, replacing it with an unconditional branch to NewDest. This is
291 /// used by the tail merging pass.
292 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
293 MachineBasicBlock *NewDest) const = 0;
295 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
296 /// block at the specified instruction (i.e. instruction would be the start
297 /// of a new basic block).
298 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator MBBI) const {
303 /// isProfitableToIfCvt - Return true if it's profitable to predicate
304 /// instructions with accumulated instruction latency of "NumCycles"
305 /// of the specified basic block, where the probability of the instructions
306 /// being executed is given by Probability, and Confidence is a measure
307 /// of our confidence that it will be properly predicted.
309 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
310 unsigned ExtraPredCycles,
311 float Probability, float Confidence) const {
315 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
316 /// checks for the case where two basic blocks from true and false path
317 /// of a if-then-else (diamond) are predicated on mutally exclusive
318 /// predicates, where the probability of the true path being taken is given
319 /// by Probability, and Confidence is a measure of our confidence that it
320 /// will be properly predicted.
322 isProfitableToIfCvt(MachineBasicBlock &TMBB,
323 unsigned NumTCycles, unsigned ExtraTCycles,
324 MachineBasicBlock &FMBB,
325 unsigned NumFCycles, unsigned ExtraFCycles,
326 float Probability, float Confidence) const {
330 /// isProfitableToDupForIfCvt - Return true if it's profitable for
331 /// if-converter to duplicate instructions of specified accumulated
332 /// instruction latencies in the specified MBB to enable if-conversion.
333 /// The probability of the instructions being executed is given by
334 /// Probability, and Confidence is a measure of our confidence that it
335 /// will be properly predicted.
337 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
338 float Probability, float Confidence) const {
342 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
343 virtual void copyPhysReg(MachineBasicBlock &MBB,
344 MachineBasicBlock::iterator MI, DebugLoc DL,
345 unsigned DestReg, unsigned SrcReg,
346 bool KillSrc) const {
347 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
350 /// storeRegToStackSlot - Store the specified register of the given register
351 /// class to the specified stack frame index. The store instruction is to be
352 /// added to the given machine basic block before the specified machine
353 /// instruction. If isKill is true, the register operand is the last use and
354 /// must be marked kill.
355 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
356 MachineBasicBlock::iterator MI,
357 unsigned SrcReg, bool isKill, int FrameIndex,
358 const TargetRegisterClass *RC,
359 const TargetRegisterInfo *TRI) const {
360 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
363 /// loadRegFromStackSlot - Load the specified register of the given register
364 /// class from the specified stack frame index. The load instruction is to be
365 /// added to the given machine basic block before the specified machine
367 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI,
369 unsigned DestReg, int FrameIndex,
370 const TargetRegisterClass *RC,
371 const TargetRegisterInfo *TRI) const {
372 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
375 /// emitFrameIndexDebugValue - Emit a target-dependent form of
376 /// DBG_VALUE encoding the address of a frame index. Addresses would
377 /// normally be lowered the same way as other addresses on the target,
378 /// e.g. in load instructions. For targets that do not support this
379 /// the debug info is simply lost.
380 /// If you add this for a target you should handle this DBG_VALUE in the
381 /// target-specific AsmPrinter code as well; you will probably get invalid
382 /// assembly output if you don't.
383 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
391 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
392 /// slot into the specified machine instruction for the specified operand(s).
393 /// If this is possible, a new instruction is returned with the specified
394 /// operand folded, otherwise NULL is returned.
395 /// The new instruction is inserted before MI, and the client is responsible
396 /// for removing the old instruction.
397 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
398 const SmallVectorImpl<unsigned> &Ops,
399 int FrameIndex) const;
401 /// foldMemoryOperand - Same as the previous version except it allows folding
402 /// of any load and store from / to any address, not just from a specific
404 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
405 const SmallVectorImpl<unsigned> &Ops,
406 MachineInstr* LoadMI) const;
409 /// foldMemoryOperandImpl - Target-dependent implementation for
410 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
411 /// take care of adding a MachineMemOperand to the newly created instruction.
412 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
414 const SmallVectorImpl<unsigned> &Ops,
415 int FrameIndex) const {
419 /// foldMemoryOperandImpl - Target-dependent implementation for
420 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
421 /// take care of adding a MachineMemOperand to the newly created instruction.
422 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
424 const SmallVectorImpl<unsigned> &Ops,
425 MachineInstr* LoadMI) const {
430 /// canFoldMemoryOperand - Returns true for the specified load / store if
431 /// folding is possible.
433 bool canFoldMemoryOperand(const MachineInstr *MI,
434 const SmallVectorImpl<unsigned> &Ops) const =0;
436 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
437 /// a store or a load and a store into two or more instruction. If this is
438 /// possible, returns true as well as the new instructions by reference.
439 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
440 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
441 SmallVectorImpl<MachineInstr*> &NewMIs) const{
445 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
446 SmallVectorImpl<SDNode*> &NewNodes) const {
450 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
451 /// instruction after load / store are unfolded from an instruction of the
452 /// specified opcode. It returns zero if the specified unfolding is not
453 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
454 /// index of the operand which will hold the register holding the loaded
456 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
457 bool UnfoldLoad, bool UnfoldStore,
458 unsigned *LoadRegIndex = 0) const {
462 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
463 /// to determine if two loads are loading from the same base address. It
464 /// should only return true if the base pointers are the same and the
465 /// only differences between the two addresses are the offset. It also returns
466 /// the offsets by reference.
467 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
468 int64_t &Offset1, int64_t &Offset2) const {
472 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
473 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
474 /// be scheduled togther. On some targets if two loads are loading from
475 /// addresses in the same cache line, it's better if they are scheduled
476 /// together. This function takes two integers that represent the load offsets
477 /// from the common base address. It returns true if it decides it's desirable
478 /// to schedule the two loads together. "NumLoads" is the number of loads that
479 /// have already been scheduled after Load1.
480 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
481 int64_t Offset1, int64_t Offset2,
482 unsigned NumLoads) const {
486 /// ReverseBranchCondition - Reverses the branch condition of the specified
487 /// condition list, returning false on success and true if it cannot be
490 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
494 /// insertNoop - Insert a noop into the instruction stream at the specified
496 virtual void insertNoop(MachineBasicBlock &MBB,
497 MachineBasicBlock::iterator MI) const;
500 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
501 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
502 // Default to just using 'nop' string.
506 /// isPredicated - Returns true if the instruction is already predicated.
508 virtual bool isPredicated(const MachineInstr *MI) const {
512 /// isUnpredicatedTerminator - Returns true if the instruction is a
513 /// terminator instruction that has not been predicated.
514 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
516 /// PredicateInstruction - Convert the instruction into a predicated
517 /// instruction. It returns true if the operation was successful.
519 bool PredicateInstruction(MachineInstr *MI,
520 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
522 /// SubsumesPredicate - Returns true if the first specified predicate
523 /// subsumes the second, e.g. GE subsumes GT.
525 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
526 const SmallVectorImpl<MachineOperand> &Pred2) const {
530 /// DefinesPredicate - If the specified instruction defines any predicate
531 /// or condition code register(s) used for predication, returns true as well
532 /// as the definition predicate(s) by reference.
533 virtual bool DefinesPredicate(MachineInstr *MI,
534 std::vector<MachineOperand> &Pred) const {
538 /// isPredicable - Return true if the specified instruction can be predicated.
539 /// By default, this returns true for every instruction with a
540 /// PredicateOperand.
541 virtual bool isPredicable(MachineInstr *MI) const {
542 return MI->getDesc().isPredicable();
545 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
546 /// instruction that defines the specified register class.
547 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
551 /// isSchedulingBoundary - Test if the given instruction should be
552 /// considered a scheduling boundary. This primarily includes labels and
554 virtual bool isSchedulingBoundary(const MachineInstr *MI,
555 const MachineBasicBlock *MBB,
556 const MachineFunction &MF) const = 0;
558 /// Measure the specified inline asm to determine an approximation of its
560 virtual unsigned getInlineAsmLength(const char *Str,
561 const MCAsmInfo &MAI) const;
563 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
564 /// use for this target when scheduling the machine instructions before
565 /// register allocation.
566 virtual ScheduleHazardRecognizer*
567 CreateTargetHazardRecognizer(const TargetMachine *TM,
568 const ScheduleDAG *DAG) const = 0;
570 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
571 /// recognizer to use for this target when scheduling the machine instructions
572 /// after register allocation.
573 virtual ScheduleHazardRecognizer*
574 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
575 const ScheduleDAG *DAG) const = 0;
577 /// AnalyzeCompare - For a comparison instruction, return the source register
578 /// in SrcReg and the value it compares against in CmpValue. Return true if
579 /// the comparison instruction can be analyzed.
580 virtual bool AnalyzeCompare(const MachineInstr *MI,
581 unsigned &SrcReg, int &Mask, int &Value) const {
585 /// OptimizeCompareInstr - See if the comparison instruction can be converted
586 /// into something more efficient. E.g., on ARM most instructions can set the
587 /// flags register, obviating the need for a separate CMP.
588 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
589 unsigned SrcReg, int Mask, int Value,
590 const MachineRegisterInfo *MRI) const {
594 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
595 /// instruction, try to fold the immediate into the use instruction.
596 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
597 unsigned Reg, MachineRegisterInfo *MRI) const {
601 /// getNumMicroOps - Return the number of u-operations the given machine
602 /// instruction will be decoded to on the target cpu.
603 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
604 const MachineInstr *MI) const;
606 /// isZeroCost - Return true for pseudo instructions that don't consume any
607 /// machine resources in their current form. These are common cases that the
608 /// scheduler should consider free, rather than conservatively handling them
609 /// as instructions with no itinerary.
610 bool isZeroCost(unsigned Opcode) const {
611 return Opcode <= TargetOpcode::COPY;
614 /// getOperandLatency - Compute and return the use operand latency of a given
615 /// pair of def and use.
616 /// In most cases, the static scheduling itinerary was enough to determine the
617 /// operand latency. But it may not be possible for instructions with variable
618 /// number of defs / uses.
619 virtual int getOperandLatency(const InstrItineraryData *ItinData,
620 const MachineInstr *DefMI, unsigned DefIdx,
621 const MachineInstr *UseMI, unsigned UseIdx) const;
623 virtual int getOperandLatency(const InstrItineraryData *ItinData,
624 SDNode *DefNode, unsigned DefIdx,
625 SDNode *UseNode, unsigned UseIdx) const;
627 /// getInstrLatency - Compute the instruction latency of a given instruction.
628 /// If the instruction has higher cost when predicated, it's returned via
630 virtual int getInstrLatency(const InstrItineraryData *ItinData,
631 const MachineInstr *MI,
632 unsigned *PredCost = 0) const;
634 virtual int getInstrLatency(const InstrItineraryData *ItinData,
637 /// isHighLatencyDef - Return true if this opcode has high latency to its
639 virtual bool isHighLatencyDef(int opc) const { return false; }
641 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
642 /// and an use in the current loop, return true if the target considered
643 /// it 'high'. This is used by optimization passes such as machine LICM to
644 /// determine whether it makes sense to hoist an instruction out even in
645 /// high register pressure situation.
647 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
648 const MachineRegisterInfo *MRI,
649 const MachineInstr *DefMI, unsigned DefIdx,
650 const MachineInstr *UseMI, unsigned UseIdx) const {
654 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
655 /// if the target considered it 'low'.
657 bool hasLowDefLatency(const InstrItineraryData *ItinData,
658 const MachineInstr *DefMI, unsigned DefIdx) const;
661 /// TargetInstrInfoImpl - This is the default implementation of
662 /// TargetInstrInfo, which just provides a couple of default implementations
663 /// for various methods. This separated out because it is implemented in
664 /// libcodegen, not in libtarget.
665 class TargetInstrInfoImpl : public TargetInstrInfo {
667 TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes)
668 : TargetInstrInfo(desc, NumOpcodes) {}
670 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
671 MachineBasicBlock *NewDest) const;
672 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
673 bool NewMI = false) const;
674 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
675 unsigned &SrcOpIdx2) const;
676 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
677 const SmallVectorImpl<unsigned> &Ops) const;
678 virtual bool PredicateInstruction(MachineInstr *MI,
679 const SmallVectorImpl<MachineOperand> &Pred) const;
680 virtual void reMaterialize(MachineBasicBlock &MBB,
681 MachineBasicBlock::iterator MI,
682 unsigned DestReg, unsigned SubReg,
683 const MachineInstr *Orig,
684 const TargetRegisterInfo &TRI) const;
685 virtual MachineInstr *duplicate(MachineInstr *Orig,
686 MachineFunction &MF) const;
687 virtual bool produceSameValue(const MachineInstr *MI0,
688 const MachineInstr *MI1,
689 const MachineRegisterInfo *MRI) const;
690 virtual bool isSchedulingBoundary(const MachineInstr *MI,
691 const MachineBasicBlock *MBB,
692 const MachineFunction &MF) const;
694 bool usePreRAHazardRecognizer() const;
696 virtual ScheduleHazardRecognizer *
697 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const;
699 virtual ScheduleHazardRecognizer *
700 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
701 const ScheduleDAG*) const;
704 } // End llvm namespace