1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instructions
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 unsigned getNumOpcodes() const { return NumOpcodes; }
57 /// get - Return the machine instruction descriptor that corresponds to the
58 /// specified instruction opcode.
60 const TargetInstrDesc &get(unsigned Opcode) const {
61 assert(Opcode < NumOpcodes && "Invalid opcode!");
62 return Descriptors[Opcode];
65 /// isTriviallyReMaterializable - Return true if the instruction is trivially
66 /// rematerializable, meaning it has no side effects and requires no operands
67 /// that aren't always available.
68 bool isTriviallyReMaterializable(MachineInstr *MI) const {
69 return MI->getDesc().isRematerializable() &&
70 isReallyTriviallyReMaterializable(MI);
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
76 /// instruction itself is actually trivially rematerializable, considering
77 /// its operands. This is used for targets that have instructions that are
78 /// only trivially rematerializable for specific uses. This predicate must
79 /// return false if the instruction has any side effects other than
80 /// producing a value, or if it requres any address registers that are not
82 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
87 /// Return true if the instruction is a register to register move
88 /// and leave the source and dest operands in the passed parameters.
89 virtual bool isMoveInstr(const MachineInstr& MI,
91 unsigned& destReg) const {
95 /// isLoadFromStackSlot - If the specified machine instruction is a direct
96 /// load from a stack slot, return the virtual or physical register number of
97 /// the destination along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than loading from the stack slot.
100 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
104 /// isStoreToStackSlot - If the specified machine instruction is a direct
105 /// store to a stack slot, return the virtual or physical register number of
106 /// the source reg along with the FrameIndex of the loaded stack slot. If
107 /// not, return 0. This predicate must return 0 if the instruction has
108 /// any side effects other than storing to the stack slot.
109 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
113 /// isInvariantLoad - Return true if the specified instruction (which is
114 /// marked mayLoad) is loading from a location whose value is invariant across
115 /// the function. For example, loading a value from the constant pool or from
116 /// from the argument area of a function if it does not change. This should
117 /// only return true of *all* loads the instruction does are invariant (if it
118 /// does multiple loads).
119 virtual bool isInvariantLoad(MachineInstr *MI) const {
124 /// convertToThreeAddress - This method must be implemented by targets that
125 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
126 /// may be able to convert a two-address instruction into one or more true
127 /// three-address instructions on demand. This allows the X86 target (for
128 /// example) to convert ADD and SHL instructions into LEA instructions if they
129 /// would require register copies due to two-addressness.
131 /// This method returns a null pointer if the transformation cannot be
132 /// performed, otherwise it returns the last new instruction.
134 virtual MachineInstr *
135 convertToThreeAddress(MachineFunction::iterator &MFI,
136 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
140 /// commuteInstruction - If a target has any instructions that are commutable,
141 /// but require converting to a different instruction or making non-trivial
142 /// changes to commute them, this method can overloaded to do this. The
143 /// default implementation of this method simply swaps the first two operands
144 /// of MI and returns it.
146 /// If a target wants to make more aggressive changes, they can construct and
147 /// return a new machine instruction. If an instruction cannot commute, it
148 /// can also return null.
150 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
152 /// CommuteChangesDestination - Return true if commuting the specified
153 /// instruction will also changes the destination operand. Also return the
154 /// current operand index of the would be new destination register by
155 /// reference. This can happen when the commutable instruction is also a
156 /// two-address instruction.
157 virtual bool CommuteChangesDestination(MachineInstr *MI,
158 unsigned &OpIdx) const = 0;
160 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
161 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
162 /// implemented for a target). Upon success, this returns false and returns
163 /// with the following information in various cases:
165 /// 1. If this block ends with no branches (it just falls through to its succ)
166 /// just return false, leaving TBB/FBB null.
167 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
168 /// the destination block.
169 /// 3. If this block ends with an conditional branch and it falls through to
170 /// an successor block, it sets TBB to be the branch destination block and a
171 /// list of operands that evaluate the condition. These
172 /// operands can be passed to other TargetInstrInfo methods to create new
174 /// 4. If this block ends with an conditional branch and an unconditional
175 /// block, it returns the 'true' destination in TBB, the 'false' destination
176 /// in FBB, and a list of operands that evaluate the condition. These
177 /// operands can be passed to other TargetInstrInfo methods to create new
180 /// Note that RemoveBranch and InsertBranch must be implemented to support
181 /// cases where this method returns success.
183 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
184 MachineBasicBlock *&FBB,
185 std::vector<MachineOperand> &Cond) const {
189 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
190 /// this is only invoked in cases where AnalyzeBranch returns success. It
191 /// returns the number of instructions that were removed.
192 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
193 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
197 /// InsertBranch - Insert a branch into the end of the specified
198 /// MachineBasicBlock. This operands to this method are the same as those
199 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
200 /// returns success and when an unconditional branch (TBB is non-null, FBB is
201 /// null, Cond is empty) needs to be inserted. It returns the number of
202 /// instructions inserted.
203 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
204 MachineBasicBlock *FBB,
205 const std::vector<MachineOperand> &Cond) const {
206 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
210 /// copyRegToReg - Add a copy between a pair of registers
211 virtual void copyRegToReg(MachineBasicBlock &MBB,
212 MachineBasicBlock::iterator MI,
213 unsigned DestReg, unsigned SrcReg,
214 const TargetRegisterClass *DestRC,
215 const TargetRegisterClass *SrcRC) const {
216 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
219 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
220 MachineBasicBlock::iterator MI,
221 unsigned SrcReg, bool isKill, int FrameIndex,
222 const TargetRegisterClass *RC) const {
223 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
226 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
227 SmallVectorImpl<MachineOperand> &Addr,
228 const TargetRegisterClass *RC,
229 SmallVectorImpl<MachineInstr*> &NewMIs) const {
230 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
233 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MI,
235 unsigned DestReg, int FrameIndex,
236 const TargetRegisterClass *RC) const {
237 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
240 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
241 SmallVectorImpl<MachineOperand> &Addr,
242 const TargetRegisterClass *RC,
243 SmallVectorImpl<MachineInstr*> &NewMIs) const {
244 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
247 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
248 /// saved registers and returns true if it isn't possible / profitable to do
249 /// so by issuing a series of store instructions via
250 /// storeRegToStackSlot(). Returns false otherwise.
251 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MI,
253 const std::vector<CalleeSavedInfo> &CSI) const {
257 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
258 /// saved registers and returns true if it isn't possible / profitable to do
259 /// so by issuing a series of load instructions via loadRegToStackSlot().
260 /// Returns false otherwise.
261 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator MI,
263 const std::vector<CalleeSavedInfo> &CSI) const {
267 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
268 /// slot into the specified machine instruction for the specified operand(s).
269 /// If this is possible, a new instruction is returned with the specified
270 /// operand folded, otherwise NULL is returned. The client is responsible for
271 /// removing the old instruction and adding the new one in the instruction
273 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
275 SmallVectorImpl<unsigned> &Ops,
276 int FrameIndex) const {
280 /// foldMemoryOperand - Same as the previous version except it allows folding
281 /// of any load and store from / to any address, not just from a specific
283 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
285 SmallVectorImpl<unsigned> &Ops,
286 MachineInstr* LoadMI) const {
290 /// canFoldMemoryOperand - Returns true if the specified load / store is
291 /// folding is possible.
293 bool canFoldMemoryOperand(MachineInstr *MI,
294 SmallVectorImpl<unsigned> &Ops) const{
298 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
299 /// a store or a load and a store into two or more instruction. If this is
300 /// possible, returns true as well as the new instructions by reference.
301 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
302 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
303 SmallVectorImpl<MachineInstr*> &NewMIs) const{
307 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
308 SmallVectorImpl<SDNode*> &NewNodes) const {
312 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
313 /// instruction after load / store are unfolded from an instruction of the
314 /// specified opcode. It returns zero if the specified unfolding is not
316 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
317 bool UnfoldLoad, bool UnfoldStore) const {
321 /// BlockHasNoFallThrough - Return true if the specified block does not
322 /// fall-through into its successor block. This is primarily used when a
323 /// branch is unanalyzable. It is useful for things like unconditional
324 /// indirect branches (jump tables).
325 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
329 /// ReverseBranchCondition - Reverses the branch condition of the specified
330 /// condition list, returning false on success and true if it cannot be
332 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
336 /// insertNoop - Insert a noop into the instruction stream at the specified
338 virtual void insertNoop(MachineBasicBlock &MBB,
339 MachineBasicBlock::iterator MI) const {
340 assert(0 && "Target didn't implement insertNoop!");
344 /// isPredicated - Returns true if the instruction is already predicated.
346 virtual bool isPredicated(const MachineInstr *MI) const {
350 /// isUnpredicatedTerminator - Returns true if the instruction is a
351 /// terminator instruction that has not been predicated.
352 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
354 /// PredicateInstruction - Convert the instruction into a predicated
355 /// instruction. It returns true if the operation was successful.
357 bool PredicateInstruction(MachineInstr *MI,
358 const std::vector<MachineOperand> &Pred) const = 0;
360 /// SubsumesPredicate - Returns true if the first specified predicate
361 /// subsumes the second, e.g. GE subsumes GT.
363 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
364 const std::vector<MachineOperand> &Pred2) const {
368 /// DefinesPredicate - If the specified instruction defines any predicate
369 /// or condition code register(s) used for predication, returns true as well
370 /// as the definition predicate(s) by reference.
371 virtual bool DefinesPredicate(MachineInstr *MI,
372 std::vector<MachineOperand> &Pred) const {
376 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
378 virtual const TargetRegisterClass *getPointerRegClass() const {
379 assert(0 && "Target didn't implement getPointerRegClass!");
381 return 0; // Must return a value in order to compile with VS 2005
385 /// TargetInstrInfoImpl - This is the default implementation of
386 /// TargetInstrInfo, which just provides a couple of default implementations
387 /// for various methods. This separated out because it is implemented in
388 /// libcodegen, not in libtarget.
389 class TargetInstrInfoImpl : public TargetInstrInfo {
391 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
392 : TargetInstrInfo(desc, NumOpcodes) {}
394 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
395 virtual bool CommuteChangesDestination(MachineInstr *MI,
396 unsigned &OpIdx) const;
397 virtual bool PredicateInstruction(MachineInstr *MI,
398 const std::vector<MachineOperand> &Pred) const;
402 } // End llvm namespace