1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
30 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
35 /// TargetInstrInfo - Interface to description of machine instruction set
37 class TargetInstrInfo {
38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
39 unsigned NumOpcodes; // Number of entries in the desc array
41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
45 virtual ~TargetInstrInfo();
47 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 /// KILL - This instruction is a noop that is used only to adjust the liveness
56 /// of registers. This can be useful when dealing with sub-registers.
59 /// EXTRACT_SUBREG - This instruction takes two operands: a register
60 /// that has subregisters, and a subregister index. It returns the
61 /// extracted subregister value. This is commonly used to implement
62 /// truncation operations on target architectures which support it.
65 /// INSERT_SUBREG - This instruction takes three operands: a register
66 /// that has subregisters, a register providing an insert value, and a
67 /// subregister index. It returns the value of the first register with
68 /// the value of the second register inserted. The first register is
69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
70 /// anyext operations on target architectures which support it.
73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
77 /// that the first operand is an immediate integer constant. This constant
78 /// is often zero, as is commonly used to implement zext operations on
79 /// target architectures which support it, such as with x86-64 (with
80 /// zext from i32 to i64 via implicit zero-extension).
83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
84 /// register-to-register copy into a specific register class. This is only
85 /// used between instruction selection and MachineInstr creation, before
86 /// virtual registers have been created for all the instructions, and it's
87 /// only needed in cases where the register classes implied by the
88 /// instructions are insufficient. The actual MachineInstrs to perform
89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
93 unsigned getNumOpcodes() const { return NumOpcodes; }
95 /// get - Return the machine instruction descriptor that corresponds to the
96 /// specified instruction opcode.
98 const TargetInstrDesc &get(unsigned Opcode) const {
99 assert(Opcode < NumOpcodes && "Invalid opcode!");
100 return Descriptors[Opcode];
103 /// isTriviallyReMaterializable - Return true if the instruction is trivially
104 /// rematerializable, meaning it has no side effects and requires no operands
105 /// that aren't always available.
106 bool isTriviallyReMaterializable(const MachineInstr *MI,
107 AliasAnalysis *AA = 0) const {
108 return MI->getOpcode() == IMPLICIT_DEF ||
109 (MI->getDesc().isRematerializable() &&
110 (isReallyTriviallyReMaterializable(MI, AA) ||
111 isReallyTriviallyReMaterializableGeneric(MI, AA)));
115 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
116 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
117 /// specify whether the instruction is actually trivially rematerializable,
118 /// taking into consideration its operands. This predicate must return false
119 /// if the instruction has any side effects other than producing a value, or
120 /// if it requres any address registers that are not always available.
121 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
122 AliasAnalysis *AA) const {
127 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
128 /// for which the M_REMATERIALIZABLE flag is set and the target hook
129 /// isReallyTriviallyReMaterializable returns false, this function does
130 /// target-independent tests to determine if the instruction is really
131 /// trivially rematerializable.
132 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
133 AliasAnalysis *AA) const;
136 /// isMoveInstr - Return true if the instruction is a register to register
137 /// move and return the source and dest operands and their sub-register
138 /// indices by reference.
139 virtual bool isMoveInstr(const MachineInstr& MI,
140 unsigned& SrcReg, unsigned& DstReg,
141 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
145 /// isIdentityCopy - Return true if the instruction is a copy (or
146 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
147 /// destination registers are the same.
148 bool isIdentityCopy(const MachineInstr &MI) const {
149 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
150 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
154 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
155 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
158 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
159 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
160 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
165 /// isLoadFromStackSlot - If the specified machine instruction is a direct
166 /// load from a stack slot, return the virtual or physical register number of
167 /// the destination along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than loading from the stack slot.
170 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const {
175 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
176 /// stack locations as well. This uses a heuristic so it isn't
177 /// reliable for correctness.
178 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
179 int &FrameIndex) const {
183 /// hasLoadFromStackSlot - If the specified machine instruction has
184 /// a load from a stack slot, return true along with the FrameIndex
185 /// of the loaded stack slot. If not, return false. Unlike
186 /// isLoadFromStackSlot, this returns true for any instructions that
187 /// loads from the stack. This is just a hint, as some cases may be
189 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
190 int &FrameIndex) const {
194 /// isStoreToStackSlot - If the specified machine instruction is a direct
195 /// store to a stack slot, return the virtual or physical register number of
196 /// the source reg along with the FrameIndex of the loaded stack slot. If
197 /// not, return 0. This predicate must return 0 if the instruction has
198 /// any side effects other than storing to the stack slot.
199 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
200 int &FrameIndex) const {
204 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
205 /// stack locations as well. This uses a heuristic so it isn't
206 /// reliable for correctness.
207 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
208 int &FrameIndex) const {
212 /// hasStoreToStackSlot - If the specified machine instruction has a
213 /// store to a stack slot, return true along with the FrameIndex of
214 /// the loaded stack slot. If not, return false. Unlike
215 /// isStoreToStackSlot, this returns true for any instructions that
216 /// loads from the stack. This is just a hint, as some cases may be
218 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
219 int &FrameIndex) const {
223 /// reMaterialize - Re-issue the specified 'original' instruction at the
224 /// specific location targeting a new destination register.
225 virtual void reMaterialize(MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator MI,
227 unsigned DestReg, unsigned SubIdx,
228 const MachineInstr *Orig,
229 const TargetRegisterInfo *TRI) const = 0;
231 /// convertToThreeAddress - This method must be implemented by targets that
232 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
233 /// may be able to convert a two-address instruction into one or more true
234 /// three-address instructions on demand. This allows the X86 target (for
235 /// example) to convert ADD and SHL instructions into LEA instructions if they
236 /// would require register copies due to two-addressness.
238 /// This method returns a null pointer if the transformation cannot be
239 /// performed, otherwise it returns the last new instruction.
241 virtual MachineInstr *
242 convertToThreeAddress(MachineFunction::iterator &MFI,
243 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
247 /// commuteInstruction - If a target has any instructions that are commutable,
248 /// but require converting to a different instruction or making non-trivial
249 /// changes to commute them, this method can overloaded to do this. The
250 /// default implementation of this method simply swaps the first two operands
251 /// of MI and returns it.
253 /// If a target wants to make more aggressive changes, they can construct and
254 /// return a new machine instruction. If an instruction cannot commute, it
255 /// can also return null.
257 /// If NewMI is true, then a new machine instruction must be created.
259 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
260 bool NewMI = false) const = 0;
262 /// findCommutedOpIndices - If specified MI is commutable, return the two
263 /// operand indices that would swap value. Return true if the instruction
264 /// is not in a form which this routine understands.
265 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
266 unsigned &SrcOpIdx2) const = 0;
268 /// isIdentical - Return true if two instructions are identical. This differs
269 /// from MachineInstr::isIdenticalTo() in that it does not require the
270 /// virtual destination registers to be the same. This is used by MachineLICM
271 /// and other MI passes to perform CSE.
272 virtual bool isIdentical(const MachineInstr *MI,
273 const MachineInstr *Other,
274 const MachineRegisterInfo *MRI) const = 0;
276 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
277 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
278 /// implemented for a target). Upon success, this returns false and returns
279 /// with the following information in various cases:
281 /// 1. If this block ends with no branches (it just falls through to its succ)
282 /// just return false, leaving TBB/FBB null.
283 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
284 /// the destination block.
285 /// 3. If this block ends with an conditional branch and it falls through to
286 /// a successor block, it sets TBB to be the branch destination block and
287 /// a list of operands that evaluate the condition. These
288 /// operands can be passed to other TargetInstrInfo methods to create new
290 /// 4. If this block ends with a conditional branch followed by an
291 /// unconditional branch, it returns the 'true' destination in TBB, the
292 /// 'false' destination in FBB, and a list of operands that evaluate the
293 /// condition. These operands can be passed to other TargetInstrInfo
294 /// methods to create new branches.
296 /// Note that RemoveBranch and InsertBranch must be implemented to support
297 /// cases where this method returns success.
299 /// If AllowModify is true, then this routine is allowed to modify the basic
300 /// block (e.g. delete instructions after the unconditional branch).
302 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
303 MachineBasicBlock *&FBB,
304 SmallVectorImpl<MachineOperand> &Cond,
305 bool AllowModify = false) const {
309 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
310 /// This is only invoked in cases where AnalyzeBranch returns success. It
311 /// returns the number of instructions that were removed.
312 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
313 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
317 /// InsertBranch - Insert branch code into the end of the specified
318 /// MachineBasicBlock. The operands to this method are the same as those
319 /// returned by AnalyzeBranch. This is only invoked in cases where
320 /// AnalyzeBranch returns success. It returns the number of instructions
323 /// It is also invoked by tail merging to add unconditional branches in
324 /// cases where AnalyzeBranch doesn't apply because there was no original
325 /// branch to analyze. At least this much must be implemented, else tail
326 /// merging needs to be disabled.
327 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
328 MachineBasicBlock *FBB,
329 const SmallVectorImpl<MachineOperand> &Cond) const {
330 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
334 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
335 /// returns false if the target does not how to copy between the specified
337 virtual bool copyRegToReg(MachineBasicBlock &MBB,
338 MachineBasicBlock::iterator MI,
339 unsigned DestReg, unsigned SrcReg,
340 const TargetRegisterClass *DestRC,
341 const TargetRegisterClass *SrcRC) const {
342 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
346 /// storeRegToStackSlot - Store the specified register of the given register
347 /// class to the specified stack frame index. The store instruction is to be
348 /// added to the given machine basic block before the specified machine
349 /// instruction. If isKill is true, the register operand is the last use and
350 /// must be marked kill.
351 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator MI,
353 unsigned SrcReg, bool isKill, int FrameIndex,
354 const TargetRegisterClass *RC) const {
355 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
358 /// loadRegFromStackSlot - Load the specified register of the given register
359 /// class from the specified stack frame index. The load instruction is to be
360 /// added to the given machine basic block before the specified machine
362 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator MI,
364 unsigned DestReg, int FrameIndex,
365 const TargetRegisterClass *RC) const {
366 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
369 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
370 /// saved registers and returns true if it isn't possible / profitable to do
371 /// so by issuing a series of store instructions via
372 /// storeRegToStackSlot(). Returns false otherwise.
373 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
374 MachineBasicBlock::iterator MI,
375 const std::vector<CalleeSavedInfo> &CSI) const {
379 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
380 /// saved registers and returns true if it isn't possible / profitable to do
381 /// so by issuing a series of load instructions via loadRegToStackSlot().
382 /// Returns false otherwise.
383 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator MI,
385 const std::vector<CalleeSavedInfo> &CSI) const {
389 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
390 /// slot into the specified machine instruction for the specified operand(s).
391 /// If this is possible, a new instruction is returned with the specified
392 /// operand folded, otherwise NULL is returned. The client is responsible for
393 /// removing the old instruction and adding the new one in the instruction
395 MachineInstr* foldMemoryOperand(MachineFunction &MF,
397 const SmallVectorImpl<unsigned> &Ops,
398 int FrameIndex) const;
400 /// foldMemoryOperand - Same as the previous version except it allows folding
401 /// of any load and store from / to any address, not just from a specific
403 MachineInstr* foldMemoryOperand(MachineFunction &MF,
405 const SmallVectorImpl<unsigned> &Ops,
406 MachineInstr* LoadMI) const;
409 /// foldMemoryOperandImpl - Target-dependent implementation for
410 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
411 /// take care of adding a MachineMemOperand to the newly created instruction.
412 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
414 const SmallVectorImpl<unsigned> &Ops,
415 int FrameIndex) const {
419 /// foldMemoryOperandImpl - Target-dependent implementation for
420 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
421 /// take care of adding a MachineMemOperand to the newly created instruction.
422 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
424 const SmallVectorImpl<unsigned> &Ops,
425 MachineInstr* LoadMI) const {
430 /// canFoldMemoryOperand - Returns true for the specified load / store if
431 /// folding is possible.
433 bool canFoldMemoryOperand(const MachineInstr *MI,
434 const SmallVectorImpl<unsigned> &Ops) const {
438 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
439 /// a store or a load and a store into two or more instruction. If this is
440 /// possible, returns true as well as the new instructions by reference.
441 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
442 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
443 SmallVectorImpl<MachineInstr*> &NewMIs) const{
447 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
448 SmallVectorImpl<SDNode*> &NewNodes) const {
452 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
453 /// instruction after load / store are unfolded from an instruction of the
454 /// specified opcode. It returns zero if the specified unfolding is not
455 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
456 /// index of the operand which will hold the register holding the loaded
458 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
459 bool UnfoldLoad, bool UnfoldStore,
460 unsigned *LoadRegIndex = 0) const {
464 /// BlockHasNoFallThrough - Return true if the specified block does not
465 /// fall-through into its successor block. This is primarily used when a
466 /// branch is unanalyzable. It is useful for things like unconditional
467 /// indirect branches (jump tables).
468 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
472 /// ReverseBranchCondition - Reverses the branch condition of the specified
473 /// condition list, returning false on success and true if it cannot be
476 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
480 /// insertNoop - Insert a noop into the instruction stream at the specified
482 virtual void insertNoop(MachineBasicBlock &MBB,
483 MachineBasicBlock::iterator MI) const;
485 /// isPredicated - Returns true if the instruction is already predicated.
487 virtual bool isPredicated(const MachineInstr *MI) const {
491 /// isUnpredicatedTerminator - Returns true if the instruction is a
492 /// terminator instruction that has not been predicated.
493 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
495 /// PredicateInstruction - Convert the instruction into a predicated
496 /// instruction. It returns true if the operation was successful.
498 bool PredicateInstruction(MachineInstr *MI,
499 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
501 /// SubsumesPredicate - Returns true if the first specified predicate
502 /// subsumes the second, e.g. GE subsumes GT.
504 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
505 const SmallVectorImpl<MachineOperand> &Pred2) const {
509 /// DefinesPredicate - If the specified instruction defines any predicate
510 /// or condition code register(s) used for predication, returns true as well
511 /// as the definition predicate(s) by reference.
512 virtual bool DefinesPredicate(MachineInstr *MI,
513 std::vector<MachineOperand> &Pred) const {
517 /// isPredicable - Return true if the specified instruction can be predicated.
518 /// By default, this returns true for every instruction with a
519 /// PredicateOperand.
520 virtual bool isPredicable(MachineInstr *MI) const {
521 return MI->getDesc().isPredicable();
524 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
525 /// instruction that defines the specified register class.
526 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
530 /// GetInstSize - Returns the size of the specified Instruction.
532 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
533 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
537 /// GetFunctionSizeInBytes - Returns the size of the specified
540 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
542 /// Measure the specified inline asm to determine an approximation of its
544 virtual unsigned getInlineAsmLength(const char *Str,
545 const MCAsmInfo &MAI) const;
547 /// isProfitableToDuplicateIndirectBranch - Returns true if tail duplication
548 /// is especially profitable for indirect branches.
549 virtual bool isProfitableToDuplicateIndirectBranch() const { return false; }
552 /// TargetInstrInfoImpl - This is the default implementation of
553 /// TargetInstrInfo, which just provides a couple of default implementations
554 /// for various methods. This separated out because it is implemented in
555 /// libcodegen, not in libtarget.
556 class TargetInstrInfoImpl : public TargetInstrInfo {
558 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
559 : TargetInstrInfo(desc, NumOpcodes) {}
561 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
562 bool NewMI = false) const;
563 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
564 unsigned &SrcOpIdx2) const;
565 virtual bool PredicateInstruction(MachineInstr *MI,
566 const SmallVectorImpl<MachineOperand> &Pred) const;
567 virtual void reMaterialize(MachineBasicBlock &MBB,
568 MachineBasicBlock::iterator MI,
569 unsigned DestReg, unsigned SubReg,
570 const MachineInstr *Orig,
571 const TargetRegisterInfo *TRI) const;
572 virtual bool isIdentical(const MachineInstr *MI,
573 const MachineInstr *Other,
574 const MachineRegisterInfo *MRI) const;
576 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
579 } // End llvm namespace