1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
27 #include "llvm/ADT/APFloat.h"
28 #include "llvm/ADT/STLExtras.h"
37 class TargetRegisterClass;
41 class MachineBasicBlock;
44 class TargetSubtarget;
46 //===----------------------------------------------------------------------===//
47 /// TargetLowering - This class defines information used to lower LLVM code to
48 /// legal SelectionDAG operators that the target instruction selector can accept
51 /// This class also defines callbacks that targets must implement to lower
52 /// target-specific constructs to SelectionDAG operators.
54 class TargetLowering {
56 /// LegalizeAction - This enum indicates whether operations are valid for a
57 /// target, and if not, what action should be used to make them valid.
59 Legal, // The target natively supports this operation.
60 Promote, // This operation should be executed in a larger type.
61 Expand, // Try to expand this to other ops, otherwise use a libcall.
62 Custom // Use the LowerOperation hook to implement custom lowering.
65 enum OutOfRangeShiftAmount {
66 Undefined, // Oversized shift amounts are undefined (default).
67 Mask, // Shift amounts are auto masked (anded) to value size.
68 Extend // Oversized shift pulls in zeros or sign bits.
71 enum SetCCResultValue {
72 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
73 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
74 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
77 enum SchedPreference {
78 SchedulingForLatency, // Scheduling for shortest total latency.
79 SchedulingForRegPressure // Scheduling for lowest register pressure.
82 explicit TargetLowering(TargetMachine &TM);
83 virtual ~TargetLowering();
85 TargetMachine &getTargetMachine() const { return TM; }
86 const TargetData *getTargetData() const { return TD; }
88 bool isLittleEndian() const { return IsLittleEndian; }
89 MVT::ValueType getPointerTy() const { return PointerTy; }
90 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
91 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
93 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
95 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
97 /// isSelectExpensive - Return true if the select operation is expensive for
99 bool isSelectExpensive() const { return SelectIsExpensive; }
101 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
102 /// a sequence of several shifts, adds, and multiplies for this target.
103 bool isIntDivCheap() const { return IntDivIsCheap; }
105 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
107 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
109 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
111 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
113 /// getSetCCResultContents - For targets without boolean registers, this flag
114 /// returns information about the contents of the high-bits in the setcc
116 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
118 /// getSchedulingPreference - Return target scheduling preference.
119 SchedPreference getSchedulingPreference() const {
120 return SchedPreferenceInfo;
123 /// getRegClassFor - Return the register class that should be used for the
124 /// specified value type. This may only be called on legal types.
125 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
126 assert(!MVT::isExtendedVT(VT));
127 TargetRegisterClass *RC = RegClassForVT[VT];
128 assert(RC && "This value type is not natively supported!");
132 /// isTypeLegal - Return true if the target has native support for the
133 /// specified value type. This means that it has a register that directly
134 /// holds it without promotions or expansions.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
139 class ValueTypeActionImpl {
140 /// ValueTypeActions - This is a bitvector that contains two bits for each
141 /// value type, where the two bits correspond to the LegalizeAction enum.
142 /// This can be queried with "getTypeAction(VT)".
143 uint32_t ValueTypeActions[2];
145 ValueTypeActionImpl() {
146 ValueTypeActions[0] = ValueTypeActions[1] = 0;
148 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
149 ValueTypeActions[0] = RHS.ValueTypeActions[0];
150 ValueTypeActions[1] = RHS.ValueTypeActions[1];
153 LegalizeAction getTypeAction(MVT::ValueType VT) const {
154 if (MVT::isExtendedVT(VT)) {
155 if (MVT::isVector(VT)) return Expand;
156 if (MVT::isInteger(VT))
157 // First promote to a power-of-two size, then expand if necessary.
158 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
159 assert(0 && "Unsupported extended type!");
161 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
163 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
164 assert(!MVT::isExtendedVT(VT));
165 assert(unsigned(VT >> 4) < array_lengthof(ValueTypeActions));
166 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
170 const ValueTypeActionImpl &getValueTypeActions() const {
171 return ValueTypeActions;
174 /// getTypeAction - Return how we should legalize values of this type, either
175 /// it is already legal (return 'Legal') or we need to promote it to a larger
176 /// type (return 'Promote'), or we need to expand it into multiple registers
177 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
178 LegalizeAction getTypeAction(MVT::ValueType VT) const {
179 return ValueTypeActions.getTypeAction(VT);
182 /// getTypeToTransformTo - For types supported by the target, this is an
183 /// identity function. For types that must be promoted to larger types, this
184 /// returns the larger type to promote to. For integer types that are larger
185 /// than the largest integer register, this contains one step in the expansion
186 /// to get to the smaller register. For illegal floating point types, this
187 /// returns the integer type to transform to.
188 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
189 if (!MVT::isExtendedVT(VT)) {
190 MVT::ValueType NVT = TransformToType[VT];
191 assert(getTypeAction(NVT) != Promote &&
192 "Promote may not follow Expand or Promote");
196 if (MVT::isVector(VT))
197 return MVT::getVectorType(MVT::getVectorElementType(VT),
198 MVT::getVectorNumElements(VT) / 2);
199 if (MVT::isInteger(VT)) {
200 MVT::ValueType NVT = MVT::RoundIntegerType(VT);
202 // Size is a power of two - expand to half the size.
203 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
205 // Promote to a power of two size, avoiding multi-step promotion.
206 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
208 assert(0 && "Unsupported extended type!");
211 /// getTypeToExpandTo - For types supported by the target, this is an
212 /// identity function. For types that must be expanded (i.e. integer types
213 /// that are larger than the largest integer register or illegal floating
214 /// point types), this returns the largest legal type it will be expanded to.
215 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
216 assert(!MVT::isVector(VT));
218 switch (getTypeAction(VT)) {
222 VT = getTypeToTransformTo(VT);
225 assert(false && "Type is not legal nor is it to be expanded!");
232 /// getVectorTypeBreakdown - Vector types are broken down into some number of
233 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
234 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
235 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
237 /// This method returns the number of registers needed, and the VT for each
238 /// register. It also returns the VT and quantity of the intermediate values
239 /// before they are promoted/expanded.
241 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
242 MVT::ValueType &IntermediateVT,
243 unsigned &NumIntermediates,
244 MVT::ValueType &RegisterVT) const;
246 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
247 legal_fpimm_iterator legal_fpimm_begin() const {
248 return LegalFPImmediates.begin();
250 legal_fpimm_iterator legal_fpimm_end() const {
251 return LegalFPImmediates.end();
254 /// isShuffleMaskLegal - Targets can use this to indicate that they only
255 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
256 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
257 /// are assumed to be legal.
258 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
262 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
263 /// used by Targets can use this to indicate if there is a suitable
264 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
266 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
268 SelectionDAG &DAG) const {
272 /// getOperationAction - Return how this operation should be treated: either
273 /// it is legal, needs to be promoted to a larger size, needs to be
274 /// expanded to some other code sequence, or the target has a custom expander
276 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
277 if (MVT::isExtendedVT(VT)) return Expand;
278 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
281 /// isOperationLegal - Return true if the specified operation is legal on this
283 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
284 return getOperationAction(Op, VT) == Legal ||
285 getOperationAction(Op, VT) == Custom;
288 /// getLoadXAction - Return how this load with extension should be treated:
289 /// either it is legal, needs to be promoted to a larger size, needs to be
290 /// expanded to some other code sequence, or the target has a custom expander
292 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
293 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
294 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
297 /// isLoadXLegal - Return true if the specified load with extension is legal
299 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
300 return getLoadXAction(LType, VT) == Legal ||
301 getLoadXAction(LType, VT) == Custom;
304 /// getStoreXAction - Return how this store with truncation should be treated:
305 /// either it is legal, needs to be promoted to a larger size, needs to be
306 /// expanded to some other code sequence, or the target has a custom expander
308 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
309 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
310 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
313 /// isStoreXLegal - Return true if the specified store with truncation is
314 /// legal on this target.
315 bool isStoreXLegal(MVT::ValueType VT) const {
316 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
319 /// getIndexedLoadAction - Return how the indexed load should be treated:
320 /// either it is legal, needs to be promoted to a larger size, needs to be
321 /// expanded to some other code sequence, or the target has a custom expander
324 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
325 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
326 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
329 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
331 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
332 return getIndexedLoadAction(IdxMode, VT) == Legal ||
333 getIndexedLoadAction(IdxMode, VT) == Custom;
336 /// getIndexedStoreAction - Return how the indexed store should be treated:
337 /// either it is legal, needs to be promoted to a larger size, needs to be
338 /// expanded to some other code sequence, or the target has a custom expander
341 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
342 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
343 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
346 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
348 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
349 return getIndexedStoreAction(IdxMode, VT) == Legal ||
350 getIndexedStoreAction(IdxMode, VT) == Custom;
353 /// getConvertAction - Return how the conversion should be treated:
354 /// either it is legal, needs to be promoted to a larger size, needs to be
355 /// expanded to some other code sequence, or the target has a custom expander
358 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
359 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
360 "Table isn't big enough!");
361 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
364 /// isConvertLegal - Return true if the specified conversion is legal
366 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
367 return getConvertAction(FromVT, ToVT) == Legal ||
368 getConvertAction(FromVT, ToVT) == Custom;
371 /// getTypeToPromoteTo - If the action for this operation is to promote, this
372 /// method returns the ValueType to promote to.
373 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
374 assert(getOperationAction(Op, VT) == Promote &&
375 "This operation isn't promoted!");
377 // See if this has an explicit type specified.
378 std::map<std::pair<unsigned, MVT::ValueType>,
379 MVT::ValueType>::const_iterator PTTI =
380 PromoteToType.find(std::make_pair(Op, VT));
381 if (PTTI != PromoteToType.end()) return PTTI->second;
383 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
384 "Cannot autopromote this type, add it with AddPromotedToType.");
386 MVT::ValueType NVT = VT;
388 NVT = (MVT::ValueType)(NVT+1);
389 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
390 "Didn't find type to promote to!");
391 } while (!isTypeLegal(NVT) ||
392 getOperationAction(Op, NVT) == Promote);
396 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
397 /// This is fixed by the LLVM operations except for the pointer size. If
398 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
399 /// counterpart (e.g. structs), otherwise it will assert.
400 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
401 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
402 return VT == MVT::iPTR ? PointerTy : VT;
405 /// getRegisterType - Return the type of registers that this ValueType will
406 /// eventually require.
407 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
408 if (!MVT::isExtendedVT(VT))
409 return RegisterTypeForVT[VT];
410 if (MVT::isVector(VT)) {
411 MVT::ValueType VT1, RegisterVT;
412 unsigned NumIntermediates;
413 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
416 assert(0 && "Unsupported extended type!");
419 /// getNumRegisters - Return the number of registers that this ValueType will
420 /// eventually require. This is one for any types promoted to live in larger
421 /// registers, but may be more than one for types (like i64) that are split
423 unsigned getNumRegisters(MVT::ValueType VT) const {
424 if (!MVT::isExtendedVT(VT))
425 return NumRegistersForVT[VT];
426 if (MVT::isVector(VT)) {
427 MVT::ValueType VT1, VT2;
428 unsigned NumIntermediates;
429 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
431 assert(0 && "Unsupported extended type!");
434 /// hasTargetDAGCombine - If true, the target has custom DAG combine
435 /// transformations that it can perform for the specified node.
436 bool hasTargetDAGCombine(ISD::NodeType NT) const {
437 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
440 /// This function returns the maximum number of store operations permitted
441 /// to replace a call to llvm.memset. The value is set by the target at the
442 /// performance threshold for such a replacement.
443 /// @brief Get maximum # of store operations permitted for llvm.memset
444 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
446 /// This function returns the maximum number of store operations permitted
447 /// to replace a call to llvm.memcpy. The value is set by the target at the
448 /// performance threshold for such a replacement.
449 /// @brief Get maximum # of store operations permitted for llvm.memcpy
450 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
452 /// This function returns the maximum number of store operations permitted
453 /// to replace a call to llvm.memmove. The value is set by the target at the
454 /// performance threshold for such a replacement.
455 /// @brief Get maximum # of store operations permitted for llvm.memmove
456 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
458 /// This function returns true if the target allows unaligned memory accesses.
459 /// This is used, for example, in situations where an array copy/move/set is
460 /// converted to a sequence of store operations. It's use helps to ensure that
461 /// such replacements don't generate code that causes an alignment error
462 /// (trap) on the target machine.
463 /// @brief Determine if the target supports unaligned memory accesses.
464 bool allowsUnalignedMemoryAccesses() const {
465 return allowUnalignedMemoryAccesses;
468 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
469 /// to implement llvm.setjmp.
470 bool usesUnderscoreSetJmp() const {
471 return UseUnderscoreSetJmp;
474 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
475 /// to implement llvm.longjmp.
476 bool usesUnderscoreLongJmp() const {
477 return UseUnderscoreLongJmp;
480 /// getStackPointerRegisterToSaveRestore - If a physical register, this
481 /// specifies the register that llvm.savestack/llvm.restorestack should save
483 unsigned getStackPointerRegisterToSaveRestore() const {
484 return StackPointerRegisterToSaveRestore;
487 /// getExceptionAddressRegister - If a physical register, this returns
488 /// the register that receives the exception address on entry to a landing
490 unsigned getExceptionAddressRegister() const {
491 return ExceptionPointerRegister;
494 /// getExceptionSelectorRegister - If a physical register, this returns
495 /// the register that receives the exception typeid on entry to a landing
497 unsigned getExceptionSelectorRegister() const {
498 return ExceptionSelectorRegister;
501 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
502 /// set, the default is 200)
503 unsigned getJumpBufSize() const {
507 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
508 /// (if never set, the default is 0)
509 unsigned getJumpBufAlignment() const {
510 return JumpBufAlignment;
513 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
514 /// limit. Any block whose size is greater should not be predicated.
515 virtual unsigned getIfCvtBlockSizeLimit() const {
516 return IfCvtBlockSizeLimit;
519 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
520 /// block to be considered for duplication. Any block whose size is greater
521 /// should not be duplicated to facilitate its predication.
522 virtual unsigned getIfCvtDupBlockSizeLimit() const {
523 return IfCvtDupBlockSizeLimit;
526 /// getPreIndexedAddressParts - returns true by value, base pointer and
527 /// offset pointer and addressing mode by reference if the node's address
528 /// can be legally represented as pre-indexed load / store address.
529 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
531 ISD::MemIndexedMode &AM,
536 /// getPostIndexedAddressParts - returns true by value, base pointer and
537 /// offset pointer and addressing mode by reference if this node can be
538 /// combined with a load / store to form a post-indexed load / store.
539 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
540 SDOperand &Base, SDOperand &Offset,
541 ISD::MemIndexedMode &AM,
546 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
548 virtual SDOperand getPICJumpTableRelocBase(SDOperand Table,
549 SelectionDAG &DAG) const;
551 //===--------------------------------------------------------------------===//
552 // TargetLowering Optimization Methods
555 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
556 /// SDOperands for returning information from TargetLowering to its clients
557 /// that want to combine
558 struct TargetLoweringOpt {
564 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
565 : DAG(InDAG), AfterLegalize(afterLegalize) {}
567 bool CombineTo(SDOperand O, SDOperand N) {
573 /// ShrinkDemandedConstant - Check to see if the specified operand of the
574 /// specified instruction is a constant integer. If so, check to see if
575 /// there are any bits set in the constant that are not demanded. If so,
576 /// shrink the constant and return true.
577 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
580 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
581 /// DemandedMask bits of the result of Op are ever used downstream. If we can
582 /// use this information to simplify Op, create a new simplified DAG node and
583 /// return true, returning the original and new nodes in Old and New.
584 /// Otherwise, analyze the expression and return a mask of KnownOne and
585 /// KnownZero bits for the expression (used to simplify the caller).
586 /// The KnownZero/One bits may only be accurate for those bits in the
588 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
589 uint64_t &KnownZero, uint64_t &KnownOne,
590 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
592 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
593 /// Mask are known to be either zero or one and return them in the
594 /// KnownZero/KnownOne bitsets.
595 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
599 const SelectionDAG &DAG,
600 unsigned Depth = 0) const;
602 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
603 /// targets that want to expose additional information about sign bits to the
605 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
606 unsigned Depth = 0) const;
608 struct DAGCombinerInfo {
609 void *DC; // The DAG Combiner object.
611 bool CalledByLegalizer;
615 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
616 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
618 bool isBeforeLegalize() const { return BeforeLegalize; }
619 bool isCalledByLegalizer() const { return CalledByLegalizer; }
621 void AddToWorklist(SDNode *N);
622 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
623 SDOperand CombineTo(SDNode *N, SDOperand Res);
624 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
627 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
628 /// and cc. If it is unable to simplify it, return a null SDOperand.
629 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
630 ISD::CondCode Cond, bool foldBooleans,
631 DAGCombinerInfo &DCI) const;
633 /// PerformDAGCombine - This method will be invoked for all target nodes and
634 /// for any target-independent nodes that the target has registered with
637 /// The semantics are as follows:
639 /// SDOperand.Val == 0 - No change was made
640 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
641 /// otherwise - N should be replaced by the returned Operand.
643 /// In addition, methods provided by DAGCombinerInfo may be used to perform
644 /// more complex transformations.
646 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
648 //===--------------------------------------------------------------------===//
649 // TargetLowering Configuration Methods - These methods should be invoked by
650 // the derived class constructor to configure this object for the target.
654 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
655 /// GOT for PC-relative code.
656 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
658 /// setShiftAmountType - Describe the type that should be used for shift
659 /// amounts. This type defaults to the pointer type.
660 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
662 /// setSetCCResultType - Describe the type that shoudl be used as the result
663 /// of a setcc operation. This defaults to the pointer type.
664 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
666 /// setSetCCResultContents - Specify how the target extends the result of a
667 /// setcc operation in a register.
668 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
670 /// setSchedulingPreference - Specify the target scheduling preference.
671 void setSchedulingPreference(SchedPreference Pref) {
672 SchedPreferenceInfo = Pref;
675 /// setShiftAmountFlavor - Describe how the target handles out of range shift
677 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
678 ShiftAmtHandling = OORSA;
681 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
682 /// use _setjmp to implement llvm.setjmp or the non _ version.
683 /// Defaults to false.
684 void setUseUnderscoreSetJmp(bool Val) {
685 UseUnderscoreSetJmp = Val;
688 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
689 /// use _longjmp to implement llvm.longjmp or the non _ version.
690 /// Defaults to false.
691 void setUseUnderscoreLongJmp(bool Val) {
692 UseUnderscoreLongJmp = Val;
695 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
696 /// specifies the register that llvm.savestack/llvm.restorestack should save
698 void setStackPointerRegisterToSaveRestore(unsigned R) {
699 StackPointerRegisterToSaveRestore = R;
702 /// setExceptionPointerRegister - If set to a physical register, this sets
703 /// the register that receives the exception address on entry to a landing
705 void setExceptionPointerRegister(unsigned R) {
706 ExceptionPointerRegister = R;
709 /// setExceptionSelectorRegister - If set to a physical register, this sets
710 /// the register that receives the exception typeid on entry to a landing
712 void setExceptionSelectorRegister(unsigned R) {
713 ExceptionSelectorRegister = R;
716 /// SelectIsExpensive - Tells the code generator not to expand operations
717 /// into sequences that use the select operations if possible.
718 void setSelectIsExpensive() { SelectIsExpensive = true; }
720 /// setIntDivIsCheap - Tells the code generator that integer divide is
721 /// expensive, and if possible, should be replaced by an alternate sequence
722 /// of instructions not containing an integer divide.
723 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
725 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
726 /// srl/add/sra for a signed divide by power of two, and let the target handle
728 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
730 /// addRegisterClass - Add the specified register class as an available
731 /// regclass for the specified value type. This indicates the selector can
732 /// handle values of that class natively.
733 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
734 assert(!MVT::isExtendedVT(VT));
735 AvailableRegClasses.push_back(std::make_pair(VT, RC));
736 RegClassForVT[VT] = RC;
739 /// computeRegisterProperties - Once all of the register classes are added,
740 /// this allows us to compute derived properties we expose.
741 void computeRegisterProperties();
743 /// setOperationAction - Indicate that the specified operation does not work
744 /// with the specified type and indicate what to do about it.
745 void setOperationAction(unsigned Op, MVT::ValueType VT,
746 LegalizeAction Action) {
747 assert(VT < 32 && Op < array_lengthof(OpActions) &&
748 "Table isn't big enough!");
749 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
750 OpActions[Op] |= (uint64_t)Action << VT*2;
753 /// setLoadXAction - Indicate that the specified load with extension does not
754 /// work with the with specified type and indicate what to do about it.
755 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
756 LegalizeAction Action) {
757 assert(VT < 32 && ExtType < array_lengthof(LoadXActions) &&
758 "Table isn't big enough!");
759 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
760 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
763 /// setStoreXAction - Indicate that the specified store with truncation does
764 /// not work with the with specified type and indicate what to do about it.
765 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
766 assert(VT < 32 && "Table isn't big enough!");
767 StoreXActions &= ~(uint64_t(3UL) << VT*2);
768 StoreXActions |= (uint64_t)Action << VT*2;
771 /// setIndexedLoadAction - Indicate that the specified indexed load does or
772 /// does not work with the with specified type and indicate what to do abort
773 /// it. NOTE: All indexed mode loads are initialized to Expand in
774 /// TargetLowering.cpp
775 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
776 LegalizeAction Action) {
777 assert(VT < 32 && IdxMode <
778 array_lengthof(IndexedModeActions[0]) &&
779 "Table isn't big enough!");
780 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
781 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
784 /// setIndexedStoreAction - Indicate that the specified indexed store does or
785 /// does not work with the with specified type and indicate what to do about
786 /// it. NOTE: All indexed mode stores are initialized to Expand in
787 /// TargetLowering.cpp
788 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
789 LegalizeAction Action) {
790 assert(VT < 32 && IdxMode <
791 array_lengthof(IndexedModeActions[1]) &&
792 "Table isn't big enough!");
793 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
794 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
797 /// setConvertAction - Indicate that the specified conversion does or does
798 /// not work with the with specified type and indicate what to do about it.
799 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
800 LegalizeAction Action) {
801 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
802 "Table isn't big enough!");
803 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
804 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
807 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
808 /// promotion code defaults to trying a larger integer/fp until it can find
809 /// one that works. If that default is insufficient, this method can be used
810 /// by the target to override the default.
811 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
812 MVT::ValueType DestVT) {
813 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
816 /// addLegalFPImmediate - Indicate that this target can instruction select
817 /// the specified FP immediate natively.
818 void addLegalFPImmediate(const APFloat& Imm) {
819 LegalFPImmediates.push_back(Imm);
822 /// setTargetDAGCombine - Targets should invoke this method for each target
823 /// independent node that they want to provide a custom DAG combiner for by
824 /// implementing the PerformDAGCombine virtual method.
825 void setTargetDAGCombine(ISD::NodeType NT) {
826 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
829 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
830 /// bytes); default is 200
831 void setJumpBufSize(unsigned Size) {
835 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
836 /// alignment (in bytes); default is 0
837 void setJumpBufAlignment(unsigned Align) {
838 JumpBufAlignment = Align;
841 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
842 /// limit (in number of instructions); default is 2.
843 void setIfCvtBlockSizeLimit(unsigned Limit) {
844 IfCvtBlockSizeLimit = Limit;
847 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
848 /// of instructions) to be considered for code duplication during
849 /// if-conversion; default is 2.
850 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
851 IfCvtDupBlockSizeLimit = Limit;
856 virtual const TargetSubtarget *getSubtarget() {
857 assert(0 && "Not Implemented");
858 return NULL; // this is here to silence compiler errors
860 //===--------------------------------------------------------------------===//
861 // Lowering methods - These methods must be implemented by targets so that
862 // the SelectionDAGLowering code knows how to lower these.
865 /// LowerArguments - This hook must be implemented to indicate how we should
866 /// lower the arguments for the specified function, into the specified DAG.
867 virtual std::vector<SDOperand>
868 LowerArguments(Function &F, SelectionDAG &DAG);
870 /// LowerCallTo - This hook lowers an abstract call to a function into an
871 /// actual call. This returns a pair of operands. The first element is the
872 /// return value for the function (if RetTy is not VoidTy). The second
873 /// element is the outgoing token chain.
874 struct ArgListEntry {
884 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
885 isSRet(false), isNest(false), isByVal(false) { }
887 typedef std::vector<ArgListEntry> ArgListTy;
888 virtual std::pair<SDOperand, SDOperand>
889 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
890 bool isVarArg, unsigned CallingConv, bool isTailCall,
891 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
894 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
895 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest,
896 SDOperand Source, SDOperand Count,
898 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
899 SDOperand Source, unsigned Size,
900 unsigned Align, SelectionDAG &DAG) {
901 assert(0 && "Not Implemented");
902 return SDOperand(); // this is here to silence compiler errors
906 /// LowerOperation - This callback is invoked for operations that are
907 /// unsupported by the target, which are registered to use 'custom' lowering,
908 /// and whose defined values are all legal.
909 /// If the target has no operations that require custom lowering, it need not
910 /// implement this. The default implementation of this aborts.
911 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
913 /// ExpandOperationResult - This callback is invoked for operations that are
914 /// unsupported by the target, which are registered to use 'custom' lowering,
915 /// and whose result type needs to be expanded. This must return a node whose
916 /// results precisely match the results of the input node. This typically
917 /// involves a MERGE_VALUES node and/or BUILD_PAIR.
919 /// If the target has no operations that require custom lowering, it need not
920 /// implement this. The default implementation of this aborts.
921 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
922 assert(0 && "ExpandOperationResult not implemented for this target!");
926 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
927 /// tail call optimization. Targets which want to do tail call optimization
928 /// should override this function.
929 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
931 SelectionDAG &DAG) const {
935 /// CustomPromoteOperation - This callback is invoked for operations that are
936 /// unsupported by the target, are registered to use 'custom' lowering, and
937 /// whose type needs to be promoted.
938 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
940 /// getTargetNodeName() - This method returns the name of a target specific
942 virtual const char *getTargetNodeName(unsigned Opcode) const;
944 //===--------------------------------------------------------------------===//
945 // Inline Asm Support hooks
948 enum ConstraintType {
949 C_Register, // Constraint represents a single register.
950 C_RegisterClass, // Constraint represents one or more registers.
951 C_Memory, // Memory constraint.
952 C_Other, // Something else.
953 C_Unknown // Unsupported constraint.
956 /// getConstraintType - Given a constraint, return the type of constraint it
957 /// is for this target.
958 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
961 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
962 /// return a list of registers that can be used to satisfy the constraint.
963 /// This should only be used for C_RegisterClass constraints.
964 virtual std::vector<unsigned>
965 getRegClassForInlineAsmConstraint(const std::string &Constraint,
966 MVT::ValueType VT) const;
968 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
969 /// {edx}), return the register number and the register class for the
972 /// Given a register class constraint, like 'r', if this corresponds directly
973 /// to an LLVM register class, return a register of 0 and the register class
976 /// This should only be used for C_Register constraints. On error,
977 /// this returns a register number of 0 and a null register class pointer..
978 virtual std::pair<unsigned, const TargetRegisterClass*>
979 getRegForInlineAsmConstraint(const std::string &Constraint,
980 MVT::ValueType VT) const;
983 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
984 /// vector. If it is invalid, don't add anything to Ops.
985 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
986 std::vector<SDOperand> &Ops,
989 //===--------------------------------------------------------------------===//
993 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
994 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
995 // instructions are special in various ways, which require special support to
996 // insert. The specified MachineInstr is created but not inserted into any
997 // basic blocks, and the scheduler passes ownership of it to this method.
998 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
999 MachineBasicBlock *MBB);
1001 //===--------------------------------------------------------------------===//
1002 // Addressing mode description hooks (used by LSR etc).
1005 /// AddrMode - This represents an addressing mode of:
1006 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1007 /// If BaseGV is null, there is no BaseGV.
1008 /// If BaseOffs is zero, there is no base offset.
1009 /// If HasBaseReg is false, there is no base register.
1010 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1014 GlobalValue *BaseGV;
1018 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1021 /// isLegalAddressingMode - Return true if the addressing mode represented by
1022 /// AM is legal for this target, for a load/store of the specified type.
1023 /// TODO: Handle pre/postinc as well.
1024 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1026 /// isTruncateFree - Return true if it's free to truncate a value of
1027 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1028 /// register EAX to i16 by referencing its sub-register AX.
1029 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1033 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const {
1037 //===--------------------------------------------------------------------===//
1038 // Div utility functions
1040 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
1041 std::vector<SDNode*>* Created) const;
1042 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
1043 std::vector<SDNode*>* Created) const;
1046 //===--------------------------------------------------------------------===//
1047 // Runtime Library hooks
1050 /// setLibcallName - Rename the default libcall routine name for the specified
1052 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1053 LibcallRoutineNames[Call] = Name;
1056 /// getLibcallName - Get the libcall routine name for the specified libcall.
1058 const char *getLibcallName(RTLIB::Libcall Call) const {
1059 return LibcallRoutineNames[Call];
1062 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1063 /// result of the comparison libcall against zero.
1064 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1065 CmpLibcallCCs[Call] = CC;
1068 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1069 /// the comparison libcall against zero.
1070 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1071 return CmpLibcallCCs[Call];
1076 const TargetData *TD;
1078 /// IsLittleEndian - True if this is a little endian target.
1080 bool IsLittleEndian;
1082 /// PointerTy - The type to use for pointers, usually i32 or i64.
1084 MVT::ValueType PointerTy;
1086 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1088 bool UsesGlobalOffsetTable;
1090 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1092 MVT::ValueType ShiftAmountTy;
1094 OutOfRangeShiftAmount ShiftAmtHandling;
1096 /// SelectIsExpensive - Tells the code generator not to expand operations
1097 /// into sequences that use the select operations if possible.
1098 bool SelectIsExpensive;
1100 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1101 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1102 /// a real cost model is in place. If we ever optimize for size, this will be
1103 /// set to true unconditionally.
1106 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1107 /// srl/add/sra for a signed divide by power of two, and let the target handle
1109 bool Pow2DivIsCheap;
1111 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
1113 MVT::ValueType SetCCResultTy;
1115 /// SetCCResultContents - Information about the contents of the high-bits in
1116 /// the result of a setcc comparison operation.
1117 SetCCResultValue SetCCResultContents;
1119 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1120 /// total cycles or lowest register usage.
1121 SchedPreference SchedPreferenceInfo;
1123 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1124 /// llvm.setjmp. Defaults to false.
1125 bool UseUnderscoreSetJmp;
1127 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1128 /// llvm.longjmp. Defaults to false.
1129 bool UseUnderscoreLongJmp;
1131 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1132 unsigned JumpBufSize;
1134 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1136 unsigned JumpBufAlignment;
1138 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1140 unsigned IfCvtBlockSizeLimit;
1142 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1143 /// duplicated during if-conversion.
1144 unsigned IfCvtDupBlockSizeLimit;
1146 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1147 /// specifies the register that llvm.savestack/llvm.restorestack should save
1149 unsigned StackPointerRegisterToSaveRestore;
1151 /// ExceptionPointerRegister - If set to a physical register, this specifies
1152 /// the register that receives the exception address on entry to a landing
1154 unsigned ExceptionPointerRegister;
1156 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1157 /// the register that receives the exception typeid on entry to a landing
1159 unsigned ExceptionSelectorRegister;
1161 /// RegClassForVT - This indicates the default register class to use for
1162 /// each ValueType the target supports natively.
1163 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1164 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1165 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1167 /// TransformToType - For any value types we are promoting or expanding, this
1168 /// contains the value type that we are changing to. For Expanded types, this
1169 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1170 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1171 /// by the system, this holds the same type (e.g. i32 -> i32).
1172 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1174 /// OpActions - For each operation and each value type, keep a LegalizeAction
1175 /// that indicates how instruction selection should deal with the operation.
1176 /// Most operations are Legal (aka, supported natively by the target), but
1177 /// operations that are not should be described. Note that operations on
1178 /// non-legal value types are not described here.
1179 uint64_t OpActions[156];
1181 /// LoadXActions - For each load of load extension type and each value type,
1182 /// keep a LegalizeAction that indicates how instruction selection should deal
1184 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1186 /// StoreXActions - For each store with truncation of each value type, keep a
1187 /// LegalizeAction that indicates how instruction selection should deal with
1189 uint64_t StoreXActions;
1191 /// IndexedModeActions - For each indexed mode and each value type, keep a
1192 /// pair of LegalizeAction that indicates how instruction selection should
1193 /// deal with the load / store.
1194 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1196 /// ConvertActions - For each conversion from source type to destination type,
1197 /// keep a LegalizeAction that indicates how instruction selection should
1198 /// deal with the conversion.
1199 /// Currently, this is used only for floating->floating conversions
1200 /// (FP_EXTEND and FP_ROUND).
1201 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1203 ValueTypeActionImpl ValueTypeActions;
1205 std::vector<APFloat> LegalFPImmediates;
1207 std::vector<std::pair<MVT::ValueType,
1208 TargetRegisterClass*> > AvailableRegClasses;
1210 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1211 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1212 /// which sets a bit in this array.
1213 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1215 /// PromoteToType - For operations that must be promoted to a specific type,
1216 /// this holds the destination type. This map should be sparse, so don't hold
1219 /// Targets add entries to this map with AddPromotedToType(..), clients access
1220 /// this with getTypeToPromoteTo(..).
1221 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1223 /// LibcallRoutineNames - Stores the name each libcall.
1225 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1227 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1228 /// of each of the comparison libcall against zero.
1229 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1232 /// When lowering %llvm.memset this field specifies the maximum number of
1233 /// store operations that may be substituted for the call to memset. Targets
1234 /// must set this value based on the cost threshold for that target. Targets
1235 /// should assume that the memset will be done using as many of the largest
1236 /// store operations first, followed by smaller ones, if necessary, per
1237 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1238 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1239 /// store. This only applies to setting a constant array of a constant size.
1240 /// @brief Specify maximum number of store instructions per memset call.
1241 unsigned maxStoresPerMemset;
1243 /// When lowering %llvm.memcpy this field specifies the maximum number of
1244 /// store operations that may be substituted for a call to memcpy. Targets
1245 /// must set this value based on the cost threshold for that target. Targets
1246 /// should assume that the memcpy will be done using as many of the largest
1247 /// store operations first, followed by smaller ones, if necessary, per
1248 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1249 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1250 /// and one 1-byte store. This only applies to copying a constant array of
1252 /// @brief Specify maximum bytes of store instructions per memcpy call.
1253 unsigned maxStoresPerMemcpy;
1255 /// When lowering %llvm.memmove this field specifies the maximum number of
1256 /// store instructions that may be substituted for a call to memmove. Targets
1257 /// must set this value based on the cost threshold for that target. Targets
1258 /// should assume that the memmove will be done using as many of the largest
1259 /// store operations first, followed by smaller ones, if necessary, per
1260 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1261 /// with 8-bit alignment would result in nine 1-byte stores. This only
1262 /// applies to copying a constant array of constant size.
1263 /// @brief Specify maximum bytes of store instructions per memmove call.
1264 unsigned maxStoresPerMemmove;
1266 /// This field specifies whether the target machine permits unaligned memory
1267 /// accesses. This is used, for example, to determine the size of store
1268 /// operations when copying small arrays and other similar tasks.
1269 /// @brief Indicate whether the target permits unaligned memory accesses.
1270 bool allowUnalignedMemoryAccesses;
1272 } // end llvm namespace