1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they
130 /// should expand to.
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
164 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
166 virtual bool useSoftFloat() const { return false; }
168 /// Return the pointer type for the given address space, defaults to
169 /// the pointer type from the data layout.
170 /// FIXME: The default needs to be removed once all the code is updated.
171 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
172 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
173 unsigned getPointerTypeSizeInBits(Type *Ty) const;
174 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
176 EVT getShiftAmountTy(EVT LHSTy) const;
178 /// Returns the type to be used for the index operand of:
179 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
180 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
181 virtual MVT getVectorIdxTy() const {
182 return getPointerTy();
185 /// Return true if the select operation is expensive for this target.
186 bool isSelectExpensive() const { return SelectIsExpensive; }
188 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
192 /// Return true if multiple condition registers are available.
193 bool hasMultipleConditionRegisters() const {
194 return HasMultipleConditionRegisters;
197 /// Return true if the target has BitExtract instructions.
198 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
200 /// Return the preferred vector type legalization action.
201 virtual TargetLoweringBase::LegalizeTypeAction
202 getPreferredVectorAction(EVT VT) const {
203 // The default action for one element vectors is to scalarize
204 if (VT.getVectorNumElements() == 1)
205 return TypeScalarizeVector;
206 // The default action for other vectors is to promote
207 return TypePromoteInteger;
210 // There are two general methods for expanding a BUILD_VECTOR node:
211 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
213 // 2. Build the vector on the stack and then load it.
214 // If this function returns true, then method (1) will be used, subject to
215 // the constraint that all of the necessary shuffles are legal (as determined
216 // by isShuffleMaskLegal). If this function returns false, then method (2) is
217 // always used. The vector type, and the number of defined values, are
220 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
221 unsigned DefinedValues) const {
222 return DefinedValues < 3;
225 /// Return true if integer divide is usually cheaper than a sequence of
226 /// several shifts, adds, and multiplies for this target.
227 bool isIntDivCheap() const { return IntDivIsCheap; }
229 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
230 bool isFsqrtCheap() const {
234 /// Returns true if target has indicated at least one type should be bypassed.
235 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
237 /// Returns map of slow types for division or remainder with corresponding
239 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
240 return BypassSlowDivWidths;
243 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
244 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
246 /// Return true if Flow Control is an expensive operation that should be
248 bool isJumpExpensive() const { return JumpIsExpensive; }
250 /// Return true if selects are only cheaper than branches if the branch is
251 /// unlikely to be predicted right.
252 bool isPredictableSelectExpensive() const {
253 return PredictableSelectIsExpensive;
256 /// isLoadBitCastBeneficial() - Return true if the following transform
258 /// fold (conv (load x)) -> (load (conv*)x)
259 /// On architectures that don't natively support some vector loads
260 /// efficiently, casting the load to a smaller vector of larger types and
261 /// loading is more efficient, however, this can be undone by optimizations in
263 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
264 EVT /* Bitcast */) const {
268 /// Return true if it is expected to be cheaper to do a store of a non-zero
269 /// vector constant with the given size and type for the address space than to
270 /// store the individual scalar element constants.
271 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
273 unsigned AddrSpace) const {
277 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
278 virtual bool isCheapToSpeculateCttz() const {
282 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
283 virtual bool isCheapToSpeculateCtlz() const {
287 /// \brief Return if the target supports combining a
290 /// %andResult = and %val1, #imm-with-one-bit-set;
291 /// %icmpResult = icmp %andResult, 0
292 /// br i1 %icmpResult, label %dest1, label %dest2
294 /// into a single machine instruction of a form like:
296 /// brOnBitSet %register, #bitNumber, dest
298 bool isMaskAndBranchFoldingLegal() const {
299 return MaskAndBranchFoldingIsLegal;
302 /// \brief Return true if the target wants to use the optimization that
303 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
304 /// promotedInst1(...(promotedInstN(ext(load)))).
305 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
307 /// Return true if the target can combine store(extractelement VectorTy,
309 /// \p Cost[out] gives the cost of that transformation when this is true.
310 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
311 unsigned &Cost) const {
315 /// Return true if target supports floating point exceptions.
316 bool hasFloatingPointExceptions() const {
317 return HasFloatingPointExceptions;
320 /// Return true if target always beneficiates from combining into FMA for a
321 /// given value type. This must typically return false on targets where FMA
322 /// takes more cycles to execute than FADD.
323 virtual bool enableAggressiveFMAFusion(EVT VT) const {
327 /// Return the ValueType of the result of SETCC operations.
328 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
330 /// Return the ValueType for comparison libcalls. Comparions libcalls include
331 /// floating point comparion calls, and Ordered/Unordered check calls on
332 /// floating point numbers.
334 MVT::SimpleValueType getCmpLibcallReturnType() const;
336 /// For targets without i1 registers, this gives the nature of the high-bits
337 /// of boolean values held in types wider than i1.
339 /// "Boolean values" are special true/false values produced by nodes like
340 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
341 /// Not to be confused with general values promoted from i1. Some cpus
342 /// distinguish between vectors of boolean and scalars; the isVec parameter
343 /// selects between the two kinds. For example on X86 a scalar boolean should
344 /// be zero extended from i1, while the elements of a vector of booleans
345 /// should be sign extended from i1.
347 /// Some cpus also treat floating point types the same way as they treat
348 /// vectors instead of the way they treat scalars.
349 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
351 return BooleanVectorContents;
352 return isFloat ? BooleanFloatContents : BooleanContents;
355 BooleanContent getBooleanContents(EVT Type) const {
356 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
359 /// Return target scheduling preference.
360 Sched::Preference getSchedulingPreference() const {
361 return SchedPreferenceInfo;
364 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
365 /// for different nodes. This function returns the preference (or none) for
367 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
371 /// Return the register class that should be used for the specified value
373 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
374 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
375 assert(RC && "This value type is not natively supported!");
379 /// Return the 'representative' register class for the specified value
382 /// The 'representative' register class is the largest legal super-reg
383 /// register class for the register class of the value type. For example, on
384 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
385 /// register class is GR64 on x86_64.
386 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
387 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
391 /// Return the cost of the 'representative' register class for the specified
393 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
394 return RepRegClassCostForVT[VT.SimpleTy];
397 /// Return true if the target has native support for the specified value type.
398 /// This means that it has a register that directly holds it without
399 /// promotions or expansions.
400 bool isTypeLegal(EVT VT) const {
401 assert(!VT.isSimple() ||
402 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
403 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
406 class ValueTypeActionImpl {
407 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
408 /// that indicates how instruction selection should deal with the type.
409 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
412 ValueTypeActionImpl() {
413 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
416 LegalizeTypeAction getTypeAction(MVT VT) const {
417 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
420 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
421 unsigned I = VT.SimpleTy;
422 ValueTypeActions[I] = Action;
426 const ValueTypeActionImpl &getValueTypeActions() const {
427 return ValueTypeActions;
430 /// Return how we should legalize values of this type, either it is already
431 /// legal (return 'Legal') or we need to promote it to a larger type (return
432 /// 'Promote'), or we need to expand it into multiple registers of smaller
433 /// integer type (return 'Expand'). 'Custom' is not an option.
434 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
435 return getTypeConversion(Context, VT).first;
437 LegalizeTypeAction getTypeAction(MVT VT) const {
438 return ValueTypeActions.getTypeAction(VT);
441 /// For types supported by the target, this is an identity function. For
442 /// types that must be promoted to larger types, this returns the larger type
443 /// to promote to. For integer types that are larger than the largest integer
444 /// register, this contains one step in the expansion to get to the smaller
445 /// register. For illegal floating point types, this returns the integer type
447 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
448 return getTypeConversion(Context, VT).second;
451 /// For types supported by the target, this is an identity function. For
452 /// types that must be expanded (i.e. integer types that are larger than the
453 /// largest integer register or illegal floating point types), this returns
454 /// the largest legal type it will be expanded to.
455 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
456 assert(!VT.isVector());
458 switch (getTypeAction(Context, VT)) {
461 case TypeExpandInteger:
462 VT = getTypeToTransformTo(Context, VT);
465 llvm_unreachable("Type is not legal nor is it to be expanded!");
470 /// Vector types are broken down into some number of legal first class types.
471 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
472 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
473 /// turns into 4 EVT::i32 values with both PPC and X86.
475 /// This method returns the number of registers needed, and the VT for each
476 /// register. It also returns the VT and quantity of the intermediate values
477 /// before they are promoted/expanded.
478 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
480 unsigned &NumIntermediates,
481 MVT &RegisterVT) const;
483 struct IntrinsicInfo {
484 unsigned opc; // target opcode
485 EVT memVT; // memory VT
486 const Value* ptrVal; // value representing memory location
487 int offset; // offset off of ptrVal
488 unsigned size; // the size of the memory location
489 // (taken from memVT if zero)
490 unsigned align; // alignment
491 bool vol; // is volatile?
492 bool readMem; // reads memory?
493 bool writeMem; // writes memory?
495 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
496 vol(false), readMem(false), writeMem(false) {}
499 /// Given an intrinsic, checks if on the target the intrinsic will need to map
500 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
501 /// true and store the intrinsic information into the IntrinsicInfo that was
502 /// passed to the function.
503 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
504 unsigned /*Intrinsic*/) const {
508 /// Returns true if the target can instruction select the specified FP
509 /// immediate natively. If false, the legalizer will materialize the FP
510 /// immediate as a load from a constant pool.
511 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
515 /// Targets can use this to indicate that they only support *some*
516 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
517 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
519 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
524 /// Returns true if the operation can trap for the value type.
526 /// VT must be a legal type. By default, we optimistically assume most
527 /// operations don't trap except for divide and remainder.
528 virtual bool canOpTrap(unsigned Op, EVT VT) const;
530 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
531 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
532 /// a VAND with a constant pool entry.
533 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
538 /// Return how this operation should be treated: either it is legal, needs to
539 /// be promoted to a larger size, needs to be expanded to some other code
540 /// sequence, or the target has a custom expander for it.
541 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
542 if (VT.isExtended()) return Expand;
543 // If a target-specific SDNode requires legalization, require the target
544 // to provide custom legalization for it.
545 if (Op > array_lengthof(OpActions[0])) return Custom;
546 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
547 return (LegalizeAction)OpActions[I][Op];
550 /// Return true if the specified operation is legal on this target or can be
551 /// made legal with custom lowering. This is used to help guide high-level
552 /// lowering decisions.
553 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
554 return (VT == MVT::Other || isTypeLegal(VT)) &&
555 (getOperationAction(Op, VT) == Legal ||
556 getOperationAction(Op, VT) == Custom);
559 /// Return true if the specified operation is legal on this target or can be
560 /// made legal using promotion. This is used to help guide high-level lowering
562 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
563 return (VT == MVT::Other || isTypeLegal(VT)) &&
564 (getOperationAction(Op, VT) == Legal ||
565 getOperationAction(Op, VT) == Promote);
568 /// Return true if the specified operation is illegal on this target or
569 /// unlikely to be made legal with custom lowering. This is used to help guide
570 /// high-level lowering decisions.
571 bool isOperationExpand(unsigned Op, EVT VT) const {
572 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
575 /// Return true if the specified operation is legal on this target.
576 bool isOperationLegal(unsigned Op, EVT VT) const {
577 return (VT == MVT::Other || isTypeLegal(VT)) &&
578 getOperationAction(Op, VT) == Legal;
581 /// Return how this load with extension should be treated: either it is legal,
582 /// needs to be promoted to a larger size, needs to be expanded to some other
583 /// code sequence, or the target has a custom expander for it.
584 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
586 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
587 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
588 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
589 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
590 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
591 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
594 /// Return true if the specified load with extension is legal on this target.
595 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
596 return ValVT.isSimple() && MemVT.isSimple() &&
597 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
600 /// Return true if the specified load with extension is legal or custom
602 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
603 return ValVT.isSimple() && MemVT.isSimple() &&
604 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
605 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
608 /// Return how this store with truncation should be treated: either it is
609 /// legal, needs to be promoted to a larger size, needs to be expanded to some
610 /// other code sequence, or the target has a custom expander for it.
611 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
612 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
613 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
614 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
615 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
616 "Table isn't big enough!");
617 return (LegalizeAction)TruncStoreActions[ValI][MemI];
620 /// Return true if the specified store with truncation is legal on this
622 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
623 return isTypeLegal(ValVT) && MemVT.isSimple() &&
624 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
627 /// Return how the indexed load should be treated: either it is legal, needs
628 /// to be promoted to a larger size, needs to be expanded to some other code
629 /// sequence, or the target has a custom expander for it.
631 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
632 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
633 "Table isn't big enough!");
634 unsigned Ty = (unsigned)VT.SimpleTy;
635 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
638 /// Return true if the specified indexed load is legal on this target.
639 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
640 return VT.isSimple() &&
641 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
642 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
645 /// Return how the indexed store should be treated: either it is legal, needs
646 /// to be promoted to a larger size, needs to be expanded to some other code
647 /// sequence, or the target has a custom expander for it.
649 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
650 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
651 "Table isn't big enough!");
652 unsigned Ty = (unsigned)VT.SimpleTy;
653 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
656 /// Return true if the specified indexed load is legal on this target.
657 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
658 return VT.isSimple() &&
659 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
660 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
663 /// Return how the condition code should be treated: either it is legal, needs
664 /// to be expanded to some other code sequence, or the target has a custom
667 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
668 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
669 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
670 "Table isn't big enough!");
671 // See setCondCodeAction for how this is encoded.
672 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
673 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
674 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
675 assert(Action != Promote && "Can't promote condition code!");
679 /// Return true if the specified condition code is legal on this target.
680 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
682 getCondCodeAction(CC, VT) == Legal ||
683 getCondCodeAction(CC, VT) == Custom;
687 /// If the action for this operation is to promote, this method returns the
688 /// ValueType to promote to.
689 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
690 assert(getOperationAction(Op, VT) == Promote &&
691 "This operation isn't promoted!");
693 // See if this has an explicit type specified.
694 std::map<std::pair<unsigned, MVT::SimpleValueType>,
695 MVT::SimpleValueType>::const_iterator PTTI =
696 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
697 if (PTTI != PromoteToType.end()) return PTTI->second;
699 assert((VT.isInteger() || VT.isFloatingPoint()) &&
700 "Cannot autopromote this type, add it with AddPromotedToType.");
704 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
705 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
706 "Didn't find type to promote to!");
707 } while (!isTypeLegal(NVT) ||
708 getOperationAction(Op, NVT) == Promote);
712 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
713 /// operations except for the pointer size. If AllowUnknown is true, this
714 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
715 /// otherwise it will assert.
716 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
717 // Lower scalar pointers to native pointer types.
718 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
719 return getPointerTy(PTy->getAddressSpace());
721 if (Ty->isVectorTy()) {
722 VectorType *VTy = cast<VectorType>(Ty);
723 Type *Elm = VTy->getElementType();
724 // Lower vectors of pointers to native pointer types.
725 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
726 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
727 Elm = PointerTy.getTypeForEVT(Ty->getContext());
730 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
731 VTy->getNumElements());
733 return EVT::getEVT(Ty, AllowUnknown);
736 /// Return the MVT corresponding to this LLVM type. See getValueType.
737 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
738 return getValueType(Ty, AllowUnknown).getSimpleVT();
741 /// Return the desired alignment for ByVal or InAlloca aggregate function
742 /// arguments in the caller parameter area. This is the actual alignment, not
744 virtual unsigned getByValTypeAlignment(Type *Ty) const;
746 /// Return the type of registers that this ValueType will eventually require.
747 MVT getRegisterType(MVT VT) const {
748 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
749 return RegisterTypeForVT[VT.SimpleTy];
752 /// Return the type of registers that this ValueType will eventually require.
753 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
755 assert((unsigned)VT.getSimpleVT().SimpleTy <
756 array_lengthof(RegisterTypeForVT));
757 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
762 unsigned NumIntermediates;
763 (void)getVectorTypeBreakdown(Context, VT, VT1,
764 NumIntermediates, RegisterVT);
767 if (VT.isInteger()) {
768 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
770 llvm_unreachable("Unsupported extended type!");
773 /// Return the number of registers that this ValueType will eventually
776 /// This is one for any types promoted to live in larger registers, but may be
777 /// more than one for types (like i64) that are split into pieces. For types
778 /// like i140, which are first promoted then expanded, it is the number of
779 /// registers needed to hold all the bits of the original type. For an i140
780 /// on a 32 bit machine this means 5 registers.
781 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
783 assert((unsigned)VT.getSimpleVT().SimpleTy <
784 array_lengthof(NumRegistersForVT));
785 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
790 unsigned NumIntermediates;
791 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
793 if (VT.isInteger()) {
794 unsigned BitWidth = VT.getSizeInBits();
795 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
796 return (BitWidth + RegWidth - 1) / RegWidth;
798 llvm_unreachable("Unsupported extended type!");
801 /// If true, then instruction selection should seek to shrink the FP constant
802 /// of the specified type to a smaller type in order to save space and / or
804 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
806 // Return true if it is profitable to reduce the given load node to a smaller
809 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
810 virtual bool shouldReduceLoadWidth(SDNode *Load,
811 ISD::LoadExtType ExtTy,
816 /// When splitting a value of the specified type into parts, does the Lo
817 /// or Hi part come first? This usually follows the endianness, except
818 /// for ppcf128, where the Hi part always comes first.
819 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
820 return DL.isBigEndian() || VT == MVT::ppcf128;
823 /// If true, the target has custom DAG combine transformations that it can
824 /// perform for the specified node.
825 bool hasTargetDAGCombine(ISD::NodeType NT) const {
826 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
827 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
830 /// \brief Get maximum # of store operations permitted for llvm.memset
832 /// This function returns the maximum number of store operations permitted
833 /// to replace a call to llvm.memset. The value is set by the target at the
834 /// performance threshold for such a replacement. If OptSize is true,
835 /// return the limit for functions that have OptSize attribute.
836 unsigned getMaxStoresPerMemset(bool OptSize) const {
837 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
840 /// \brief Get maximum # of store operations permitted for llvm.memcpy
842 /// This function returns the maximum number of store operations permitted
843 /// to replace a call to llvm.memcpy. The value is set by the target at the
844 /// performance threshold for such a replacement. If OptSize is true,
845 /// return the limit for functions that have OptSize attribute.
846 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
847 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
850 /// \brief Get maximum # of store operations permitted for llvm.memmove
852 /// This function returns the maximum number of store operations permitted
853 /// to replace a call to llvm.memmove. The value is set by the target at the
854 /// performance threshold for such a replacement. If OptSize is true,
855 /// return the limit for functions that have OptSize attribute.
856 unsigned getMaxStoresPerMemmove(bool OptSize) const {
857 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
860 /// \brief Determine if the target supports unaligned memory accesses.
862 /// This function returns true if the target allows unaligned memory accesses
863 /// of the specified type in the given address space. If true, it also returns
864 /// whether the unaligned memory access is "fast" in the last argument by
865 /// reference. This is used, for example, in situations where an array
866 /// copy/move/set is converted to a sequence of store operations. Its use
867 /// helps to ensure that such replacements don't generate code that causes an
868 /// alignment error (trap) on the target machine.
869 virtual bool allowsMisalignedMemoryAccesses(EVT,
870 unsigned AddrSpace = 0,
872 bool * /*Fast*/ = nullptr) const {
876 /// Returns the target specific optimal type for load and store operations as
877 /// a result of memset, memcpy, and memmove lowering.
879 /// If DstAlign is zero that means it's safe to destination alignment can
880 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
881 /// a need to check it against alignment requirement, probably because the
882 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
883 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
884 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
885 /// does not need to be loaded. It returns EVT::Other if the type should be
886 /// determined using generic target-independent logic.
887 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
888 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
891 bool /*MemcpyStrSrc*/,
892 MachineFunction &/*MF*/) const {
896 /// Returns true if it's safe to use load / store of the specified type to
897 /// expand memcpy / memset inline.
899 /// This is mostly true for all types except for some special cases. For
900 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
901 /// fstpl which also does type conversion. Note the specified type doesn't
902 /// have to be legal as the hook is used before type legalization.
903 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
905 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
906 bool usesUnderscoreSetJmp() const {
907 return UseUnderscoreSetJmp;
910 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
911 bool usesUnderscoreLongJmp() const {
912 return UseUnderscoreLongJmp;
915 /// Return integer threshold on number of blocks to use jump tables rather
916 /// than if sequence.
917 int getMinimumJumpTableEntries() const {
918 return MinimumJumpTableEntries;
921 /// If a physical register, this specifies the register that
922 /// llvm.savestack/llvm.restorestack should save and restore.
923 unsigned getStackPointerRegisterToSaveRestore() const {
924 return StackPointerRegisterToSaveRestore;
927 /// If a physical register, this returns the register that receives the
928 /// exception address on entry to a landing pad.
929 unsigned getExceptionPointerRegister() const {
930 return ExceptionPointerRegister;
933 /// If a physical register, this returns the register that receives the
934 /// exception typeid on entry to a landing pad.
935 unsigned getExceptionSelectorRegister() const {
936 return ExceptionSelectorRegister;
939 /// Returns the target's jmp_buf size in bytes (if never set, the default is
941 unsigned getJumpBufSize() const {
945 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
947 unsigned getJumpBufAlignment() const {
948 return JumpBufAlignment;
951 /// Return the minimum stack alignment of an argument.
952 unsigned getMinStackArgumentAlignment() const {
953 return MinStackArgumentAlignment;
956 /// Return the minimum function alignment.
957 unsigned getMinFunctionAlignment() const {
958 return MinFunctionAlignment;
961 /// Return the preferred function alignment.
962 unsigned getPrefFunctionAlignment() const {
963 return PrefFunctionAlignment;
966 /// Return the preferred loop alignment.
967 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
968 return PrefLoopAlignment;
971 /// Return whether the DAG builder should automatically insert fences and
972 /// reduce ordering for atomics.
973 bool getInsertFencesForAtomic() const {
974 return InsertFencesForAtomic;
977 /// Return true if the target stores stack protector cookies at a fixed offset
978 /// in some non-standard address space, and populates the address space and
979 /// offset as appropriate.
980 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
981 unsigned &/*Offset*/) const {
985 /// Returns true if a cast between SrcAS and DestAS is a noop.
986 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
990 /// Return true if the pointer arguments to CI should be aligned by aligning
991 /// the object whose address is being passed. If so then MinSize is set to the
992 /// minimum size the object must be to be aligned and PrefAlign is set to the
993 /// preferred alignment.
994 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
995 unsigned & /*PrefAlign*/) const {
999 //===--------------------------------------------------------------------===//
1000 /// \name Helpers for TargetTransformInfo implementations
1003 /// Get the ISD node that corresponds to the Instruction class opcode.
1004 int InstructionOpcodeToISD(unsigned Opcode) const;
1006 /// Estimate the cost of type-legalization and the legalized type.
1007 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
1011 //===--------------------------------------------------------------------===//
1012 /// \name Helpers for atomic expansion.
1015 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1016 /// and expand AtomicCmpXchgInst.
1017 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1019 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1020 /// corresponding pointee type. This may entail some non-trivial operations to
1021 /// truncate or reconstruct types that will be illegal in the backend. See
1022 /// ARMISelLowering for an example implementation.
1023 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1024 AtomicOrdering Ord) const {
1025 llvm_unreachable("Load linked unimplemented on this target");
1028 /// Perform a store-conditional operation to Addr. Return the status of the
1029 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1030 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1031 Value *Addr, AtomicOrdering Ord) const {
1032 llvm_unreachable("Store conditional unimplemented on this target");
1035 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1036 /// It is called by AtomicExpandPass before expanding an
1037 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1038 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1039 /// This function should either return a nullptr, or a pointer to an IR-level
1040 /// Instruction*. Even complex fence sequences can be represented by a
1041 /// single Instruction* through an intrinsic to be lowered later.
1042 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1043 /// Backends should override this method to produce target-specific intrinsic
1044 /// for their fences.
1045 /// FIXME: Please note that the default implementation here in terms of
1046 /// IR-level fences exists for historical/compatibility reasons and is
1047 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1048 /// consistency. For example, consider the following example:
1049 /// atomic<int> x = y = 0;
1050 /// int r1, r2, r3, r4;
1061 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1062 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1063 /// IR-level fences can prevent it.
1065 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1066 AtomicOrdering Ord, bool IsStore,
1067 bool IsLoad) const {
1068 if (!getInsertFencesForAtomic())
1071 if (isAtLeastRelease(Ord) && IsStore)
1072 return Builder.CreateFence(Ord);
1077 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1078 AtomicOrdering Ord, bool IsStore,
1079 bool IsLoad) const {
1080 if (!getInsertFencesForAtomic())
1083 if (isAtLeastAcquire(Ord))
1084 return Builder.CreateFence(Ord);
1090 /// Returns true if the given (atomic) store should be expanded by the
1091 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1092 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1096 /// Returns true if arguments should be sign-extended in lib calls.
1097 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1101 /// Returns true if the given (atomic) load should be expanded by the
1102 /// IR-level AtomicExpand pass into a load-linked instruction
1103 /// (through emitLoadLinked()).
1104 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1106 /// Returns how the IR-level AtomicExpand pass should expand the given
1107 /// AtomicRMW, if at all. Default is to never expand.
1108 virtual AtomicRMWExpansionKind
1109 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1110 return AtomicRMWExpansionKind::None;
1113 /// On some platforms, an AtomicRMW that never actually modifies the value
1114 /// (such as fetch_add of 0) can be turned into a fence followed by an
1115 /// atomic load. This may sound useless, but it makes it possible for the
1116 /// processor to keep the cacheline shared, dramatically improving
1117 /// performance. And such idempotent RMWs are useful for implementing some
1118 /// kinds of locks, see for example (justification + benchmarks):
1119 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1120 /// This method tries doing that transformation, returning the atomic load if
1121 /// it succeeds, and nullptr otherwise.
1122 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1123 /// another round of expansion.
1125 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1129 /// Returns true if we should normalize
1130 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1131 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1132 /// that it saves us from materializing N0 and N1 in an integer register.
1133 /// Targets that are able to perform and/or on flags should return false here.
1134 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1136 // If a target has multiple condition registers, then it likely has logical
1137 // operations on those registers.
1138 if (hasMultipleConditionRegisters())
1140 // Only do the transform if the value won't be split into multiple
1142 LegalizeTypeAction Action = getTypeAction(Context, VT);
1143 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1144 Action != TypeSplitVector;
1147 //===--------------------------------------------------------------------===//
1148 // TargetLowering Configuration Methods - These methods should be invoked by
1149 // the derived class constructor to configure this object for the target.
1152 /// Specify how the target extends the result of integer and floating point
1153 /// boolean values from i1 to a wider type. See getBooleanContents.
1154 void setBooleanContents(BooleanContent Ty) {
1155 BooleanContents = Ty;
1156 BooleanFloatContents = Ty;
1159 /// Specify how the target extends the result of integer and floating point
1160 /// boolean values from i1 to a wider type. See getBooleanContents.
1161 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1162 BooleanContents = IntTy;
1163 BooleanFloatContents = FloatTy;
1166 /// Specify how the target extends the result of a vector boolean value from a
1167 /// vector of i1 to a wider type. See getBooleanContents.
1168 void setBooleanVectorContents(BooleanContent Ty) {
1169 BooleanVectorContents = Ty;
1172 /// Specify the target scheduling preference.
1173 void setSchedulingPreference(Sched::Preference Pref) {
1174 SchedPreferenceInfo = Pref;
1177 /// Indicate whether this target prefers to use _setjmp to implement
1178 /// llvm.setjmp or the version without _. Defaults to false.
1179 void setUseUnderscoreSetJmp(bool Val) {
1180 UseUnderscoreSetJmp = Val;
1183 /// Indicate whether this target prefers to use _longjmp to implement
1184 /// llvm.longjmp or the version without _. Defaults to false.
1185 void setUseUnderscoreLongJmp(bool Val) {
1186 UseUnderscoreLongJmp = Val;
1189 /// Indicate the number of blocks to generate jump tables rather than if
1191 void setMinimumJumpTableEntries(int Val) {
1192 MinimumJumpTableEntries = Val;
1195 /// If set to a physical register, this specifies the register that
1196 /// llvm.savestack/llvm.restorestack should save and restore.
1197 void setStackPointerRegisterToSaveRestore(unsigned R) {
1198 StackPointerRegisterToSaveRestore = R;
1201 /// If set to a physical register, this sets the register that receives the
1202 /// exception address on entry to a landing pad.
1203 void setExceptionPointerRegister(unsigned R) {
1204 ExceptionPointerRegister = R;
1207 /// If set to a physical register, this sets the register that receives the
1208 /// exception typeid on entry to a landing pad.
1209 void setExceptionSelectorRegister(unsigned R) {
1210 ExceptionSelectorRegister = R;
1213 /// Tells the code generator not to expand operations into sequences that use
1214 /// the select operations if possible.
1215 void setSelectIsExpensive(bool isExpensive = true) {
1216 SelectIsExpensive = isExpensive;
1219 /// Tells the code generator that the target has multiple (allocatable)
1220 /// condition registers that can be used to store the results of comparisons
1221 /// for use by selects and conditional branches. With multiple condition
1222 /// registers, the code generator will not aggressively sink comparisons into
1223 /// the blocks of their users.
1224 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1225 HasMultipleConditionRegisters = hasManyRegs;
1228 /// Tells the code generator that the target has BitExtract instructions.
1229 /// The code generator will aggressively sink "shift"s into the blocks of
1230 /// their users if the users will generate "and" instructions which can be
1231 /// combined with "shift" to BitExtract instructions.
1232 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1233 HasExtractBitsInsn = hasExtractInsn;
1236 /// Tells the code generator not to expand logic operations on comparison
1237 /// predicates into separate sequences that increase the amount of flow
1239 void setJumpIsExpensive(bool isExpensive = true);
1241 /// Tells the code generator that integer divide is expensive, and if
1242 /// possible, should be replaced by an alternate sequence of instructions not
1243 /// containing an integer divide.
1244 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1246 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1247 /// with an alternative sequence of instructions.
1248 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1250 /// Tells the code generator that this target supports floating point
1251 /// exceptions and cares about preserving floating point exception behavior.
1252 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1253 HasFloatingPointExceptions = FPExceptions;
1256 /// Tells the code generator which bitwidths to bypass.
1257 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1258 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1261 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1262 /// signed divide by power of two; let the target handle it.
1263 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1265 /// Add the specified register class as an available regclass for the
1266 /// specified value type. This indicates the selector can handle values of
1267 /// that class natively.
1268 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1269 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1270 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1271 RegClassForVT[VT.SimpleTy] = RC;
1274 /// Remove all register classes.
1275 void clearRegisterClasses() {
1276 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1278 AvailableRegClasses.clear();
1281 /// \brief Remove all operation actions.
1282 void clearOperationActions() {
1285 /// Return the largest legal super-reg register class of the register class
1286 /// for the specified type and its associated "cost".
1287 virtual std::pair<const TargetRegisterClass *, uint8_t>
1288 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1290 /// Once all of the register classes are added, this allows us to compute
1291 /// derived properties we expose.
1292 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1294 /// Indicate that the specified operation does not work with the specified
1295 /// type and indicate what to do about it.
1296 void setOperationAction(unsigned Op, MVT VT,
1297 LegalizeAction Action) {
1298 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1299 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1302 /// Indicate that the specified load with extension does not work with the
1303 /// specified type and indicate what to do about it.
1304 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1305 LegalizeAction Action) {
1306 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1307 MemVT.isValid() && "Table isn't big enough!");
1308 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1311 /// Indicate that the specified truncating store does not work with the
1312 /// specified type and indicate what to do about it.
1313 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1314 LegalizeAction Action) {
1315 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1316 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1319 /// Indicate that the specified indexed load does or does not work with the
1320 /// specified type and indicate what to do abort it.
1322 /// NOTE: All indexed mode loads are initialized to Expand in
1323 /// TargetLowering.cpp
1324 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1325 LegalizeAction Action) {
1326 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1327 (unsigned)Action < 0xf && "Table isn't big enough!");
1328 // Load action are kept in the upper half.
1329 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1330 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1333 /// Indicate that the specified indexed store does or does not work with the
1334 /// specified type and indicate what to do about it.
1336 /// NOTE: All indexed mode stores are initialized to Expand in
1337 /// TargetLowering.cpp
1338 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1339 LegalizeAction Action) {
1340 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1341 (unsigned)Action < 0xf && "Table isn't big enough!");
1342 // Store action are kept in the lower half.
1343 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1344 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1347 /// Indicate that the specified condition code is or isn't supported on the
1348 /// target and indicate what to do about it.
1349 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1350 LegalizeAction Action) {
1351 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1352 "Table isn't big enough!");
1353 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1354 /// value and the upper 27 bits index into the second dimension of the array
1355 /// to select what 32-bit value to use.
1356 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1357 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1358 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1361 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1362 /// to trying a larger integer/fp until it can find one that works. If that
1363 /// default is insufficient, this method can be used by the target to override
1365 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1366 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1369 /// Targets should invoke this method for each target independent node that
1370 /// they want to provide a custom DAG combiner for by implementing the
1371 /// PerformDAGCombine virtual method.
1372 void setTargetDAGCombine(ISD::NodeType NT) {
1373 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1374 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1377 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1378 void setJumpBufSize(unsigned Size) {
1382 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1384 void setJumpBufAlignment(unsigned Align) {
1385 JumpBufAlignment = Align;
1388 /// Set the target's minimum function alignment (in log2(bytes))
1389 void setMinFunctionAlignment(unsigned Align) {
1390 MinFunctionAlignment = Align;
1393 /// Set the target's preferred function alignment. This should be set if
1394 /// there is a performance benefit to higher-than-minimum alignment (in
1396 void setPrefFunctionAlignment(unsigned Align) {
1397 PrefFunctionAlignment = Align;
1400 /// Set the target's preferred loop alignment. Default alignment is zero, it
1401 /// means the target does not care about loop alignment. The alignment is
1402 /// specified in log2(bytes). The target may also override
1403 /// getPrefLoopAlignment to provide per-loop values.
1404 void setPrefLoopAlignment(unsigned Align) {
1405 PrefLoopAlignment = Align;
1408 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1409 void setMinStackArgumentAlignment(unsigned Align) {
1410 MinStackArgumentAlignment = Align;
1413 /// Set if the DAG builder should automatically insert fences and reduce the
1414 /// order of atomic memory operations to Monotonic.
1415 void setInsertFencesForAtomic(bool fence) {
1416 InsertFencesForAtomic = fence;
1420 //===--------------------------------------------------------------------===//
1421 // Addressing mode description hooks (used by LSR etc).
1424 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1425 /// instructions reading the address. This allows as much computation as
1426 /// possible to be done in the address mode for that operand. This hook lets
1427 /// targets also pass back when this should be done on intrinsics which
1429 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1430 SmallVectorImpl<Value*> &/*Ops*/,
1431 Type *&/*AccessTy*/,
1432 unsigned AddrSpace = 0) const {
1436 /// This represents an addressing mode of:
1437 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1438 /// If BaseGV is null, there is no BaseGV.
1439 /// If BaseOffs is zero, there is no base offset.
1440 /// If HasBaseReg is false, there is no base register.
1441 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1444 GlobalValue *BaseGV;
1448 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1451 /// Return true if the addressing mode represented by AM is legal for this
1452 /// target, for a load/store of the specified type.
1454 /// The type may be VoidTy, in which case only return true if the addressing
1455 /// mode is legal for a load/store of any legal type. TODO: Handle
1456 /// pre/postinc as well.
1458 /// If the address space cannot be determined, it will be -1.
1460 /// TODO: Remove default argument
1461 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
1462 unsigned AddrSpace) const;
1464 /// \brief Return the cost of the scaling factor used in the addressing mode
1465 /// represented by AM for this target, for a load/store of the specified type.
1467 /// If the AM is supported, the return value must be >= 0.
1468 /// If the AM is not supported, it returns a negative value.
1469 /// TODO: Handle pre/postinc as well.
1470 /// TODO: Remove default argument
1471 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty,
1472 unsigned AS = 0) const {
1473 // Default: assume that any scaling factor used in a legal AM is free.
1474 if (isLegalAddressingMode(AM, Ty, AS))
1479 /// Return true if the specified immediate is legal icmp immediate, that is
1480 /// the target has icmp instructions which can compare a register against the
1481 /// immediate without having to materialize the immediate into a register.
1482 virtual bool isLegalICmpImmediate(int64_t) const {
1486 /// Return true if the specified immediate is legal add immediate, that is the
1487 /// target has add instructions which can add a register with the immediate
1488 /// without having to materialize the immediate into a register.
1489 virtual bool isLegalAddImmediate(int64_t) const {
1493 /// Return true if it's significantly cheaper to shift a vector by a uniform
1494 /// scalar than by an amount which will vary across each lane. On x86, for
1495 /// example, there is a "psllw" instruction for the former case, but no simple
1496 /// instruction for a general "a << b" operation on vectors.
1497 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1501 /// Return true if it's free to truncate a value of type Ty1 to type
1502 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1503 /// by referencing its sub-register AX.
1504 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1508 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1509 /// whether a call is in tail position. Typically this means that both results
1510 /// would be assigned to the same register or stack slot, but it could mean
1511 /// the target performs adequate checks of its own before proceeding with the
1513 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1517 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1521 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1523 /// Return true if the extension represented by \p I is free.
1524 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1525 /// this method can use the context provided by \p I to decide
1526 /// whether or not \p I is free.
1527 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1528 /// In other words, if is[Z|FP]Free returns true, then this method
1529 /// returns true as well. The converse is not true.
1530 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1531 /// \pre \p I must be a sign, zero, or fp extension.
1532 bool isExtFree(const Instruction *I) const {
1533 switch (I->getOpcode()) {
1534 case Instruction::FPExt:
1535 if (isFPExtFree(EVT::getEVT(I->getType())))
1538 case Instruction::ZExt:
1539 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1542 case Instruction::SExt:
1545 llvm_unreachable("Instruction is not an extension");
1547 return isExtFreeImpl(I);
1550 /// Return true if any actual instruction that defines a value of type Ty1
1551 /// implicitly zero-extends the value to Ty2 in the result register.
1553 /// This does not necessarily include registers defined in unknown ways, such
1554 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1555 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1556 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1557 /// values implicit zero-extend the result out to 64 bits.
1558 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1562 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1566 /// Return true if the target supplies and combines to a paired load
1567 /// two loaded values of type LoadedType next to each other in memory.
1568 /// RequiredAlignment gives the minimal alignment constraints that must be met
1569 /// to be able to select this paired load.
1571 /// This information is *not* used to generate actual paired loads, but it is
1572 /// used to generate a sequence of loads that is easier to combine into a
1574 /// For instance, something like this:
1575 /// a = load i64* addr
1576 /// b = trunc i64 a to i32
1577 /// c = lshr i64 a, 32
1578 /// d = trunc i64 c to i32
1579 /// will be optimized into:
1580 /// b = load i32* addr1
1581 /// d = load i32* addr2
1582 /// Where addr1 = addr2 +/- sizeof(i32).
1584 /// In other words, unless the target performs a post-isel load combining,
1585 /// this information should not be provided because it will generate more
1587 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1588 unsigned & /*RequiredAligment*/) const {
1592 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1593 unsigned & /*RequiredAligment*/) const {
1597 /// \brief Get the maximum supported factor for interleaved memory accesses.
1598 /// Default to be the minimum interleave factor: 2.
1599 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1601 /// \brief Lower an interleaved load to target specific intrinsics. Return
1602 /// true on success.
1604 /// \p LI is the vector load instruction.
1605 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1606 /// \p Indices is the corresponding indices for each shufflevector.
1607 /// \p Factor is the interleave factor.
1608 virtual bool lowerInterleavedLoad(LoadInst *LI,
1609 ArrayRef<ShuffleVectorInst *> Shuffles,
1610 ArrayRef<unsigned> Indices,
1611 unsigned Factor) const {
1615 /// \brief Lower an interleaved store to target specific intrinsics. Return
1616 /// true on success.
1618 /// \p SI is the vector store instruction.
1619 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1620 /// \p Factor is the interleave factor.
1621 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1622 unsigned Factor) const {
1626 /// Return true if zero-extending the specific node Val to type VT2 is free
1627 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1628 /// because it's folded such as X86 zero-extending loads).
1629 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1630 return isZExtFree(Val.getValueType(), VT2);
1633 /// Return true if an fpext operation is free (for instance, because
1634 /// single-precision floating-point numbers are implicitly extended to
1635 /// double-precision).
1636 virtual bool isFPExtFree(EVT VT) const {
1637 assert(VT.isFloatingPoint());
1641 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1642 /// extend node) is profitable.
1643 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1645 /// Return true if an fneg operation is free to the point where it is never
1646 /// worthwhile to replace it with a bitwise operation.
1647 virtual bool isFNegFree(EVT VT) const {
1648 assert(VT.isFloatingPoint());
1652 /// Return true if an fabs operation is free to the point where it is never
1653 /// worthwhile to replace it with a bitwise operation.
1654 virtual bool isFAbsFree(EVT VT) const {
1655 assert(VT.isFloatingPoint());
1659 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1660 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1661 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1663 /// NOTE: This may be called before legalization on types for which FMAs are
1664 /// not legal, but should return true if those types will eventually legalize
1665 /// to types that support FMAs. After legalization, it will only be called on
1666 /// types that support FMAs (via Legal or Custom actions)
1667 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1671 /// Return true if it's profitable to narrow operations of type VT1 to
1672 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1674 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1678 /// \brief Return true if it is beneficial to convert a load of a constant to
1679 /// just the constant itself.
1680 /// On some targets it might be more efficient to use a combination of
1681 /// arithmetic instructions to materialize the constant instead of loading it
1682 /// from a constant pool.
1683 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1688 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1689 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1690 /// has custom lowering that depends on the index of the first element,
1691 /// and only the target knows which lowering is cheap.
1692 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1696 //===--------------------------------------------------------------------===//
1697 // Runtime Library hooks
1700 /// Rename the default libcall routine name for the specified libcall.
1701 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1702 LibcallRoutineNames[Call] = Name;
1705 /// Get the libcall routine name for the specified libcall.
1706 const char *getLibcallName(RTLIB::Libcall Call) const {
1707 return LibcallRoutineNames[Call];
1710 /// Override the default CondCode to be used to test the result of the
1711 /// comparison libcall against zero.
1712 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1713 CmpLibcallCCs[Call] = CC;
1716 /// Get the CondCode that's to be used to test the result of the comparison
1717 /// libcall against zero.
1718 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1719 return CmpLibcallCCs[Call];
1722 /// Set the CallingConv that should be used for the specified libcall.
1723 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1724 LibcallCallingConvs[Call] = CC;
1727 /// Get the CallingConv that should be used for the specified libcall.
1728 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1729 return LibcallCallingConvs[Call];
1733 const TargetMachine &TM;
1735 /// Tells the code generator not to expand operations into sequences that use
1736 /// the select operations if possible.
1737 bool SelectIsExpensive;
1739 /// Tells the code generator that the target has multiple (allocatable)
1740 /// condition registers that can be used to store the results of comparisons
1741 /// for use by selects and conditional branches. With multiple condition
1742 /// registers, the code generator will not aggressively sink comparisons into
1743 /// the blocks of their users.
1744 bool HasMultipleConditionRegisters;
1746 /// Tells the code generator that the target has BitExtract instructions.
1747 /// The code generator will aggressively sink "shift"s into the blocks of
1748 /// their users if the users will generate "and" instructions which can be
1749 /// combined with "shift" to BitExtract instructions.
1750 bool HasExtractBitsInsn;
1752 /// Tells the code generator not to expand integer divides by constants into a
1753 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1754 /// model is in place. If we ever optimize for size, this will be set to true
1755 /// unconditionally.
1758 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1761 /// Tells the code generator to bypass slow divide or remainder
1762 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1763 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1764 /// div/rem when the operands are positive and less than 256.
1765 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1767 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1768 /// signed divide by power of two; let the target handle it.
1769 bool Pow2SDivIsCheap;
1771 /// Tells the code generator that it shouldn't generate extra flow control
1772 /// instructions and should attempt to combine flow control instructions via
1774 bool JumpIsExpensive;
1776 /// Whether the target supports or cares about preserving floating point
1777 /// exception behavior.
1778 bool HasFloatingPointExceptions;
1780 /// This target prefers to use _setjmp to implement llvm.setjmp.
1782 /// Defaults to false.
1783 bool UseUnderscoreSetJmp;
1785 /// This target prefers to use _longjmp to implement llvm.longjmp.
1787 /// Defaults to false.
1788 bool UseUnderscoreLongJmp;
1790 /// Number of blocks threshold to use jump tables.
1791 int MinimumJumpTableEntries;
1793 /// Information about the contents of the high-bits in boolean values held in
1794 /// a type wider than i1. See getBooleanContents.
1795 BooleanContent BooleanContents;
1797 /// Information about the contents of the high-bits in boolean values held in
1798 /// a type wider than i1. See getBooleanContents.
1799 BooleanContent BooleanFloatContents;
1801 /// Information about the contents of the high-bits in boolean vector values
1802 /// when the element type is wider than i1. See getBooleanContents.
1803 BooleanContent BooleanVectorContents;
1805 /// The target scheduling preference: shortest possible total cycles or lowest
1807 Sched::Preference SchedPreferenceInfo;
1809 /// The size, in bytes, of the target's jmp_buf buffers
1810 unsigned JumpBufSize;
1812 /// The alignment, in bytes, of the target's jmp_buf buffers
1813 unsigned JumpBufAlignment;
1815 /// The minimum alignment that any argument on the stack needs to have.
1816 unsigned MinStackArgumentAlignment;
1818 /// The minimum function alignment (used when optimizing for size, and to
1819 /// prevent explicitly provided alignment from leading to incorrect code).
1820 unsigned MinFunctionAlignment;
1822 /// The preferred function alignment (used when alignment unspecified and
1823 /// optimizing for speed).
1824 unsigned PrefFunctionAlignment;
1826 /// The preferred loop alignment.
1827 unsigned PrefLoopAlignment;
1829 /// Whether the DAG builder should automatically insert fences and reduce
1830 /// ordering for atomics. (This will be set for for most architectures with
1831 /// weak memory ordering.)
1832 bool InsertFencesForAtomic;
1834 /// If set to a physical register, this specifies the register that
1835 /// llvm.savestack/llvm.restorestack should save and restore.
1836 unsigned StackPointerRegisterToSaveRestore;
1838 /// If set to a physical register, this specifies the register that receives
1839 /// the exception address on entry to a landing pad.
1840 unsigned ExceptionPointerRegister;
1842 /// If set to a physical register, this specifies the register that receives
1843 /// the exception typeid on entry to a landing pad.
1844 unsigned ExceptionSelectorRegister;
1846 /// This indicates the default register class to use for each ValueType the
1847 /// target supports natively.
1848 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1849 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1850 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1852 /// This indicates the "representative" register class to use for each
1853 /// ValueType the target supports natively. This information is used by the
1854 /// scheduler to track register pressure. By default, the representative
1855 /// register class is the largest legal super-reg register class of the
1856 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1857 /// representative class would be GR32.
1858 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1860 /// This indicates the "cost" of the "representative" register class for each
1861 /// ValueType. The cost is used by the scheduler to approximate register
1863 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1865 /// For any value types we are promoting or expanding, this contains the value
1866 /// type that we are changing to. For Expanded types, this contains one step
1867 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1868 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1869 /// the same type (e.g. i32 -> i32).
1870 MVT TransformToType[MVT::LAST_VALUETYPE];
1872 /// For each operation and each value type, keep a LegalizeAction that
1873 /// indicates how instruction selection should deal with the operation. Most
1874 /// operations are Legal (aka, supported natively by the target), but
1875 /// operations that are not should be described. Note that operations on
1876 /// non-legal value types are not described here.
1877 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1879 /// For each load extension type and each value type, keep a LegalizeAction
1880 /// that indicates how instruction selection should deal with a load of a
1881 /// specific value type and extension type.
1882 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1883 [ISD::LAST_LOADEXT_TYPE];
1885 /// For each value type pair keep a LegalizeAction that indicates whether a
1886 /// truncating store of a specific value type and truncating type is legal.
1887 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1889 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1890 /// that indicates how instruction selection should deal with the load /
1893 /// The first dimension is the value_type for the reference. The second
1894 /// dimension represents the various modes for load store.
1895 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1897 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1898 /// indicates how instruction selection should deal with the condition code.
1900 /// Because each CC action takes up 2 bits, we need to have the array size be
1901 /// large enough to fit all of the value types. This can be done by rounding
1902 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1903 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1905 ValueTypeActionImpl ValueTypeActions;
1908 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1911 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1913 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1914 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1917 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1919 /// For operations that must be promoted to a specific type, this holds the
1920 /// destination type. This map should be sparse, so don't hold it as an
1923 /// Targets add entries to this map with AddPromotedToType(..), clients access
1924 /// this with getTypeToPromoteTo(..).
1925 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1928 /// Stores the name each libcall.
1929 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1931 /// The ISD::CondCode that should be used to test the result of each of the
1932 /// comparison libcall against zero.
1933 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1935 /// Stores the CallingConv that should be used for each libcall.
1936 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1939 /// Return true if the extension represented by \p I is free.
1940 /// \pre \p I is a sign, zero, or fp extension and
1941 /// is[Z|FP]ExtFree of the related types is not true.
1942 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1944 /// \brief Specify maximum number of store instructions per memset call.
1946 /// When lowering \@llvm.memset this field specifies the maximum number of
1947 /// store operations that may be substituted for the call to memset. Targets
1948 /// must set this value based on the cost threshold for that target. Targets
1949 /// should assume that the memset will be done using as many of the largest
1950 /// store operations first, followed by smaller ones, if necessary, per
1951 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1952 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1953 /// store. This only applies to setting a constant array of a constant size.
1954 unsigned MaxStoresPerMemset;
1956 /// Maximum number of stores operations that may be substituted for the call
1957 /// to memset, used for functions with OptSize attribute.
1958 unsigned MaxStoresPerMemsetOptSize;
1960 /// \brief Specify maximum bytes of store instructions per memcpy call.
1962 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1963 /// store operations that may be substituted for a call to memcpy. Targets
1964 /// must set this value based on the cost threshold for that target. Targets
1965 /// should assume that the memcpy will be done using as many of the largest
1966 /// store operations first, followed by smaller ones, if necessary, per
1967 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1968 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1969 /// and one 1-byte store. This only applies to copying a constant array of
1971 unsigned MaxStoresPerMemcpy;
1973 /// Maximum number of store operations that may be substituted for a call to
1974 /// memcpy, used for functions with OptSize attribute.
1975 unsigned MaxStoresPerMemcpyOptSize;
1977 /// \brief Specify maximum bytes of store instructions per memmove call.
1979 /// When lowering \@llvm.memmove this field specifies the maximum number of
1980 /// store instructions that may be substituted for a call to memmove. Targets
1981 /// must set this value based on the cost threshold for that target. Targets
1982 /// should assume that the memmove will be done using as many of the largest
1983 /// store operations first, followed by smaller ones, if necessary, per
1984 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1985 /// with 8-bit alignment would result in nine 1-byte stores. This only
1986 /// applies to copying a constant array of constant size.
1987 unsigned MaxStoresPerMemmove;
1989 /// Maximum number of store instructions that may be substituted for a call to
1990 /// memmove, used for functions with OpSize attribute.
1991 unsigned MaxStoresPerMemmoveOptSize;
1993 /// Tells the code generator that select is more expensive than a branch if
1994 /// the branch is usually predicted right.
1995 bool PredictableSelectIsExpensive;
1997 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1998 /// a mask of a single bit, a compare, and a branch into a single instruction.
1999 bool MaskAndBranchFoldingIsLegal;
2001 /// \see enableExtLdPromotion.
2002 bool EnableExtLdPromotion;
2005 /// Return true if the value types that can be represented by the specified
2006 /// register class are all legal.
2007 bool isLegalRC(const TargetRegisterClass *RC) const;
2009 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2010 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2011 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
2012 MachineBasicBlock *MBB) const;
2015 /// This class defines information used to lower LLVM code to legal SelectionDAG
2016 /// operators that the target instruction selector can accept natively.
2018 /// This class also defines callbacks that targets must implement to lower
2019 /// target-specific constructs to SelectionDAG operators.
2020 class TargetLowering : public TargetLoweringBase {
2021 TargetLowering(const TargetLowering&) = delete;
2022 void operator=(const TargetLowering&) = delete;
2025 /// NOTE: The TargetMachine owns TLOF.
2026 explicit TargetLowering(const TargetMachine &TM);
2028 /// Returns true by value, base pointer and offset pointer and addressing mode
2029 /// by reference if the node's address can be legally represented as
2030 /// pre-indexed load / store address.
2031 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2032 SDValue &/*Offset*/,
2033 ISD::MemIndexedMode &/*AM*/,
2034 SelectionDAG &/*DAG*/) const {
2038 /// Returns true by value, base pointer and offset pointer and addressing mode
2039 /// by reference if this node can be combined with a load / store to form a
2040 /// post-indexed load / store.
2041 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2043 SDValue &/*Offset*/,
2044 ISD::MemIndexedMode &/*AM*/,
2045 SelectionDAG &/*DAG*/) const {
2049 /// Return the entry encoding for a jump table in the current function. The
2050 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2051 virtual unsigned getJumpTableEncoding() const;
2053 virtual const MCExpr *
2054 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2055 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2056 MCContext &/*Ctx*/) const {
2057 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2060 /// Returns relocation base for the given PIC jumptable.
2061 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2062 SelectionDAG &DAG) const;
2064 /// This returns the relocation base for the given PIC jumptable, the same as
2065 /// getPICJumpTableRelocBase, but as an MCExpr.
2066 virtual const MCExpr *
2067 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2068 unsigned JTI, MCContext &Ctx) const;
2070 /// Return true if folding a constant offset with the given GlobalAddress is
2071 /// legal. It is frequently not legal in PIC relocation models.
2072 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2074 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2075 SDValue &Chain) const;
2077 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2078 SDValue &NewLHS, SDValue &NewRHS,
2079 ISD::CondCode &CCCode, SDLoc DL) const;
2081 /// Returns a pair of (return value, chain).
2082 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2083 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2084 EVT RetVT, const SDValue *Ops,
2085 unsigned NumOps, bool isSigned,
2086 SDLoc dl, bool doesNotReturn = false,
2087 bool isReturnValueUsed = true) const;
2089 //===--------------------------------------------------------------------===//
2090 // TargetLowering Optimization Methods
2093 /// A convenience struct that encapsulates a DAG, and two SDValues for
2094 /// returning information from TargetLowering to its clients that want to
2096 struct TargetLoweringOpt {
2103 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2105 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2107 bool LegalTypes() const { return LegalTys; }
2108 bool LegalOperations() const { return LegalOps; }
2110 bool CombineTo(SDValue O, SDValue N) {
2116 /// Check to see if the specified operand of the specified instruction is a
2117 /// constant integer. If so, check to see if there are any bits set in the
2118 /// constant that are not demanded. If so, shrink the constant and return
2120 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2122 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2123 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2124 /// generalized for targets with other types of implicit widening casts.
2125 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2129 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2130 /// result of Op are ever used downstream. If we can use this information to
2131 /// simplify Op, create a new simplified DAG node and return true, returning
2132 /// the original and new nodes in Old and New. Otherwise, analyze the
2133 /// expression and return a mask of KnownOne and KnownZero bits for the
2134 /// expression (used to simplify the caller). The KnownZero/One bits may only
2135 /// be accurate for those bits in the DemandedMask.
2136 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2137 APInt &KnownZero, APInt &KnownOne,
2138 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2140 /// Determine which of the bits specified in Mask are known to be either zero
2141 /// or one and return them in the KnownZero/KnownOne bitsets.
2142 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2145 const SelectionDAG &DAG,
2146 unsigned Depth = 0) const;
2148 /// This method can be implemented by targets that want to expose additional
2149 /// information about sign bits to the DAG Combiner.
2150 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2151 const SelectionDAG &DAG,
2152 unsigned Depth = 0) const;
2154 struct DAGCombinerInfo {
2155 void *DC; // The DAG Combiner object.
2157 bool CalledByLegalizer;
2161 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2162 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2164 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2165 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2166 bool isAfterLegalizeVectorOps() const {
2167 return Level == AfterLegalizeDAG;
2169 CombineLevel getDAGCombineLevel() { return Level; }
2170 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2172 void AddToWorklist(SDNode *N);
2173 void RemoveFromWorklist(SDNode *N);
2174 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2175 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2176 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2178 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2181 /// Return if the N is a constant or constant vector equal to the true value
2182 /// from getBooleanContents().
2183 bool isConstTrueVal(const SDNode *N) const;
2185 /// Return if the N is a constant or constant vector equal to the false value
2186 /// from getBooleanContents().
2187 bool isConstFalseVal(const SDNode *N) const;
2189 /// Try to simplify a setcc built with the specified operands and cc. If it is
2190 /// unable to simplify it, return a null SDValue.
2191 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2192 ISD::CondCode Cond, bool foldBooleans,
2193 DAGCombinerInfo &DCI, SDLoc dl) const;
2195 /// Returns true (and the GlobalValue and the offset) if the node is a
2196 /// GlobalAddress + offset.
2198 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2200 /// This method will be invoked for all target nodes and for any
2201 /// target-independent nodes that the target has registered with invoke it
2204 /// The semantics are as follows:
2206 /// SDValue.Val == 0 - No change was made
2207 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2208 /// otherwise - N should be replaced by the returned Operand.
2210 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2211 /// more complex transformations.
2213 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2215 /// Return true if it is profitable to move a following shift through this
2216 // node, adjusting any immediate operands as necessary to preserve semantics.
2217 // This transformation may not be desirable if it disrupts a particularly
2218 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2219 // By default, it returns true.
2220 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2224 /// Return true if the target has native support for the specified value type
2225 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2226 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2227 /// and some i16 instructions are slow.
2228 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2229 // By default, assume all legal types are desirable.
2230 return isTypeLegal(VT);
2233 /// Return true if it is profitable for dag combiner to transform a floating
2234 /// point op of specified opcode to a equivalent op of an integer
2235 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2236 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2241 /// This method query the target whether it is beneficial for dag combiner to
2242 /// promote the specified node. If true, it should return the desired
2243 /// promotion type by reference.
2244 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2248 //===--------------------------------------------------------------------===//
2249 // Lowering methods - These methods must be implemented by targets so that
2250 // the SelectionDAGBuilder code knows how to lower these.
2253 /// This hook must be implemented to lower the incoming (formal) arguments,
2254 /// described by the Ins array, into the specified DAG. The implementation
2255 /// should fill in the InVals array with legal-type argument values, and
2256 /// return the resulting token chain value.
2259 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2261 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2262 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2263 SmallVectorImpl<SDValue> &/*InVals*/) const {
2264 llvm_unreachable("Not Implemented");
2267 struct ArgListEntry {
2276 bool isInAlloca : 1;
2277 bool isReturned : 1;
2280 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2281 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2282 isReturned(false), Alignment(0) { }
2284 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2286 typedef std::vector<ArgListEntry> ArgListTy;
2288 /// This structure contains all information that is necessary for lowering
2289 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2290 /// needs to lower a call, and targets will see this struct in their LowerCall
2292 struct CallLoweringInfo {
2299 bool DoesNotReturn : 1;
2300 bool IsReturnValueUsed : 1;
2302 // IsTailCall should be modified by implementations of
2303 // TargetLowering::LowerCall that perform tail call conversions.
2306 unsigned NumFixedArgs;
2307 CallingConv::ID CallConv;
2312 ImmutableCallSite *CS;
2314 SmallVector<ISD::OutputArg, 32> Outs;
2315 SmallVector<SDValue, 32> OutVals;
2316 SmallVector<ISD::InputArg, 32> Ins;
2318 CallLoweringInfo(SelectionDAG &DAG)
2319 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2320 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2321 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2322 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2324 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2329 CallLoweringInfo &setChain(SDValue InChain) {
2334 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2335 SDValue Target, ArgListTy &&ArgsList,
2336 unsigned FixedArgs = -1) {
2341 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2342 Args = std::move(ArgsList);
2346 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2347 SDValue Target, ArgListTy &&ArgsList,
2348 ImmutableCallSite &Call) {
2351 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2352 DoesNotReturn = Call.doesNotReturn();
2353 IsVarArg = FTy->isVarArg();
2354 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2355 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2356 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2360 CallConv = Call.getCallingConv();
2361 NumFixedArgs = FTy->getNumParams();
2362 Args = std::move(ArgsList);
2369 CallLoweringInfo &setInRegister(bool Value = true) {
2374 CallLoweringInfo &setNoReturn(bool Value = true) {
2375 DoesNotReturn = Value;
2379 CallLoweringInfo &setVarArg(bool Value = true) {
2384 CallLoweringInfo &setTailCall(bool Value = true) {
2389 CallLoweringInfo &setDiscardResult(bool Value = true) {
2390 IsReturnValueUsed = !Value;
2394 CallLoweringInfo &setSExtResult(bool Value = true) {
2399 CallLoweringInfo &setZExtResult(bool Value = true) {
2404 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2405 IsPatchPoint = Value;
2409 ArgListTy &getArgs() {
2415 /// This function lowers an abstract call to a function into an actual call.
2416 /// This returns a pair of operands. The first element is the return value
2417 /// for the function (if RetTy is not VoidTy). The second element is the
2418 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2419 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2421 /// This hook must be implemented to lower calls into the specified
2422 /// DAG. The outgoing arguments to the call are described by the Outs array,
2423 /// and the values to be returned by the call are described by the Ins
2424 /// array. The implementation should fill in the InVals array with legal-type
2425 /// return values from the call, and return the resulting token chain value.
2427 LowerCall(CallLoweringInfo &/*CLI*/,
2428 SmallVectorImpl<SDValue> &/*InVals*/) const {
2429 llvm_unreachable("Not Implemented");
2432 /// Target-specific cleanup for formal ByVal parameters.
2433 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2435 /// This hook should be implemented to check whether the return values
2436 /// described by the Outs array can fit into the return registers. If false
2437 /// is returned, an sret-demotion is performed.
2438 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2439 MachineFunction &/*MF*/, bool /*isVarArg*/,
2440 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2441 LLVMContext &/*Context*/) const
2443 // Return true by default to get preexisting behavior.
2447 /// This hook must be implemented to lower outgoing return values, described
2448 /// by the Outs array, into the specified DAG. The implementation should
2449 /// return the resulting token chain value.
2451 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2453 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2454 const SmallVectorImpl<SDValue> &/*OutVals*/,
2455 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2456 llvm_unreachable("Not Implemented");
2459 /// Return true if result of the specified node is used by a return node
2460 /// only. It also compute and return the input chain for the tail call.
2462 /// This is used to determine whether it is possible to codegen a libcall as
2463 /// tail call at legalization time.
2464 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2468 /// Return true if the target may be able emit the call instruction as a tail
2469 /// call. This is used by optimization passes to determine if it's profitable
2470 /// to duplicate return instructions to enable tailcall optimization.
2471 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2475 /// Return the builtin name for the __builtin___clear_cache intrinsic
2476 /// Default is to invoke the clear cache library call
2477 virtual const char * getClearCacheBuiltinName() const {
2478 return "__clear_cache";
2481 /// Return the register ID of the name passed in. Used by named register
2482 /// global variables extension. There is no target-independent behaviour
2483 /// so the default action is to bail.
2484 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2485 report_fatal_error("Named registers not implemented for this target");
2488 /// Return the type that should be used to zero or sign extend a
2489 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2490 /// convention requires the return type to be promoted, but this is not true
2491 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2492 /// calling conventions. The frontend should handle this and include all of
2493 /// the necessary information.
2494 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2495 ISD::NodeType /*ExtendKind*/) const {
2496 EVT MinVT = getRegisterType(Context, MVT::i32);
2497 return VT.bitsLT(MinVT) ? MinVT : VT;
2500 /// For some targets, an LLVM struct type must be broken down into multiple
2501 /// simple types, but the calling convention specifies that the entire struct
2502 /// must be passed in a block of consecutive registers.
2504 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2505 bool isVarArg) const {
2509 /// Returns a 0 terminated array of registers that can be safely used as
2510 /// scratch registers.
2511 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2515 /// This callback is used to prepare for a volatile or atomic load.
2516 /// It takes a chain node as input and returns the chain for the load itself.
2518 /// Having a callback like this is necessary for targets like SystemZ,
2519 /// which allows a CPU to reuse the result of a previous load indefinitely,
2520 /// even if a cache-coherent store is performed by another CPU. The default
2521 /// implementation does nothing.
2522 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2523 SelectionDAG &DAG) const {
2527 /// This callback is invoked by the type legalizer to legalize nodes with an
2528 /// illegal operand type but legal result types. It replaces the
2529 /// LowerOperation callback in the type Legalizer. The reason we can not do
2530 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2531 /// use this callback.
2533 /// TODO: Consider merging with ReplaceNodeResults.
2535 /// The target places new result values for the node in Results (their number
2536 /// and types must exactly match those of the original return values of
2537 /// the node), or leaves Results empty, which indicates that the node is not
2538 /// to be custom lowered after all.
2539 /// The default implementation calls LowerOperation.
2540 virtual void LowerOperationWrapper(SDNode *N,
2541 SmallVectorImpl<SDValue> &Results,
2542 SelectionDAG &DAG) const;
2544 /// This callback is invoked for operations that are unsupported by the
2545 /// target, which are registered to use 'custom' lowering, and whose defined
2546 /// values are all legal. If the target has no operations that require custom
2547 /// lowering, it need not implement this. The default implementation of this
2549 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2551 /// This callback is invoked when a node result type is illegal for the
2552 /// target, and the operation was registered to use 'custom' lowering for that
2553 /// result type. The target places new result values for the node in Results
2554 /// (their number and types must exactly match those of the original return
2555 /// values of the node), or leaves Results empty, which indicates that the
2556 /// node is not to be custom lowered after all.
2558 /// If the target has no operations that require custom lowering, it need not
2559 /// implement this. The default implementation aborts.
2560 virtual void ReplaceNodeResults(SDNode * /*N*/,
2561 SmallVectorImpl<SDValue> &/*Results*/,
2562 SelectionDAG &/*DAG*/) const {
2563 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2566 /// This method returns the name of a target specific DAG node.
2567 virtual const char *getTargetNodeName(unsigned Opcode) const;
2569 /// This method returns a target specific FastISel object, or null if the
2570 /// target does not support "fast" ISel.
2571 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2572 const TargetLibraryInfo *) const {
2577 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2578 SelectionDAG &DAG) const;
2580 //===--------------------------------------------------------------------===//
2581 // Inline Asm Support hooks
2584 /// This hook allows the target to expand an inline asm call to be explicit
2585 /// llvm code if it wants to. This is useful for turning simple inline asms
2586 /// into LLVM intrinsics, which gives the compiler more information about the
2587 /// behavior of the code.
2588 virtual bool ExpandInlineAsm(CallInst *) const {
2592 enum ConstraintType {
2593 C_Register, // Constraint represents specific register(s).
2594 C_RegisterClass, // Constraint represents any of register(s) in class.
2595 C_Memory, // Memory constraint.
2596 C_Other, // Something else.
2597 C_Unknown // Unsupported constraint.
2600 enum ConstraintWeight {
2602 CW_Invalid = -1, // No match.
2603 CW_Okay = 0, // Acceptable.
2604 CW_Good = 1, // Good weight.
2605 CW_Better = 2, // Better weight.
2606 CW_Best = 3, // Best weight.
2608 // Well-known weights.
2609 CW_SpecificReg = CW_Okay, // Specific register operands.
2610 CW_Register = CW_Good, // Register operands.
2611 CW_Memory = CW_Better, // Memory operands.
2612 CW_Constant = CW_Best, // Constant operand.
2613 CW_Default = CW_Okay // Default or don't know type.
2616 /// This contains information for each constraint that we are lowering.
2617 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2618 /// This contains the actual string for the code, like "m". TargetLowering
2619 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2620 /// matches the operand.
2621 std::string ConstraintCode;
2623 /// Information about the constraint code, e.g. Register, RegisterClass,
2624 /// Memory, Other, Unknown.
2625 TargetLowering::ConstraintType ConstraintType;
2627 /// If this is the result output operand or a clobber, this is null,
2628 /// otherwise it is the incoming operand to the CallInst. This gets
2629 /// modified as the asm is processed.
2630 Value *CallOperandVal;
2632 /// The ValueType for the operand value.
2635 /// Return true of this is an input operand that is a matching constraint
2637 bool isMatchingInputConstraint() const;
2639 /// If this is an input matching constraint, this method returns the output
2640 /// operand it matches.
2641 unsigned getMatchedOperand() const;
2643 /// Copy constructor for copying from a ConstraintInfo.
2644 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2645 : InlineAsm::ConstraintInfo(std::move(Info)),
2646 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2647 ConstraintVT(MVT::Other) {}
2650 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2652 /// Split up the constraint string from the inline assembly value into the
2653 /// specific constraints and their prefixes, and also tie in the associated
2654 /// operand values. If this returns an empty vector, and if the constraint
2655 /// string itself isn't empty, there was an error parsing.
2656 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2657 const TargetRegisterInfo *TRI,
2658 ImmutableCallSite CS) const;
2660 /// Examine constraint type and operand type and determine a weight value.
2661 /// The operand object must already have been set up with the operand type.
2662 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2663 AsmOperandInfo &info, int maIndex) const;
2665 /// Examine constraint string and operand type and determine a weight value.
2666 /// The operand object must already have been set up with the operand type.
2667 virtual ConstraintWeight getSingleConstraintMatchWeight(
2668 AsmOperandInfo &info, const char *constraint) const;
2670 /// Determines the constraint code and constraint type to use for the specific
2671 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2672 /// If the actual operand being passed in is available, it can be passed in as
2673 /// Op, otherwise an empty SDValue can be passed.
2674 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2676 SelectionDAG *DAG = nullptr) const;
2678 /// Given a constraint, return the type of constraint it is for this target.
2679 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2681 /// Given a physical register constraint (e.g. {edx}), return the register
2682 /// number and the register class for the register.
2684 /// Given a register class constraint, like 'r', if this corresponds directly
2685 /// to an LLVM register class, return a register of 0 and the register class
2688 /// This should only be used for C_Register constraints. On error, this
2689 /// returns a register number of 0 and a null register class pointer.
2690 virtual std::pair<unsigned, const TargetRegisterClass *>
2691 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2692 StringRef Constraint, MVT VT) const;
2694 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2695 if (ConstraintCode == "i")
2696 return InlineAsm::Constraint_i;
2697 else if (ConstraintCode == "m")
2698 return InlineAsm::Constraint_m;
2699 return InlineAsm::Constraint_Unknown;
2702 /// Try to replace an X constraint, which matches anything, with another that
2703 /// has more specific requirements based on the type of the corresponding
2704 /// operand. This returns null if there is no replacement to make.
2705 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2707 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2708 /// add anything to Ops.
2709 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2710 std::vector<SDValue> &Ops,
2711 SelectionDAG &DAG) const;
2713 //===--------------------------------------------------------------------===//
2714 // Div utility functions
2716 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2717 bool IsAfterLegalization,
2718 std::vector<SDNode *> *Created) const;
2719 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2720 bool IsAfterLegalization,
2721 std::vector<SDNode *> *Created) const;
2722 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2724 std::vector<SDNode *> *Created) const {
2728 /// Indicate whether this target prefers to combine the given number of FDIVs
2729 /// with the same divisor.
2730 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2734 /// Hooks for building estimates in place of slower divisions and square
2737 /// Return a reciprocal square root estimate value for the input operand.
2738 /// The RefinementSteps output is the number of Newton-Raphson refinement
2739 /// iterations required to generate a sufficient (though not necessarily
2740 /// IEEE-754 compliant) estimate for the value type.
2741 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2742 /// algorithm implementation that uses one constant or two constants.
2743 /// A target may choose to implement its own refinement within this function.
2744 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2745 /// any further refinement of the estimate.
2746 /// An empty SDValue return means no estimate sequence can be created.
2747 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2748 unsigned &RefinementSteps,
2749 bool &UseOneConstNR) const {
2753 /// Return a reciprocal estimate value for the input operand.
2754 /// The RefinementSteps output is the number of Newton-Raphson refinement
2755 /// iterations required to generate a sufficient (though not necessarily
2756 /// IEEE-754 compliant) estimate for the value type.
2757 /// A target may choose to implement its own refinement within this function.
2758 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2759 /// any further refinement of the estimate.
2760 /// An empty SDValue return means no estimate sequence can be created.
2761 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2762 unsigned &RefinementSteps) const {
2766 //===--------------------------------------------------------------------===//
2767 // Legalization utility functions
2770 /// Expand a MUL into two nodes. One that computes the high bits of
2771 /// the result and one that computes the low bits.
2772 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2773 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2774 /// if you want to control how low bits are extracted from the LHS.
2775 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2776 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2777 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2778 /// \returns true if the node has been expanded. false if it has not
2779 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2780 SelectionDAG &DAG, SDValue LL = SDValue(),
2781 SDValue LH = SDValue(), SDValue RL = SDValue(),
2782 SDValue RH = SDValue()) const;
2784 /// Expand float(f32) to SINT(i64) conversion
2785 /// \param N Node to expand
2786 /// \param Result output after conversion
2787 /// \returns True, if the expansion was successful, false otherwise
2788 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2790 //===--------------------------------------------------------------------===//
2791 // Instruction Emitting Hooks
2794 /// This method should be implemented by targets that mark instructions with
2795 /// the 'usesCustomInserter' flag. These instructions are special in various
2796 /// ways, which require special support to insert. The specified MachineInstr
2797 /// is created but not inserted into any basic blocks, and this method is
2798 /// called to expand it into a sequence of instructions, potentially also
2799 /// creating new basic blocks and control flow.
2800 /// As long as the returned basic block is different (i.e., we created a new
2801 /// one), the custom inserter is free to modify the rest of \p MBB.
2802 virtual MachineBasicBlock *
2803 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2805 /// This method should be implemented by targets that mark instructions with
2806 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2807 /// instruction selection by target hooks. e.g. To fill in optional defs for
2808 /// ARM 's' setting instructions.
2810 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2812 /// If this function returns true, SelectionDAGBuilder emits a
2813 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2814 virtual bool useLoadStackGuardNode() const {
2819 /// Given an LLVM IR type and return type attributes, compute the return value
2820 /// EVTs and flags, and optionally also the offsets, if the return value is
2821 /// being lowered to memory.
2822 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
2823 SmallVectorImpl<ISD::OutputArg> &Outs,
2824 const TargetLowering &TLI, const DataLayout &DL);
2826 } // end llvm namespace