1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/Support/DataTypes.h"
36 class TargetRegisterClass;
40 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData &getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// isSetCCExpensive - Return true if the setcc operation is expensive for
92 bool isSetCCExpensive() const { return SetCCIsExpensive; }
94 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
95 /// a sequence of several shifts, adds, and multiplies for this target.
96 bool isIntDivCheap() const { return IntDivIsCheap; }
98 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
100 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
102 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
104 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
106 /// getSetCCResultContents - For targets without boolean registers, this flag
107 /// returns information about the contents of the high-bits in the setcc
109 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
111 /// getSchedulingPreference - Return target scheduling preference.
112 SchedPreference getSchedulingPreference() const {
113 return SchedPreferenceInfo;
116 /// getRegClassFor - Return the register class that should be used for the
117 /// specified value type. This may only be called on legal types.
118 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
119 TargetRegisterClass *RC = RegClassForVT[VT];
120 assert(RC && "This value type is not natively supported!");
124 /// isTypeLegal - Return true if the target has native support for the
125 /// specified value type. This means that it has a register that directly
126 /// holds it without promotions or expansions.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return RegClassForVT[VT] != 0;
131 class ValueTypeActionImpl {
132 /// ValueTypeActions - This is a bitvector that contains two bits for each
133 /// value type, where the two bits correspond to the LegalizeAction enum.
134 /// This can be queried with "getTypeAction(VT)".
135 uint32_t ValueTypeActions[2];
137 ValueTypeActionImpl() {
138 ValueTypeActions[0] = ValueTypeActions[1] = 0;
140 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
141 ValueTypeActions[0] = RHS.ValueTypeActions[0];
142 ValueTypeActions[1] = RHS.ValueTypeActions[1];
145 LegalizeAction getTypeAction(MVT::ValueType VT) const {
146 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
148 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
149 assert(unsigned(VT >> 4) <
150 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
151 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
155 const ValueTypeActionImpl &getValueTypeActions() const {
156 return ValueTypeActions;
159 /// getTypeAction - Return how we should legalize values of this type, either
160 /// it is already legal (return 'Legal') or we need to promote it to a larger
161 /// type (return 'Promote'), or we need to expand it into multiple registers
162 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
163 LegalizeAction getTypeAction(MVT::ValueType VT) const {
164 return ValueTypeActions.getTypeAction(VT);
167 /// getTypeToTransformTo - For types supported by the target, this is an
168 /// identity function. For types that must be promoted to larger types, this
169 /// returns the larger type to promote to. For types that are larger than the
170 /// largest integer register, this contains one step in the expansion to get
171 /// to the smaller register.
172 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
173 return TransformToType[VT];
176 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
177 legal_fpimm_iterator legal_fpimm_begin() const {
178 return LegalFPImmediates.begin();
180 legal_fpimm_iterator legal_fpimm_end() const {
181 return LegalFPImmediates.end();
184 /// getOperationAction - Return how this operation should be treated: either
185 /// it is legal, needs to be promoted to a larger size, needs to be
186 /// expanded to some other code sequence, or the target has a custom expander
188 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
189 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
192 /// isOperationLegal - Return true if the specified operation is legal on this
194 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
195 return getOperationAction(Op, VT) == Legal;
198 /// getTypeToPromoteTo - If the action for this operation is to promote, this
199 /// method returns the ValueType to promote to.
200 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
201 assert(getOperationAction(Op, VT) == Promote &&
202 "This operation isn't promoted!");
203 MVT::ValueType NVT = VT;
205 NVT = (MVT::ValueType)(NVT+1);
206 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
207 "Didn't find type to promote to!");
208 } while (!isTypeLegal(NVT) ||
209 getOperationAction(Op, NVT) == Promote);
213 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
214 /// This is fixed by the LLVM operations except for the pointer size.
215 MVT::ValueType getValueType(const Type *Ty) const {
216 switch (Ty->getTypeID()) {
217 default: assert(0 && "Unknown type!");
218 case Type::VoidTyID: return MVT::isVoid;
219 case Type::BoolTyID: return MVT::i1;
220 case Type::UByteTyID:
221 case Type::SByteTyID: return MVT::i8;
222 case Type::ShortTyID:
223 case Type::UShortTyID: return MVT::i16;
225 case Type::UIntTyID: return MVT::i32;
227 case Type::ULongTyID: return MVT::i64;
228 case Type::FloatTyID: return MVT::f32;
229 case Type::DoubleTyID: return MVT::f64;
230 case Type::PointerTyID: return PointerTy;
231 case Type::PackedTyID: return MVT::Vector;
235 /// getNumElements - Return the number of registers that this ValueType will
236 /// eventually require. This is always one for all non-integer types, is
237 /// one for any types promoted to live in larger registers, but may be more
238 /// than one for types (like i64) that are split into pieces.
239 unsigned getNumElements(MVT::ValueType VT) const {
240 return NumElementsForVT[VT];
243 /// This function returns the maximum number of store operations permitted
244 /// to replace a call to llvm.memset. The value is set by the target at the
245 /// performance threshold for such a replacement.
246 /// @brief Get maximum # of store operations permitted for llvm.memset
247 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
249 /// This function returns the maximum number of store operations permitted
250 /// to replace a call to llvm.memcpy. The value is set by the target at the
251 /// performance threshold for such a replacement.
252 /// @brief Get maximum # of store operations permitted for llvm.memcpy
253 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
255 /// This function returns the maximum number of store operations permitted
256 /// to replace a call to llvm.memmove. The value is set by the target at the
257 /// performance threshold for such a replacement.
258 /// @brief Get maximum # of store operations permitted for llvm.memmove
259 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
261 /// This function returns true if the target allows unaligned memory accesses.
262 /// This is used, for example, in situations where an array copy/move/set is
263 /// converted to a sequence of store operations. It's use helps to ensure that
264 /// such replacements don't generate code that causes an alignment error
265 /// (trap) on the target machine.
266 /// @brief Determine if the target supports unaligned memory accesses.
267 bool allowsUnalignedMemoryAccesses() const {
268 return allowUnalignedMemoryAccesses;
271 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
272 /// to implement llvm.setjmp.
273 bool usesUnderscoreSetJmpLongJmp() const {
274 return UseUnderscoreSetJmpLongJmp;
277 /// getStackPointerRegisterToSaveRestore - If a physical register, this
278 /// specifies the register that llvm.savestack/llvm.restorestack should save
280 unsigned getStackPointerRegisterToSaveRestore() const {
281 return StackPointerRegisterToSaveRestore;
284 //===--------------------------------------------------------------------===//
285 // TargetLowering Optimization Methods
288 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
289 /// SDOperands for returning information from TargetLowering to its clients
290 /// that want to combine
291 struct TargetLoweringOpt {
296 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
298 bool CombineTo(SDOperand O, SDOperand N) {
304 /// ShrinkDemandedConstant - Check to see if the specified operand of the
305 /// specified instruction is a constant integer. If so, check to see if there
306 /// are any bits set in the constant that are not demanded. If so, shrink the
307 /// constant and return true.
308 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
311 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
312 /// use this predicate to simplify operations downstream. Op and Mask are
313 /// known to be the same type.
314 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
317 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
318 /// known to be either zero or one and return them in the KnownZero/KnownOne
319 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
320 /// processing. Targets can implement the computeMaskedBitsForTargetNode
321 /// method, to allow target nodes to be understood.
322 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
323 uint64_t &KnownOne, unsigned Depth = 0) const;
325 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
326 /// DemandedMask bits of the result of Op are ever used downstream. If we can
327 /// use this information to simplify Op, create a new simplified DAG node and
328 /// return true, returning the original and new nodes in Old and New.
329 /// Otherwise, analyze the expression and return a mask of KnownOne and
330 /// KnownZero bits for the expression (used to simplify the caller).
331 /// The KnownZero/One bits may only be accurate for those bits in the
333 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
334 uint64_t &KnownZero, uint64_t &KnownOne,
335 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
337 //===--------------------------------------------------------------------===//
338 // TargetLowering Configuration Methods - These methods should be invoked by
339 // the derived class constructor to configure this object for the target.
344 /// setShiftAmountType - Describe the type that should be used for shift
345 /// amounts. This type defaults to the pointer type.
346 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
348 /// setSetCCResultType - Describe the type that shoudl be used as the result
349 /// of a setcc operation. This defaults to the pointer type.
350 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
352 /// setSetCCResultContents - Specify how the target extends the result of a
353 /// setcc operation in a register.
354 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
356 /// setSchedulingPreference - Specify the target scheduling preference.
357 void setSchedulingPreference(SchedPreference Pref) {
358 SchedPreferenceInfo = Pref;
361 /// setShiftAmountFlavor - Describe how the target handles out of range shift
363 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
364 ShiftAmtHandling = OORSA;
367 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
368 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
369 /// the non _ versions. Defaults to false.
370 void setUseUnderscoreSetJmpLongJmp(bool Val) {
371 UseUnderscoreSetJmpLongJmp = Val;
374 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
375 /// specifies the register that llvm.savestack/llvm.restorestack should save
377 void setStackPointerRegisterToSaveRestore(unsigned R) {
378 StackPointerRegisterToSaveRestore = R;
381 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
382 /// setcc as a conditional branch. This encourages the code generator to fold
383 /// setcc operations into other operations if possible.
384 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
386 /// setIntDivIsCheap - Tells the code generator that integer divide is
387 /// expensive, and if possible, should be replaced by an alternate sequence
388 /// of instructions not containing an integer divide.
389 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
391 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
392 /// srl/add/sra for a signed divide by power of two, and let the target handle
394 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
396 /// addRegisterClass - Add the specified register class as an available
397 /// regclass for the specified value type. This indicates the selector can
398 /// handle values of that class natively.
399 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
400 AvailableRegClasses.push_back(std::make_pair(VT, RC));
401 RegClassForVT[VT] = RC;
404 /// computeRegisterProperties - Once all of the register classes are added,
405 /// this allows us to compute derived properties we expose.
406 void computeRegisterProperties();
408 /// setOperationAction - Indicate that the specified operation does not work
409 /// with the specified type and indicate what to do about it.
410 void setOperationAction(unsigned Op, MVT::ValueType VT,
411 LegalizeAction Action) {
412 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
413 "Table isn't big enough!");
414 OpActions[Op] &= ~(3ULL << VT*2);
415 OpActions[Op] |= Action << VT*2;
418 /// addLegalFPImmediate - Indicate that this target can instruction select
419 /// the specified FP immediate natively.
420 void addLegalFPImmediate(double Imm) {
421 LegalFPImmediates.push_back(Imm);
426 //===--------------------------------------------------------------------===//
427 // Lowering methods - These methods must be implemented by targets so that
428 // the SelectionDAGLowering code knows how to lower these.
431 /// LowerArguments - This hook must be implemented to indicate how we should
432 /// lower the arguments for the specified function, into the specified DAG.
433 virtual std::vector<SDOperand>
434 LowerArguments(Function &F, SelectionDAG &DAG) = 0;
436 /// LowerCallTo - This hook lowers an abstract call to a function into an
437 /// actual call. This returns a pair of operands. The first element is the
438 /// return value for the function (if RetTy is not VoidTy). The second
439 /// element is the outgoing token chain.
440 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
441 virtual std::pair<SDOperand, SDOperand>
442 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
443 unsigned CallingConv, bool isTailCall, SDOperand Callee,
444 ArgListTy &Args, SelectionDAG &DAG) = 0;
446 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
447 /// llvm.frameaddress (depending on the value of the first argument). The
448 /// return values are the result pointer and the resultant token chain. If
449 /// not implemented, both of these intrinsics will return null.
450 virtual std::pair<SDOperand, SDOperand>
451 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
454 /// LowerOperation - This callback is invoked for operations that are
455 /// unsupported by the target, which are registered to use 'custom' lowering,
456 /// and whose defined values are all legal.
457 /// If the target has no operations that require custom lowering, it need not
458 /// implement this. The default implementation of this aborts.
459 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
461 /// CustomPromoteOperation - This callback is invoked for operations that are
462 /// unsupported by the target, are registered to use 'custom' lowering, and
463 /// whose type needs to be promoted.
464 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
466 /// getTargetNodeName() - This method returns the name of a target specific
468 virtual const char *getTargetNodeName(unsigned Opcode) const;
470 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
471 /// Mask are known to be either zero or one and return them in the
472 /// KnownZero/KnownOne bitsets.
473 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
477 unsigned Depth = 0) const;
479 //===--------------------------------------------------------------------===//
480 // Inline Asm Support hooks
483 enum ConstraintType {
484 C_Register, // Constraint represents a single register.
485 C_RegisterClass, // Constraint represents one or more registers.
486 C_Other, // Something else.
487 C_Unknown // Unsupported constraint.
488 // INTEGER, ADDRESS, MEMORY?
491 /// getConstraintType - Given a constraint letter, return the type of
492 /// constraint it is for this target.
493 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
496 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
497 /// return a list of registers that can be used to satisfy the constraint.
498 /// This should only be used for C_RegisterClass constraints.
499 virtual std::vector<unsigned>
500 getRegClassForInlineAsmConstraint(const std::string &Constraint,
501 MVT::ValueType VT) const;
503 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
504 /// {edx}), return the register number and the register class for the
505 /// register. This should only be used for C_Register constraints. On error,
506 /// this returns a register number of 0.
507 virtual std::pair<unsigned, const TargetRegisterClass*>
508 getRegForInlineAsmConstraint(const std::string &Constraint,
509 MVT::ValueType VT) const;
512 /// isOperandValidForConstraint - Return true if the specified SDOperand is
513 /// valid for the specified target constraint letter.
514 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
516 //===--------------------------------------------------------------------===//
520 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
521 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
522 // instructions are special in various ways, which require special support to
523 // insert. The specified MachineInstr is created but not inserted into any
524 // basic blocks, and the scheduler passes ownership of it to this method.
525 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
526 MachineBasicBlock *MBB);
530 const TargetData &TD;
532 /// IsLittleEndian - True if this is a little endian target.
536 /// PointerTy - The type to use for pointers, usually i32 or i64.
538 MVT::ValueType PointerTy;
540 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
542 MVT::ValueType ShiftAmountTy;
544 OutOfRangeShiftAmount ShiftAmtHandling;
546 /// SetCCIsExpensive - This is a short term hack for targets that codegen
547 /// setcc as a conditional branch. This encourages the code generator to fold
548 /// setcc operations into other operations if possible.
549 bool SetCCIsExpensive;
551 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
552 /// constants into a sequence of muls, adds, and shifts. This is a hack until
553 /// a real cost model is in place. If we ever optimize for size, this will be
554 /// set to true unconditionally.
557 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
558 /// srl/add/sra for a signed divide by power of two, and let the target handle
562 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
564 MVT::ValueType SetCCResultTy;
566 /// SetCCResultContents - Information about the contents of the high-bits in
567 /// the result of a setcc comparison operation.
568 SetCCResultValue SetCCResultContents;
570 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
571 /// total cycles or lowest register usage.
572 SchedPreference SchedPreferenceInfo;
574 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
575 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
576 bool UseUnderscoreSetJmpLongJmp;
578 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
579 /// specifies the register that llvm.savestack/llvm.restorestack should save
581 unsigned StackPointerRegisterToSaveRestore;
583 /// RegClassForVT - This indicates the default register class to use for
584 /// each ValueType the target supports natively.
585 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
586 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
588 /// TransformToType - For any value types we are promoting or expanding, this
589 /// contains the value type that we are changing to. For Expanded types, this
590 /// contains one step of the expand (e.g. i64 -> i32), even if there are
591 /// multiple steps required (e.g. i64 -> i16). For types natively supported
592 /// by the system, this holds the same type (e.g. i32 -> i32).
593 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
595 /// OpActions - For each operation and each value type, keep a LegalizeAction
596 /// that indicates how instruction selection should deal with the operation.
597 /// Most operations are Legal (aka, supported natively by the target), but
598 /// operations that are not should be described. Note that operations on
599 /// non-legal value types are not described here.
600 uint64_t OpActions[128];
602 ValueTypeActionImpl ValueTypeActions;
604 std::vector<double> LegalFPImmediates;
606 std::vector<std::pair<MVT::ValueType,
607 TargetRegisterClass*> > AvailableRegClasses;
610 /// When lowering %llvm.memset this field specifies the maximum number of
611 /// store operations that may be substituted for the call to memset. Targets
612 /// must set this value based on the cost threshold for that target. Targets
613 /// should assume that the memset will be done using as many of the largest
614 /// store operations first, followed by smaller ones, if necessary, per
615 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
616 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
617 /// store. This only applies to setting a constant array of a constant size.
618 /// @brief Specify maximum number of store instructions per memset call.
619 unsigned maxStoresPerMemset;
621 /// When lowering %llvm.memcpy this field specifies the maximum number of
622 /// store operations that may be substituted for a call to memcpy. Targets
623 /// must set this value based on the cost threshold for that target. Targets
624 /// should assume that the memcpy will be done using as many of the largest
625 /// store operations first, followed by smaller ones, if necessary, per
626 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
627 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
628 /// and one 1-byte store. This only applies to copying a constant array of
630 /// @brief Specify maximum bytes of store instructions per memcpy call.
631 unsigned maxStoresPerMemcpy;
633 /// When lowering %llvm.memmove this field specifies the maximum number of
634 /// store instructions that may be substituted for a call to memmove. Targets
635 /// must set this value based on the cost threshold for that target. Targets
636 /// should assume that the memmove will be done using as many of the largest
637 /// store operations first, followed by smaller ones, if necessary, per
638 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
639 /// with 8-bit alignment would result in nine 1-byte stores. This only
640 /// applies to copying a constant array of constant size.
641 /// @brief Specify maximum bytes of store instructions per memmove call.
642 unsigned maxStoresPerMemmove;
644 /// This field specifies whether the target machine permits unaligned memory
645 /// accesses. This is used, for example, to determine the size of store
646 /// operations when copying small arrays and other similar tasks.
647 /// @brief Indicate whether the target permits unaligned memory accesses.
648 bool allowUnalignedMemoryAccesses;
650 } // end llvm namespace