1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 class TargetRegisterClass;
39 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData *getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
94 /// isSelectExpensive - Return true if the select operation is expensive for
96 bool isSelectExpensive() const { return SelectIsExpensive; }
98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
99 /// a sequence of several shifts, adds, and multiplies for this target.
100 bool isIntDivCheap() const { return IntDivIsCheap; }
102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
104 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
110 /// getSetCCResultContents - For targets without boolean registers, this flag
111 /// returns information about the contents of the high-bits in the setcc
113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
115 /// getSchedulingPreference - Return target scheduling preference.
116 SchedPreference getSchedulingPreference() const {
117 return SchedPreferenceInfo;
120 /// getRegClassFor - Return the register class that should be used for the
121 /// specified value type. This may only be called on legal types.
122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
123 assert(!MVT::isExtendedVT(VT));
124 TargetRegisterClass *RC = RegClassForVT[VT];
125 assert(RC && "This value type is not natively supported!");
129 /// isTypeLegal - Return true if the target has native support for the
130 /// specified value type. This means that it has a register that directly
131 /// holds it without promotions or expansions.
132 bool isTypeLegal(MVT::ValueType VT) const {
133 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
136 class ValueTypeActionImpl {
137 /// ValueTypeActions - This is a bitvector that contains two bits for each
138 /// value type, where the two bits correspond to the LegalizeAction enum.
139 /// This can be queried with "getTypeAction(VT)".
140 uint32_t ValueTypeActions[2];
142 ValueTypeActionImpl() {
143 ValueTypeActions[0] = ValueTypeActions[1] = 0;
145 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
146 ValueTypeActions[0] = RHS.ValueTypeActions[0];
147 ValueTypeActions[1] = RHS.ValueTypeActions[1];
150 LegalizeAction getTypeAction(MVT::ValueType VT) const {
151 if (MVT::isExtendedVT(VT)) return Expand;
152 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
154 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
155 assert(!MVT::isExtendedVT(VT));
156 assert(unsigned(VT >> 4) <
157 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
158 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
162 const ValueTypeActionImpl &getValueTypeActions() const {
163 return ValueTypeActions;
166 /// getTypeAction - Return how we should legalize values of this type, either
167 /// it is already legal (return 'Legal') or we need to promote it to a larger
168 /// type (return 'Promote'), or we need to expand it into multiple registers
169 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
170 LegalizeAction getTypeAction(MVT::ValueType VT) const {
171 return ValueTypeActions.getTypeAction(VT);
174 /// getTypeToTransformTo - For types supported by the target, this is an
175 /// identity function. For types that must be promoted to larger types, this
176 /// returns the larger type to promote to. For integer types that are larger
177 /// than the largest integer register, this contains one step in the expansion
178 /// to get to the smaller register. For illegal floating point types, this
179 /// returns the integer type to transform to.
180 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
181 if (MVT::isExtendedVT(VT))
182 return MVT::getVectorType(MVT::getVectorElementType(VT),
183 MVT::getVectorNumElements(VT) / 2);
185 return TransformToType[VT];
188 /// getTypeToExpandTo - For types supported by the target, this is an
189 /// identity function. For types that must be expanded (i.e. integer types
190 /// that are larger than the largest integer register or illegal floating
191 /// point types), this returns the largest legal type it will be expanded to.
192 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
193 assert(!MVT::isExtendedVT(VT));
195 switch (getTypeAction(VT)) {
199 VT = getTypeToTransformTo(VT);
202 assert(false && "Type is not legal nor is it to be expanded!");
209 /// getVectorTypeBreakdown - Vector types are broken down into some number of
210 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
211 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
212 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
214 /// This method returns the number of registers needed, and the VT for each
215 /// register. It also returns the VT of the VectorType elements before they
216 /// are promoted/expanded.
218 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
219 MVT::ValueType &ElementVT,
220 MVT::ValueType &LegalElementVT) const;
222 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
223 legal_fpimm_iterator legal_fpimm_begin() const {
224 return LegalFPImmediates.begin();
226 legal_fpimm_iterator legal_fpimm_end() const {
227 return LegalFPImmediates.end();
230 /// isShuffleMaskLegal - Targets can use this to indicate that they only
231 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
232 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
233 /// are assumed to be legal.
234 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
238 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
239 /// used by Targets can use this to indicate if there is a suitable
240 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
242 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
244 SelectionDAG &DAG) const {
248 /// getOperationAction - Return how this operation should be treated: either
249 /// it is legal, needs to be promoted to a larger size, needs to be
250 /// expanded to some other code sequence, or the target has a custom expander
252 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
253 if (MVT::isExtendedVT(VT)) return Expand;
254 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
257 /// isOperationLegal - Return true if the specified operation is legal on this
259 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
260 return getOperationAction(Op, VT) == Legal ||
261 getOperationAction(Op, VT) == Custom;
264 /// getLoadXAction - Return how this load with extension should be treated:
265 /// either it is legal, needs to be promoted to a larger size, needs to be
266 /// expanded to some other code sequence, or the target has a custom expander
268 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
269 if (MVT::isExtendedVT(VT)) return Expand;
270 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
273 /// isLoadXLegal - Return true if the specified load with extension is legal
275 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
276 return getLoadXAction(LType, VT) == Legal ||
277 getLoadXAction(LType, VT) == Custom;
280 /// getStoreXAction - Return how this store with truncation should be treated:
281 /// either it is legal, needs to be promoted to a larger size, needs to be
282 /// expanded to some other code sequence, or the target has a custom expander
284 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
285 if (MVT::isExtendedVT(VT)) return Expand;
286 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
289 /// isStoreXLegal - Return true if the specified store with truncation is
290 /// legal on this target.
291 bool isStoreXLegal(MVT::ValueType VT) const {
292 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
295 /// getIndexedLoadAction - Return how the indexed load should be treated:
296 /// either it is legal, needs to be promoted to a larger size, needs to be
297 /// expanded to some other code sequence, or the target has a custom expander
300 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
301 if (MVT::isExtendedVT(VT)) return Expand;
302 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
305 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
307 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
308 return getIndexedLoadAction(IdxMode, VT) == Legal ||
309 getIndexedLoadAction(IdxMode, VT) == Custom;
312 /// getIndexedStoreAction - Return how the indexed store should be treated:
313 /// either it is legal, needs to be promoted to a larger size, needs to be
314 /// expanded to some other code sequence, or the target has a custom expander
317 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
318 if (MVT::isExtendedVT(VT)) return Expand;
319 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
322 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
324 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
325 return getIndexedStoreAction(IdxMode, VT) == Legal ||
326 getIndexedStoreAction(IdxMode, VT) == Custom;
329 /// getTypeToPromoteTo - If the action for this operation is to promote, this
330 /// method returns the ValueType to promote to.
331 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
332 assert(getOperationAction(Op, VT) == Promote &&
333 "This operation isn't promoted!");
335 // See if this has an explicit type specified.
336 std::map<std::pair<unsigned, MVT::ValueType>,
337 MVT::ValueType>::const_iterator PTTI =
338 PromoteToType.find(std::make_pair(Op, VT));
339 if (PTTI != PromoteToType.end()) return PTTI->second;
341 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
342 "Cannot autopromote this type, add it with AddPromotedToType.");
344 MVT::ValueType NVT = VT;
346 NVT = (MVT::ValueType)(NVT+1);
347 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
348 "Didn't find type to promote to!");
349 } while (!isTypeLegal(NVT) ||
350 getOperationAction(Op, NVT) == Promote);
354 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
355 /// This is fixed by the LLVM operations except for the pointer size. If
356 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
357 /// counterpart (e.g. structs), otherwise it will assert.
358 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
359 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
360 return VT == MVT::iPTR ? PointerTy : VT;
363 /// getNumRegisters - Return the number of registers that this ValueType will
364 /// eventually require. This is one for any types promoted to live in larger
365 /// registers, but may be more than one for types (like i64) that are split
367 unsigned getNumRegisters(MVT::ValueType VT) const {
368 if (!MVT::isExtendedVT(VT))
369 return NumRegistersForVT[VT];
371 MVT::ValueType VT1, VT2;
372 return getVectorTypeBreakdown(VT, VT1, VT2);
375 /// hasTargetDAGCombine - If true, the target has custom DAG combine
376 /// transformations that it can perform for the specified node.
377 bool hasTargetDAGCombine(ISD::NodeType NT) const {
378 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
381 /// This function returns the maximum number of store operations permitted
382 /// to replace a call to llvm.memset. The value is set by the target at the
383 /// performance threshold for such a replacement.
384 /// @brief Get maximum # of store operations permitted for llvm.memset
385 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
387 /// This function returns the maximum number of store operations permitted
388 /// to replace a call to llvm.memcpy. The value is set by the target at the
389 /// performance threshold for such a replacement.
390 /// @brief Get maximum # of store operations permitted for llvm.memcpy
391 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
393 /// This function returns the maximum number of store operations permitted
394 /// to replace a call to llvm.memmove. The value is set by the target at the
395 /// performance threshold for such a replacement.
396 /// @brief Get maximum # of store operations permitted for llvm.memmove
397 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
399 /// This function returns true if the target allows unaligned memory accesses.
400 /// This is used, for example, in situations where an array copy/move/set is
401 /// converted to a sequence of store operations. It's use helps to ensure that
402 /// such replacements don't generate code that causes an alignment error
403 /// (trap) on the target machine.
404 /// @brief Determine if the target supports unaligned memory accesses.
405 bool allowsUnalignedMemoryAccesses() const {
406 return allowUnalignedMemoryAccesses;
409 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
410 /// to implement llvm.setjmp.
411 bool usesUnderscoreSetJmp() const {
412 return UseUnderscoreSetJmp;
415 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
416 /// to implement llvm.longjmp.
417 bool usesUnderscoreLongJmp() const {
418 return UseUnderscoreLongJmp;
421 /// getStackPointerRegisterToSaveRestore - If a physical register, this
422 /// specifies the register that llvm.savestack/llvm.restorestack should save
424 unsigned getStackPointerRegisterToSaveRestore() const {
425 return StackPointerRegisterToSaveRestore;
428 /// getExceptionAddressRegister - If a physical register, this returns
429 /// the register that receives the exception address on entry to a landing
431 unsigned getExceptionAddressRegister() const {
432 return ExceptionPointerRegister;
435 /// getExceptionSelectorRegister - If a physical register, this returns
436 /// the register that receives the exception typeid on entry to a landing
438 unsigned getExceptionSelectorRegister() const {
439 return ExceptionSelectorRegister;
442 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
443 /// set, the default is 200)
444 unsigned getJumpBufSize() const {
448 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
449 /// (if never set, the default is 0)
450 unsigned getJumpBufAlignment() const {
451 return JumpBufAlignment;
454 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
455 /// limit. Any block whose size is greater should not be predicated.
456 virtual unsigned getIfCvtBlockSizeLimit() const {
457 return IfCvtBlockSizeLimit;
460 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
461 /// block to be considered for duplication. Any block whose size is greater
462 /// should not be duplicated to facilitate its predication.
463 virtual unsigned getIfCvtDupBlockSizeLimit() const {
464 return IfCvtDupBlockSizeLimit;
467 /// getPreIndexedAddressParts - returns true by value, base pointer and
468 /// offset pointer and addressing mode by reference if the node's address
469 /// can be legally represented as pre-indexed load / store address.
470 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
472 ISD::MemIndexedMode &AM,
477 /// getPostIndexedAddressParts - returns true by value, base pointer and
478 /// offset pointer and addressing mode by reference if this node can be
479 /// combined with a load / store to form a post-indexed load / store.
480 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
481 SDOperand &Base, SDOperand &Offset,
482 ISD::MemIndexedMode &AM,
487 //===--------------------------------------------------------------------===//
488 // TargetLowering Optimization Methods
491 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
492 /// SDOperands for returning information from TargetLowering to its clients
493 /// that want to combine
494 struct TargetLoweringOpt {
499 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
501 bool CombineTo(SDOperand O, SDOperand N) {
507 /// ShrinkDemandedConstant - Check to see if the specified operand of the
508 /// specified instruction is a constant integer. If so, check to see if there
509 /// are any bits set in the constant that are not demanded. If so, shrink the
510 /// constant and return true.
511 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
514 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
515 /// DemandedMask bits of the result of Op are ever used downstream. If we can
516 /// use this information to simplify Op, create a new simplified DAG node and
517 /// return true, returning the original and new nodes in Old and New.
518 /// Otherwise, analyze the expression and return a mask of KnownOne and
519 /// KnownZero bits for the expression (used to simplify the caller).
520 /// The KnownZero/One bits may only be accurate for those bits in the
522 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
523 uint64_t &KnownZero, uint64_t &KnownOne,
524 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
526 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
527 /// Mask are known to be either zero or one and return them in the
528 /// KnownZero/KnownOne bitsets.
529 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
533 const SelectionDAG &DAG,
534 unsigned Depth = 0) const;
536 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
537 /// targets that want to expose additional information about sign bits to the
539 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
540 unsigned Depth = 0) const;
542 struct DAGCombinerInfo {
543 void *DC; // The DAG Combiner object.
545 bool CalledByLegalizer;
549 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
550 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
552 bool isBeforeLegalize() const { return BeforeLegalize; }
553 bool isCalledByLegalizer() const { return CalledByLegalizer; }
555 void AddToWorklist(SDNode *N);
556 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
557 SDOperand CombineTo(SDNode *N, SDOperand Res);
558 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
561 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
562 /// and cc. If it is unable to simplify it, return a null SDOperand.
563 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
564 ISD::CondCode Cond, bool foldBooleans,
565 DAGCombinerInfo &DCI) const;
567 /// PerformDAGCombine - This method will be invoked for all target nodes and
568 /// for any target-independent nodes that the target has registered with
571 /// The semantics are as follows:
573 /// SDOperand.Val == 0 - No change was made
574 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
575 /// otherwise - N should be replaced by the returned Operand.
577 /// In addition, methods provided by DAGCombinerInfo may be used to perform
578 /// more complex transformations.
580 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
582 //===--------------------------------------------------------------------===//
583 // TargetLowering Configuration Methods - These methods should be invoked by
584 // the derived class constructor to configure this object for the target.
588 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
589 /// GOT for PC-relative code.
590 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
592 /// setShiftAmountType - Describe the type that should be used for shift
593 /// amounts. This type defaults to the pointer type.
594 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
596 /// setSetCCResultType - Describe the type that shoudl be used as the result
597 /// of a setcc operation. This defaults to the pointer type.
598 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
600 /// setSetCCResultContents - Specify how the target extends the result of a
601 /// setcc operation in a register.
602 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
604 /// setSchedulingPreference - Specify the target scheduling preference.
605 void setSchedulingPreference(SchedPreference Pref) {
606 SchedPreferenceInfo = Pref;
609 /// setShiftAmountFlavor - Describe how the target handles out of range shift
611 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
612 ShiftAmtHandling = OORSA;
615 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
616 /// use _setjmp to implement llvm.setjmp or the non _ version.
617 /// Defaults to false.
618 void setUseUnderscoreSetJmp(bool Val) {
619 UseUnderscoreSetJmp = Val;
622 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
623 /// use _longjmp to implement llvm.longjmp or the non _ version.
624 /// Defaults to false.
625 void setUseUnderscoreLongJmp(bool Val) {
626 UseUnderscoreLongJmp = Val;
629 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
630 /// specifies the register that llvm.savestack/llvm.restorestack should save
632 void setStackPointerRegisterToSaveRestore(unsigned R) {
633 StackPointerRegisterToSaveRestore = R;
636 /// setExceptionPointerRegister - If set to a physical register, this sets
637 /// the register that receives the exception address on entry to a landing
639 void setExceptionPointerRegister(unsigned R) {
640 ExceptionPointerRegister = R;
643 /// setExceptionSelectorRegister - If set to a physical register, this sets
644 /// the register that receives the exception typeid on entry to a landing
646 void setExceptionSelectorRegister(unsigned R) {
647 ExceptionSelectorRegister = R;
650 /// SelectIsExpensive - Tells the code generator not to expand operations
651 /// into sequences that use the select operations if possible.
652 void setSelectIsExpensive() { SelectIsExpensive = true; }
654 /// setIntDivIsCheap - Tells the code generator that integer divide is
655 /// expensive, and if possible, should be replaced by an alternate sequence
656 /// of instructions not containing an integer divide.
657 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
659 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
660 /// srl/add/sra for a signed divide by power of two, and let the target handle
662 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
664 /// addRegisterClass - Add the specified register class as an available
665 /// regclass for the specified value type. This indicates the selector can
666 /// handle values of that class natively.
667 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
668 assert(!MVT::isExtendedVT(VT));
669 AvailableRegClasses.push_back(std::make_pair(VT, RC));
670 RegClassForVT[VT] = RC;
673 /// computeRegisterProperties - Once all of the register classes are added,
674 /// this allows us to compute derived properties we expose.
675 void computeRegisterProperties();
677 /// setOperationAction - Indicate that the specified operation does not work
678 /// with the specified type and indicate what to do about it.
679 void setOperationAction(unsigned Op, MVT::ValueType VT,
680 LegalizeAction Action) {
681 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
682 "Table isn't big enough!");
683 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
684 OpActions[Op] |= (uint64_t)Action << VT*2;
687 /// setLoadXAction - Indicate that the specified load with extension does not
688 /// work with the with specified type and indicate what to do about it.
689 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
690 LegalizeAction Action) {
691 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
692 "Table isn't big enough!");
693 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
694 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
697 /// setStoreXAction - Indicate that the specified store with truncation does
698 /// not work with the with specified type and indicate what to do about it.
699 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
700 assert(VT < 32 && "Table isn't big enough!");
701 StoreXActions &= ~(uint64_t(3UL) << VT*2);
702 StoreXActions |= (uint64_t)Action << VT*2;
705 /// setIndexedLoadAction - Indicate that the specified indexed load does or
706 /// does not work with the with specified type and indicate what to do abort
707 /// it. NOTE: All indexed mode loads are initialized to Expand in
708 /// TargetLowering.cpp
709 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
710 LegalizeAction Action) {
711 assert(VT < 32 && IdxMode <
712 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) &&
713 "Table isn't big enough!");
714 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
715 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
718 /// setIndexedStoreAction - Indicate that the specified indexed store does or
719 /// does not work with the with specified type and indicate what to do about
720 /// it. NOTE: All indexed mode stores are initialized to Expand in
721 /// TargetLowering.cpp
722 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
723 LegalizeAction Action) {
724 assert(VT < 32 && IdxMode <
725 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) &&
726 "Table isn't big enough!");
727 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
728 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
731 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
732 /// promotion code defaults to trying a larger integer/fp until it can find
733 /// one that works. If that default is insufficient, this method can be used
734 /// by the target to override the default.
735 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
736 MVT::ValueType DestVT) {
737 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
740 /// addLegalFPImmediate - Indicate that this target can instruction select
741 /// the specified FP immediate natively.
742 void addLegalFPImmediate(double Imm) {
743 LegalFPImmediates.push_back(Imm);
746 /// setTargetDAGCombine - Targets should invoke this method for each target
747 /// independent node that they want to provide a custom DAG combiner for by
748 /// implementing the PerformDAGCombine virtual method.
749 void setTargetDAGCombine(ISD::NodeType NT) {
750 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
753 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
754 /// bytes); default is 200
755 void setJumpBufSize(unsigned Size) {
759 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
760 /// alignment (in bytes); default is 0
761 void setJumpBufAlignment(unsigned Align) {
762 JumpBufAlignment = Align;
765 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
766 /// limit (in number of instructions); default is 2.
767 void setIfCvtBlockSizeLimit(unsigned Limit) {
768 IfCvtBlockSizeLimit = Limit;
771 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
772 /// of instructions) to be considered for code duplication during
773 /// if-conversion; default is 2.
774 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
775 IfCvtDupBlockSizeLimit = Limit;
780 //===--------------------------------------------------------------------===//
781 // Lowering methods - These methods must be implemented by targets so that
782 // the SelectionDAGLowering code knows how to lower these.
785 /// LowerArguments - This hook must be implemented to indicate how we should
786 /// lower the arguments for the specified function, into the specified DAG.
787 virtual std::vector<SDOperand>
788 LowerArguments(Function &F, SelectionDAG &DAG);
790 /// LowerCallTo - This hook lowers an abstract call to a function into an
791 /// actual call. This returns a pair of operands. The first element is the
792 /// return value for the function (if RetTy is not VoidTy). The second
793 /// element is the outgoing token chain.
794 struct ArgListEntry {
802 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { };
804 typedef std::vector<ArgListEntry> ArgListTy;
805 virtual std::pair<SDOperand, SDOperand>
806 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
807 bool isVarArg, unsigned CallingConv, bool isTailCall,
808 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
810 /// LowerOperation - This callback is invoked for operations that are
811 /// unsupported by the target, which are registered to use 'custom' lowering,
812 /// and whose defined values are all legal.
813 /// If the target has no operations that require custom lowering, it need not
814 /// implement this. The default implementation of this aborts.
815 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
817 /// CustomPromoteOperation - This callback is invoked for operations that are
818 /// unsupported by the target, are registered to use 'custom' lowering, and
819 /// whose type needs to be promoted.
820 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
822 /// getTargetNodeName() - This method returns the name of a target specific
824 virtual const char *getTargetNodeName(unsigned Opcode) const;
826 //===--------------------------------------------------------------------===//
827 // Inline Asm Support hooks
830 enum ConstraintType {
831 C_Register, // Constraint represents a single register.
832 C_RegisterClass, // Constraint represents one or more registers.
833 C_Memory, // Memory constraint.
834 C_Other, // Something else.
835 C_Unknown // Unsupported constraint.
838 /// getConstraintType - Given a constraint, return the type of constraint it
839 /// is for this target.
840 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
843 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
844 /// return a list of registers that can be used to satisfy the constraint.
845 /// This should only be used for C_RegisterClass constraints.
846 virtual std::vector<unsigned>
847 getRegClassForInlineAsmConstraint(const std::string &Constraint,
848 MVT::ValueType VT) const;
850 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
851 /// {edx}), return the register number and the register class for the
854 /// Given a register class constraint, like 'r', if this corresponds directly
855 /// to an LLVM register class, return a register of 0 and the register class
858 /// This should only be used for C_Register constraints. On error,
859 /// this returns a register number of 0 and a null register class pointer..
860 virtual std::pair<unsigned, const TargetRegisterClass*>
861 getRegForInlineAsmConstraint(const std::string &Constraint,
862 MVT::ValueType VT) const;
865 /// isOperandValidForConstraint - Return the specified operand (possibly
866 /// modified) if the specified SDOperand is valid for the specified target
867 /// constraint letter, otherwise return null.
869 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
872 //===--------------------------------------------------------------------===//
876 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
877 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
878 // instructions are special in various ways, which require special support to
879 // insert. The specified MachineInstr is created but not inserted into any
880 // basic blocks, and the scheduler passes ownership of it to this method.
881 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
882 MachineBasicBlock *MBB);
884 //===--------------------------------------------------------------------===//
885 // Addressing mode description hooks (used by LSR etc).
888 /// AddrMode - This represents an addressing mode of:
889 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
890 /// If BaseGV is null, there is no BaseGV.
891 /// If BaseOffs is zero, there is no base offset.
892 /// If HasBaseReg is false, there is no base register.
893 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
901 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
904 /// isLegalAddressingMode - Return true if the addressing mode represented by
905 /// AM is legal for this target, for a load/store of the specified type.
906 /// TODO: Handle pre/postinc as well.
907 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
909 //===--------------------------------------------------------------------===//
910 // Div utility functions
912 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
913 std::vector<SDNode*>* Created) const;
914 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
915 std::vector<SDNode*>* Created) const;
918 //===--------------------------------------------------------------------===//
919 // Runtime Library hooks
922 /// setLibcallName - Rename the default libcall routine name for the specified
924 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
925 LibcallRoutineNames[Call] = Name;
928 /// getLibcallName - Get the libcall routine name for the specified libcall.
930 const char *getLibcallName(RTLIB::Libcall Call) const {
931 return LibcallRoutineNames[Call];
934 /// setCmpLibcallCC - Override the default CondCode to be used to test the
935 /// result of the comparison libcall against zero.
936 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
937 CmpLibcallCCs[Call] = CC;
940 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
941 /// the comparison libcall against zero.
942 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
943 return CmpLibcallCCs[Call];
948 const TargetData *TD;
950 /// IsLittleEndian - True if this is a little endian target.
954 /// PointerTy - The type to use for pointers, usually i32 or i64.
956 MVT::ValueType PointerTy;
958 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
960 bool UsesGlobalOffsetTable;
962 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
964 MVT::ValueType ShiftAmountTy;
966 OutOfRangeShiftAmount ShiftAmtHandling;
968 /// SelectIsExpensive - Tells the code generator not to expand operations
969 /// into sequences that use the select operations if possible.
970 bool SelectIsExpensive;
972 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
973 /// constants into a sequence of muls, adds, and shifts. This is a hack until
974 /// a real cost model is in place. If we ever optimize for size, this will be
975 /// set to true unconditionally.
978 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
979 /// srl/add/sra for a signed divide by power of two, and let the target handle
983 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
985 MVT::ValueType SetCCResultTy;
987 /// SetCCResultContents - Information about the contents of the high-bits in
988 /// the result of a setcc comparison operation.
989 SetCCResultValue SetCCResultContents;
991 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
992 /// total cycles or lowest register usage.
993 SchedPreference SchedPreferenceInfo;
995 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
996 /// llvm.setjmp. Defaults to false.
997 bool UseUnderscoreSetJmp;
999 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1000 /// llvm.longjmp. Defaults to false.
1001 bool UseUnderscoreLongJmp;
1003 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1004 unsigned JumpBufSize;
1006 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1008 unsigned JumpBufAlignment;
1010 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1012 unsigned IfCvtBlockSizeLimit;
1014 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1015 /// duplicated during if-conversion.
1016 unsigned IfCvtDupBlockSizeLimit;
1018 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1019 /// specifies the register that llvm.savestack/llvm.restorestack should save
1021 unsigned StackPointerRegisterToSaveRestore;
1023 /// ExceptionPointerRegister - If set to a physical register, this specifies
1024 /// the register that receives the exception address on entry to a landing
1026 unsigned ExceptionPointerRegister;
1028 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1029 /// the register that receives the exception typeid on entry to a landing
1031 unsigned ExceptionSelectorRegister;
1033 /// RegClassForVT - This indicates the default register class to use for
1034 /// each ValueType the target supports natively.
1035 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1036 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1038 /// TransformToType - For any value types we are promoting or expanding, this
1039 /// contains the value type that we are changing to. For Expanded types, this
1040 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1041 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1042 /// by the system, this holds the same type (e.g. i32 -> i32).
1043 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1045 /// OpActions - For each operation and each value type, keep a LegalizeAction
1046 /// that indicates how instruction selection should deal with the operation.
1047 /// Most operations are Legal (aka, supported natively by the target), but
1048 /// operations that are not should be described. Note that operations on
1049 /// non-legal value types are not described here.
1050 uint64_t OpActions[156];
1052 /// LoadXActions - For each load of load extension type and each value type,
1053 /// keep a LegalizeAction that indicates how instruction selection should deal
1055 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1057 /// StoreXActions - For each store with truncation of each value type, keep a
1058 /// LegalizeAction that indicates how instruction selection should deal with
1060 uint64_t StoreXActions;
1062 /// IndexedModeActions - For each indexed mode and each value type, keep a
1063 /// pair of LegalizeAction that indicates how instruction selection should
1064 /// deal with the load / store.
1065 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1067 ValueTypeActionImpl ValueTypeActions;
1069 std::vector<double> LegalFPImmediates;
1071 std::vector<std::pair<MVT::ValueType,
1072 TargetRegisterClass*> > AvailableRegClasses;
1074 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1075 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1076 /// which sets a bit in this array.
1077 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1079 /// PromoteToType - For operations that must be promoted to a specific type,
1080 /// this holds the destination type. This map should be sparse, so don't hold
1083 /// Targets add entries to this map with AddPromotedToType(..), clients access
1084 /// this with getTypeToPromoteTo(..).
1085 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1087 /// LibcallRoutineNames - Stores the name each libcall.
1089 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1091 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1092 /// of each of the comparison libcall against zero.
1093 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1096 /// When lowering %llvm.memset this field specifies the maximum number of
1097 /// store operations that may be substituted for the call to memset. Targets
1098 /// must set this value based on the cost threshold for that target. Targets
1099 /// should assume that the memset will be done using as many of the largest
1100 /// store operations first, followed by smaller ones, if necessary, per
1101 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1102 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1103 /// store. This only applies to setting a constant array of a constant size.
1104 /// @brief Specify maximum number of store instructions per memset call.
1105 unsigned maxStoresPerMemset;
1107 /// When lowering %llvm.memcpy this field specifies the maximum number of
1108 /// store operations that may be substituted for a call to memcpy. Targets
1109 /// must set this value based on the cost threshold for that target. Targets
1110 /// should assume that the memcpy will be done using as many of the largest
1111 /// store operations first, followed by smaller ones, if necessary, per
1112 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1113 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1114 /// and one 1-byte store. This only applies to copying a constant array of
1116 /// @brief Specify maximum bytes of store instructions per memcpy call.
1117 unsigned maxStoresPerMemcpy;
1119 /// When lowering %llvm.memmove this field specifies the maximum number of
1120 /// store instructions that may be substituted for a call to memmove. Targets
1121 /// must set this value based on the cost threshold for that target. Targets
1122 /// should assume that the memmove will be done using as many of the largest
1123 /// store operations first, followed by smaller ones, if necessary, per
1124 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1125 /// with 8-bit alignment would result in nine 1-byte stores. This only
1126 /// applies to copying a constant array of constant size.
1127 /// @brief Specify maximum bytes of store instructions per memmove call.
1128 unsigned maxStoresPerMemmove;
1130 /// This field specifies whether the target machine permits unaligned memory
1131 /// accesses. This is used, for example, to determine the size of store
1132 /// operations when copying small arrays and other similar tasks.
1133 /// @brief Indicate whether the target permits unaligned memory accesses.
1134 bool allowUnalignedMemoryAccesses;
1136 } // end llvm namespace