1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/DebugLoc.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFunction;
50 class MachineFrameInfo;
52 class MachineJumpTableInfo;
60 class TargetRegisterClass;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 /// NOTE: The constructor takes ownership of TLOF.
104 explicit TargetLowering(const TargetMachine &TM,
105 const TargetLoweringObjectFile *TLOF);
106 virtual ~TargetLowering();
108 const TargetMachine &getTargetMachine() const { return TM; }
109 const TargetData *getTargetData() const { return TD; }
110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT getPointerTy() const { return PointerTy; }
115 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 /// isSelectExpensive - Return true if the select operation is expensive for
119 bool isSelectExpensive() const { return SelectIsExpensive; }
121 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
122 /// a sequence of several shifts, adds, and multiplies for this target.
123 bool isIntDivCheap() const { return IntDivIsCheap; }
125 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
127 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
129 /// getSetCCResultType - Return the ValueType of the result of SETCC
130 /// operations. Also used to obtain the target's preferred type for
131 /// the condition operand of SELECT and BRCOND nodes. In the case of
132 /// BRCOND the argument passed is MVT::Other since there are no other
133 /// operands to get a type hint from.
135 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
137 /// getCmpLibcallReturnType - Return the ValueType for comparison
138 /// libcalls. Comparions libcalls include floating point comparion calls,
139 /// and Ordered/Unordered check calls on floating point numbers.
141 MVT::SimpleValueType getCmpLibcallReturnType() const;
143 /// getBooleanContents - For targets without i1 registers, this gives the
144 /// nature of the high-bits of boolean values held in types wider than i1.
145 /// "Boolean values" are special true/false values produced by nodes like
146 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
147 /// Not to be confused with general values promoted from i1.
148 BooleanContent getBooleanContents() const { return BooleanContents;}
150 /// getSchedulingPreference - Return target scheduling preference.
151 Sched::Preference getSchedulingPreference() const {
152 return SchedPreferenceInfo;
155 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
156 /// different scheduling heuristics for different nodes. This function returns
157 /// the preference (or none) for the given node.
158 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
162 /// getRegClassFor - Return the register class that should be used for the
163 /// specified value type.
164 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
165 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
166 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
167 assert(RC && "This value type is not natively supported!");
171 /// getRepRegClassFor - Return the 'representative' register class for the
172 /// specified value type. The 'representative' register class is the largest
173 /// legal super-reg register class for the register class of the value type.
174 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
175 /// while the rep register class is GR64 on x86_64.
176 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
177 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
178 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
182 /// getRepRegClassCostFor - Return the cost of the 'representative' register
183 /// class for the specified value type.
184 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
185 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
186 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
189 /// getRegPressureLimit - Return the register pressure "high water mark" for
190 /// the specific register class. The scheduler is in high register pressure
191 /// mode (for the specific register class) if it goes over the limit.
192 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
193 MachineFunction &MF) const {
197 /// isTypeLegal - Return true if the target has native support for the
198 /// specified value type. This means that it has a register that directly
199 /// holds it without promotions or expansions.
200 bool isTypeLegal(EVT VT) const {
201 assert(!VT.isSimple() ||
202 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
203 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
206 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
207 /// new operations of this type. All Legal types are synthesizable except
208 /// MMX vector types on X86. Non-Legal types are not synthesizable.
209 bool isTypeSynthesizable(EVT VT) const {
210 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
213 class ValueTypeActionImpl {
214 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
215 /// that indicates how instruction selection should deal with the type.
216 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
218 LegalizeAction getExtendedTypeAction(EVT VT) const {
219 // Handle non-vector integers.
220 if (!VT.isVector()) {
221 assert(VT.isInteger() && "Unsupported extended type!");
222 unsigned BitSize = VT.getSizeInBits();
223 // First promote to a power-of-two size, then expand if necessary.
224 if (BitSize < 8 || !isPowerOf2_32(BitSize))
229 // If this is a type smaller than a legal vector type, promote to that
230 // type, e.g. <2 x float> -> <4 x float>.
231 if (VT.getVectorElementType().isSimple() &&
232 VT.getVectorNumElements() != 1) {
233 MVT EltType = VT.getVectorElementType().getSimpleVT();
234 unsigned NumElts = VT.getVectorNumElements();
236 // Round up to the nearest power of 2.
237 NumElts = (unsigned)NextPowerOf2(NumElts);
239 MVT LargerVector = MVT::getVectorVT(EltType, NumElts);
240 if (LargerVector == MVT()) break;
242 // If this the larger type is legal, promote to it.
243 if (getTypeAction(LargerVector) == Legal) return Promote;
247 return VT.isPow2VectorType() ? Expand : Promote;
250 ValueTypeActionImpl() {
251 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
254 LegalizeAction getTypeAction(EVT VT) const {
255 if (!VT.isExtended())
256 return getTypeAction(VT.getSimpleVT());
257 return getExtendedTypeAction(VT);
260 LegalizeAction getTypeAction(MVT VT) const {
261 return (LegalizeAction)ValueTypeActions[VT.SimpleTy];
264 void setTypeAction(EVT VT, LegalizeAction Action) {
265 unsigned I = VT.getSimpleVT().SimpleTy;
266 ValueTypeActions[I] = Action;
270 const ValueTypeActionImpl &getValueTypeActions() const {
271 return ValueTypeActions;
274 /// getTypeAction - Return how we should legalize values of this type, either
275 /// it is already legal (return 'Legal') or we need to promote it to a larger
276 /// type (return 'Promote'), or we need to expand it into multiple registers
277 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
278 LegalizeAction getTypeAction(EVT VT) const {
279 return ValueTypeActions.getTypeAction(VT);
281 LegalizeAction getTypeAction(MVT VT) const {
282 return ValueTypeActions.getTypeAction(VT);
285 /// getTypeToTransformTo - For types supported by the target, this is an
286 /// identity function. For types that must be promoted to larger types, this
287 /// returns the larger type to promote to. For integer types that are larger
288 /// than the largest integer register, this contains one step in the expansion
289 /// to get to the smaller register. For illegal floating point types, this
290 /// returns the integer type to transform to.
291 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
293 assert((unsigned)VT.getSimpleVT().SimpleTy <
294 array_lengthof(TransformToType));
295 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
296 assert(getTypeAction(NVT) != Promote &&
297 "Promote may not follow Expand or Promote");
302 EVT NVT = VT.getPow2VectorType(Context);
304 // Vector length is a power of 2 - split to half the size.
305 unsigned NumElts = VT.getVectorNumElements();
306 EVT EltVT = VT.getVectorElementType();
307 return (NumElts == 1) ?
308 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
310 // Promote to a power of two size, avoiding multi-step promotion.
311 return getTypeAction(NVT) == Promote ?
312 getTypeToTransformTo(Context, NVT) : NVT;
313 } else if (VT.isInteger()) {
314 EVT NVT = VT.getRoundIntegerType(Context);
315 if (NVT == VT) // Size is a power of two - expand to half the size.
316 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
318 // Promote to a power of two size, avoiding multi-step promotion.
319 return getTypeAction(NVT) == Promote ?
320 getTypeToTransformTo(Context, NVT) : NVT;
322 assert(0 && "Unsupported extended type!");
323 return MVT(MVT::Other); // Not reached
326 /// getTypeToExpandTo - For types supported by the target, this is an
327 /// identity function. For types that must be expanded (i.e. integer types
328 /// that are larger than the largest integer register or illegal floating
329 /// point types), this returns the largest legal type it will be expanded to.
330 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
331 assert(!VT.isVector());
333 switch (getTypeAction(VT)) {
337 VT = getTypeToTransformTo(Context, VT);
340 assert(false && "Type is not legal nor is it to be expanded!");
347 /// getVectorTypeBreakdown - Vector types are broken down into some number of
348 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
349 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
350 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
352 /// This method returns the number of registers needed, and the VT for each
353 /// register. It also returns the VT and quantity of the intermediate values
354 /// before they are promoted/expanded.
356 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
358 unsigned &NumIntermediates,
359 EVT &RegisterVT) const;
361 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
362 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
363 /// this is the case, it returns true and store the intrinsic
364 /// information into the IntrinsicInfo that was passed to the function.
365 struct IntrinsicInfo {
366 unsigned opc; // target opcode
367 EVT memVT; // memory VT
368 const Value* ptrVal; // value representing memory location
369 int offset; // offset off of ptrVal
370 unsigned align; // alignment
371 bool vol; // is volatile?
372 bool readMem; // reads memory?
373 bool writeMem; // writes memory?
376 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
377 const CallInst &I, unsigned Intrinsic) const {
381 /// isFPImmLegal - Returns true if the target can instruction select the
382 /// specified FP immediate natively. If false, the legalizer will materialize
383 /// the FP immediate as a load from a constant pool.
384 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
388 /// isShuffleMaskLegal - Targets can use this to indicate that they only
389 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
390 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
391 /// are assumed to be legal.
392 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
397 /// canOpTrap - Returns true if the operation can trap for the value type.
398 /// VT must be a legal type. By default, we optimistically assume most
399 /// operations don't trap except for divide and remainder.
400 virtual bool canOpTrap(unsigned Op, EVT VT) const;
402 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
403 /// used by Targets can use this to indicate if there is a suitable
404 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
406 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
411 /// getOperationAction - Return how this operation should be treated: either
412 /// it is legal, needs to be promoted to a larger size, needs to be
413 /// expanded to some other code sequence, or the target has a custom expander
415 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
416 if (VT.isExtended()) return Expand;
417 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
418 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
419 return (LegalizeAction)OpActions[I][Op];
422 /// isOperationLegalOrCustom - Return true if the specified operation is
423 /// legal on this target or can be made legal with custom lowering. This
424 /// is used to help guide high-level lowering decisions.
425 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
426 return (VT == MVT::Other || isTypeLegal(VT)) &&
427 (getOperationAction(Op, VT) == Legal ||
428 getOperationAction(Op, VT) == Custom);
431 /// isOperationLegal - Return true if the specified operation is legal on this
433 bool isOperationLegal(unsigned Op, EVT VT) const {
434 return (VT == MVT::Other || isTypeLegal(VT)) &&
435 getOperationAction(Op, VT) == Legal;
438 /// getLoadExtAction - Return how this load with extension should be treated:
439 /// either it is legal, needs to be promoted to a larger size, needs to be
440 /// expanded to some other code sequence, or the target has a custom expander
442 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
443 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
444 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
445 "Table isn't big enough!");
446 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
449 /// isLoadExtLegal - Return true if the specified load with extension is legal
451 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
452 return VT.isSimple() &&
453 (getLoadExtAction(ExtType, VT) == Legal ||
454 getLoadExtAction(ExtType, VT) == Custom);
457 /// getTruncStoreAction - Return how this store with truncation should be
458 /// treated: either it is legal, needs to be promoted to a larger size, needs
459 /// to be expanded to some other code sequence, or the target has a custom
461 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
462 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
463 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
464 "Table isn't big enough!");
465 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
466 [MemVT.getSimpleVT().SimpleTy];
469 /// isTruncStoreLegal - Return true if the specified store with truncation is
470 /// legal on this target.
471 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
472 return isTypeLegal(ValVT) && MemVT.isSimple() &&
473 (getTruncStoreAction(ValVT, MemVT) == Legal ||
474 getTruncStoreAction(ValVT, MemVT) == Custom);
477 /// getIndexedLoadAction - Return how the indexed load should be treated:
478 /// either it is legal, needs to be promoted to a larger size, needs to be
479 /// expanded to some other code sequence, or the target has a custom expander
482 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
483 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
484 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
485 "Table isn't big enough!");
486 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
487 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
490 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
492 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
493 return VT.isSimple() &&
494 (getIndexedLoadAction(IdxMode, VT) == Legal ||
495 getIndexedLoadAction(IdxMode, VT) == Custom);
498 /// getIndexedStoreAction - Return how the indexed store should be treated:
499 /// either it is legal, needs to be promoted to a larger size, needs to be
500 /// expanded to some other code sequence, or the target has a custom expander
503 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
504 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
505 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
506 "Table isn't big enough!");
507 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
508 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
511 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
513 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
514 return VT.isSimple() &&
515 (getIndexedStoreAction(IdxMode, VT) == Legal ||
516 getIndexedStoreAction(IdxMode, VT) == Custom);
519 /// getCondCodeAction - Return how the condition code should be treated:
520 /// either it is legal, needs to be expanded to some other code sequence,
521 /// or the target has a custom expander for it.
523 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
524 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
525 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
526 "Table isn't big enough!");
527 LegalizeAction Action = (LegalizeAction)
528 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
529 assert(Action != Promote && "Can't promote condition code!");
533 /// isCondCodeLegal - Return true if the specified condition code is legal
535 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
536 return getCondCodeAction(CC, VT) == Legal ||
537 getCondCodeAction(CC, VT) == Custom;
541 /// getTypeToPromoteTo - If the action for this operation is to promote, this
542 /// method returns the ValueType to promote to.
543 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
544 assert(getOperationAction(Op, VT) == Promote &&
545 "This operation isn't promoted!");
547 // See if this has an explicit type specified.
548 std::map<std::pair<unsigned, MVT::SimpleValueType>,
549 MVT::SimpleValueType>::const_iterator PTTI =
550 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
551 if (PTTI != PromoteToType.end()) return PTTI->second;
553 assert((VT.isInteger() || VT.isFloatingPoint()) &&
554 "Cannot autopromote this type, add it with AddPromotedToType.");
558 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
559 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
560 "Didn't find type to promote to!");
561 } while (!isTypeLegal(NVT) ||
562 getOperationAction(Op, NVT) == Promote);
566 /// getValueType - Return the EVT corresponding to this LLVM type.
567 /// This is fixed by the LLVM operations except for the pointer size. If
568 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
569 /// counterpart (e.g. structs), otherwise it will assert.
570 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
571 EVT VT = EVT::getEVT(Ty, AllowUnknown);
572 return VT == MVT::iPTR ? PointerTy : VT;
575 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
576 /// function arguments in the caller parameter area. This is the actual
577 /// alignment, not its logarithm.
578 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
580 /// getRegisterType - Return the type of registers that this ValueType will
581 /// eventually require.
582 EVT getRegisterType(MVT VT) const {
583 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
584 return RegisterTypeForVT[VT.SimpleTy];
587 /// getRegisterType - Return the type of registers that this ValueType will
588 /// eventually require.
589 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
591 assert((unsigned)VT.getSimpleVT().SimpleTy <
592 array_lengthof(RegisterTypeForVT));
593 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
597 unsigned NumIntermediates;
598 (void)getVectorTypeBreakdown(Context, VT, VT1,
599 NumIntermediates, RegisterVT);
602 if (VT.isInteger()) {
603 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
605 assert(0 && "Unsupported extended type!");
606 return EVT(MVT::Other); // Not reached
609 /// getNumRegisters - Return the number of registers that this ValueType will
610 /// eventually require. This is one for any types promoted to live in larger
611 /// registers, but may be more than one for types (like i64) that are split
612 /// into pieces. For types like i140, which are first promoted then expanded,
613 /// it is the number of registers needed to hold all the bits of the original
614 /// type. For an i140 on a 32 bit machine this means 5 registers.
615 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
617 assert((unsigned)VT.getSimpleVT().SimpleTy <
618 array_lengthof(NumRegistersForVT));
619 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
623 unsigned NumIntermediates;
624 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
626 if (VT.isInteger()) {
627 unsigned BitWidth = VT.getSizeInBits();
628 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
629 return (BitWidth + RegWidth - 1) / RegWidth;
631 assert(0 && "Unsupported extended type!");
632 return 0; // Not reached
635 /// ShouldShrinkFPConstant - If true, then instruction selection should
636 /// seek to shrink the FP constant of the specified type to a smaller type
637 /// in order to save space and / or reduce runtime.
638 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
640 /// hasTargetDAGCombine - If true, the target has custom DAG combine
641 /// transformations that it can perform for the specified node.
642 bool hasTargetDAGCombine(ISD::NodeType NT) const {
643 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
644 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
647 /// This function returns the maximum number of store operations permitted
648 /// to replace a call to llvm.memset. The value is set by the target at the
649 /// performance threshold for such a replacement.
650 /// @brief Get maximum # of store operations permitted for llvm.memset
651 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
653 /// This function returns the maximum number of store operations permitted
654 /// to replace a call to llvm.memcpy. The value is set by the target at the
655 /// performance threshold for such a replacement.
656 /// @brief Get maximum # of store operations permitted for llvm.memcpy
657 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
659 /// This function returns the maximum number of store operations permitted
660 /// to replace a call to llvm.memmove. The value is set by the target at the
661 /// performance threshold for such a replacement.
662 /// @brief Get maximum # of store operations permitted for llvm.memmove
663 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
665 /// This function returns true if the target allows unaligned memory accesses.
666 /// of the specified type. This is used, for example, in situations where an
667 /// array copy/move/set is converted to a sequence of store operations. It's
668 /// use helps to ensure that such replacements don't generate code that causes
669 /// an alignment error (trap) on the target machine.
670 /// @brief Determine if the target supports unaligned memory accesses.
671 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
675 /// This function returns true if the target would benefit from code placement
677 /// @brief Determine if the target should perform code placement optimization.
678 bool shouldOptimizeCodePlacement() const {
679 return benefitFromCodePlacementOpt;
682 /// getOptimalMemOpType - Returns the target specific optimal type for load
683 /// and store operations as a result of memset, memcpy, and memmove
684 /// lowering. If DstAlign is zero that means it's safe to destination
685 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
686 /// means there isn't a need to check it against alignment requirement,
687 /// probably because the source does not need to be loaded. If
688 /// 'NonScalarIntSafe' is true, that means it's safe to return a
689 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
690 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
691 /// constant so it does not need to be loaded.
692 /// It returns EVT::Other if the type should be determined using generic
693 /// target-independent logic.
694 virtual EVT getOptimalMemOpType(uint64_t Size,
695 unsigned DstAlign, unsigned SrcAlign,
696 bool NonScalarIntSafe, bool MemcpyStrSrc,
697 MachineFunction &MF) const {
701 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
702 /// to implement llvm.setjmp.
703 bool usesUnderscoreSetJmp() const {
704 return UseUnderscoreSetJmp;
707 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
708 /// to implement llvm.longjmp.
709 bool usesUnderscoreLongJmp() const {
710 return UseUnderscoreLongJmp;
713 /// getStackPointerRegisterToSaveRestore - If a physical register, this
714 /// specifies the register that llvm.savestack/llvm.restorestack should save
716 unsigned getStackPointerRegisterToSaveRestore() const {
717 return StackPointerRegisterToSaveRestore;
720 /// getExceptionAddressRegister - If a physical register, this returns
721 /// the register that receives the exception address on entry to a landing
723 unsigned getExceptionAddressRegister() const {
724 return ExceptionPointerRegister;
727 /// getExceptionSelectorRegister - If a physical register, this returns
728 /// the register that receives the exception typeid on entry to a landing
730 unsigned getExceptionSelectorRegister() const {
731 return ExceptionSelectorRegister;
734 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
735 /// set, the default is 200)
736 unsigned getJumpBufSize() const {
740 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
741 /// (if never set, the default is 0)
742 unsigned getJumpBufAlignment() const {
743 return JumpBufAlignment;
746 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
748 unsigned getMinStackArgumentAlignment() const {
749 return MinStackArgumentAlignment;
752 /// getPrefLoopAlignment - return the preferred loop alignment.
754 unsigned getPrefLoopAlignment() const {
755 return PrefLoopAlignment;
758 /// getShouldFoldAtomicFences - return whether the combiner should fold
759 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
761 bool getShouldFoldAtomicFences() const {
762 return ShouldFoldAtomicFences;
765 /// getPreIndexedAddressParts - returns true by value, base pointer and
766 /// offset pointer and addressing mode by reference if the node's address
767 /// can be legally represented as pre-indexed load / store address.
768 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
770 ISD::MemIndexedMode &AM,
771 SelectionDAG &DAG) const {
775 /// getPostIndexedAddressParts - returns true by value, base pointer and
776 /// offset pointer and addressing mode by reference if this node can be
777 /// combined with a load / store to form a post-indexed load / store.
778 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
779 SDValue &Base, SDValue &Offset,
780 ISD::MemIndexedMode &AM,
781 SelectionDAG &DAG) const {
785 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
786 /// current function. The returned value is a member of the
787 /// MachineJumpTableInfo::JTEntryKind enum.
788 virtual unsigned getJumpTableEncoding() const;
790 virtual const MCExpr *
791 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
792 const MachineBasicBlock *MBB, unsigned uid,
793 MCContext &Ctx) const {
794 assert(0 && "Need to implement this hook if target has custom JTIs");
798 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
800 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
801 SelectionDAG &DAG) const;
803 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
804 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
806 virtual const MCExpr *
807 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
808 unsigned JTI, MCContext &Ctx) const;
810 /// isOffsetFoldingLegal - Return true if folding a constant offset
811 /// with the given GlobalAddress is legal. It is frequently not legal in
812 /// PIC relocation models.
813 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
815 /// getFunctionAlignment - Return the Log2 alignment of this function.
816 virtual unsigned getFunctionAlignment(const Function *) const = 0;
818 /// getStackCookieLocation - Return true if the target stores stack
819 /// protector cookies at a fixed offset in some non-standard address
820 /// space, and populates the address space and offset as
822 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
826 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
827 /// used for loads / stores from the global.
828 virtual unsigned getMaximalGlobalOffset() const {
832 //===--------------------------------------------------------------------===//
833 // TargetLowering Optimization Methods
836 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
837 /// SDValues for returning information from TargetLowering to its clients
838 /// that want to combine
839 struct TargetLoweringOpt {
846 explicit TargetLoweringOpt(SelectionDAG &InDAG,
848 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
850 bool LegalTypes() const { return LegalTys; }
851 bool LegalOperations() const { return LegalOps; }
853 bool CombineTo(SDValue O, SDValue N) {
859 /// ShrinkDemandedConstant - Check to see if the specified operand of the
860 /// specified instruction is a constant integer. If so, check to see if
861 /// there are any bits set in the constant that are not demanded. If so,
862 /// shrink the constant and return true.
863 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
865 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
866 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
867 /// cast, but it could be generalized for targets with other types of
868 /// implicit widening casts.
869 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
873 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
874 /// DemandedMask bits of the result of Op are ever used downstream. If we can
875 /// use this information to simplify Op, create a new simplified DAG node and
876 /// return true, returning the original and new nodes in Old and New.
877 /// Otherwise, analyze the expression and return a mask of KnownOne and
878 /// KnownZero bits for the expression (used to simplify the caller).
879 /// The KnownZero/One bits may only be accurate for those bits in the
881 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
882 APInt &KnownZero, APInt &KnownOne,
883 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
885 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
886 /// Mask are known to be either zero or one and return them in the
887 /// KnownZero/KnownOne bitsets.
888 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
892 const SelectionDAG &DAG,
893 unsigned Depth = 0) const;
895 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
896 /// targets that want to expose additional information about sign bits to the
898 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
899 unsigned Depth = 0) const;
901 struct DAGCombinerInfo {
902 void *DC; // The DAG Combiner object.
904 bool BeforeLegalizeOps;
905 bool CalledByLegalizer;
909 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
910 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
911 CalledByLegalizer(cl), DAG(dag) {}
913 bool isBeforeLegalize() const { return BeforeLegalize; }
914 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
915 bool isCalledByLegalizer() const { return CalledByLegalizer; }
917 void AddToWorklist(SDNode *N);
918 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
920 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
921 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
923 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
926 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
927 /// and cc. If it is unable to simplify it, return a null SDValue.
928 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
929 ISD::CondCode Cond, bool foldBooleans,
930 DAGCombinerInfo &DCI, DebugLoc dl) const;
932 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
933 /// node is a GlobalAddress + offset.
935 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
937 /// PerformDAGCombine - This method will be invoked for all target nodes and
938 /// for any target-independent nodes that the target has registered with
941 /// The semantics are as follows:
943 /// SDValue.Val == 0 - No change was made
944 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
945 /// otherwise - N should be replaced by the returned Operand.
947 /// In addition, methods provided by DAGCombinerInfo may be used to perform
948 /// more complex transformations.
950 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
952 /// isTypeDesirableForOp - Return true if the target has native support for
953 /// the specified value type and it is 'desirable' to use the type for the
954 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
955 /// instruction encodings are longer and some i16 instructions are slow.
956 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
957 // By default, assume all legal types are desirable.
958 return isTypeLegal(VT);
961 /// IsDesirableToPromoteOp - This method query the target whether it is
962 /// beneficial for dag combiner to promote the specified node. If true, it
963 /// should return the desired promotion type by reference.
964 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
968 //===--------------------------------------------------------------------===//
969 // TargetLowering Configuration Methods - These methods should be invoked by
970 // the derived class constructor to configure this object for the target.
974 /// setShiftAmountType - Describe the type that should be used for shift
975 /// amounts. This type defaults to the pointer type.
976 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
978 /// setBooleanContents - Specify how the target extends the result of a
979 /// boolean value from i1 to a wider type. See getBooleanContents.
980 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
982 /// setSchedulingPreference - Specify the target scheduling preference.
983 void setSchedulingPreference(Sched::Preference Pref) {
984 SchedPreferenceInfo = Pref;
987 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
988 /// use _setjmp to implement llvm.setjmp or the non _ version.
989 /// Defaults to false.
990 void setUseUnderscoreSetJmp(bool Val) {
991 UseUnderscoreSetJmp = Val;
994 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
995 /// use _longjmp to implement llvm.longjmp or the non _ version.
996 /// Defaults to false.
997 void setUseUnderscoreLongJmp(bool Val) {
998 UseUnderscoreLongJmp = Val;
1001 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
1002 /// specifies the register that llvm.savestack/llvm.restorestack should save
1004 void setStackPointerRegisterToSaveRestore(unsigned R) {
1005 StackPointerRegisterToSaveRestore = R;
1008 /// setExceptionPointerRegister - If set to a physical register, this sets
1009 /// the register that receives the exception address on entry to a landing
1011 void setExceptionPointerRegister(unsigned R) {
1012 ExceptionPointerRegister = R;
1015 /// setExceptionSelectorRegister - If set to a physical register, this sets
1016 /// the register that receives the exception typeid on entry to a landing
1018 void setExceptionSelectorRegister(unsigned R) {
1019 ExceptionSelectorRegister = R;
1022 /// SelectIsExpensive - Tells the code generator not to expand operations
1023 /// into sequences that use the select operations if possible.
1024 void setSelectIsExpensive() { SelectIsExpensive = true; }
1026 /// setIntDivIsCheap - Tells the code generator that integer divide is
1027 /// expensive, and if possible, should be replaced by an alternate sequence
1028 /// of instructions not containing an integer divide.
1029 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1031 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1032 /// srl/add/sra for a signed divide by power of two, and let the target handle
1034 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1036 /// addRegisterClass - Add the specified register class as an available
1037 /// regclass for the specified value type. This indicates the selector can
1038 /// handle values of that class natively.
1039 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
1040 bool isSynthesizable = true) {
1041 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1042 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1043 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1044 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
1047 /// findRepresentativeClass - Return the largest legal super-reg register class
1048 /// of the register class for the specified type and its associated "cost".
1049 virtual std::pair<const TargetRegisterClass*, uint8_t>
1050 findRepresentativeClass(EVT VT) const;
1052 /// computeRegisterProperties - Once all of the register classes are added,
1053 /// this allows us to compute derived properties we expose.
1054 void computeRegisterProperties();
1056 /// setOperationAction - Indicate that the specified operation does not work
1057 /// with the specified type and indicate what to do about it.
1058 void setOperationAction(unsigned Op, MVT VT,
1059 LegalizeAction Action) {
1060 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1061 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1064 /// setLoadExtAction - Indicate that the specified load with extension does
1065 /// not work with the specified type and indicate what to do about it.
1066 void setLoadExtAction(unsigned ExtType, MVT VT,
1067 LegalizeAction Action) {
1068 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
1069 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1070 "Table isn't big enough!");
1071 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1074 /// setTruncStoreAction - Indicate that the specified truncating store does
1075 /// not work with the specified type and indicate what to do about it.
1076 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1077 LegalizeAction Action) {
1078 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1079 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1080 "Table isn't big enough!");
1081 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1084 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1085 /// does not work with the specified type and indicate what to do abort
1086 /// it. NOTE: All indexed mode loads are initialized to Expand in
1087 /// TargetLowering.cpp
1088 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1089 LegalizeAction Action) {
1090 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1091 IdxMode < ISD::LAST_INDEXED_MODE &&
1092 (unsigned)Action < 0xf &&
1093 "Table isn't big enough!");
1094 // Load action are kept in the upper half.
1095 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1096 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1099 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1100 /// does not work with the specified type and indicate what to do about
1101 /// it. NOTE: All indexed mode stores are initialized to Expand in
1102 /// TargetLowering.cpp
1103 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1104 LegalizeAction Action) {
1105 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1106 IdxMode < ISD::LAST_INDEXED_MODE &&
1107 (unsigned)Action < 0xf &&
1108 "Table isn't big enough!");
1109 // Store action are kept in the lower half.
1110 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1111 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1114 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1115 /// supported on the target and indicate what to do about it.
1116 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1117 LegalizeAction Action) {
1118 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1119 (unsigned)CC < array_lengthof(CondCodeActions) &&
1120 "Table isn't big enough!");
1121 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1122 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1125 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1126 /// promotion code defaults to trying a larger integer/fp until it can find
1127 /// one that works. If that default is insufficient, this method can be used
1128 /// by the target to override the default.
1129 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1130 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1133 /// setTargetDAGCombine - Targets should invoke this method for each target
1134 /// independent node that they want to provide a custom DAG combiner for by
1135 /// implementing the PerformDAGCombine virtual method.
1136 void setTargetDAGCombine(ISD::NodeType NT) {
1137 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1138 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1141 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1142 /// bytes); default is 200
1143 void setJumpBufSize(unsigned Size) {
1147 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1148 /// alignment (in bytes); default is 0
1149 void setJumpBufAlignment(unsigned Align) {
1150 JumpBufAlignment = Align;
1153 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1154 /// alignment is zero, it means the target does not care about loop alignment.
1155 void setPrefLoopAlignment(unsigned Align) {
1156 PrefLoopAlignment = Align;
1159 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1161 void setMinStackArgumentAlignment(unsigned Align) {
1162 MinStackArgumentAlignment = Align;
1165 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1166 /// atomic operation intrinsics includes locking. Default is false.
1167 void setShouldFoldAtomicFences(bool fold) {
1168 ShouldFoldAtomicFences = fold;
1172 //===--------------------------------------------------------------------===//
1173 // Lowering methods - These methods must be implemented by targets so that
1174 // the SelectionDAGLowering code knows how to lower these.
1177 /// LowerFormalArguments - This hook must be implemented to lower the
1178 /// incoming (formal) arguments, described by the Ins array, into the
1179 /// specified DAG. The implementation should fill in the InVals array
1180 /// with legal-type argument values, and return the resulting token
1184 LowerFormalArguments(SDValue Chain,
1185 CallingConv::ID CallConv, bool isVarArg,
1186 const SmallVectorImpl<ISD::InputArg> &Ins,
1187 DebugLoc dl, SelectionDAG &DAG,
1188 SmallVectorImpl<SDValue> &InVals) const {
1189 assert(0 && "Not Implemented");
1190 return SDValue(); // this is here to silence compiler errors
1193 /// LowerCallTo - This function lowers an abstract call to a function into an
1194 /// actual call. This returns a pair of operands. The first element is the
1195 /// return value for the function (if RetTy is not VoidTy). The second
1196 /// element is the outgoing token chain. It calls LowerCall to do the actual
1198 struct ArgListEntry {
1209 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1210 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1212 typedef std::vector<ArgListEntry> ArgListTy;
1213 std::pair<SDValue, SDValue>
1214 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1215 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1216 CallingConv::ID CallConv, bool isTailCall,
1217 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1218 SelectionDAG &DAG, DebugLoc dl) const;
1220 /// LowerCall - This hook must be implemented to lower calls into the
1221 /// the specified DAG. The outgoing arguments to the call are described
1222 /// by the Outs array, and the values to be returned by the call are
1223 /// described by the Ins array. The implementation should fill in the
1224 /// InVals array with legal-type return values from the call, and return
1225 /// the resulting token chain value.
1227 LowerCall(SDValue Chain, SDValue Callee,
1228 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1229 const SmallVectorImpl<ISD::OutputArg> &Outs,
1230 const SmallVectorImpl<SDValue> &OutVals,
1231 const SmallVectorImpl<ISD::InputArg> &Ins,
1232 DebugLoc dl, SelectionDAG &DAG,
1233 SmallVectorImpl<SDValue> &InVals) const {
1234 assert(0 && "Not Implemented");
1235 return SDValue(); // this is here to silence compiler errors
1238 /// CanLowerReturn - This hook should be implemented to check whether the
1239 /// return values described by the Outs array can fit into the return
1240 /// registers. If false is returned, an sret-demotion is performed.
1242 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1243 const SmallVectorImpl<ISD::OutputArg> &Outs,
1244 LLVMContext &Context) const
1246 // Return true by default to get preexisting behavior.
1250 /// LowerReturn - This hook must be implemented to lower outgoing
1251 /// return values, described by the Outs array, into the specified
1252 /// DAG. The implementation should return the resulting token chain
1256 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1257 const SmallVectorImpl<ISD::OutputArg> &Outs,
1258 const SmallVectorImpl<SDValue> &OutVals,
1259 DebugLoc dl, SelectionDAG &DAG) const {
1260 assert(0 && "Not Implemented");
1261 return SDValue(); // this is here to silence compiler errors
1264 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1265 /// to legalize nodes with an illegal operand type but legal result types.
1266 /// It replaces the LowerOperation callback in the type Legalizer.
1267 /// The reason we can not do away with LowerOperation entirely is that
1268 /// LegalizeDAG isn't yet ready to use this callback.
1269 /// TODO: Consider merging with ReplaceNodeResults.
1271 /// The target places new result values for the node in Results (their number
1272 /// and types must exactly match those of the original return values of
1273 /// the node), or leaves Results empty, which indicates that the node is not
1274 /// to be custom lowered after all.
1275 /// The default implementation calls LowerOperation.
1276 virtual void LowerOperationWrapper(SDNode *N,
1277 SmallVectorImpl<SDValue> &Results,
1278 SelectionDAG &DAG) const;
1280 /// LowerOperation - This callback is invoked for operations that are
1281 /// unsupported by the target, which are registered to use 'custom' lowering,
1282 /// and whose defined values are all legal.
1283 /// If the target has no operations that require custom lowering, it need not
1284 /// implement this. The default implementation of this aborts.
1285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1287 /// ReplaceNodeResults - This callback is invoked when a node result type is
1288 /// illegal for the target, and the operation was registered to use 'custom'
1289 /// lowering for that result type. The target places new result values for
1290 /// the node in Results (their number and types must exactly match those of
1291 /// the original return values of the node), or leaves Results empty, which
1292 /// indicates that the node is not to be custom lowered after all.
1294 /// If the target has no operations that require custom lowering, it need not
1295 /// implement this. The default implementation aborts.
1296 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1297 SelectionDAG &DAG) const {
1298 assert(0 && "ReplaceNodeResults not implemented for this target!");
1301 /// getTargetNodeName() - This method returns the name of a target specific
1303 virtual const char *getTargetNodeName(unsigned Opcode) const;
1305 /// createFastISel - This method returns a target specific FastISel object,
1306 /// or null if the target does not support "fast" ISel.
1307 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1311 //===--------------------------------------------------------------------===//
1312 // Inline Asm Support hooks
1315 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1316 /// call to be explicit llvm code if it wants to. This is useful for
1317 /// turning simple inline asms into LLVM intrinsics, which gives the
1318 /// compiler more information about the behavior of the code.
1319 virtual bool ExpandInlineAsm(CallInst *CI) const {
1323 enum ConstraintType {
1324 C_Register, // Constraint represents specific register(s).
1325 C_RegisterClass, // Constraint represents any of register(s) in class.
1326 C_Memory, // Memory constraint.
1327 C_Other, // Something else.
1328 C_Unknown // Unsupported constraint.
1331 /// AsmOperandInfo - This contains information for each constraint that we are
1333 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1334 /// ConstraintCode - This contains the actual string for the code, like "m".
1335 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1336 /// most closely matches the operand.
1337 std::string ConstraintCode;
1339 /// ConstraintType - Information about the constraint code, e.g. Register,
1340 /// RegisterClass, Memory, Other, Unknown.
1341 TargetLowering::ConstraintType ConstraintType;
1343 /// CallOperandval - If this is the result output operand or a
1344 /// clobber, this is null, otherwise it is the incoming operand to the
1345 /// CallInst. This gets modified as the asm is processed.
1346 Value *CallOperandVal;
1348 /// ConstraintVT - The ValueType for the operand value.
1351 /// isMatchingInputConstraint - Return true of this is an input operand that
1352 /// is a matching constraint like "4".
1353 bool isMatchingInputConstraint() const;
1355 /// getMatchedOperand - If this is an input matching constraint, this method
1356 /// returns the output operand it matches.
1357 unsigned getMatchedOperand() const;
1359 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1360 : InlineAsm::ConstraintInfo(info),
1361 ConstraintType(TargetLowering::C_Unknown),
1362 CallOperandVal(0), ConstraintVT(MVT::Other) {
1366 /// ComputeConstraintToUse - Determines the constraint code and constraint
1367 /// type to use for the specific AsmOperandInfo, setting
1368 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1369 /// being passed in is available, it can be passed in as Op, otherwise an
1370 /// empty SDValue can be passed.
1371 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1373 SelectionDAG *DAG = 0) const;
1375 /// getConstraintType - Given a constraint, return the type of constraint it
1376 /// is for this target.
1377 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1379 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1380 /// return a list of registers that can be used to satisfy the constraint.
1381 /// This should only be used for C_RegisterClass constraints.
1382 virtual std::vector<unsigned>
1383 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1386 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1387 /// {edx}), return the register number and the register class for the
1390 /// Given a register class constraint, like 'r', if this corresponds directly
1391 /// to an LLVM register class, return a register of 0 and the register class
1394 /// This should only be used for C_Register constraints. On error,
1395 /// this returns a register number of 0 and a null register class pointer..
1396 virtual std::pair<unsigned, const TargetRegisterClass*>
1397 getRegForInlineAsmConstraint(const std::string &Constraint,
1400 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1401 /// with another that has more specific requirements based on the type of the
1402 /// corresponding operand. This returns null if there is no replacement to
1404 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1406 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1407 /// vector. If it is invalid, don't add anything to Ops.
1408 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1409 std::vector<SDValue> &Ops,
1410 SelectionDAG &DAG) const;
1412 //===--------------------------------------------------------------------===//
1413 // Instruction Emitting Hooks
1416 // EmitInstrWithCustomInserter - This method should be implemented by targets
1417 // that mark instructions with the 'usesCustomInserter' flag. These
1418 // instructions are special in various ways, which require special support to
1419 // insert. The specified MachineInstr is created but not inserted into any
1420 // basic blocks, and this method is called to expand it into a sequence of
1421 // instructions, potentially also creating new basic blocks and control flow.
1422 virtual MachineBasicBlock *
1423 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1425 //===--------------------------------------------------------------------===//
1426 // Addressing mode description hooks (used by LSR etc).
1429 /// AddrMode - This represents an addressing mode of:
1430 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1431 /// If BaseGV is null, there is no BaseGV.
1432 /// If BaseOffs is zero, there is no base offset.
1433 /// If HasBaseReg is false, there is no base register.
1434 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1438 GlobalValue *BaseGV;
1442 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1445 /// isLegalAddressingMode - Return true if the addressing mode represented by
1446 /// AM is legal for this target, for a load/store of the specified type.
1447 /// The type may be VoidTy, in which case only return true if the addressing
1448 /// mode is legal for a load/store of any legal type.
1449 /// TODO: Handle pre/postinc as well.
1450 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1452 /// isTruncateFree - Return true if it's free to truncate a value of
1453 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1454 /// register EAX to i16 by referencing its sub-register AX.
1455 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1459 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1463 /// isZExtFree - Return true if any actual instruction that defines a
1464 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1465 /// register. This does not necessarily include registers defined in
1466 /// unknown ways, such as incoming arguments, or copies from unknown
1467 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1468 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1469 /// all instructions that define 32-bit values implicit zero-extend the
1470 /// result out to 64 bits.
1471 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1475 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1479 /// isNarrowingProfitable - Return true if it's profitable to narrow
1480 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1481 /// from i32 to i8 but not from i32 to i16.
1482 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1486 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1487 /// icmp immediate, that is the target has icmp instructions which can compare
1488 /// a register against the immediate without having to materialize the
1489 /// immediate into a register.
1490 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1494 //===--------------------------------------------------------------------===//
1495 // Div utility functions
1497 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1498 std::vector<SDNode*>* Created) const;
1499 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1500 std::vector<SDNode*>* Created) const;
1503 //===--------------------------------------------------------------------===//
1504 // Runtime Library hooks
1507 /// setLibcallName - Rename the default libcall routine name for the specified
1509 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1510 LibcallRoutineNames[Call] = Name;
1513 /// getLibcallName - Get the libcall routine name for the specified libcall.
1515 const char *getLibcallName(RTLIB::Libcall Call) const {
1516 return LibcallRoutineNames[Call];
1519 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1520 /// result of the comparison libcall against zero.
1521 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1522 CmpLibcallCCs[Call] = CC;
1525 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1526 /// the comparison libcall against zero.
1527 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1528 return CmpLibcallCCs[Call];
1531 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1532 /// specified libcall.
1533 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1534 LibcallCallingConvs[Call] = CC;
1537 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1538 /// specified libcall.
1539 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1540 return LibcallCallingConvs[Call];
1544 const TargetMachine &TM;
1545 const TargetData *TD;
1546 const TargetLoweringObjectFile &TLOF;
1548 /// PointerTy - The type to use for pointers, usually i32 or i64.
1552 /// IsLittleEndian - True if this is a little endian target.
1554 bool IsLittleEndian;
1556 /// SelectIsExpensive - Tells the code generator not to expand operations
1557 /// into sequences that use the select operations if possible.
1558 bool SelectIsExpensive;
1560 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1561 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1562 /// a real cost model is in place. If we ever optimize for size, this will be
1563 /// set to true unconditionally.
1566 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1567 /// srl/add/sra for a signed divide by power of two, and let the target handle
1569 bool Pow2DivIsCheap;
1571 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1572 /// llvm.setjmp. Defaults to false.
1573 bool UseUnderscoreSetJmp;
1575 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1576 /// llvm.longjmp. Defaults to false.
1577 bool UseUnderscoreLongJmp;
1579 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1583 /// BooleanContents - Information about the contents of the high-bits in
1584 /// boolean values held in a type wider than i1. See getBooleanContents.
1585 BooleanContent BooleanContents;
1587 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1588 /// total cycles or lowest register usage.
1589 Sched::Preference SchedPreferenceInfo;
1591 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1592 unsigned JumpBufSize;
1594 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1596 unsigned JumpBufAlignment;
1598 /// MinStackArgumentAlignment - The minimum alignment that any argument
1599 /// on the stack needs to have.
1601 unsigned MinStackArgumentAlignment;
1603 /// PrefLoopAlignment - The perferred loop alignment.
1605 unsigned PrefLoopAlignment;
1607 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1608 /// be folded into the enclosed atomic intrinsic instruction by the
1610 bool ShouldFoldAtomicFences;
1612 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1613 /// specifies the register that llvm.savestack/llvm.restorestack should save
1615 unsigned StackPointerRegisterToSaveRestore;
1617 /// ExceptionPointerRegister - If set to a physical register, this specifies
1618 /// the register that receives the exception address on entry to a landing
1620 unsigned ExceptionPointerRegister;
1622 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1623 /// the register that receives the exception typeid on entry to a landing
1625 unsigned ExceptionSelectorRegister;
1627 /// RegClassForVT - This indicates the default register class to use for
1628 /// each ValueType the target supports natively.
1629 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1630 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1631 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1633 /// RepRegClassForVT - This indicates the "representative" register class to
1634 /// use for each ValueType the target supports natively. This information is
1635 /// used by the scheduler to track register pressure. By default, the
1636 /// representative register class is the largest legal super-reg register
1637 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1638 /// and i32's representative class would be GR32.
1639 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1641 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1642 /// register class for each ValueType. The cost is used by the scheduler to
1643 /// approximate register pressure.
1644 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1646 /// Synthesizable indicates whether it is OK for the compiler to create new
1647 /// operations using this type. All Legal types are Synthesizable except
1648 /// MMX types on X86. Non-Legal types are not Synthesizable.
1649 bool Synthesizable[MVT::LAST_VALUETYPE];
1651 /// TransformToType - For any value types we are promoting or expanding, this
1652 /// contains the value type that we are changing to. For Expanded types, this
1653 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1654 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1655 /// by the system, this holds the same type (e.g. i32 -> i32).
1656 EVT TransformToType[MVT::LAST_VALUETYPE];
1658 /// OpActions - For each operation and each value type, keep a LegalizeAction
1659 /// that indicates how instruction selection should deal with the operation.
1660 /// Most operations are Legal (aka, supported natively by the target), but
1661 /// operations that are not should be described. Note that operations on
1662 /// non-legal value types are not described here.
1663 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1665 /// LoadExtActions - For each load extension type and each value type,
1666 /// keep a LegalizeAction that indicates how instruction selection should deal
1667 /// with a load of a specific value type and extension type.
1668 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1670 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1671 /// indicates whether a truncating store of a specific value type and
1672 /// truncating type is legal.
1673 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1675 /// IndexedModeActions - For each indexed mode and each value type,
1676 /// keep a pair of LegalizeAction that indicates how instruction
1677 /// selection should deal with the load / store. The first dimension is the
1678 /// value_type for the reference. The second dimension represents the various
1679 /// modes for load store.
1680 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1682 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1683 /// LegalizeAction that indicates how instruction selection should
1684 /// deal with the condition code.
1685 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1687 ValueTypeActionImpl ValueTypeActions;
1689 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1691 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1692 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1693 /// which sets a bit in this array.
1695 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1697 /// PromoteToType - For operations that must be promoted to a specific type,
1698 /// this holds the destination type. This map should be sparse, so don't hold
1701 /// Targets add entries to this map with AddPromotedToType(..), clients access
1702 /// this with getTypeToPromoteTo(..).
1703 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1706 /// LibcallRoutineNames - Stores the name each libcall.
1708 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1710 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1711 /// of each of the comparison libcall against zero.
1712 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1714 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1716 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1719 /// When lowering \@llvm.memset this field specifies the maximum number of
1720 /// store operations that may be substituted for the call to memset. Targets
1721 /// must set this value based on the cost threshold for that target. Targets
1722 /// should assume that the memset will be done using as many of the largest
1723 /// store operations first, followed by smaller ones, if necessary, per
1724 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1725 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1726 /// store. This only applies to setting a constant array of a constant size.
1727 /// @brief Specify maximum number of store instructions per memset call.
1728 unsigned maxStoresPerMemset;
1730 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1731 /// store operations that may be substituted for a call to memcpy. Targets
1732 /// must set this value based on the cost threshold for that target. Targets
1733 /// should assume that the memcpy will be done using as many of the largest
1734 /// store operations first, followed by smaller ones, if necessary, per
1735 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1736 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1737 /// and one 1-byte store. This only applies to copying a constant array of
1739 /// @brief Specify maximum bytes of store instructions per memcpy call.
1740 unsigned maxStoresPerMemcpy;
1742 /// When lowering \@llvm.memmove this field specifies the maximum number of
1743 /// store instructions that may be substituted for a call to memmove. Targets
1744 /// must set this value based on the cost threshold for that target. Targets
1745 /// should assume that the memmove will be done using as many of the largest
1746 /// store operations first, followed by smaller ones, if necessary, per
1747 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1748 /// with 8-bit alignment would result in nine 1-byte stores. This only
1749 /// applies to copying a constant array of constant size.
1750 /// @brief Specify maximum bytes of store instructions per memmove call.
1751 unsigned maxStoresPerMemmove;
1753 /// This field specifies whether the target can benefit from code placement
1755 bool benefitFromCodePlacementOpt;
1758 /// isLegalRC - Return true if the value types that can be represented by the
1759 /// specified register class are all legal.
1760 bool isLegalRC(const TargetRegisterClass *RC) const;
1762 /// hasLegalSuperRegRegClasses - Return true if the specified register class
1763 /// has one or more super-reg register classes that are legal.
1764 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
1767 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1768 /// compute the return value EVTs and flags, and optionally also
1769 /// the offsets, if the return value is being lowered to memory.
1770 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1771 SmallVectorImpl<ISD::OutputArg> &Outs,
1772 const TargetLowering &TLI,
1773 SmallVectorImpl<uint64_t> *Offsets = 0);
1775 } // end llvm namespace