1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector // This vector should be widened into a larger vector.
106 /// LegalizeKind holds the legalization kind that needs to happen to EVT
107 /// in order to type-legalize it.
108 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
110 /// Enum that describes how the target represents true/false values.
111 enum BooleanContent {
112 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
113 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
114 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
117 /// Enum that describes what type of support for selects the target has.
118 enum SelectSupportKind {
119 ScalarValSelect, // The target supports scalar selects (ex: cmov).
120 ScalarCondVectorVal, // The target supports selects with a scalar condition
121 // and vector values (ex: cmov).
122 VectorMaskSelect // The target supports vector selects with a vector
123 // mask (ex: x86 blends).
126 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
127 /// because different targets have different levels of support for these
128 /// atomic RMW instructions, and also have different options w.r.t. what they should
130 enum class AtomicRMWExpansionKind {
131 None, // Don't expand the instruction.
132 LLSC, // Expand the instruction into loadlinked/storeconditional; used
133 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
135 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
138 static ISD::NodeType getExtendForContent(BooleanContent Content) {
140 case UndefinedBooleanContent:
141 // Extend by adding rubbish bits.
142 return ISD::ANY_EXTEND;
143 case ZeroOrOneBooleanContent:
144 // Extend by adding zero bits.
145 return ISD::ZERO_EXTEND;
146 case ZeroOrNegativeOneBooleanContent:
147 // Extend by copying the sign bit.
148 return ISD::SIGN_EXTEND;
150 llvm_unreachable("Invalid content kind");
153 /// NOTE: The TargetMachine owns TLOF.
154 explicit TargetLoweringBase(const TargetMachine &TM);
155 virtual ~TargetLoweringBase() {}
158 /// \brief Initialize all of the actions to default values.
162 const TargetMachine &getTargetMachine() const { return TM; }
163 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
165 bool isBigEndian() const { return !IsLittleEndian; }
166 bool isLittleEndian() const { return IsLittleEndian; }
168 /// Return the pointer type for the given address space, defaults to
169 /// the pointer type from the data layout.
170 /// FIXME: The default needs to be removed once all the code is updated.
171 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
172 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
173 unsigned getPointerTypeSizeInBits(Type *Ty) const;
174 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
176 EVT getShiftAmountTy(EVT LHSTy) const;
178 /// Returns the type to be used for the index operand of:
179 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
180 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
181 virtual MVT getVectorIdxTy() const {
182 return getPointerTy();
185 /// Return true if the select operation is expensive for this target.
186 bool isSelectExpensive() const { return SelectIsExpensive; }
188 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
192 /// Return true if multiple condition registers are available.
193 bool hasMultipleConditionRegisters() const {
194 return HasMultipleConditionRegisters;
197 /// Return true if the target has BitExtract instructions.
198 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
200 /// Return the preferred vector type legalization action.
201 virtual TargetLoweringBase::LegalizeTypeAction
202 getPreferredVectorAction(EVT VT) const {
203 // The default action for one element vectors is to scalarize
204 if (VT.getVectorNumElements() == 1)
205 return TypeScalarizeVector;
206 // The default action for other vectors is to promote
207 return TypePromoteInteger;
210 // There are two general methods for expanding a BUILD_VECTOR node:
211 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
213 // 2. Build the vector on the stack and then load it.
214 // If this function returns true, then method (1) will be used, subject to
215 // the constraint that all of the necessary shuffles are legal (as determined
216 // by isShuffleMaskLegal). If this function returns false, then method (2) is
217 // always used. The vector type, and the number of defined values, are
220 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
221 unsigned DefinedValues) const {
222 return DefinedValues < 3;
225 /// Return true if integer divide is usually cheaper than a sequence of
226 /// several shifts, adds, and multiplies for this target.
227 bool isIntDivCheap() const { return IntDivIsCheap; }
229 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
230 bool isFsqrtCheap() const {
234 /// Returns true if target has indicated at least one type should be bypassed.
235 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
237 /// Returns map of slow types for division or remainder with corresponding
239 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
240 return BypassSlowDivWidths;
243 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
244 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
246 /// Return true if Flow Control is an expensive operation that should be
248 bool isJumpExpensive() const { return JumpIsExpensive; }
250 /// Return true if selects are only cheaper than branches if the branch is
251 /// unlikely to be predicted right.
252 bool isPredictableSelectExpensive() const {
253 return PredictableSelectIsExpensive;
256 /// isLoadBitCastBeneficial() - Return true if the following transform
258 /// fold (conv (load x)) -> (load (conv*)x)
259 /// On architectures that don't natively support some vector loads efficiently,
260 /// casting the load to a smaller vector of larger types and loading
261 /// is more efficient, however, this can be undone by optimizations in
263 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
267 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
268 virtual bool isCheapToSpeculateCttz() const {
272 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
273 virtual bool isCheapToSpeculateCtlz() const {
277 /// \brief Return if the target supports combining a
280 /// %andResult = and %val1, #imm-with-one-bit-set;
281 /// %icmpResult = icmp %andResult, 0
282 /// br i1 %icmpResult, label %dest1, label %dest2
284 /// into a single machine instruction of a form like:
286 /// brOnBitSet %register, #bitNumber, dest
288 bool isMaskAndBranchFoldingLegal() const {
289 return MaskAndBranchFoldingIsLegal;
292 /// \brief Return true if the target wants to use the optimization that
293 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
294 /// promotedInst1(...(promotedInstN(ext(load)))).
295 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
297 /// Return true if the target can combine store(extractelement VectorTy,
299 /// \p Cost[out] gives the cost of that transformation when this is true.
300 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
301 unsigned &Cost) const {
305 /// Return true if target supports floating point exceptions.
306 bool hasFloatingPointExceptions() const {
307 return HasFloatingPointExceptions;
310 /// Return true if target always beneficiates from combining into FMA for a
311 /// given value type. This must typically return false on targets where FMA
312 /// takes more cycles to execute than FADD.
313 virtual bool enableAggressiveFMAFusion(EVT VT) const {
317 /// Return the ValueType of the result of SETCC operations.
318 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
320 /// Return the ValueType for comparison libcalls. Comparions libcalls include
321 /// floating point comparion calls, and Ordered/Unordered check calls on
322 /// floating point numbers.
324 MVT::SimpleValueType getCmpLibcallReturnType() const;
326 /// For targets without i1 registers, this gives the nature of the high-bits
327 /// of boolean values held in types wider than i1.
329 /// "Boolean values" are special true/false values produced by nodes like
330 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
331 /// Not to be confused with general values promoted from i1. Some cpus
332 /// distinguish between vectors of boolean and scalars; the isVec parameter
333 /// selects between the two kinds. For example on X86 a scalar boolean should
334 /// be zero extended from i1, while the elements of a vector of booleans
335 /// should be sign extended from i1.
337 /// Some cpus also treat floating point types the same way as they treat
338 /// vectors instead of the way they treat scalars.
339 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
341 return BooleanVectorContents;
342 return isFloat ? BooleanFloatContents : BooleanContents;
345 BooleanContent getBooleanContents(EVT Type) const {
346 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
349 /// Return target scheduling preference.
350 Sched::Preference getSchedulingPreference() const {
351 return SchedPreferenceInfo;
354 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
355 /// for different nodes. This function returns the preference (or none) for
357 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
361 /// Return the register class that should be used for the specified value
363 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
364 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
365 assert(RC && "This value type is not natively supported!");
369 /// Return the 'representative' register class for the specified value
372 /// The 'representative' register class is the largest legal super-reg
373 /// register class for the register class of the value type. For example, on
374 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
375 /// register class is GR64 on x86_64.
376 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
377 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
381 /// Return the cost of the 'representative' register class for the specified
383 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
384 return RepRegClassCostForVT[VT.SimpleTy];
387 /// Return true if the target has native support for the specified value type.
388 /// This means that it has a register that directly holds it without
389 /// promotions or expansions.
390 bool isTypeLegal(EVT VT) const {
391 assert(!VT.isSimple() ||
392 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
393 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
396 class ValueTypeActionImpl {
397 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
398 /// that indicates how instruction selection should deal with the type.
399 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
402 ValueTypeActionImpl() {
403 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
406 LegalizeTypeAction getTypeAction(MVT VT) const {
407 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
410 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
411 unsigned I = VT.SimpleTy;
412 ValueTypeActions[I] = Action;
416 const ValueTypeActionImpl &getValueTypeActions() const {
417 return ValueTypeActions;
420 /// Return how we should legalize values of this type, either it is already
421 /// legal (return 'Legal') or we need to promote it to a larger type (return
422 /// 'Promote'), or we need to expand it into multiple registers of smaller
423 /// integer type (return 'Expand'). 'Custom' is not an option.
424 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
425 return getTypeConversion(Context, VT).first;
427 LegalizeTypeAction getTypeAction(MVT VT) const {
428 return ValueTypeActions.getTypeAction(VT);
431 /// For types supported by the target, this is an identity function. For
432 /// types that must be promoted to larger types, this returns the larger type
433 /// to promote to. For integer types that are larger than the largest integer
434 /// register, this contains one step in the expansion to get to the smaller
435 /// register. For illegal floating point types, this returns the integer type
437 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
438 return getTypeConversion(Context, VT).second;
441 /// For types supported by the target, this is an identity function. For
442 /// types that must be expanded (i.e. integer types that are larger than the
443 /// largest integer register or illegal floating point types), this returns
444 /// the largest legal type it will be expanded to.
445 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
446 assert(!VT.isVector());
448 switch (getTypeAction(Context, VT)) {
451 case TypeExpandInteger:
452 VT = getTypeToTransformTo(Context, VT);
455 llvm_unreachable("Type is not legal nor is it to be expanded!");
460 /// Vector types are broken down into some number of legal first class types.
461 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
462 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
463 /// turns into 4 EVT::i32 values with both PPC and X86.
465 /// This method returns the number of registers needed, and the VT for each
466 /// register. It also returns the VT and quantity of the intermediate values
467 /// before they are promoted/expanded.
468 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
470 unsigned &NumIntermediates,
471 MVT &RegisterVT) const;
473 struct IntrinsicInfo {
474 unsigned opc; // target opcode
475 EVT memVT; // memory VT
476 const Value* ptrVal; // value representing memory location
477 int offset; // offset off of ptrVal
478 unsigned size; // the size of the memory location
479 // (taken from memVT if zero)
480 unsigned align; // alignment
481 bool vol; // is volatile?
482 bool readMem; // reads memory?
483 bool writeMem; // writes memory?
485 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
486 vol(false), readMem(false), writeMem(false) {}
489 /// Given an intrinsic, checks if on the target the intrinsic will need to map
490 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
491 /// true and store the intrinsic information into the IntrinsicInfo that was
492 /// passed to the function.
493 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
494 unsigned /*Intrinsic*/) const {
498 /// Returns true if the target can instruction select the specified FP
499 /// immediate natively. If false, the legalizer will materialize the FP
500 /// immediate as a load from a constant pool.
501 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
505 /// Targets can use this to indicate that they only support *some*
506 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
507 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
509 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
514 /// Returns true if the operation can trap for the value type.
516 /// VT must be a legal type. By default, we optimistically assume most
517 /// operations don't trap except for divide and remainder.
518 virtual bool canOpTrap(unsigned Op, EVT VT) const;
520 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
521 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
522 /// a VAND with a constant pool entry.
523 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
528 /// Return how this operation should be treated: either it is legal, needs to
529 /// be promoted to a larger size, needs to be expanded to some other code
530 /// sequence, or the target has a custom expander for it.
531 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
532 if (VT.isExtended()) return Expand;
533 // If a target-specific SDNode requires legalization, require the target
534 // to provide custom legalization for it.
535 if (Op > array_lengthof(OpActions[0])) return Custom;
536 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
537 return (LegalizeAction)OpActions[I][Op];
540 /// Return true if the specified operation is legal on this target or can be
541 /// made legal with custom lowering. This is used to help guide high-level
542 /// lowering decisions.
543 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
544 return (VT == MVT::Other || isTypeLegal(VT)) &&
545 (getOperationAction(Op, VT) == Legal ||
546 getOperationAction(Op, VT) == Custom);
549 /// Return true if the specified operation is legal on this target or can be
550 /// made legal using promotion. This is used to help guide high-level lowering
552 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
553 return (VT == MVT::Other || isTypeLegal(VT)) &&
554 (getOperationAction(Op, VT) == Legal ||
555 getOperationAction(Op, VT) == Promote);
558 /// Return true if the specified operation is illegal on this target or
559 /// unlikely to be made legal with custom lowering. This is used to help guide
560 /// high-level lowering decisions.
561 bool isOperationExpand(unsigned Op, EVT VT) const {
562 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
565 /// Return true if the specified operation is legal on this target.
566 bool isOperationLegal(unsigned Op, EVT VT) const {
567 return (VT == MVT::Other || isTypeLegal(VT)) &&
568 getOperationAction(Op, VT) == Legal;
571 /// Return how this load with extension should be treated: either it is legal,
572 /// needs to be promoted to a larger size, needs to be expanded to some other
573 /// code sequence, or the target has a custom expander for it.
574 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const {
575 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
576 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
577 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
578 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
579 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
580 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
583 /// Return true if the specified load with extension is legal on this target.
584 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
585 return ValVT.isSimple() && MemVT.isSimple() &&
586 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
589 /// Return true if the specified load with extension is legal or custom
591 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
592 return ValVT.isSimple() && MemVT.isSimple() &&
593 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
594 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
597 /// Return how this store with truncation should be treated: either it is
598 /// legal, needs to be promoted to a larger size, needs to be expanded to some
599 /// other code sequence, or the target has a custom expander for it.
600 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
601 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
602 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
603 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
604 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
605 "Table isn't big enough!");
606 return (LegalizeAction)TruncStoreActions[ValI][MemI];
609 /// Return true if the specified store with truncation is legal on this
611 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
612 return isTypeLegal(ValVT) && MemVT.isSimple() &&
613 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
616 /// Return how the indexed load should be treated: either it is legal, needs
617 /// to be promoted to a larger size, needs to be expanded to some other code
618 /// sequence, or the target has a custom expander for it.
620 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
621 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
622 "Table isn't big enough!");
623 unsigned Ty = (unsigned)VT.SimpleTy;
624 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
627 /// Return true if the specified indexed load is legal on this target.
628 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
629 return VT.isSimple() &&
630 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
631 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
634 /// Return how the indexed store should be treated: either it is legal, needs
635 /// to be promoted to a larger size, needs to be expanded to some other code
636 /// sequence, or the target has a custom expander for it.
638 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
639 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
640 "Table isn't big enough!");
641 unsigned Ty = (unsigned)VT.SimpleTy;
642 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
645 /// Return true if the specified indexed load is legal on this target.
646 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
647 return VT.isSimple() &&
648 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
649 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
652 /// Return how the condition code should be treated: either it is legal, needs
653 /// to be expanded to some other code sequence, or the target has a custom
656 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
657 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
658 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
659 "Table isn't big enough!");
660 // See setCondCodeAction for how this is encoded.
661 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
662 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
663 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
664 assert(Action != Promote && "Can't promote condition code!");
668 /// Return true if the specified condition code is legal on this target.
669 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
671 getCondCodeAction(CC, VT) == Legal ||
672 getCondCodeAction(CC, VT) == Custom;
676 /// If the action for this operation is to promote, this method returns the
677 /// ValueType to promote to.
678 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
679 assert(getOperationAction(Op, VT) == Promote &&
680 "This operation isn't promoted!");
682 // See if this has an explicit type specified.
683 std::map<std::pair<unsigned, MVT::SimpleValueType>,
684 MVT::SimpleValueType>::const_iterator PTTI =
685 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
686 if (PTTI != PromoteToType.end()) return PTTI->second;
688 assert((VT.isInteger() || VT.isFloatingPoint()) &&
689 "Cannot autopromote this type, add it with AddPromotedToType.");
693 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
694 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
695 "Didn't find type to promote to!");
696 } while (!isTypeLegal(NVT) ||
697 getOperationAction(Op, NVT) == Promote);
701 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
702 /// operations except for the pointer size. If AllowUnknown is true, this
703 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
704 /// otherwise it will assert.
705 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
706 // Lower scalar pointers to native pointer types.
707 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
708 return getPointerTy(PTy->getAddressSpace());
710 if (Ty->isVectorTy()) {
711 VectorType *VTy = cast<VectorType>(Ty);
712 Type *Elm = VTy->getElementType();
713 // Lower vectors of pointers to native pointer types.
714 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
715 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
716 Elm = PointerTy.getTypeForEVT(Ty->getContext());
719 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
720 VTy->getNumElements());
722 return EVT::getEVT(Ty, AllowUnknown);
725 /// Return the MVT corresponding to this LLVM type. See getValueType.
726 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
727 return getValueType(Ty, AllowUnknown).getSimpleVT();
730 /// Return the desired alignment for ByVal or InAlloca aggregate function
731 /// arguments in the caller parameter area. This is the actual alignment, not
733 virtual unsigned getByValTypeAlignment(Type *Ty) const;
735 /// Return the type of registers that this ValueType will eventually require.
736 MVT getRegisterType(MVT VT) const {
737 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
738 return RegisterTypeForVT[VT.SimpleTy];
741 /// Return the type of registers that this ValueType will eventually require.
742 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
744 assert((unsigned)VT.getSimpleVT().SimpleTy <
745 array_lengthof(RegisterTypeForVT));
746 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
751 unsigned NumIntermediates;
752 (void)getVectorTypeBreakdown(Context, VT, VT1,
753 NumIntermediates, RegisterVT);
756 if (VT.isInteger()) {
757 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
759 llvm_unreachable("Unsupported extended type!");
762 /// Return the number of registers that this ValueType will eventually
765 /// This is one for any types promoted to live in larger registers, but may be
766 /// more than one for types (like i64) that are split into pieces. For types
767 /// like i140, which are first promoted then expanded, it is the number of
768 /// registers needed to hold all the bits of the original type. For an i140
769 /// on a 32 bit machine this means 5 registers.
770 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
772 assert((unsigned)VT.getSimpleVT().SimpleTy <
773 array_lengthof(NumRegistersForVT));
774 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
779 unsigned NumIntermediates;
780 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
782 if (VT.isInteger()) {
783 unsigned BitWidth = VT.getSizeInBits();
784 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
785 return (BitWidth + RegWidth - 1) / RegWidth;
787 llvm_unreachable("Unsupported extended type!");
790 /// If true, then instruction selection should seek to shrink the FP constant
791 /// of the specified type to a smaller type in order to save space and / or
793 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
795 // Return true if it is profitable to reduce the given load node to a smaller
798 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
799 virtual bool shouldReduceLoadWidth(SDNode *Load,
800 ISD::LoadExtType ExtTy,
805 /// When splitting a value of the specified type into parts, does the Lo
806 /// or Hi part come first? This usually follows the endianness, except
807 /// for ppcf128, where the Hi part always comes first.
808 bool hasBigEndianPartOrdering(EVT VT) const {
809 return isBigEndian() || VT == MVT::ppcf128;
812 /// If true, the target has custom DAG combine transformations that it can
813 /// perform for the specified node.
814 bool hasTargetDAGCombine(ISD::NodeType NT) const {
815 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
816 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
819 /// \brief Get maximum # of store operations permitted for llvm.memset
821 /// This function returns the maximum number of store operations permitted
822 /// to replace a call to llvm.memset. The value is set by the target at the
823 /// performance threshold for such a replacement. If OptSize is true,
824 /// return the limit for functions that have OptSize attribute.
825 unsigned getMaxStoresPerMemset(bool OptSize) const {
826 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
829 /// \brief Get maximum # of store operations permitted for llvm.memcpy
831 /// This function returns the maximum number of store operations permitted
832 /// to replace a call to llvm.memcpy. The value is set by the target at the
833 /// performance threshold for such a replacement. If OptSize is true,
834 /// return the limit for functions that have OptSize attribute.
835 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
836 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
839 /// \brief Get maximum # of store operations permitted for llvm.memmove
841 /// This function returns the maximum number of store operations permitted
842 /// to replace a call to llvm.memmove. The value is set by the target at the
843 /// performance threshold for such a replacement. If OptSize is true,
844 /// return the limit for functions that have OptSize attribute.
845 unsigned getMaxStoresPerMemmove(bool OptSize) const {
846 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
849 /// \brief Determine if the target supports unaligned memory accesses.
851 /// This function returns true if the target allows unaligned memory accesses
852 /// of the specified type in the given address space. If true, it also returns
853 /// whether the unaligned memory access is "fast" in the last argument by
854 /// reference. This is used, for example, in situations where an array
855 /// copy/move/set is converted to a sequence of store operations. Its use
856 /// helps to ensure that such replacements don't generate code that causes an
857 /// alignment error (trap) on the target machine.
858 virtual bool allowsMisalignedMemoryAccesses(EVT,
859 unsigned AddrSpace = 0,
861 bool * /*Fast*/ = nullptr) const {
865 /// Returns the target specific optimal type for load and store operations as
866 /// a result of memset, memcpy, and memmove lowering.
868 /// If DstAlign is zero that means it's safe to destination alignment can
869 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
870 /// a need to check it against alignment requirement, probably because the
871 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
872 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
873 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
874 /// does not need to be loaded. It returns EVT::Other if the type should be
875 /// determined using generic target-independent logic.
876 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
877 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
880 bool /*MemcpyStrSrc*/,
881 MachineFunction &/*MF*/) const {
885 /// Returns true if it's safe to use load / store of the specified type to
886 /// expand memcpy / memset inline.
888 /// This is mostly true for all types except for some special cases. For
889 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
890 /// fstpl which also does type conversion. Note the specified type doesn't
891 /// have to be legal as the hook is used before type legalization.
892 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
894 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
895 bool usesUnderscoreSetJmp() const {
896 return UseUnderscoreSetJmp;
899 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
900 bool usesUnderscoreLongJmp() const {
901 return UseUnderscoreLongJmp;
904 /// Return integer threshold on number of blocks to use jump tables rather
905 /// than if sequence.
906 int getMinimumJumpTableEntries() const {
907 return MinimumJumpTableEntries;
910 /// If a physical register, this specifies the register that
911 /// llvm.savestack/llvm.restorestack should save and restore.
912 unsigned getStackPointerRegisterToSaveRestore() const {
913 return StackPointerRegisterToSaveRestore;
916 /// If a physical register, this returns the register that receives the
917 /// exception address on entry to a landing pad.
918 unsigned getExceptionPointerRegister() const {
919 return ExceptionPointerRegister;
922 /// If a physical register, this returns the register that receives the
923 /// exception typeid on entry to a landing pad.
924 unsigned getExceptionSelectorRegister() const {
925 return ExceptionSelectorRegister;
928 /// Returns the target's jmp_buf size in bytes (if never set, the default is
930 unsigned getJumpBufSize() const {
934 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
936 unsigned getJumpBufAlignment() const {
937 return JumpBufAlignment;
940 /// Return the minimum stack alignment of an argument.
941 unsigned getMinStackArgumentAlignment() const {
942 return MinStackArgumentAlignment;
945 /// Return the minimum function alignment.
946 unsigned getMinFunctionAlignment() const {
947 return MinFunctionAlignment;
950 /// Return the preferred function alignment.
951 unsigned getPrefFunctionAlignment() const {
952 return PrefFunctionAlignment;
955 /// Return the preferred loop alignment.
956 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
957 return PrefLoopAlignment;
960 /// Return whether the DAG builder should automatically insert fences and
961 /// reduce ordering for atomics.
962 bool getInsertFencesForAtomic() const {
963 return InsertFencesForAtomic;
966 /// Return true if the target stores stack protector cookies at a fixed offset
967 /// in some non-standard address space, and populates the address space and
968 /// offset as appropriate.
969 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
970 unsigned &/*Offset*/) const {
974 /// Returns true if a cast between SrcAS and DestAS is a noop.
975 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
979 /// Return true if the pointer arguments to CI should be aligned by aligning
980 /// the object whose address is being passed. If so then MinSize is set to the
981 /// minimum size the object must be to be aligned and PrefAlign is set to the
982 /// preferred alignment.
983 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
984 unsigned & /*PrefAlign*/) const {
988 //===--------------------------------------------------------------------===//
989 /// \name Helpers for TargetTransformInfo implementations
992 /// Get the ISD node that corresponds to the Instruction class opcode.
993 int InstructionOpcodeToISD(unsigned Opcode) const;
995 /// Estimate the cost of type-legalization and the legalized type.
996 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
1000 //===--------------------------------------------------------------------===//
1001 /// \name Helpers for atomic expansion.
1004 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1005 /// and expand AtomicCmpXchgInst.
1006 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1008 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1009 /// corresponding pointee type. This may entail some non-trivial operations to
1010 /// truncate or reconstruct types that will be illegal in the backend. See
1011 /// ARMISelLowering for an example implementation.
1012 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1013 AtomicOrdering Ord) const {
1014 llvm_unreachable("Load linked unimplemented on this target");
1017 /// Perform a store-conditional operation to Addr. Return the status of the
1018 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1019 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1020 Value *Addr, AtomicOrdering Ord) const {
1021 llvm_unreachable("Store conditional unimplemented on this target");
1024 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1025 /// It is called by AtomicExpandPass before expanding an
1026 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1027 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1028 /// This function should either return a nullptr, or a pointer to an IR-level
1029 /// Instruction*. Even complex fence sequences can be represented by a
1030 /// single Instruction* through an intrinsic to be lowered later.
1031 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1032 /// Backends should override this method to produce target-specific intrinsic
1033 /// for their fences.
1034 /// FIXME: Please note that the default implementation here in terms of
1035 /// IR-level fences exists for historical/compatibility reasons and is
1036 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1037 /// consistency. For example, consider the following example:
1038 /// atomic<int> x = y = 0;
1039 /// int r1, r2, r3, r4;
1050 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1051 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1052 /// IR-level fences can prevent it.
1054 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1055 bool IsStore, bool IsLoad) const {
1056 if (!getInsertFencesForAtomic())
1059 if (isAtLeastRelease(Ord) && IsStore)
1060 return Builder.CreateFence(Ord);
1065 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1066 bool IsStore, bool IsLoad) const {
1067 if (!getInsertFencesForAtomic())
1070 if (isAtLeastAcquire(Ord))
1071 return Builder.CreateFence(Ord);
1077 /// Returns true if the given (atomic) store should be expanded by the
1078 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1079 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1083 /// Returns true if arguments should be sign-extended in lib calls.
1084 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1088 /// Returns true if the given (atomic) load should be expanded by the
1089 /// IR-level AtomicExpand pass into a load-linked instruction
1090 /// (through emitLoadLinked()).
1091 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1093 /// Returns how the IR-level AtomicExpand pass should expand the given
1094 /// AtomicRMW, if at all. Default is to never expand.
1095 virtual AtomicRMWExpansionKind
1096 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1097 return AtomicRMWExpansionKind::None;
1100 /// On some platforms, an AtomicRMW that never actually modifies the value
1101 /// (such as fetch_add of 0) can be turned into a fence followed by an
1102 /// atomic load. This may sound useless, but it makes it possible for the
1103 /// processor to keep the cacheline shared, dramatically improving
1104 /// performance. And such idempotent RMWs are useful for implementing some
1105 /// kinds of locks, see for example (justification + benchmarks):
1106 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1107 /// This method tries doing that transformation, returning the atomic load if
1108 /// it succeeds, and nullptr otherwise.
1109 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1110 /// another round of expansion.
1111 virtual LoadInst *lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1115 /// Returns true if we should normalize
1116 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1117 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1118 /// that it saves us from materializing N0 and N1 in an integer register.
1119 /// Targets that are able to perform and/or on flags should return false here.
1120 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1122 // If a target has multiple condition registers, then it likely has logical
1123 // operations on those registers.
1124 if (hasMultipleConditionRegisters())
1126 // Only do the transform if the value won't be split into multiple
1128 LegalizeTypeAction Action = getTypeAction(Context, VT);
1129 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1130 Action != TypeSplitVector;
1133 //===--------------------------------------------------------------------===//
1134 // TargetLowering Configuration Methods - These methods should be invoked by
1135 // the derived class constructor to configure this object for the target.
1138 /// Specify how the target extends the result of integer and floating point
1139 /// boolean values from i1 to a wider type. See getBooleanContents.
1140 void setBooleanContents(BooleanContent Ty) {
1141 BooleanContents = Ty;
1142 BooleanFloatContents = Ty;
1145 /// Specify how the target extends the result of integer and floating point
1146 /// boolean values from i1 to a wider type. See getBooleanContents.
1147 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1148 BooleanContents = IntTy;
1149 BooleanFloatContents = FloatTy;
1152 /// Specify how the target extends the result of a vector boolean value from a
1153 /// vector of i1 to a wider type. See getBooleanContents.
1154 void setBooleanVectorContents(BooleanContent Ty) {
1155 BooleanVectorContents = Ty;
1158 /// Specify the target scheduling preference.
1159 void setSchedulingPreference(Sched::Preference Pref) {
1160 SchedPreferenceInfo = Pref;
1163 /// Indicate whether this target prefers to use _setjmp to implement
1164 /// llvm.setjmp or the version without _. Defaults to false.
1165 void setUseUnderscoreSetJmp(bool Val) {
1166 UseUnderscoreSetJmp = Val;
1169 /// Indicate whether this target prefers to use _longjmp to implement
1170 /// llvm.longjmp or the version without _. Defaults to false.
1171 void setUseUnderscoreLongJmp(bool Val) {
1172 UseUnderscoreLongJmp = Val;
1175 /// Indicate the number of blocks to generate jump tables rather than if
1177 void setMinimumJumpTableEntries(int Val) {
1178 MinimumJumpTableEntries = Val;
1181 /// If set to a physical register, this specifies the register that
1182 /// llvm.savestack/llvm.restorestack should save and restore.
1183 void setStackPointerRegisterToSaveRestore(unsigned R) {
1184 StackPointerRegisterToSaveRestore = R;
1187 /// If set to a physical register, this sets the register that receives the
1188 /// exception address on entry to a landing pad.
1189 void setExceptionPointerRegister(unsigned R) {
1190 ExceptionPointerRegister = R;
1193 /// If set to a physical register, this sets the register that receives the
1194 /// exception typeid on entry to a landing pad.
1195 void setExceptionSelectorRegister(unsigned R) {
1196 ExceptionSelectorRegister = R;
1199 /// Tells the code generator not to expand operations into sequences that use
1200 /// the select operations if possible.
1201 void setSelectIsExpensive(bool isExpensive = true) {
1202 SelectIsExpensive = isExpensive;
1205 /// Tells the code generator that the target has multiple (allocatable)
1206 /// condition registers that can be used to store the results of comparisons
1207 /// for use by selects and conditional branches. With multiple condition
1208 /// registers, the code generator will not aggressively sink comparisons into
1209 /// the blocks of their users.
1210 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1211 HasMultipleConditionRegisters = hasManyRegs;
1214 /// Tells the code generator that the target has BitExtract instructions.
1215 /// The code generator will aggressively sink "shift"s into the blocks of
1216 /// their users if the users will generate "and" instructions which can be
1217 /// combined with "shift" to BitExtract instructions.
1218 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1219 HasExtractBitsInsn = hasExtractInsn;
1222 /// Tells the code generator not to expand sequence of operations into a
1223 /// separate sequences that increases the amount of flow control.
1224 void setJumpIsExpensive(bool isExpensive = true) {
1225 JumpIsExpensive = isExpensive;
1228 /// Tells the code generator that integer divide is expensive, and if
1229 /// possible, should be replaced by an alternate sequence of instructions not
1230 /// containing an integer divide.
1231 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1233 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1234 /// with an alternative sequence of instructions.
1235 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1237 /// Tells the code generator that this target supports floating point
1238 /// exceptions and cares about preserving floating point exception behavior.
1239 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1240 HasFloatingPointExceptions = FPExceptions;
1243 /// Tells the code generator which bitwidths to bypass.
1244 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1245 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1248 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1249 /// signed divide by power of two; let the target handle it.
1250 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1252 /// Add the specified register class as an available regclass for the
1253 /// specified value type. This indicates the selector can handle values of
1254 /// that class natively.
1255 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1256 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1257 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1258 RegClassForVT[VT.SimpleTy] = RC;
1261 /// Remove all register classes.
1262 void clearRegisterClasses() {
1263 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1265 AvailableRegClasses.clear();
1268 /// \brief Remove all operation actions.
1269 void clearOperationActions() {
1272 /// Return the largest legal super-reg register class of the register class
1273 /// for the specified type and its associated "cost".
1274 virtual std::pair<const TargetRegisterClass *, uint8_t>
1275 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1277 /// Once all of the register classes are added, this allows us to compute
1278 /// derived properties we expose.
1279 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1281 /// Indicate that the specified operation does not work with the specified
1282 /// type and indicate what to do about it.
1283 void setOperationAction(unsigned Op, MVT VT,
1284 LegalizeAction Action) {
1285 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1286 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1289 /// Indicate that the specified load with extension does not work with the
1290 /// specified type and indicate what to do about it.
1291 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1292 LegalizeAction Action) {
1293 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1294 MemVT.isValid() && "Table isn't big enough!");
1295 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1298 /// Indicate that the specified truncating store does not work with the
1299 /// specified type and indicate what to do about it.
1300 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1301 LegalizeAction Action) {
1302 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1303 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1306 /// Indicate that the specified indexed load does or does not work with the
1307 /// specified type and indicate what to do abort it.
1309 /// NOTE: All indexed mode loads are initialized to Expand in
1310 /// TargetLowering.cpp
1311 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1312 LegalizeAction Action) {
1313 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1314 (unsigned)Action < 0xf && "Table isn't big enough!");
1315 // Load action are kept in the upper half.
1316 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1317 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1320 /// Indicate that the specified indexed store does or does not work with the
1321 /// specified type and indicate what to do about it.
1323 /// NOTE: All indexed mode stores are initialized to Expand in
1324 /// TargetLowering.cpp
1325 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1326 LegalizeAction Action) {
1327 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1328 (unsigned)Action < 0xf && "Table isn't big enough!");
1329 // Store action are kept in the lower half.
1330 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1331 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1334 /// Indicate that the specified condition code is or isn't supported on the
1335 /// target and indicate what to do about it.
1336 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1337 LegalizeAction Action) {
1338 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1339 "Table isn't big enough!");
1340 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1341 /// value and the upper 27 bits index into the second dimension of the array
1342 /// to select what 32-bit value to use.
1343 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1344 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1345 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1348 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1349 /// to trying a larger integer/fp until it can find one that works. If that
1350 /// default is insufficient, this method can be used by the target to override
1352 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1353 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1356 /// Targets should invoke this method for each target independent node that
1357 /// they want to provide a custom DAG combiner for by implementing the
1358 /// PerformDAGCombine virtual method.
1359 void setTargetDAGCombine(ISD::NodeType NT) {
1360 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1361 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1364 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1365 void setJumpBufSize(unsigned Size) {
1369 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1371 void setJumpBufAlignment(unsigned Align) {
1372 JumpBufAlignment = Align;
1375 /// Set the target's minimum function alignment (in log2(bytes))
1376 void setMinFunctionAlignment(unsigned Align) {
1377 MinFunctionAlignment = Align;
1380 /// Set the target's preferred function alignment. This should be set if
1381 /// there is a performance benefit to higher-than-minimum alignment (in
1383 void setPrefFunctionAlignment(unsigned Align) {
1384 PrefFunctionAlignment = Align;
1387 /// Set the target's preferred loop alignment. Default alignment is zero, it
1388 /// means the target does not care about loop alignment. The alignment is
1389 /// specified in log2(bytes). The target may also override
1390 /// getPrefLoopAlignment to provide per-loop values.
1391 void setPrefLoopAlignment(unsigned Align) {
1392 PrefLoopAlignment = Align;
1395 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1396 void setMinStackArgumentAlignment(unsigned Align) {
1397 MinStackArgumentAlignment = Align;
1400 /// Set if the DAG builder should automatically insert fences and reduce the
1401 /// order of atomic memory operations to Monotonic.
1402 void setInsertFencesForAtomic(bool fence) {
1403 InsertFencesForAtomic = fence;
1407 //===--------------------------------------------------------------------===//
1408 // Addressing mode description hooks (used by LSR etc).
1411 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1412 /// instructions reading the address. This allows as much computation as
1413 /// possible to be done in the address mode for that operand. This hook lets
1414 /// targets also pass back when this should be done on intrinsics which
1416 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1417 SmallVectorImpl<Value*> &/*Ops*/,
1418 Type *&/*AccessTy*/) const {
1422 /// This represents an addressing mode of:
1423 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1424 /// If BaseGV is null, there is no BaseGV.
1425 /// If BaseOffs is zero, there is no base offset.
1426 /// If HasBaseReg is false, there is no base register.
1427 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1430 GlobalValue *BaseGV;
1434 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1437 /// Return true if the addressing mode represented by AM is legal for this
1438 /// target, for a load/store of the specified type.
1440 /// The type may be VoidTy, in which case only return true if the addressing
1441 /// mode is legal for a load/store of any legal type. TODO: Handle
1442 /// pre/postinc as well.
1443 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1445 /// \brief Return the cost of the scaling factor used in the addressing mode
1446 /// represented by AM for this target, for a load/store of the specified type.
1448 /// If the AM is supported, the return value must be >= 0.
1449 /// If the AM is not supported, it returns a negative value.
1450 /// TODO: Handle pre/postinc as well.
1451 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1452 // Default: assume that any scaling factor used in a legal AM is free.
1453 if (isLegalAddressingMode(AM, Ty)) return 0;
1457 /// Return true if the specified immediate is legal icmp immediate, that is
1458 /// the target has icmp instructions which can compare a register against the
1459 /// immediate without having to materialize the immediate into a register.
1460 virtual bool isLegalICmpImmediate(int64_t) const {
1464 /// Return true if the specified immediate is legal add immediate, that is the
1465 /// target has add instructions which can add a register with the immediate
1466 /// without having to materialize the immediate into a register.
1467 virtual bool isLegalAddImmediate(int64_t) const {
1471 /// Return true if it's significantly cheaper to shift a vector by a uniform
1472 /// scalar than by an amount which will vary across each lane. On x86, for
1473 /// example, there is a "psllw" instruction for the former case, but no simple
1474 /// instruction for a general "a << b" operation on vectors.
1475 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1479 /// Return true if it's free to truncate a value of type Ty1 to type
1480 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1481 /// by referencing its sub-register AX.
1482 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1486 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1487 /// whether a call is in tail position. Typically this means that both results
1488 /// would be assigned to the same register or stack slot, but it could mean
1489 /// the target performs adequate checks of its own before proceeding with the
1491 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1495 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1499 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1501 /// Return true if the extension represented by \p I is free.
1502 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1503 /// this method can use the context provided by \p I to decide
1504 /// whether or not \p I is free.
1505 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1506 /// In other words, if is[Z|FP]Free returns true, then this method
1507 /// returns true as well. The converse is not true.
1508 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1509 /// \pre \p I must be a sign, zero, or fp extension.
1510 bool isExtFree(const Instruction *I) const {
1511 switch (I->getOpcode()) {
1512 case Instruction::FPExt:
1513 if (isFPExtFree(EVT::getEVT(I->getType())))
1516 case Instruction::ZExt:
1517 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1520 case Instruction::SExt:
1523 llvm_unreachable("Instruction is not an extension");
1525 return isExtFreeImpl(I);
1528 /// Return true if any actual instruction that defines a value of type Ty1
1529 /// implicitly zero-extends the value to Ty2 in the result register.
1531 /// This does not necessarily include registers defined in unknown ways, such
1532 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1533 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1534 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1535 /// values implicit zero-extend the result out to 64 bits.
1536 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1540 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1544 /// Return true if the target supplies and combines to a paired load
1545 /// two loaded values of type LoadedType next to each other in memory.
1546 /// RequiredAlignment gives the minimal alignment constraints that must be met
1547 /// to be able to select this paired load.
1549 /// This information is *not* used to generate actual paired loads, but it is
1550 /// used to generate a sequence of loads that is easier to combine into a
1552 /// For instance, something like this:
1553 /// a = load i64* addr
1554 /// b = trunc i64 a to i32
1555 /// c = lshr i64 a, 32
1556 /// d = trunc i64 c to i32
1557 /// will be optimized into:
1558 /// b = load i32* addr1
1559 /// d = load i32* addr2
1560 /// Where addr1 = addr2 +/- sizeof(i32).
1562 /// In other words, unless the target performs a post-isel load combining,
1563 /// this information should not be provided because it will generate more
1565 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1566 unsigned & /*RequiredAligment*/) const {
1570 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1571 unsigned & /*RequiredAligment*/) const {
1575 /// Return true if zero-extending the specific node Val to type VT2 is free
1576 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1577 /// because it's folded such as X86 zero-extending loads).
1578 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1579 return isZExtFree(Val.getValueType(), VT2);
1582 /// Return true if an fpext operation is free (for instance, because
1583 /// single-precision floating-point numbers are implicitly extended to
1584 /// double-precision).
1585 virtual bool isFPExtFree(EVT VT) const {
1586 assert(VT.isFloatingPoint());
1590 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1591 /// extend node) is profitable.
1592 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1594 /// Return true if an fneg operation is free to the point where it is never
1595 /// worthwhile to replace it with a bitwise operation.
1596 virtual bool isFNegFree(EVT VT) const {
1597 assert(VT.isFloatingPoint());
1601 /// Return true if an fabs operation is free to the point where it is never
1602 /// worthwhile to replace it with a bitwise operation.
1603 virtual bool isFAbsFree(EVT VT) const {
1604 assert(VT.isFloatingPoint());
1608 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1609 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1610 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1612 /// NOTE: This may be called before legalization on types for which FMAs are
1613 /// not legal, but should return true if those types will eventually legalize
1614 /// to types that support FMAs. After legalization, it will only be called on
1615 /// types that support FMAs (via Legal or Custom actions)
1616 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1620 /// Return true if it's profitable to narrow operations of type VT1 to
1621 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1623 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1627 /// \brief Return true if it is beneficial to convert a load of a constant to
1628 /// just the constant itself.
1629 /// On some targets it might be more efficient to use a combination of
1630 /// arithmetic instructions to materialize the constant instead of loading it
1631 /// from a constant pool.
1632 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1637 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1638 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1639 /// has custom lowering that depends on the index of the first element,
1640 /// and only the target knows which lowering is cheap.
1641 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1645 //===--------------------------------------------------------------------===//
1646 // Runtime Library hooks
1649 /// Rename the default libcall routine name for the specified libcall.
1650 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1651 LibcallRoutineNames[Call] = Name;
1654 /// Get the libcall routine name for the specified libcall.
1655 const char *getLibcallName(RTLIB::Libcall Call) const {
1656 return LibcallRoutineNames[Call];
1659 /// Override the default CondCode to be used to test the result of the
1660 /// comparison libcall against zero.
1661 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1662 CmpLibcallCCs[Call] = CC;
1665 /// Get the CondCode that's to be used to test the result of the comparison
1666 /// libcall against zero.
1667 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1668 return CmpLibcallCCs[Call];
1671 /// Set the CallingConv that should be used for the specified libcall.
1672 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1673 LibcallCallingConvs[Call] = CC;
1676 /// Get the CallingConv that should be used for the specified libcall.
1677 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1678 return LibcallCallingConvs[Call];
1682 const TargetMachine &TM;
1684 /// True if this is a little endian target.
1685 bool IsLittleEndian;
1687 /// Tells the code generator not to expand operations into sequences that use
1688 /// the select operations if possible.
1689 bool SelectIsExpensive;
1691 /// Tells the code generator that the target has multiple (allocatable)
1692 /// condition registers that can be used to store the results of comparisons
1693 /// for use by selects and conditional branches. With multiple condition
1694 /// registers, the code generator will not aggressively sink comparisons into
1695 /// the blocks of their users.
1696 bool HasMultipleConditionRegisters;
1698 /// Tells the code generator that the target has BitExtract instructions.
1699 /// The code generator will aggressively sink "shift"s into the blocks of
1700 /// their users if the users will generate "and" instructions which can be
1701 /// combined with "shift" to BitExtract instructions.
1702 bool HasExtractBitsInsn;
1704 /// Tells the code generator not to expand integer divides by constants into a
1705 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1706 /// model is in place. If we ever optimize for size, this will be set to true
1707 /// unconditionally.
1710 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1713 /// Tells the code generator to bypass slow divide or remainder
1714 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1715 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1716 /// div/rem when the operands are positive and less than 256.
1717 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1719 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1720 /// signed divide by power of two; let the target handle it.
1721 bool Pow2SDivIsCheap;
1723 /// Tells the code generator that it shouldn't generate extra flow control
1724 /// instructions and should attempt to combine flow control instructions via
1726 bool JumpIsExpensive;
1728 /// Whether the target supports or cares about preserving floating point
1729 /// exception behavior.
1730 bool HasFloatingPointExceptions;
1732 /// This target prefers to use _setjmp to implement llvm.setjmp.
1734 /// Defaults to false.
1735 bool UseUnderscoreSetJmp;
1737 /// This target prefers to use _longjmp to implement llvm.longjmp.
1739 /// Defaults to false.
1740 bool UseUnderscoreLongJmp;
1742 /// Number of blocks threshold to use jump tables.
1743 int MinimumJumpTableEntries;
1745 /// Information about the contents of the high-bits in boolean values held in
1746 /// a type wider than i1. See getBooleanContents.
1747 BooleanContent BooleanContents;
1749 /// Information about the contents of the high-bits in boolean values held in
1750 /// a type wider than i1. See getBooleanContents.
1751 BooleanContent BooleanFloatContents;
1753 /// Information about the contents of the high-bits in boolean vector values
1754 /// when the element type is wider than i1. See getBooleanContents.
1755 BooleanContent BooleanVectorContents;
1757 /// The target scheduling preference: shortest possible total cycles or lowest
1759 Sched::Preference SchedPreferenceInfo;
1761 /// The size, in bytes, of the target's jmp_buf buffers
1762 unsigned JumpBufSize;
1764 /// The alignment, in bytes, of the target's jmp_buf buffers
1765 unsigned JumpBufAlignment;
1767 /// The minimum alignment that any argument on the stack needs to have.
1768 unsigned MinStackArgumentAlignment;
1770 /// The minimum function alignment (used when optimizing for size, and to
1771 /// prevent explicitly provided alignment from leading to incorrect code).
1772 unsigned MinFunctionAlignment;
1774 /// The preferred function alignment (used when alignment unspecified and
1775 /// optimizing for speed).
1776 unsigned PrefFunctionAlignment;
1778 /// The preferred loop alignment.
1779 unsigned PrefLoopAlignment;
1781 /// Whether the DAG builder should automatically insert fences and reduce
1782 /// ordering for atomics. (This will be set for for most architectures with
1783 /// weak memory ordering.)
1784 bool InsertFencesForAtomic;
1786 /// If set to a physical register, this specifies the register that
1787 /// llvm.savestack/llvm.restorestack should save and restore.
1788 unsigned StackPointerRegisterToSaveRestore;
1790 /// If set to a physical register, this specifies the register that receives
1791 /// the exception address on entry to a landing pad.
1792 unsigned ExceptionPointerRegister;
1794 /// If set to a physical register, this specifies the register that receives
1795 /// the exception typeid on entry to a landing pad.
1796 unsigned ExceptionSelectorRegister;
1798 /// This indicates the default register class to use for each ValueType the
1799 /// target supports natively.
1800 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1801 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1802 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1804 /// This indicates the "representative" register class to use for each
1805 /// ValueType the target supports natively. This information is used by the
1806 /// scheduler to track register pressure. By default, the representative
1807 /// register class is the largest legal super-reg register class of the
1808 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1809 /// representative class would be GR32.
1810 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1812 /// This indicates the "cost" of the "representative" register class for each
1813 /// ValueType. The cost is used by the scheduler to approximate register
1815 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1817 /// For any value types we are promoting or expanding, this contains the value
1818 /// type that we are changing to. For Expanded types, this contains one step
1819 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1820 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1821 /// the same type (e.g. i32 -> i32).
1822 MVT TransformToType[MVT::LAST_VALUETYPE];
1824 /// For each operation and each value type, keep a LegalizeAction that
1825 /// indicates how instruction selection should deal with the operation. Most
1826 /// operations are Legal (aka, supported natively by the target), but
1827 /// operations that are not should be described. Note that operations on
1828 /// non-legal value types are not described here.
1829 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1831 /// For each load extension type and each value type, keep a LegalizeAction
1832 /// that indicates how instruction selection should deal with a load of a
1833 /// specific value type and extension type.
1834 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1835 [ISD::LAST_LOADEXT_TYPE];
1837 /// For each value type pair keep a LegalizeAction that indicates whether a
1838 /// truncating store of a specific value type and truncating type is legal.
1839 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1841 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1842 /// that indicates how instruction selection should deal with the load /
1845 /// The first dimension is the value_type for the reference. The second
1846 /// dimension represents the various modes for load store.
1847 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1849 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1850 /// indicates how instruction selection should deal with the condition code.
1852 /// Because each CC action takes up 2 bits, we need to have the array size be
1853 /// large enough to fit all of the value types. This can be done by rounding
1854 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1855 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1857 ValueTypeActionImpl ValueTypeActions;
1860 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1863 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1865 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1866 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1869 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1871 /// For operations that must be promoted to a specific type, this holds the
1872 /// destination type. This map should be sparse, so don't hold it as an
1875 /// Targets add entries to this map with AddPromotedToType(..), clients access
1876 /// this with getTypeToPromoteTo(..).
1877 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1880 /// Stores the name each libcall.
1881 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1883 /// The ISD::CondCode that should be used to test the result of each of the
1884 /// comparison libcall against zero.
1885 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1887 /// Stores the CallingConv that should be used for each libcall.
1888 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1891 /// Return true if the extension represented by \p I is free.
1892 /// \pre \p I is a sign, zero, or fp extension and
1893 /// is[Z|FP]ExtFree of the related types is not true.
1894 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1896 /// \brief Specify maximum number of store instructions per memset call.
1898 /// When lowering \@llvm.memset this field specifies the maximum number of
1899 /// store operations that may be substituted for the call to memset. Targets
1900 /// must set this value based on the cost threshold for that target. Targets
1901 /// should assume that the memset will be done using as many of the largest
1902 /// store operations first, followed by smaller ones, if necessary, per
1903 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1904 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1905 /// store. This only applies to setting a constant array of a constant size.
1906 unsigned MaxStoresPerMemset;
1908 /// Maximum number of stores operations that may be substituted for the call
1909 /// to memset, used for functions with OptSize attribute.
1910 unsigned MaxStoresPerMemsetOptSize;
1912 /// \brief Specify maximum bytes of store instructions per memcpy call.
1914 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1915 /// store operations that may be substituted for a call to memcpy. Targets
1916 /// must set this value based on the cost threshold for that target. Targets
1917 /// should assume that the memcpy will be done using as many of the largest
1918 /// store operations first, followed by smaller ones, if necessary, per
1919 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1920 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1921 /// and one 1-byte store. This only applies to copying a constant array of
1923 unsigned MaxStoresPerMemcpy;
1925 /// Maximum number of store operations that may be substituted for a call to
1926 /// memcpy, used for functions with OptSize attribute.
1927 unsigned MaxStoresPerMemcpyOptSize;
1929 /// \brief Specify maximum bytes of store instructions per memmove call.
1931 /// When lowering \@llvm.memmove this field specifies the maximum number of
1932 /// store instructions that may be substituted for a call to memmove. Targets
1933 /// must set this value based on the cost threshold for that target. Targets
1934 /// should assume that the memmove will be done using as many of the largest
1935 /// store operations first, followed by smaller ones, if necessary, per
1936 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1937 /// with 8-bit alignment would result in nine 1-byte stores. This only
1938 /// applies to copying a constant array of constant size.
1939 unsigned MaxStoresPerMemmove;
1941 /// Maximum number of store instructions that may be substituted for a call to
1942 /// memmove, used for functions with OpSize attribute.
1943 unsigned MaxStoresPerMemmoveOptSize;
1945 /// Tells the code generator that select is more expensive than a branch if
1946 /// the branch is usually predicted right.
1947 bool PredictableSelectIsExpensive;
1949 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1950 /// a mask of a single bit, a compare, and a branch into a single instruction.
1951 bool MaskAndBranchFoldingIsLegal;
1953 /// \see enableExtLdPromotion.
1954 bool EnableExtLdPromotion;
1957 /// Return true if the value types that can be represented by the specified
1958 /// register class are all legal.
1959 bool isLegalRC(const TargetRegisterClass *RC) const;
1961 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1962 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1963 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1966 /// This class defines information used to lower LLVM code to legal SelectionDAG
1967 /// operators that the target instruction selector can accept natively.
1969 /// This class also defines callbacks that targets must implement to lower
1970 /// target-specific constructs to SelectionDAG operators.
1971 class TargetLowering : public TargetLoweringBase {
1972 TargetLowering(const TargetLowering&) = delete;
1973 void operator=(const TargetLowering&) = delete;
1976 /// NOTE: The TargetMachine owns TLOF.
1977 explicit TargetLowering(const TargetMachine &TM);
1979 /// Returns true by value, base pointer and offset pointer and addressing mode
1980 /// by reference if the node's address can be legally represented as
1981 /// pre-indexed load / store address.
1982 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1983 SDValue &/*Offset*/,
1984 ISD::MemIndexedMode &/*AM*/,
1985 SelectionDAG &/*DAG*/) const {
1989 /// Returns true by value, base pointer and offset pointer and addressing mode
1990 /// by reference if this node can be combined with a load / store to form a
1991 /// post-indexed load / store.
1992 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1994 SDValue &/*Offset*/,
1995 ISD::MemIndexedMode &/*AM*/,
1996 SelectionDAG &/*DAG*/) const {
2000 /// Return the entry encoding for a jump table in the current function. The
2001 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2002 virtual unsigned getJumpTableEncoding() const;
2004 virtual const MCExpr *
2005 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2006 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2007 MCContext &/*Ctx*/) const {
2008 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2011 /// Returns relocation base for the given PIC jumptable.
2012 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2013 SelectionDAG &DAG) const;
2015 /// This returns the relocation base for the given PIC jumptable, the same as
2016 /// getPICJumpTableRelocBase, but as an MCExpr.
2017 virtual const MCExpr *
2018 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2019 unsigned JTI, MCContext &Ctx) const;
2021 /// Return true if folding a constant offset with the given GlobalAddress is
2022 /// legal. It is frequently not legal in PIC relocation models.
2023 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2025 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2026 SDValue &Chain) const;
2028 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2029 SDValue &NewLHS, SDValue &NewRHS,
2030 ISD::CondCode &CCCode, SDLoc DL) const;
2032 /// Returns a pair of (return value, chain).
2033 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2034 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2035 EVT RetVT, const SDValue *Ops,
2036 unsigned NumOps, bool isSigned,
2037 SDLoc dl, bool doesNotReturn = false,
2038 bool isReturnValueUsed = true) const;
2040 //===--------------------------------------------------------------------===//
2041 // TargetLowering Optimization Methods
2044 /// A convenience struct that encapsulates a DAG, and two SDValues for
2045 /// returning information from TargetLowering to its clients that want to
2047 struct TargetLoweringOpt {
2054 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2056 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2058 bool LegalTypes() const { return LegalTys; }
2059 bool LegalOperations() const { return LegalOps; }
2061 bool CombineTo(SDValue O, SDValue N) {
2067 /// Check to see if the specified operand of the specified instruction is a
2068 /// constant integer. If so, check to see if there are any bits set in the
2069 /// constant that are not demanded. If so, shrink the constant and return
2071 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2073 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2074 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2075 /// generalized for targets with other types of implicit widening casts.
2076 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2080 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2081 /// result of Op are ever used downstream. If we can use this information to
2082 /// simplify Op, create a new simplified DAG node and return true, returning
2083 /// the original and new nodes in Old and New. Otherwise, analyze the
2084 /// expression and return a mask of KnownOne and KnownZero bits for the
2085 /// expression (used to simplify the caller). The KnownZero/One bits may only
2086 /// be accurate for those bits in the DemandedMask.
2087 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2088 APInt &KnownZero, APInt &KnownOne,
2089 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2091 /// Determine which of the bits specified in Mask are known to be either zero
2092 /// or one and return them in the KnownZero/KnownOne bitsets.
2093 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2096 const SelectionDAG &DAG,
2097 unsigned Depth = 0) const;
2099 /// This method can be implemented by targets that want to expose additional
2100 /// information about sign bits to the DAG Combiner.
2101 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2102 const SelectionDAG &DAG,
2103 unsigned Depth = 0) const;
2105 struct DAGCombinerInfo {
2106 void *DC; // The DAG Combiner object.
2108 bool CalledByLegalizer;
2112 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2113 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2115 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2116 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2117 bool isAfterLegalizeVectorOps() const {
2118 return Level == AfterLegalizeDAG;
2120 CombineLevel getDAGCombineLevel() { return Level; }
2121 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2123 void AddToWorklist(SDNode *N);
2124 void RemoveFromWorklist(SDNode *N);
2125 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2126 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2127 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2129 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2132 /// Return if the N is a constant or constant vector equal to the true value
2133 /// from getBooleanContents().
2134 bool isConstTrueVal(const SDNode *N) const;
2136 /// Return if the N is a constant or constant vector equal to the false value
2137 /// from getBooleanContents().
2138 bool isConstFalseVal(const SDNode *N) const;
2140 /// Try to simplify a setcc built with the specified operands and cc. If it is
2141 /// unable to simplify it, return a null SDValue.
2142 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2143 ISD::CondCode Cond, bool foldBooleans,
2144 DAGCombinerInfo &DCI, SDLoc dl) const;
2146 /// Returns true (and the GlobalValue and the offset) if the node is a
2147 /// GlobalAddress + offset.
2149 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2151 /// This method will be invoked for all target nodes and for any
2152 /// target-independent nodes that the target has registered with invoke it
2155 /// The semantics are as follows:
2157 /// SDValue.Val == 0 - No change was made
2158 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2159 /// otherwise - N should be replaced by the returned Operand.
2161 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2162 /// more complex transformations.
2164 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2166 /// Return true if it is profitable to move a following shift through this
2167 // node, adjusting any immediate operands as necessary to preserve semantics.
2168 // This transformation may not be desirable if it disrupts a particularly
2169 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2170 // By default, it returns true.
2171 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2175 /// Return true if the target has native support for the specified value type
2176 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2177 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2178 /// and some i16 instructions are slow.
2179 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2180 // By default, assume all legal types are desirable.
2181 return isTypeLegal(VT);
2184 /// Return true if it is profitable for dag combiner to transform a floating
2185 /// point op of specified opcode to a equivalent op of an integer
2186 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2187 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2192 /// This method query the target whether it is beneficial for dag combiner to
2193 /// promote the specified node. If true, it should return the desired
2194 /// promotion type by reference.
2195 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2199 //===--------------------------------------------------------------------===//
2200 // Lowering methods - These methods must be implemented by targets so that
2201 // the SelectionDAGBuilder code knows how to lower these.
2204 /// This hook must be implemented to lower the incoming (formal) arguments,
2205 /// described by the Ins array, into the specified DAG. The implementation
2206 /// should fill in the InVals array with legal-type argument values, and
2207 /// return the resulting token chain value.
2210 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2212 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2213 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2214 SmallVectorImpl<SDValue> &/*InVals*/) const {
2215 llvm_unreachable("Not Implemented");
2218 struct ArgListEntry {
2227 bool isInAlloca : 1;
2228 bool isReturned : 1;
2231 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2232 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2233 isReturned(false), Alignment(0) { }
2235 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2237 typedef std::vector<ArgListEntry> ArgListTy;
2239 /// This structure contains all information that is necessary for lowering
2240 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2241 /// needs to lower a call, and targets will see this struct in their LowerCall
2243 struct CallLoweringInfo {
2250 bool DoesNotReturn : 1;
2251 bool IsReturnValueUsed : 1;
2253 // IsTailCall should be modified by implementations of
2254 // TargetLowering::LowerCall that perform tail call conversions.
2257 unsigned NumFixedArgs;
2258 CallingConv::ID CallConv;
2263 ImmutableCallSite *CS;
2265 SmallVector<ISD::OutputArg, 32> Outs;
2266 SmallVector<SDValue, 32> OutVals;
2267 SmallVector<ISD::InputArg, 32> Ins;
2269 CallLoweringInfo(SelectionDAG &DAG)
2270 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2271 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2272 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2273 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2275 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2280 CallLoweringInfo &setChain(SDValue InChain) {
2285 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2286 SDValue Target, ArgListTy &&ArgsList,
2287 unsigned FixedArgs = -1) {
2292 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2293 Args = std::move(ArgsList);
2297 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2298 SDValue Target, ArgListTy &&ArgsList,
2299 ImmutableCallSite &Call) {
2302 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2303 DoesNotReturn = Call.doesNotReturn();
2304 IsVarArg = FTy->isVarArg();
2305 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2306 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2307 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2311 CallConv = Call.getCallingConv();
2312 NumFixedArgs = FTy->getNumParams();
2313 Args = std::move(ArgsList);
2320 CallLoweringInfo &setInRegister(bool Value = true) {
2325 CallLoweringInfo &setNoReturn(bool Value = true) {
2326 DoesNotReturn = Value;
2330 CallLoweringInfo &setVarArg(bool Value = true) {
2335 CallLoweringInfo &setTailCall(bool Value = true) {
2340 CallLoweringInfo &setDiscardResult(bool Value = true) {
2341 IsReturnValueUsed = !Value;
2345 CallLoweringInfo &setSExtResult(bool Value = true) {
2350 CallLoweringInfo &setZExtResult(bool Value = true) {
2355 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2356 IsPatchPoint = Value;
2360 ArgListTy &getArgs() {
2365 /// This function lowers an abstract call to a function into an actual call.
2366 /// This returns a pair of operands. The first element is the return value
2367 /// for the function (if RetTy is not VoidTy). The second element is the
2368 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2369 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2371 /// This hook must be implemented to lower calls into the the specified
2372 /// DAG. The outgoing arguments to the call are described by the Outs array,
2373 /// and the values to be returned by the call are described by the Ins
2374 /// array. The implementation should fill in the InVals array with legal-type
2375 /// return values from the call, and return the resulting token chain value.
2377 LowerCall(CallLoweringInfo &/*CLI*/,
2378 SmallVectorImpl<SDValue> &/*InVals*/) const {
2379 llvm_unreachable("Not Implemented");
2382 /// Target-specific cleanup for formal ByVal parameters.
2383 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2385 /// This hook should be implemented to check whether the return values
2386 /// described by the Outs array can fit into the return registers. If false
2387 /// is returned, an sret-demotion is performed.
2388 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2389 MachineFunction &/*MF*/, bool /*isVarArg*/,
2390 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2391 LLVMContext &/*Context*/) const
2393 // Return true by default to get preexisting behavior.
2397 /// This hook must be implemented to lower outgoing return values, described
2398 /// by the Outs array, into the specified DAG. The implementation should
2399 /// return the resulting token chain value.
2401 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2403 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2404 const SmallVectorImpl<SDValue> &/*OutVals*/,
2405 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2406 llvm_unreachable("Not Implemented");
2409 /// Return true if result of the specified node is used by a return node
2410 /// only. It also compute and return the input chain for the tail call.
2412 /// This is used to determine whether it is possible to codegen a libcall as
2413 /// tail call at legalization time.
2414 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2418 /// Return true if the target may be able emit the call instruction as a tail
2419 /// call. This is used by optimization passes to determine if it's profitable
2420 /// to duplicate return instructions to enable tailcall optimization.
2421 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2425 /// Return the builtin name for the __builtin___clear_cache intrinsic
2426 /// Default is to invoke the clear cache library call
2427 virtual const char * getClearCacheBuiltinName() const {
2428 return "__clear_cache";
2431 /// Return the register ID of the name passed in. Used by named register
2432 /// global variables extension. There is no target-independent behaviour
2433 /// so the default action is to bail.
2434 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2435 report_fatal_error("Named registers not implemented for this target");
2438 /// Return the type that should be used to zero or sign extend a
2439 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2440 /// convention requires the return type to be promoted, but this is not true
2441 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2442 /// calling conventions. The frontend should handle this and include all of
2443 /// the necessary information.
2444 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2445 ISD::NodeType /*ExtendKind*/) const {
2446 EVT MinVT = getRegisterType(Context, MVT::i32);
2447 return VT.bitsLT(MinVT) ? MinVT : VT;
2450 /// For some targets, an LLVM struct type must be broken down into multiple
2451 /// simple types, but the calling convention specifies that the entire struct
2452 /// must be passed in a block of consecutive registers.
2454 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2455 bool isVarArg) const {
2459 /// Returns a 0 terminated array of registers that can be safely used as
2460 /// scratch registers.
2461 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2465 /// This callback is used to prepare for a volatile or atomic load.
2466 /// It takes a chain node as input and returns the chain for the load itself.
2468 /// Having a callback like this is necessary for targets like SystemZ,
2469 /// which allows a CPU to reuse the result of a previous load indefinitely,
2470 /// even if a cache-coherent store is performed by another CPU. The default
2471 /// implementation does nothing.
2472 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2473 SelectionDAG &DAG) const {
2477 /// This callback is invoked by the type legalizer to legalize nodes with an
2478 /// illegal operand type but legal result types. It replaces the
2479 /// LowerOperation callback in the type Legalizer. The reason we can not do
2480 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2481 /// use this callback.
2483 /// TODO: Consider merging with ReplaceNodeResults.
2485 /// The target places new result values for the node in Results (their number
2486 /// and types must exactly match those of the original return values of
2487 /// the node), or leaves Results empty, which indicates that the node is not
2488 /// to be custom lowered after all.
2489 /// The default implementation calls LowerOperation.
2490 virtual void LowerOperationWrapper(SDNode *N,
2491 SmallVectorImpl<SDValue> &Results,
2492 SelectionDAG &DAG) const;
2494 /// This callback is invoked for operations that are unsupported by the
2495 /// target, which are registered to use 'custom' lowering, and whose defined
2496 /// values are all legal. If the target has no operations that require custom
2497 /// lowering, it need not implement this. The default implementation of this
2499 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2501 /// This callback is invoked when a node result type is illegal for the
2502 /// target, and the operation was registered to use 'custom' lowering for that
2503 /// result type. The target places new result values for the node in Results
2504 /// (their number and types must exactly match those of the original return
2505 /// values of the node), or leaves Results empty, which indicates that the
2506 /// node is not to be custom lowered after all.
2508 /// If the target has no operations that require custom lowering, it need not
2509 /// implement this. The default implementation aborts.
2510 virtual void ReplaceNodeResults(SDNode * /*N*/,
2511 SmallVectorImpl<SDValue> &/*Results*/,
2512 SelectionDAG &/*DAG*/) const {
2513 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2516 /// This method returns the name of a target specific DAG node.
2517 virtual const char *getTargetNodeName(unsigned Opcode) const;
2519 /// This method returns a target specific FastISel object, or null if the
2520 /// target does not support "fast" ISel.
2521 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2522 const TargetLibraryInfo *) const {
2527 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2528 SelectionDAG &DAG) const;
2530 //===--------------------------------------------------------------------===//
2531 // Inline Asm Support hooks
2534 /// This hook allows the target to expand an inline asm call to be explicit
2535 /// llvm code if it wants to. This is useful for turning simple inline asms
2536 /// into LLVM intrinsics, which gives the compiler more information about the
2537 /// behavior of the code.
2538 virtual bool ExpandInlineAsm(CallInst *) const {
2542 enum ConstraintType {
2543 C_Register, // Constraint represents specific register(s).
2544 C_RegisterClass, // Constraint represents any of register(s) in class.
2545 C_Memory, // Memory constraint.
2546 C_Other, // Something else.
2547 C_Unknown // Unsupported constraint.
2550 enum ConstraintWeight {
2552 CW_Invalid = -1, // No match.
2553 CW_Okay = 0, // Acceptable.
2554 CW_Good = 1, // Good weight.
2555 CW_Better = 2, // Better weight.
2556 CW_Best = 3, // Best weight.
2558 // Well-known weights.
2559 CW_SpecificReg = CW_Okay, // Specific register operands.
2560 CW_Register = CW_Good, // Register operands.
2561 CW_Memory = CW_Better, // Memory operands.
2562 CW_Constant = CW_Best, // Constant operand.
2563 CW_Default = CW_Okay // Default or don't know type.
2566 /// This contains information for each constraint that we are lowering.
2567 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2568 /// This contains the actual string for the code, like "m". TargetLowering
2569 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2570 /// matches the operand.
2571 std::string ConstraintCode;
2573 /// Information about the constraint code, e.g. Register, RegisterClass,
2574 /// Memory, Other, Unknown.
2575 TargetLowering::ConstraintType ConstraintType;
2577 /// If this is the result output operand or a clobber, this is null,
2578 /// otherwise it is the incoming operand to the CallInst. This gets
2579 /// modified as the asm is processed.
2580 Value *CallOperandVal;
2582 /// The ValueType for the operand value.
2585 /// Return true of this is an input operand that is a matching constraint
2587 bool isMatchingInputConstraint() const;
2589 /// If this is an input matching constraint, this method returns the output
2590 /// operand it matches.
2591 unsigned getMatchedOperand() const;
2593 /// Copy constructor for copying from a ConstraintInfo.
2594 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2595 : InlineAsm::ConstraintInfo(std::move(Info)),
2596 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2597 ConstraintVT(MVT::Other) {}
2600 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2602 /// Split up the constraint string from the inline assembly value into the
2603 /// specific constraints and their prefixes, and also tie in the associated
2604 /// operand values. If this returns an empty vector, and if the constraint
2605 /// string itself isn't empty, there was an error parsing.
2606 virtual AsmOperandInfoVector ParseConstraints(const TargetRegisterInfo *TRI,
2607 ImmutableCallSite CS) const;
2609 /// Examine constraint type and operand type and determine a weight value.
2610 /// The operand object must already have been set up with the operand type.
2611 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2612 AsmOperandInfo &info, int maIndex) const;
2614 /// Examine constraint string and operand type and determine a weight value.
2615 /// The operand object must already have been set up with the operand type.
2616 virtual ConstraintWeight getSingleConstraintMatchWeight(
2617 AsmOperandInfo &info, const char *constraint) const;
2619 /// Determines the constraint code and constraint type to use for the specific
2620 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2621 /// If the actual operand being passed in is available, it can be passed in as
2622 /// Op, otherwise an empty SDValue can be passed.
2623 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2625 SelectionDAG *DAG = nullptr) const;
2627 /// Given a constraint, return the type of constraint it is for this target.
2628 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2630 /// Given a physical register constraint (e.g. {edx}), return the register
2631 /// number and the register class for the register.
2633 /// Given a register class constraint, like 'r', if this corresponds directly
2634 /// to an LLVM register class, return a register of 0 and the register class
2637 /// This should only be used for C_Register constraints. On error, this
2638 /// returns a register number of 0 and a null register class pointer.
2639 virtual std::pair<unsigned, const TargetRegisterClass *>
2640 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2641 const std::string &Constraint, MVT VT) const;
2644 getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
2645 if (ConstraintCode == "i")
2646 return InlineAsm::Constraint_i;
2647 else if (ConstraintCode == "m")
2648 return InlineAsm::Constraint_m;
2649 return InlineAsm::Constraint_Unknown;
2652 /// Try to replace an X constraint, which matches anything, with another that
2653 /// has more specific requirements based on the type of the corresponding
2654 /// operand. This returns null if there is no replacement to make.
2655 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2657 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2658 /// add anything to Ops.
2659 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2660 std::vector<SDValue> &Ops,
2661 SelectionDAG &DAG) const;
2663 //===--------------------------------------------------------------------===//
2664 // Div utility functions
2666 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2667 SelectionDAG &DAG) const;
2668 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2669 bool IsAfterLegalization,
2670 std::vector<SDNode *> *Created) const;
2671 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2672 bool IsAfterLegalization,
2673 std::vector<SDNode *> *Created) const;
2674 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2676 std::vector<SDNode *> *Created) const {
2680 /// Indicate whether this target prefers to combine the given number of FDIVs
2681 /// with the same divisor.
2682 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2686 /// Hooks for building estimates in place of slower divisions and square
2689 /// Return a reciprocal square root estimate value for the input operand.
2690 /// The RefinementSteps output is the number of Newton-Raphson refinement
2691 /// iterations required to generate a sufficient (though not necessarily
2692 /// IEEE-754 compliant) estimate for the value type.
2693 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2694 /// algorithm implementation that uses one constant or two constants.
2695 /// A target may choose to implement its own refinement within this function.
2696 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2697 /// any further refinement of the estimate.
2698 /// An empty SDValue return means no estimate sequence can be created.
2699 virtual SDValue getRsqrtEstimate(SDValue Operand,
2700 DAGCombinerInfo &DCI,
2701 unsigned &RefinementSteps,
2702 bool &UseOneConstNR) const {
2706 /// Return a reciprocal estimate value for the input operand.
2707 /// The RefinementSteps output is the number of Newton-Raphson refinement
2708 /// iterations required to generate a sufficient (though not necessarily
2709 /// IEEE-754 compliant) estimate for the value type.
2710 /// A target may choose to implement its own refinement within this function.
2711 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2712 /// any further refinement of the estimate.
2713 /// An empty SDValue return means no estimate sequence can be created.
2714 virtual SDValue getRecipEstimate(SDValue Operand,
2715 DAGCombinerInfo &DCI,
2716 unsigned &RefinementSteps) const {
2720 //===--------------------------------------------------------------------===//
2721 // Legalization utility functions
2724 /// Expand a MUL into two nodes. One that computes the high bits of
2725 /// the result and one that computes the low bits.
2726 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2727 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2728 /// if you want to control how low bits are extracted from the LHS.
2729 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2730 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2731 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2732 /// \returns true if the node has been expanded. false if it has not
2733 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2734 SelectionDAG &DAG, SDValue LL = SDValue(),
2735 SDValue LH = SDValue(), SDValue RL = SDValue(),
2736 SDValue RH = SDValue()) const;
2738 /// Expand float(f32) to SINT(i64) conversion
2739 /// \param N Node to expand
2740 /// \param Result output after conversion
2741 /// \returns True, if the expansion was successful, false otherwise
2742 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2744 //===--------------------------------------------------------------------===//
2745 // Instruction Emitting Hooks
2748 /// This method should be implemented by targets that mark instructions with
2749 /// the 'usesCustomInserter' flag. These instructions are special in various
2750 /// ways, which require special support to insert. The specified MachineInstr
2751 /// is created but not inserted into any basic blocks, and this method is
2752 /// called to expand it into a sequence of instructions, potentially also
2753 /// creating new basic blocks and control flow.
2754 /// As long as the returned basic block is different (i.e., we created a new
2755 /// one), the custom inserter is free to modify the rest of \p MBB.
2756 virtual MachineBasicBlock *
2757 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2759 /// This method should be implemented by targets that mark instructions with
2760 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2761 /// instruction selection by target hooks. e.g. To fill in optional defs for
2762 /// ARM 's' setting instructions.
2764 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2766 /// If this function returns true, SelectionDAGBuilder emits a
2767 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2768 virtual bool useLoadStackGuardNode() const {
2773 /// Given an LLVM IR type and return type attributes, compute the return value
2774 /// EVTs and flags, and optionally also the offsets, if the return value is
2775 /// being lowered to memory.
2776 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2777 SmallVectorImpl<ISD::OutputArg> &Outs,
2778 const TargetLowering &TLI);
2780 } // end llvm namespace