1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/Target/TargetCallingConv.h"
35 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
47 class MachineBasicBlock;
48 class MachineFunction;
50 class MachineJumpTableInfo;
55 template<typename T> class SmallVectorImpl;
57 class TargetRegisterClass;
58 class TargetLibraryInfo;
59 class TargetLoweringObjectFile;
64 None, // No preference
65 Source, // Follow source order.
66 RegPressure, // Scheduling for lowest register pressure.
67 Hybrid, // Scheduling for both latency and register pressure.
68 ILP, // Scheduling for ILP in low register pressure mode.
69 VLIW // Scheduling for VLIW targets.
73 /// This base class for TargetLowering contains the SelectionDAG-independent
74 /// parts that can be used from the rest of CodeGen.
75 class TargetLoweringBase {
76 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
77 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
80 /// This enum indicates whether operations are valid for a target, and if not,
81 /// what action should be used to make them valid.
83 Legal, // The target natively supports this operation.
84 Promote, // This operation should be executed in a larger type.
85 Expand, // Try to expand this to other ops, otherwise use a libcall.
86 Custom // Use the LowerOperation hook to implement custom lowering.
89 /// This enum indicates whether a types are legal for a target, and if not,
90 /// what action should be used to make them valid.
91 enum LegalizeTypeAction {
92 TypeLegal, // The target natively supports this type.
93 TypePromoteInteger, // Replace this integer with a larger one.
94 TypeExpandInteger, // Split this integer into two of half the size.
95 TypeSoftenFloat, // Convert this float to a same size integer type.
96 TypeExpandFloat, // Split this float into two of half the size.
97 TypeScalarizeVector, // Replace this one-element vector with its element.
98 TypeSplitVector, // Split this vector into two of half the size.
99 TypeWidenVector // This vector should be widened into a larger vector.
102 /// LegalizeKind holds the legalization kind that needs to happen to EVT
103 /// in order to type-legalize it.
104 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
106 /// Enum that describes how the target represents true/false values.
107 enum BooleanContent {
108 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
109 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
110 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
113 /// Enum that describes what type of support for selects the target has.
114 enum SelectSupportKind {
115 ScalarValSelect, // The target supports scalar selects (ex: cmov).
116 ScalarCondVectorVal, // The target supports selects with a scalar condition
117 // and vector values (ex: cmov).
118 VectorMaskSelect // The target supports vector selects with a vector
119 // mask (ex: x86 blends).
122 static ISD::NodeType getExtendForContent(BooleanContent Content) {
124 case UndefinedBooleanContent:
125 // Extend by adding rubbish bits.
126 return ISD::ANY_EXTEND;
127 case ZeroOrOneBooleanContent:
128 // Extend by adding zero bits.
129 return ISD::ZERO_EXTEND;
130 case ZeroOrNegativeOneBooleanContent:
131 // Extend by copying the sign bit.
132 return ISD::SIGN_EXTEND;
134 llvm_unreachable("Invalid content kind");
137 /// NOTE: The constructor takes ownership of TLOF.
138 explicit TargetLoweringBase(const TargetMachine &TM,
139 const TargetLoweringObjectFile *TLOF);
140 virtual ~TargetLoweringBase();
143 /// \brief Initialize all of the actions to default values.
147 const TargetMachine &getTargetMachine() const { return TM; }
148 const DataLayout *getDataLayout() const { return DL; }
149 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
151 bool isBigEndian() const { return !IsLittleEndian; }
152 bool isLittleEndian() const { return IsLittleEndian; }
154 /// Return the pointer type for the given address space, defaults to
155 /// the pointer type from the data layout.
156 /// FIXME: The default needs to be removed once all the code is updated.
157 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
158 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
159 unsigned getPointerTypeSizeInBits(Type *Ty) const;
160 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
162 EVT getShiftAmountTy(EVT LHSTy) const;
164 /// Returns the type to be used for the index operand of:
165 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
166 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
167 virtual MVT getVectorIdxTy() const {
168 return getPointerTy();
171 /// Return true if the select operation is expensive for this target.
172 bool isSelectExpensive() const { return SelectIsExpensive; }
174 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
178 /// Return true if multiple condition registers are available.
179 bool hasMultipleConditionRegisters() const {
180 return HasMultipleConditionRegisters;
183 /// Return true if a vector of the given type should be split
184 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
186 virtual bool shouldSplitVectorType(EVT /*VT*/) const { return false; }
188 // There are two general methods for expanding a BUILD_VECTOR node:
189 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
191 // 2. Build the vector on the stack and then load it.
192 // If this function returns true, then method (1) will be used, subject to
193 // the constraint that all of the necessary shuffles are legal (as determined
194 // by isShuffleMaskLegal). If this function returns false, then method (2) is
195 // always used. The vector type, and the number of defined values, are
198 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
199 unsigned DefinedValues) const {
200 return DefinedValues < 3;
203 /// Return true if integer divide is usually cheaper than a sequence of
204 /// several shifts, adds, and multiplies for this target.
205 bool isIntDivCheap() const { return IntDivIsCheap; }
207 /// Returns true if target has indicated at least one type should be bypassed.
208 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
210 /// Returns map of slow types for division or remainder with corresponding
212 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
213 return BypassSlowDivWidths;
216 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
217 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
219 /// Return true if Flow Control is an expensive operation that should be
221 bool isJumpExpensive() const { return JumpIsExpensive; }
223 /// Return true if selects are only cheaper than branches if the branch is
224 /// unlikely to be predicted right.
225 bool isPredictableSelectExpensive() const {
226 return PredictableSelectIsExpensive;
229 /// isLoadBitCastBeneficial() - Return true if the following transform
231 /// fold (conv (load x)) -> (load (conv*)x)
232 /// On architectures that don't natively support some vector loads efficiently,
233 /// casting the load to a smaller vector of larger types and loading
234 /// is more efficient, however, this can be undone by optimizations in
236 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
240 /// \brief Return if the target supports combining a
243 /// %andResult = and %val1, #imm-with-one-bit-set;
244 /// %icmpResult = icmp %andResult, 0
245 /// br i1 %icmpResult, label %dest1, label %dest2
247 /// into a single machine instruction of a form like:
249 /// brOnBitSet %register, #bitNumber, dest
251 bool isMaskAndBranchFoldingLegal() const {
252 return MaskAndBranchFoldingIsLegal;
255 /// Return the ValueType of the result of SETCC operations. Also used to
256 /// obtain the target's preferred type for the condition operand of SELECT and
257 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
258 /// since there are no other operands to get a type hint from.
259 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
261 /// Return the ValueType for comparison libcalls. Comparions libcalls include
262 /// floating point comparion calls, and Ordered/Unordered check calls on
263 /// floating point numbers.
265 MVT::SimpleValueType getCmpLibcallReturnType() const;
267 /// For targets without i1 registers, this gives the nature of the high-bits
268 /// of boolean values held in types wider than i1.
270 /// "Boolean values" are special true/false values produced by nodes like
271 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
272 /// Not to be confused with general values promoted from i1. Some cpus
273 /// distinguish between vectors of boolean and scalars; the isVec parameter
274 /// selects between the two kinds. For example on X86 a scalar boolean should
275 /// be zero extended from i1, while the elements of a vector of booleans
276 /// should be sign extended from i1.
277 BooleanContent getBooleanContents(bool isVec) const {
278 return isVec ? BooleanVectorContents : BooleanContents;
281 /// Return target scheduling preference.
282 Sched::Preference getSchedulingPreference() const {
283 return SchedPreferenceInfo;
286 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
287 /// for different nodes. This function returns the preference (or none) for
289 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
293 /// Return the register class that should be used for the specified value
295 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
296 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
297 assert(RC && "This value type is not natively supported!");
301 /// Return the 'representative' register class for the specified value
304 /// The 'representative' register class is the largest legal super-reg
305 /// register class for the register class of the value type. For example, on
306 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
307 /// register class is GR64 on x86_64.
308 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
309 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
313 /// Return the cost of the 'representative' register class for the specified
315 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
316 return RepRegClassCostForVT[VT.SimpleTy];
319 /// Return true if the target has native support for the specified value type.
320 /// This means that it has a register that directly holds it without
321 /// promotions or expansions.
322 bool isTypeLegal(EVT VT) const {
323 assert(!VT.isSimple() ||
324 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
325 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
328 class ValueTypeActionImpl {
329 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
330 /// that indicates how instruction selection should deal with the type.
331 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
334 ValueTypeActionImpl() {
335 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
338 LegalizeTypeAction getTypeAction(MVT VT) const {
339 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
342 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
343 unsigned I = VT.SimpleTy;
344 ValueTypeActions[I] = Action;
348 const ValueTypeActionImpl &getValueTypeActions() const {
349 return ValueTypeActions;
352 /// Return how we should legalize values of this type, either it is already
353 /// legal (return 'Legal') or we need to promote it to a larger type (return
354 /// 'Promote'), or we need to expand it into multiple registers of smaller
355 /// integer type (return 'Expand'). 'Custom' is not an option.
356 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
357 return getTypeConversion(Context, VT).first;
359 LegalizeTypeAction getTypeAction(MVT VT) const {
360 return ValueTypeActions.getTypeAction(VT);
363 /// For types supported by the target, this is an identity function. For
364 /// types that must be promoted to larger types, this returns the larger type
365 /// to promote to. For integer types that are larger than the largest integer
366 /// register, this contains one step in the expansion to get to the smaller
367 /// register. For illegal floating point types, this returns the integer type
369 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
370 return getTypeConversion(Context, VT).second;
373 /// For types supported by the target, this is an identity function. For
374 /// types that must be expanded (i.e. integer types that are larger than the
375 /// largest integer register or illegal floating point types), this returns
376 /// the largest legal type it will be expanded to.
377 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
378 assert(!VT.isVector());
380 switch (getTypeAction(Context, VT)) {
383 case TypeExpandInteger:
384 VT = getTypeToTransformTo(Context, VT);
387 llvm_unreachable("Type is not legal nor is it to be expanded!");
392 /// Vector types are broken down into some number of legal first class types.
393 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
394 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
395 /// turns into 4 EVT::i32 values with both PPC and X86.
397 /// This method returns the number of registers needed, and the VT for each
398 /// register. It also returns the VT and quantity of the intermediate values
399 /// before they are promoted/expanded.
400 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
402 unsigned &NumIntermediates,
403 MVT &RegisterVT) const;
405 struct IntrinsicInfo {
406 unsigned opc; // target opcode
407 EVT memVT; // memory VT
408 const Value* ptrVal; // value representing memory location
409 int offset; // offset off of ptrVal
410 unsigned align; // alignment
411 bool vol; // is volatile?
412 bool readMem; // reads memory?
413 bool writeMem; // writes memory?
416 /// Given an intrinsic, checks if on the target the intrinsic will need to map
417 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
418 /// true and store the intrinsic information into the IntrinsicInfo that was
419 /// passed to the function.
420 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
421 unsigned /*Intrinsic*/) const {
425 /// Returns true if the target can instruction select the specified FP
426 /// immediate natively. If false, the legalizer will materialize the FP
427 /// immediate as a load from a constant pool.
428 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
432 /// Targets can use this to indicate that they only support *some*
433 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
434 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
436 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
441 /// Returns true if the operation can trap for the value type.
443 /// VT must be a legal type. By default, we optimistically assume most
444 /// operations don't trap except for divide and remainder.
445 virtual bool canOpTrap(unsigned Op, EVT VT) const;
447 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
448 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
449 /// a VAND with a constant pool entry.
450 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
455 /// Return how this operation should be treated: either it is legal, needs to
456 /// be promoted to a larger size, needs to be expanded to some other code
457 /// sequence, or the target has a custom expander for it.
458 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
459 if (VT.isExtended()) return Expand;
460 // If a target-specific SDNode requires legalization, require the target
461 // to provide custom legalization for it.
462 if (Op > array_lengthof(OpActions[0])) return Custom;
463 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
464 return (LegalizeAction)OpActions[I][Op];
467 /// Return true if the specified operation is legal on this target or can be
468 /// made legal with custom lowering. This is used to help guide high-level
469 /// lowering decisions.
470 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
471 return (VT == MVT::Other || isTypeLegal(VT)) &&
472 (getOperationAction(Op, VT) == Legal ||
473 getOperationAction(Op, VT) == Custom);
476 /// Return true if the specified operation is legal on this target or can be
477 /// made legal using promotion. This is used to help guide high-level lowering
479 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
480 return (VT == MVT::Other || isTypeLegal(VT)) &&
481 (getOperationAction(Op, VT) == Legal ||
482 getOperationAction(Op, VT) == Promote);
485 /// Return true if the specified operation is illegal on this target or
486 /// unlikely to be made legal with custom lowering. This is used to help guide
487 /// high-level lowering decisions.
488 bool isOperationExpand(unsigned Op, EVT VT) const {
489 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
492 /// Return true if the specified operation is legal on this target.
493 bool isOperationLegal(unsigned Op, EVT VT) const {
494 return (VT == MVT::Other || isTypeLegal(VT)) &&
495 getOperationAction(Op, VT) == Legal;
498 /// Return how this load with extension should be treated: either it is legal,
499 /// needs to be promoted to a larger size, needs to be expanded to some other
500 /// code sequence, or the target has a custom expander for it.
501 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
502 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
503 "Table isn't big enough!");
504 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
507 /// Return true if the specified load with extension is legal on this target.
508 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
509 return VT.isSimple() &&
510 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
513 /// Return how this store with truncation should be treated: either it is
514 /// legal, needs to be promoted to a larger size, needs to be expanded to some
515 /// other code sequence, or the target has a custom expander for it.
516 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
517 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
518 "Table isn't big enough!");
519 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
523 /// Return true if the specified store with truncation is legal on this
525 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
526 return isTypeLegal(ValVT) && MemVT.isSimple() &&
527 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
530 /// Return how the indexed load should be treated: either it is legal, needs
531 /// to be promoted to a larger size, needs to be expanded to some other code
532 /// sequence, or the target has a custom expander for it.
534 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
535 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
536 "Table isn't big enough!");
537 unsigned Ty = (unsigned)VT.SimpleTy;
538 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
541 /// Return true if the specified indexed load is legal on this target.
542 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
543 return VT.isSimple() &&
544 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
545 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
548 /// Return how the indexed store should be treated: either it is legal, needs
549 /// to be promoted to a larger size, needs to be expanded to some other code
550 /// sequence, or the target has a custom expander for it.
552 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
553 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
554 "Table isn't big enough!");
555 unsigned Ty = (unsigned)VT.SimpleTy;
556 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
559 /// Return true if the specified indexed load is legal on this target.
560 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
561 return VT.isSimple() &&
562 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
563 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
566 /// Return how the condition code should be treated: either it is legal, needs
567 /// to be expanded to some other code sequence, or the target has a custom
570 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
571 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
572 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
573 "Table isn't big enough!");
574 // See setCondCodeAction for how this is encoded.
575 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
576 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
577 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
578 assert(Action != Promote && "Can't promote condition code!");
582 /// Return true if the specified condition code is legal on this target.
583 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
585 getCondCodeAction(CC, VT) == Legal ||
586 getCondCodeAction(CC, VT) == Custom;
590 /// If the action for this operation is to promote, this method returns the
591 /// ValueType to promote to.
592 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
593 assert(getOperationAction(Op, VT) == Promote &&
594 "This operation isn't promoted!");
596 // See if this has an explicit type specified.
597 std::map<std::pair<unsigned, MVT::SimpleValueType>,
598 MVT::SimpleValueType>::const_iterator PTTI =
599 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
600 if (PTTI != PromoteToType.end()) return PTTI->second;
602 assert((VT.isInteger() || VT.isFloatingPoint()) &&
603 "Cannot autopromote this type, add it with AddPromotedToType.");
607 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
608 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
609 "Didn't find type to promote to!");
610 } while (!isTypeLegal(NVT) ||
611 getOperationAction(Op, NVT) == Promote);
615 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
616 /// operations except for the pointer size. If AllowUnknown is true, this
617 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
618 /// otherwise it will assert.
619 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
620 // Lower scalar pointers to native pointer types.
621 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
622 return getPointerTy(PTy->getAddressSpace());
624 if (Ty->isVectorTy()) {
625 VectorType *VTy = cast<VectorType>(Ty);
626 Type *Elm = VTy->getElementType();
627 // Lower vectors of pointers to native pointer types.
628 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
629 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
630 Elm = PointerTy.getTypeForEVT(Ty->getContext());
633 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
634 VTy->getNumElements());
636 return EVT::getEVT(Ty, AllowUnknown);
639 /// Return the MVT corresponding to this LLVM type. See getValueType.
640 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
641 return getValueType(Ty, AllowUnknown).getSimpleVT();
644 /// Return the desired alignment for ByVal or InAlloca aggregate function
645 /// arguments in the caller parameter area. This is the actual alignment, not
647 virtual unsigned getByValTypeAlignment(Type *Ty) const;
649 /// Return the type of registers that this ValueType will eventually require.
650 MVT getRegisterType(MVT VT) const {
651 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
652 return RegisterTypeForVT[VT.SimpleTy];
655 /// Return the type of registers that this ValueType will eventually require.
656 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
658 assert((unsigned)VT.getSimpleVT().SimpleTy <
659 array_lengthof(RegisterTypeForVT));
660 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
665 unsigned NumIntermediates;
666 (void)getVectorTypeBreakdown(Context, VT, VT1,
667 NumIntermediates, RegisterVT);
670 if (VT.isInteger()) {
671 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
673 llvm_unreachable("Unsupported extended type!");
676 /// Return the number of registers that this ValueType will eventually
679 /// This is one for any types promoted to live in larger registers, but may be
680 /// more than one for types (like i64) that are split into pieces. For types
681 /// like i140, which are first promoted then expanded, it is the number of
682 /// registers needed to hold all the bits of the original type. For an i140
683 /// on a 32 bit machine this means 5 registers.
684 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
686 assert((unsigned)VT.getSimpleVT().SimpleTy <
687 array_lengthof(NumRegistersForVT));
688 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
693 unsigned NumIntermediates;
694 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
696 if (VT.isInteger()) {
697 unsigned BitWidth = VT.getSizeInBits();
698 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
699 return (BitWidth + RegWidth - 1) / RegWidth;
701 llvm_unreachable("Unsupported extended type!");
704 /// If true, then instruction selection should seek to shrink the FP constant
705 /// of the specified type to a smaller type in order to save space and / or
707 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
709 /// If true, the target has custom DAG combine transformations that it can
710 /// perform for the specified node.
711 bool hasTargetDAGCombine(ISD::NodeType NT) const {
712 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
713 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
716 /// \brief Get maximum # of store operations permitted for llvm.memset
718 /// This function returns the maximum number of store operations permitted
719 /// to replace a call to llvm.memset. The value is set by the target at the
720 /// performance threshold for such a replacement. If OptSize is true,
721 /// return the limit for functions that have OptSize attribute.
722 unsigned getMaxStoresPerMemset(bool OptSize) const {
723 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
726 /// \brief Get maximum # of store operations permitted for llvm.memcpy
728 /// This function returns the maximum number of store operations permitted
729 /// to replace a call to llvm.memcpy. The value is set by the target at the
730 /// performance threshold for such a replacement. If OptSize is true,
731 /// return the limit for functions that have OptSize attribute.
732 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
733 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
736 /// \brief Get maximum # of store operations permitted for llvm.memmove
738 /// This function returns the maximum number of store operations permitted
739 /// to replace a call to llvm.memmove. The value is set by the target at the
740 /// performance threshold for such a replacement. If OptSize is true,
741 /// return the limit for functions that have OptSize attribute.
742 unsigned getMaxStoresPerMemmove(bool OptSize) const {
743 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
746 /// \brief Determine if the target supports unaligned memory accesses.
748 /// This function returns true if the target allows unaligned memory accesses
749 /// of the specified type in the given address space. If true, it also returns
750 /// whether the unaligned memory access is "fast" in the third argument by
751 /// reference. This is used, for example, in situations where an array
752 /// copy/move/set is converted to a sequence of store operations. Its use
753 /// helps to ensure that such replacements don't generate code that causes an
754 /// alignment error (trap) on the target machine.
755 virtual bool allowsUnalignedMemoryAccesses(EVT,
756 unsigned AddrSpace = 0,
757 bool * /*Fast*/ = 0) const {
761 /// Returns the target specific optimal type for load and store operations as
762 /// a result of memset, memcpy, and memmove lowering.
764 /// If DstAlign is zero that means it's safe to destination alignment can
765 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
766 /// a need to check it against alignment requirement, probably because the
767 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
768 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
769 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
770 /// does not need to be loaded. It returns EVT::Other if the type should be
771 /// determined using generic target-independent logic.
772 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
773 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
776 bool /*MemcpyStrSrc*/,
777 MachineFunction &/*MF*/) const {
781 /// Returns true if it's safe to use load / store of the specified type to
782 /// expand memcpy / memset inline.
784 /// This is mostly true for all types except for some special cases. For
785 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
786 /// fstpl which also does type conversion. Note the specified type doesn't
787 /// have to be legal as the hook is used before type legalization.
788 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
790 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
791 bool usesUnderscoreSetJmp() const {
792 return UseUnderscoreSetJmp;
795 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
796 bool usesUnderscoreLongJmp() const {
797 return UseUnderscoreLongJmp;
800 /// Return whether the target can generate code for jump tables.
801 bool supportJumpTables() const {
802 return SupportJumpTables;
805 /// Return integer threshold on number of blocks to use jump tables rather
806 /// than if sequence.
807 int getMinimumJumpTableEntries() const {
808 return MinimumJumpTableEntries;
811 /// If a physical register, this specifies the register that
812 /// llvm.savestack/llvm.restorestack should save and restore.
813 unsigned getStackPointerRegisterToSaveRestore() const {
814 return StackPointerRegisterToSaveRestore;
817 /// If a physical register, this returns the register that receives the
818 /// exception address on entry to a landing pad.
819 unsigned getExceptionPointerRegister() const {
820 return ExceptionPointerRegister;
823 /// If a physical register, this returns the register that receives the
824 /// exception typeid on entry to a landing pad.
825 unsigned getExceptionSelectorRegister() const {
826 return ExceptionSelectorRegister;
829 /// Returns the target's jmp_buf size in bytes (if never set, the default is
831 unsigned getJumpBufSize() const {
835 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
837 unsigned getJumpBufAlignment() const {
838 return JumpBufAlignment;
841 /// Return the minimum stack alignment of an argument.
842 unsigned getMinStackArgumentAlignment() const {
843 return MinStackArgumentAlignment;
846 /// Return the minimum function alignment.
847 unsigned getMinFunctionAlignment() const {
848 return MinFunctionAlignment;
851 /// Return the preferred function alignment.
852 unsigned getPrefFunctionAlignment() const {
853 return PrefFunctionAlignment;
856 /// Return the preferred loop alignment.
857 unsigned getPrefLoopAlignment() const {
858 return PrefLoopAlignment;
861 /// Return whether the DAG builder should automatically insert fences and
862 /// reduce ordering for atomics.
863 bool getInsertFencesForAtomic() const {
864 return InsertFencesForAtomic;
867 /// Return true if the target stores stack protector cookies at a fixed offset
868 /// in some non-standard address space, and populates the address space and
869 /// offset as appropriate.
870 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
871 unsigned &/*Offset*/) const {
875 /// Returns the maximal possible offset which can be used for loads / stores
877 virtual unsigned getMaximalGlobalOffset() const {
881 /// Returns true if a cast between SrcAS and DestAS is a noop.
882 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
886 //===--------------------------------------------------------------------===//
887 /// \name Helpers for TargetTransformInfo implementations
890 /// Get the ISD node that corresponds to the Instruction class opcode.
891 int InstructionOpcodeToISD(unsigned Opcode) const;
893 /// Estimate the cost of type-legalization and the legalized type.
894 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
898 //===--------------------------------------------------------------------===//
899 // TargetLowering Configuration Methods - These methods should be invoked by
900 // the derived class constructor to configure this object for the target.
903 /// \brief Reset the operation actions based on target options.
904 virtual void resetOperationActions() {}
907 /// Specify how the target extends the result of a boolean value from i1 to a
908 /// wider type. See getBooleanContents.
909 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
911 /// Specify how the target extends the result of a vector boolean value from a
912 /// vector of i1 to a wider type. See getBooleanContents.
913 void setBooleanVectorContents(BooleanContent Ty) {
914 BooleanVectorContents = Ty;
917 /// Specify the target scheduling preference.
918 void setSchedulingPreference(Sched::Preference Pref) {
919 SchedPreferenceInfo = Pref;
922 /// Indicate whether this target prefers to use _setjmp to implement
923 /// llvm.setjmp or the version without _. Defaults to false.
924 void setUseUnderscoreSetJmp(bool Val) {
925 UseUnderscoreSetJmp = Val;
928 /// Indicate whether this target prefers to use _longjmp to implement
929 /// llvm.longjmp or the version without _. Defaults to false.
930 void setUseUnderscoreLongJmp(bool Val) {
931 UseUnderscoreLongJmp = Val;
934 /// Indicate whether the target can generate code for jump tables.
935 void setSupportJumpTables(bool Val) {
936 SupportJumpTables = Val;
939 /// Indicate the number of blocks to generate jump tables rather than if
941 void setMinimumJumpTableEntries(int Val) {
942 MinimumJumpTableEntries = Val;
945 /// If set to a physical register, this specifies the register that
946 /// llvm.savestack/llvm.restorestack should save and restore.
947 void setStackPointerRegisterToSaveRestore(unsigned R) {
948 StackPointerRegisterToSaveRestore = R;
951 /// If set to a physical register, this sets the register that receives the
952 /// exception address on entry to a landing pad.
953 void setExceptionPointerRegister(unsigned R) {
954 ExceptionPointerRegister = R;
957 /// If set to a physical register, this sets the register that receives the
958 /// exception typeid on entry to a landing pad.
959 void setExceptionSelectorRegister(unsigned R) {
960 ExceptionSelectorRegister = R;
963 /// Tells the code generator not to expand operations into sequences that use
964 /// the select operations if possible.
965 void setSelectIsExpensive(bool isExpensive = true) {
966 SelectIsExpensive = isExpensive;
969 /// Tells the code generator that the target has multiple (allocatable)
970 /// condition registers that can be used to store the results of comparisons
971 /// for use by selects and conditional branches. With multiple condition
972 /// registers, the code generator will not aggressively sink comparisons into
973 /// the blocks of their users.
974 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
975 HasMultipleConditionRegisters = hasManyRegs;
978 /// Tells the code generator not to expand sequence of operations into a
979 /// separate sequences that increases the amount of flow control.
980 void setJumpIsExpensive(bool isExpensive = true) {
981 JumpIsExpensive = isExpensive;
984 /// Tells the code generator that integer divide is expensive, and if
985 /// possible, should be replaced by an alternate sequence of instructions not
986 /// containing an integer divide.
987 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
989 /// Tells the code generator which bitwidths to bypass.
990 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
991 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
994 /// Tells the code generator that it shouldn't generate srl/add/sra for a
995 /// signed divide by power of two, and let the target handle it.
996 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
998 /// Add the specified register class as an available regclass for the
999 /// specified value type. This indicates the selector can handle values of
1000 /// that class natively.
1001 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1002 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1003 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1004 RegClassForVT[VT.SimpleTy] = RC;
1007 /// Remove all register classes.
1008 void clearRegisterClasses() {
1009 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1011 AvailableRegClasses.clear();
1014 /// \brief Remove all operation actions.
1015 void clearOperationActions() {
1018 /// Return the largest legal super-reg register class of the register class
1019 /// for the specified type and its associated "cost".
1020 virtual std::pair<const TargetRegisterClass*, uint8_t>
1021 findRepresentativeClass(MVT VT) const;
1023 /// Once all of the register classes are added, this allows us to compute
1024 /// derived properties we expose.
1025 void computeRegisterProperties();
1027 /// Indicate that the specified operation does not work with the specified
1028 /// type and indicate what to do about it.
1029 void setOperationAction(unsigned Op, MVT VT,
1030 LegalizeAction Action) {
1031 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1032 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1035 /// Indicate that the specified load with extension does not work with the
1036 /// specified type and indicate what to do about it.
1037 void setLoadExtAction(unsigned ExtType, MVT VT,
1038 LegalizeAction Action) {
1039 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1040 "Table isn't big enough!");
1041 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1044 /// Indicate that the specified truncating store does not work with the
1045 /// specified type and indicate what to do about it.
1046 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1047 LegalizeAction Action) {
1048 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1049 "Table isn't big enough!");
1050 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1053 /// Indicate that the specified indexed load does or does not work with the
1054 /// specified type and indicate what to do abort it.
1056 /// NOTE: All indexed mode loads are initialized to Expand in
1057 /// TargetLowering.cpp
1058 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1059 LegalizeAction Action) {
1060 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1061 (unsigned)Action < 0xf && "Table isn't big enough!");
1062 // Load action are kept in the upper half.
1063 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1064 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1067 /// Indicate that the specified indexed store does or does not work with the
1068 /// specified type and indicate what to do about it.
1070 /// NOTE: All indexed mode stores are initialized to Expand in
1071 /// TargetLowering.cpp
1072 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1073 LegalizeAction Action) {
1074 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1075 (unsigned)Action < 0xf && "Table isn't big enough!");
1076 // Store action are kept in the lower half.
1077 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1078 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1081 /// Indicate that the specified condition code is or isn't supported on the
1082 /// target and indicate what to do about it.
1083 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1084 LegalizeAction Action) {
1085 assert(VT < MVT::LAST_VALUETYPE &&
1086 (unsigned)CC < array_lengthof(CondCodeActions) &&
1087 "Table isn't big enough!");
1088 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1089 /// value and the upper 27 bits index into the second dimension of the array
1090 /// to select what 32-bit value to use.
1091 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1092 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1093 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1096 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1097 /// to trying a larger integer/fp until it can find one that works. If that
1098 /// default is insufficient, this method can be used by the target to override
1100 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1101 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1104 /// Targets should invoke this method for each target independent node that
1105 /// they want to provide a custom DAG combiner for by implementing the
1106 /// PerformDAGCombine virtual method.
1107 void setTargetDAGCombine(ISD::NodeType NT) {
1108 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1109 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1112 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1113 void setJumpBufSize(unsigned Size) {
1117 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1119 void setJumpBufAlignment(unsigned Align) {
1120 JumpBufAlignment = Align;
1123 /// Set the target's minimum function alignment (in log2(bytes))
1124 void setMinFunctionAlignment(unsigned Align) {
1125 MinFunctionAlignment = Align;
1128 /// Set the target's preferred function alignment. This should be set if
1129 /// there is a performance benefit to higher-than-minimum alignment (in
1131 void setPrefFunctionAlignment(unsigned Align) {
1132 PrefFunctionAlignment = Align;
1135 /// Set the target's preferred loop alignment. Default alignment is zero, it
1136 /// means the target does not care about loop alignment. The alignment is
1137 /// specified in log2(bytes).
1138 void setPrefLoopAlignment(unsigned Align) {
1139 PrefLoopAlignment = Align;
1142 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1143 void setMinStackArgumentAlignment(unsigned Align) {
1144 MinStackArgumentAlignment = Align;
1147 /// Set if the DAG builder should automatically insert fences and reduce the
1148 /// order of atomic memory operations to Monotonic.
1149 void setInsertFencesForAtomic(bool fence) {
1150 InsertFencesForAtomic = fence;
1154 //===--------------------------------------------------------------------===//
1155 // Addressing mode description hooks (used by LSR etc).
1158 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1159 /// instructions reading the address. This allows as much computation as
1160 /// possible to be done in the address mode for that operand. This hook lets
1161 /// targets also pass back when this should be done on intrinsics which
1163 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1164 SmallVectorImpl<Value*> &/*Ops*/,
1165 Type *&/*AccessTy*/) const {
1169 /// This represents an addressing mode of:
1170 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1171 /// If BaseGV is null, there is no BaseGV.
1172 /// If BaseOffs is zero, there is no base offset.
1173 /// If HasBaseReg is false, there is no base register.
1174 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1177 GlobalValue *BaseGV;
1181 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1184 /// Return true if the addressing mode represented by AM is legal for this
1185 /// target, for a load/store of the specified type.
1187 /// The type may be VoidTy, in which case only return true if the addressing
1188 /// mode is legal for a load/store of any legal type. TODO: Handle
1189 /// pre/postinc as well.
1190 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1192 /// \brief Return the cost of the scaling factor used in the addressing mode
1193 /// represented by AM for this target, for a load/store of the specified type.
1195 /// If the AM is supported, the return value must be >= 0.
1196 /// If the AM is not supported, it returns a negative value.
1197 /// TODO: Handle pre/postinc as well.
1198 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1199 // Default: assume that any scaling factor used in a legal AM is free.
1200 if (isLegalAddressingMode(AM, Ty)) return 0;
1204 /// Return true if the specified immediate is legal icmp immediate, that is
1205 /// the target has icmp instructions which can compare a register against the
1206 /// immediate without having to materialize the immediate into a register.
1207 virtual bool isLegalICmpImmediate(int64_t) const {
1211 /// Return true if the specified immediate is legal add immediate, that is the
1212 /// target has add instructions which can add a register with the immediate
1213 /// without having to materialize the immediate into a register.
1214 virtual bool isLegalAddImmediate(int64_t) const {
1218 /// Return true if it's significantly cheaper to shift a vector by a uniform
1219 /// scalar than by an amount which will vary across each lane. On x86, for
1220 /// example, there is a "psllw" instruction for the former case, but no simple
1221 /// instruction for a general "a << b" operation on vectors.
1222 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1226 /// Return true if it's free to truncate a value of type Ty1 to type
1227 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1228 /// by referencing its sub-register AX.
1229 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1233 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1234 /// whether a call is in tail position. Typically this means that both results
1235 /// would be assigned to the same register or stack slot, but it could mean
1236 /// the target performs adequate checks of its own before proceeding with the
1238 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1242 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1246 /// Return true if any actual instruction that defines a value of type Ty1
1247 /// implicitly zero-extends the value to Ty2 in the result register.
1249 /// This does not necessarily include registers defined in unknown ways, such
1250 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1251 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1252 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1253 /// values implicit zero-extend the result out to 64 bits.
1254 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1258 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1262 /// Return true if the target supplies and combines to a paired load
1263 /// two loaded values of type LoadedType next to each other in memory.
1264 /// RequiredAlignment gives the minimal alignment constraints that must be met
1265 /// to be able to select this paired load.
1267 /// This information is *not* used to generate actual paired loads, but it is
1268 /// used to generate a sequence of loads that is easier to combine into a
1270 /// For instance, something like this:
1271 /// a = load i64* addr
1272 /// b = trunc i64 a to i32
1273 /// c = lshr i64 a, 32
1274 /// d = trunc i64 c to i32
1275 /// will be optimized into:
1276 /// b = load i32* addr1
1277 /// d = load i32* addr2
1278 /// Where addr1 = addr2 +/- sizeof(i32).
1280 /// In other words, unless the target performs a post-isel load combining,
1281 /// this information should not be provided because it will generate more
1283 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1284 unsigned & /*RequiredAligment*/) const {
1288 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1289 unsigned & /*RequiredAligment*/) const {
1293 /// Return true if zero-extending the specific node Val to type VT2 is free
1294 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1295 /// because it's folded such as X86 zero-extending loads).
1296 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1297 return isZExtFree(Val.getValueType(), VT2);
1300 /// Return true if an fneg operation is free to the point where it is never
1301 /// worthwhile to replace it with a bitwise operation.
1302 virtual bool isFNegFree(EVT VT) const {
1303 assert(VT.isFloatingPoint());
1307 /// Return true if an fabs operation is free to the point where it is never
1308 /// worthwhile to replace it with a bitwise operation.
1309 virtual bool isFAbsFree(EVT VT) const {
1310 assert(VT.isFloatingPoint());
1314 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1315 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1316 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1318 /// NOTE: This may be called before legalization on types for which FMAs are
1319 /// not legal, but should return true if those types will eventually legalize
1320 /// to types that support FMAs. After legalization, it will only be called on
1321 /// types that support FMAs (via Legal or Custom actions)
1322 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1326 /// Return true if it's profitable to narrow operations of type VT1 to
1327 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1329 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1333 /// \brief Return true if it is beneficial to convert a load of a constant to
1334 /// just the constant itself.
1335 /// On some targets it might be more efficient to use a combination of
1336 /// arithmetic instructions to materialize the constant instead of loading it
1337 /// from a constant pool.
1338 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1342 //===--------------------------------------------------------------------===//
1343 // Runtime Library hooks
1346 /// Rename the default libcall routine name for the specified libcall.
1347 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1348 LibcallRoutineNames[Call] = Name;
1351 /// Get the libcall routine name for the specified libcall.
1352 const char *getLibcallName(RTLIB::Libcall Call) const {
1353 return LibcallRoutineNames[Call];
1356 /// Override the default CondCode to be used to test the result of the
1357 /// comparison libcall against zero.
1358 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1359 CmpLibcallCCs[Call] = CC;
1362 /// Get the CondCode that's to be used to test the result of the comparison
1363 /// libcall against zero.
1364 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1365 return CmpLibcallCCs[Call];
1368 /// Set the CallingConv that should be used for the specified libcall.
1369 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1370 LibcallCallingConvs[Call] = CC;
1373 /// Get the CallingConv that should be used for the specified libcall.
1374 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1375 return LibcallCallingConvs[Call];
1379 const TargetMachine &TM;
1380 const DataLayout *DL;
1381 const TargetLoweringObjectFile &TLOF;
1383 /// True if this is a little endian target.
1384 bool IsLittleEndian;
1386 /// Tells the code generator not to expand operations into sequences that use
1387 /// the select operations if possible.
1388 bool SelectIsExpensive;
1390 /// Tells the code generator that the target has multiple (allocatable)
1391 /// condition registers that can be used to store the results of comparisons
1392 /// for use by selects and conditional branches. With multiple condition
1393 /// registers, the code generator will not aggressively sink comparisons into
1394 /// the blocks of their users.
1395 bool HasMultipleConditionRegisters;
1397 /// Tells the code generator not to expand integer divides by constants into a
1398 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1399 /// model is in place. If we ever optimize for size, this will be set to true
1400 /// unconditionally.
1403 /// Tells the code generator to bypass slow divide or remainder
1404 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1405 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1406 /// div/rem when the operands are positive and less than 256.
1407 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1409 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1410 /// signed divide by power of two, and let the target handle it.
1411 bool Pow2DivIsCheap;
1413 /// Tells the code generator that it shouldn't generate extra flow control
1414 /// instructions and should attempt to combine flow control instructions via
1416 bool JumpIsExpensive;
1418 /// This target prefers to use _setjmp to implement llvm.setjmp.
1420 /// Defaults to false.
1421 bool UseUnderscoreSetJmp;
1423 /// This target prefers to use _longjmp to implement llvm.longjmp.
1425 /// Defaults to false.
1426 bool UseUnderscoreLongJmp;
1428 /// Whether the target can generate code for jumptables. If it's not true,
1429 /// then each jumptable must be lowered into if-then-else's.
1430 bool SupportJumpTables;
1432 /// Number of blocks threshold to use jump tables.
1433 int MinimumJumpTableEntries;
1435 /// Information about the contents of the high-bits in boolean values held in
1436 /// a type wider than i1. See getBooleanContents.
1437 BooleanContent BooleanContents;
1439 /// Information about the contents of the high-bits in boolean vector values
1440 /// when the element type is wider than i1. See getBooleanContents.
1441 BooleanContent BooleanVectorContents;
1443 /// The target scheduling preference: shortest possible total cycles or lowest
1445 Sched::Preference SchedPreferenceInfo;
1447 /// The size, in bytes, of the target's jmp_buf buffers
1448 unsigned JumpBufSize;
1450 /// The alignment, in bytes, of the target's jmp_buf buffers
1451 unsigned JumpBufAlignment;
1453 /// The minimum alignment that any argument on the stack needs to have.
1454 unsigned MinStackArgumentAlignment;
1456 /// The minimum function alignment (used when optimizing for size, and to
1457 /// prevent explicitly provided alignment from leading to incorrect code).
1458 unsigned MinFunctionAlignment;
1460 /// The preferred function alignment (used when alignment unspecified and
1461 /// optimizing for speed).
1462 unsigned PrefFunctionAlignment;
1464 /// The preferred loop alignment.
1465 unsigned PrefLoopAlignment;
1467 /// Whether the DAG builder should automatically insert fences and reduce
1468 /// ordering for atomics. (This will be set for for most architectures with
1469 /// weak memory ordering.)
1470 bool InsertFencesForAtomic;
1472 /// If set to a physical register, this specifies the register that
1473 /// llvm.savestack/llvm.restorestack should save and restore.
1474 unsigned StackPointerRegisterToSaveRestore;
1476 /// If set to a physical register, this specifies the register that receives
1477 /// the exception address on entry to a landing pad.
1478 unsigned ExceptionPointerRegister;
1480 /// If set to a physical register, this specifies the register that receives
1481 /// the exception typeid on entry to a landing pad.
1482 unsigned ExceptionSelectorRegister;
1484 /// This indicates the default register class to use for each ValueType the
1485 /// target supports natively.
1486 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1487 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1488 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1490 /// This indicates the "representative" register class to use for each
1491 /// ValueType the target supports natively. This information is used by the
1492 /// scheduler to track register pressure. By default, the representative
1493 /// register class is the largest legal super-reg register class of the
1494 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1495 /// representative class would be GR32.
1496 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1498 /// This indicates the "cost" of the "representative" register class for each
1499 /// ValueType. The cost is used by the scheduler to approximate register
1501 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1503 /// For any value types we are promoting or expanding, this contains the value
1504 /// type that we are changing to. For Expanded types, this contains one step
1505 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1506 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1507 /// the same type (e.g. i32 -> i32).
1508 MVT TransformToType[MVT::LAST_VALUETYPE];
1510 /// For each operation and each value type, keep a LegalizeAction that
1511 /// indicates how instruction selection should deal with the operation. Most
1512 /// operations are Legal (aka, supported natively by the target), but
1513 /// operations that are not should be described. Note that operations on
1514 /// non-legal value types are not described here.
1515 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1517 /// For each load extension type and each value type, keep a LegalizeAction
1518 /// that indicates how instruction selection should deal with a load of a
1519 /// specific value type and extension type.
1520 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1522 /// For each value type pair keep a LegalizeAction that indicates whether a
1523 /// truncating store of a specific value type and truncating type is legal.
1524 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1526 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1527 /// that indicates how instruction selection should deal with the load /
1530 /// The first dimension is the value_type for the reference. The second
1531 /// dimension represents the various modes for load store.
1532 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1534 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1535 /// indicates how instruction selection should deal with the condition code.
1537 /// Because each CC action takes up 2 bits, we need to have the array size be
1538 /// large enough to fit all of the value types. This can be done by rounding
1539 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1540 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1542 ValueTypeActionImpl ValueTypeActions;
1546 getTypeConversion(LLVMContext &Context, EVT VT) const {
1547 // If this is a simple type, use the ComputeRegisterProp mechanism.
1548 if (VT.isSimple()) {
1549 MVT SVT = VT.getSimpleVT();
1550 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1551 MVT NVT = TransformToType[SVT.SimpleTy];
1552 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1556 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1557 && "Promote may not follow Expand or Promote");
1559 if (LA == TypeSplitVector)
1560 return LegalizeKind(LA, EVT::getVectorVT(Context,
1561 SVT.getVectorElementType(),
1562 SVT.getVectorNumElements()/2));
1563 if (LA == TypeScalarizeVector)
1564 return LegalizeKind(LA, SVT.getVectorElementType());
1565 return LegalizeKind(LA, NVT);
1568 // Handle Extended Scalar Types.
1569 if (!VT.isVector()) {
1570 assert(VT.isInteger() && "Float types must be simple");
1571 unsigned BitSize = VT.getSizeInBits();
1572 // First promote to a power-of-two size, then expand if necessary.
1573 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1574 EVT NVT = VT.getRoundIntegerType(Context);
1575 assert(NVT != VT && "Unable to round integer VT");
1576 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1577 // Avoid multi-step promotion.
1578 if (NextStep.first == TypePromoteInteger) return NextStep;
1579 // Return rounded integer type.
1580 return LegalizeKind(TypePromoteInteger, NVT);
1583 return LegalizeKind(TypeExpandInteger,
1584 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1587 // Handle vector types.
1588 unsigned NumElts = VT.getVectorNumElements();
1589 EVT EltVT = VT.getVectorElementType();
1591 // Vectors with only one element are always scalarized.
1593 return LegalizeKind(TypeScalarizeVector, EltVT);
1595 // Try to widen vector elements until the element type is a power of two and
1596 // promote it to a legal type later on, for example:
1597 // <3 x i8> -> <4 x i8> -> <4 x i32>
1598 if (EltVT.isInteger()) {
1599 // Vectors with a number of elements that is not a power of two are always
1600 // widened, for example <3 x i8> -> <4 x i8>.
1601 if (!VT.isPow2VectorType()) {
1602 NumElts = (unsigned)NextPowerOf2(NumElts);
1603 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1604 return LegalizeKind(TypeWidenVector, NVT);
1607 // Examine the element type.
1608 LegalizeKind LK = getTypeConversion(Context, EltVT);
1610 // If type is to be expanded, split the vector.
1611 // <4 x i140> -> <2 x i140>
1612 if (LK.first == TypeExpandInteger)
1613 return LegalizeKind(TypeSplitVector,
1614 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1616 // Promote the integer element types until a legal vector type is found
1617 // or until the element integer type is too big. If a legal type was not
1618 // found, fallback to the usual mechanism of widening/splitting the
1620 EVT OldEltVT = EltVT;
1622 // Increase the bitwidth of the element to the next pow-of-two
1623 // (which is greater than 8 bits).
1624 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1625 ).getRoundIntegerType(Context);
1627 // Stop trying when getting a non-simple element type.
1628 // Note that vector elements may be greater than legal vector element
1629 // types. Example: X86 XMM registers hold 64bit element on 32bit
1631 if (!EltVT.isSimple()) break;
1633 // Build a new vector type and check if it is legal.
1634 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1635 // Found a legal promoted vector type.
1636 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1637 return LegalizeKind(TypePromoteInteger,
1638 EVT::getVectorVT(Context, EltVT, NumElts));
1641 // Reset the type to the unexpanded type if we did not find a legal vector
1642 // type with a promoted vector element type.
1646 // Try to widen the vector until a legal type is found.
1647 // If there is no wider legal type, split the vector.
1649 // Round up to the next power of 2.
1650 NumElts = (unsigned)NextPowerOf2(NumElts);
1652 // If there is no simple vector type with this many elements then there
1653 // cannot be a larger legal vector type. Note that this assumes that
1654 // there are no skipped intermediate vector types in the simple types.
1655 if (!EltVT.isSimple()) break;
1656 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1657 if (LargerVector == MVT()) break;
1659 // If this type is legal then widen the vector.
1660 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1661 return LegalizeKind(TypeWidenVector, LargerVector);
1664 // Widen odd vectors to next power of two.
1665 if (!VT.isPow2VectorType()) {
1666 EVT NVT = VT.getPow2VectorType(Context);
1667 return LegalizeKind(TypeWidenVector, NVT);
1670 // Vectors with illegal element types are expanded.
1671 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1672 return LegalizeKind(TypeSplitVector, NVT);
1676 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1678 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1679 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1682 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1684 /// For operations that must be promoted to a specific type, this holds the
1685 /// destination type. This map should be sparse, so don't hold it as an
1688 /// Targets add entries to this map with AddPromotedToType(..), clients access
1689 /// this with getTypeToPromoteTo(..).
1690 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1693 /// Stores the name each libcall.
1694 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1696 /// The ISD::CondCode that should be used to test the result of each of the
1697 /// comparison libcall against zero.
1698 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1700 /// Stores the CallingConv that should be used for each libcall.
1701 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1704 /// \brief Specify maximum number of store instructions per memset call.
1706 /// When lowering \@llvm.memset this field specifies the maximum number of
1707 /// store operations that may be substituted for the call to memset. Targets
1708 /// must set this value based on the cost threshold for that target. Targets
1709 /// should assume that the memset will be done using as many of the largest
1710 /// store operations first, followed by smaller ones, if necessary, per
1711 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1712 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1713 /// store. This only applies to setting a constant array of a constant size.
1714 unsigned MaxStoresPerMemset;
1716 /// Maximum number of stores operations that may be substituted for the call
1717 /// to memset, used for functions with OptSize attribute.
1718 unsigned MaxStoresPerMemsetOptSize;
1720 /// \brief Specify maximum bytes of store instructions per memcpy call.
1722 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1723 /// store operations that may be substituted for a call to memcpy. Targets
1724 /// must set this value based on the cost threshold for that target. Targets
1725 /// should assume that the memcpy will be done using as many of the largest
1726 /// store operations first, followed by smaller ones, if necessary, per
1727 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1728 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1729 /// and one 1-byte store. This only applies to copying a constant array of
1731 unsigned MaxStoresPerMemcpy;
1733 /// Maximum number of store operations that may be substituted for a call to
1734 /// memcpy, used for functions with OptSize attribute.
1735 unsigned MaxStoresPerMemcpyOptSize;
1737 /// \brief Specify maximum bytes of store instructions per memmove call.
1739 /// When lowering \@llvm.memmove this field specifies the maximum number of
1740 /// store instructions that may be substituted for a call to memmove. Targets
1741 /// must set this value based on the cost threshold for that target. Targets
1742 /// should assume that the memmove will be done using as many of the largest
1743 /// store operations first, followed by smaller ones, if necessary, per
1744 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1745 /// with 8-bit alignment would result in nine 1-byte stores. This only
1746 /// applies to copying a constant array of constant size.
1747 unsigned MaxStoresPerMemmove;
1749 /// Maximum number of store instructions that may be substituted for a call to
1750 /// memmove, used for functions with OpSize attribute.
1751 unsigned MaxStoresPerMemmoveOptSize;
1753 /// Tells the code generator that select is more expensive than a branch if
1754 /// the branch is usually predicted right.
1755 bool PredictableSelectIsExpensive;
1757 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1758 /// a mask of a single bit, a compare, and a branch into a single instruction.
1759 bool MaskAndBranchFoldingIsLegal;
1762 /// Return true if the value types that can be represented by the specified
1763 /// register class are all legal.
1764 bool isLegalRC(const TargetRegisterClass *RC) const;
1766 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1767 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1768 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1771 /// This class defines information used to lower LLVM code to legal SelectionDAG
1772 /// operators that the target instruction selector can accept natively.
1774 /// This class also defines callbacks that targets must implement to lower
1775 /// target-specific constructs to SelectionDAG operators.
1776 class TargetLowering : public TargetLoweringBase {
1777 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1778 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1781 /// NOTE: The constructor takes ownership of TLOF.
1782 explicit TargetLowering(const TargetMachine &TM,
1783 const TargetLoweringObjectFile *TLOF);
1785 /// Returns true by value, base pointer and offset pointer and addressing mode
1786 /// by reference if the node's address can be legally represented as
1787 /// pre-indexed load / store address.
1788 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1789 SDValue &/*Offset*/,
1790 ISD::MemIndexedMode &/*AM*/,
1791 SelectionDAG &/*DAG*/) const {
1795 /// Returns true by value, base pointer and offset pointer and addressing mode
1796 /// by reference if this node can be combined with a load / store to form a
1797 /// post-indexed load / store.
1798 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1800 SDValue &/*Offset*/,
1801 ISD::MemIndexedMode &/*AM*/,
1802 SelectionDAG &/*DAG*/) const {
1806 /// Return the entry encoding for a jump table in the current function. The
1807 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1808 virtual unsigned getJumpTableEncoding() const;
1810 virtual const MCExpr *
1811 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1812 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1813 MCContext &/*Ctx*/) const {
1814 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1817 /// Returns relocation base for the given PIC jumptable.
1818 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1819 SelectionDAG &DAG) const;
1821 /// This returns the relocation base for the given PIC jumptable, the same as
1822 /// getPICJumpTableRelocBase, but as an MCExpr.
1823 virtual const MCExpr *
1824 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1825 unsigned JTI, MCContext &Ctx) const;
1827 /// Return true if folding a constant offset with the given GlobalAddress is
1828 /// legal. It is frequently not legal in PIC relocation models.
1829 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1831 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1832 SDValue &Chain) const;
1834 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1835 SDValue &NewLHS, SDValue &NewRHS,
1836 ISD::CondCode &CCCode, SDLoc DL) const;
1838 /// Returns a pair of (return value, chain).
1839 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1840 EVT RetVT, const SDValue *Ops,
1841 unsigned NumOps, bool isSigned,
1842 SDLoc dl, bool doesNotReturn = false,
1843 bool isReturnValueUsed = true) const;
1845 //===--------------------------------------------------------------------===//
1846 // TargetLowering Optimization Methods
1849 /// A convenience struct that encapsulates a DAG, and two SDValues for
1850 /// returning information from TargetLowering to its clients that want to
1852 struct TargetLoweringOpt {
1859 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1861 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1863 bool LegalTypes() const { return LegalTys; }
1864 bool LegalOperations() const { return LegalOps; }
1866 bool CombineTo(SDValue O, SDValue N) {
1872 /// Check to see if the specified operand of the specified instruction is a
1873 /// constant integer. If so, check to see if there are any bits set in the
1874 /// constant that are not demanded. If so, shrink the constant and return
1876 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1878 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1879 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1880 /// generalized for targets with other types of implicit widening casts.
1881 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1885 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1886 /// result of Op are ever used downstream. If we can use this information to
1887 /// simplify Op, create a new simplified DAG node and return true, returning
1888 /// the original and new nodes in Old and New. Otherwise, analyze the
1889 /// expression and return a mask of KnownOne and KnownZero bits for the
1890 /// expression (used to simplify the caller). The KnownZero/One bits may only
1891 /// be accurate for those bits in the DemandedMask.
1892 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1893 APInt &KnownZero, APInt &KnownOne,
1894 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1896 /// Determine which of the bits specified in Mask are known to be either zero
1897 /// or one and return them in the KnownZero/KnownOne bitsets.
1898 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1901 const SelectionDAG &DAG,
1902 unsigned Depth = 0) const;
1904 /// This method can be implemented by targets that want to expose additional
1905 /// information about sign bits to the DAG Combiner.
1906 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1907 unsigned Depth = 0) const;
1909 struct DAGCombinerInfo {
1910 void *DC; // The DAG Combiner object.
1912 bool CalledByLegalizer;
1916 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1917 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1919 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1920 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1921 bool isAfterLegalizeVectorOps() const {
1922 return Level == AfterLegalizeDAG;
1924 CombineLevel getDAGCombineLevel() { return Level; }
1925 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1927 void AddToWorklist(SDNode *N);
1928 void RemoveFromWorklist(SDNode *N);
1929 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1931 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1932 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1934 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1937 /// Return if the N is a constant or constant vector equal to the true value
1938 /// from getBooleanContents().
1939 bool isConstTrueVal(const SDNode *N) const;
1941 /// Return if the N is a constant or constant vector equal to the false value
1942 /// from getBooleanContents().
1943 bool isConstFalseVal(const SDNode *N) const;
1945 /// Try to simplify a setcc built with the specified operands and cc. If it is
1946 /// unable to simplify it, return a null SDValue.
1947 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1948 ISD::CondCode Cond, bool foldBooleans,
1949 DAGCombinerInfo &DCI, SDLoc dl) const;
1951 /// Returns true (and the GlobalValue and the offset) if the node is a
1952 /// GlobalAddress + offset.
1954 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1956 /// This method will be invoked for all target nodes and for any
1957 /// target-independent nodes that the target has registered with invoke it
1960 /// The semantics are as follows:
1962 /// SDValue.Val == 0 - No change was made
1963 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1964 /// otherwise - N should be replaced by the returned Operand.
1966 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1967 /// more complex transformations.
1969 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1971 /// Return true if the target has native support for the specified value type
1972 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
1973 /// i16 is legal, but undesirable since i16 instruction encodings are longer
1974 /// and some i16 instructions are slow.
1975 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1976 // By default, assume all legal types are desirable.
1977 return isTypeLegal(VT);
1980 /// Return true if it is profitable for dag combiner to transform a floating
1981 /// point op of specified opcode to a equivalent op of an integer
1982 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
1983 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1988 /// This method query the target whether it is beneficial for dag combiner to
1989 /// promote the specified node. If true, it should return the desired
1990 /// promotion type by reference.
1991 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1995 //===--------------------------------------------------------------------===//
1996 // Lowering methods - These methods must be implemented by targets so that
1997 // the SelectionDAGBuilder code knows how to lower these.
2000 /// This hook must be implemented to lower the incoming (formal) arguments,
2001 /// described by the Ins array, into the specified DAG. The implementation
2002 /// should fill in the InVals array with legal-type argument values, and
2003 /// return the resulting token chain value.
2006 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2008 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2009 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2010 SmallVectorImpl<SDValue> &/*InVals*/) const {
2011 llvm_unreachable("Not Implemented");
2014 struct ArgListEntry {
2023 bool isInAlloca : 1;
2024 bool isReturned : 1;
2027 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2028 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2029 isReturned(false), Alignment(0) { }
2031 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2033 typedef std::vector<ArgListEntry> ArgListTy;
2035 /// This structure contains all information that is necessary for lowering
2036 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2037 /// needs to lower a call, and targets will see this struct in their LowerCall
2039 struct CallLoweringInfo {
2046 bool DoesNotReturn : 1;
2047 bool IsReturnValueUsed : 1;
2049 // IsTailCall should be modified by implementations of
2050 // TargetLowering::LowerCall that perform tail call conversions.
2053 unsigned NumFixedArgs;
2054 CallingConv::ID CallConv;
2059 ImmutableCallSite *CS;
2060 SmallVector<ISD::OutputArg, 32> Outs;
2061 SmallVector<SDValue, 32> OutVals;
2062 SmallVector<ISD::InputArg, 32> Ins;
2065 /// Constructs a call lowering context based on the ImmutableCallSite \p cs.
2066 CallLoweringInfo(SDValue chain, Type *retTy,
2067 FunctionType *FTy, bool isTailCall, SDValue callee,
2068 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
2069 ImmutableCallSite &cs)
2070 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
2071 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
2072 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
2073 DoesNotReturn(cs.doesNotReturn()),
2074 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
2075 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
2076 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
2079 /// Constructs a call lowering context based on the provided call
2081 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
2082 bool isVarArg, bool isInReg, unsigned numFixedArgs,
2083 CallingConv::ID callConv, bool isTailCall,
2084 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
2085 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
2086 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
2087 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
2088 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
2089 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
2090 Args(args), DAG(dag), DL(dl), CS(NULL) {}
2093 /// This function lowers an abstract call to a function into an actual call.
2094 /// This returns a pair of operands. The first element is the return value
2095 /// for the function (if RetTy is not VoidTy). The second element is the
2096 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2097 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2099 /// This hook must be implemented to lower calls into the the specified
2100 /// DAG. The outgoing arguments to the call are described by the Outs array,
2101 /// and the values to be returned by the call are described by the Ins
2102 /// array. The implementation should fill in the InVals array with legal-type
2103 /// return values from the call, and return the resulting token chain value.
2105 LowerCall(CallLoweringInfo &/*CLI*/,
2106 SmallVectorImpl<SDValue> &/*InVals*/) const {
2107 llvm_unreachable("Not Implemented");
2110 /// Target-specific cleanup for formal ByVal parameters.
2111 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2113 /// This hook should be implemented to check whether the return values
2114 /// described by the Outs array can fit into the return registers. If false
2115 /// is returned, an sret-demotion is performed.
2116 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2117 MachineFunction &/*MF*/, bool /*isVarArg*/,
2118 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2119 LLVMContext &/*Context*/) const
2121 // Return true by default to get preexisting behavior.
2125 /// This hook must be implemented to lower outgoing return values, described
2126 /// by the Outs array, into the specified DAG. The implementation should
2127 /// return the resulting token chain value.
2129 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2131 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2132 const SmallVectorImpl<SDValue> &/*OutVals*/,
2133 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2134 llvm_unreachable("Not Implemented");
2137 /// Return true if result of the specified node is used by a return node
2138 /// only. It also compute and return the input chain for the tail call.
2140 /// This is used to determine whether it is possible to codegen a libcall as
2141 /// tail call at legalization time.
2142 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2146 /// Return true if the target may be able emit the call instruction as a tail
2147 /// call. This is used by optimization passes to determine if it's profitable
2148 /// to duplicate return instructions to enable tailcall optimization.
2149 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2153 /// Return the builtin name for the __builtin___clear_cache intrinsic
2154 /// Default is to invoke the clear cache library call
2155 virtual const char * getClearCacheBuiltinName() const {
2156 return "__clear_cache";
2159 /// Return the type that should be used to zero or sign extend a
2160 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2161 /// convention requires the return type to be promoted, but this is not true
2162 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2163 /// calling conventions. The frontend should handle this and include all of
2164 /// the necessary information.
2165 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2166 ISD::NodeType /*ExtendKind*/) const {
2167 MVT MinVT = getRegisterType(MVT::i32);
2168 return VT.bitsLT(MinVT) ? MinVT : VT;
2171 /// Returns a 0 terminated array of registers that can be safely used as
2172 /// scratch registers.
2173 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const {
2177 /// This callback is used to prepare for a volatile or atomic load.
2178 /// It takes a chain node as input and returns the chain for the load itself.
2180 /// Having a callback like this is necessary for targets like SystemZ,
2181 /// which allows a CPU to reuse the result of a previous load indefinitely,
2182 /// even if a cache-coherent store is performed by another CPU. The default
2183 /// implementation does nothing.
2184 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2185 SelectionDAG &DAG) const {
2189 /// This callback is invoked by the type legalizer to legalize nodes with an
2190 /// illegal operand type but legal result types. It replaces the
2191 /// LowerOperation callback in the type Legalizer. The reason we can not do
2192 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2193 /// use this callback.
2195 /// TODO: Consider merging with ReplaceNodeResults.
2197 /// The target places new result values for the node in Results (their number
2198 /// and types must exactly match those of the original return values of
2199 /// the node), or leaves Results empty, which indicates that the node is not
2200 /// to be custom lowered after all.
2201 /// The default implementation calls LowerOperation.
2202 virtual void LowerOperationWrapper(SDNode *N,
2203 SmallVectorImpl<SDValue> &Results,
2204 SelectionDAG &DAG) const;
2206 /// This callback is invoked for operations that are unsupported by the
2207 /// target, which are registered to use 'custom' lowering, and whose defined
2208 /// values are all legal. If the target has no operations that require custom
2209 /// lowering, it need not implement this. The default implementation of this
2211 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2213 /// This callback is invoked when a node result type is illegal for the
2214 /// target, and the operation was registered to use 'custom' lowering for that
2215 /// result type. The target places new result values for the node in Results
2216 /// (their number and types must exactly match those of the original return
2217 /// values of the node), or leaves Results empty, which indicates that the
2218 /// node is not to be custom lowered after all.
2220 /// If the target has no operations that require custom lowering, it need not
2221 /// implement this. The default implementation aborts.
2222 virtual void ReplaceNodeResults(SDNode * /*N*/,
2223 SmallVectorImpl<SDValue> &/*Results*/,
2224 SelectionDAG &/*DAG*/) const {
2225 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2228 /// This method returns the name of a target specific DAG node.
2229 virtual const char *getTargetNodeName(unsigned Opcode) const;
2231 /// This method returns a target specific FastISel object, or null if the
2232 /// target does not support "fast" ISel.
2233 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2234 const TargetLibraryInfo *) const {
2239 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2240 SelectionDAG &DAG) const;
2242 //===--------------------------------------------------------------------===//
2243 // Inline Asm Support hooks
2246 /// This hook allows the target to expand an inline asm call to be explicit
2247 /// llvm code if it wants to. This is useful for turning simple inline asms
2248 /// into LLVM intrinsics, which gives the compiler more information about the
2249 /// behavior of the code.
2250 virtual bool ExpandInlineAsm(CallInst *) const {
2254 enum ConstraintType {
2255 C_Register, // Constraint represents specific register(s).
2256 C_RegisterClass, // Constraint represents any of register(s) in class.
2257 C_Memory, // Memory constraint.
2258 C_Other, // Something else.
2259 C_Unknown // Unsupported constraint.
2262 enum ConstraintWeight {
2264 CW_Invalid = -1, // No match.
2265 CW_Okay = 0, // Acceptable.
2266 CW_Good = 1, // Good weight.
2267 CW_Better = 2, // Better weight.
2268 CW_Best = 3, // Best weight.
2270 // Well-known weights.
2271 CW_SpecificReg = CW_Okay, // Specific register operands.
2272 CW_Register = CW_Good, // Register operands.
2273 CW_Memory = CW_Better, // Memory operands.
2274 CW_Constant = CW_Best, // Constant operand.
2275 CW_Default = CW_Okay // Default or don't know type.
2278 /// This contains information for each constraint that we are lowering.
2279 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2280 /// This contains the actual string for the code, like "m". TargetLowering
2281 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2282 /// matches the operand.
2283 std::string ConstraintCode;
2285 /// Information about the constraint code, e.g. Register, RegisterClass,
2286 /// Memory, Other, Unknown.
2287 TargetLowering::ConstraintType ConstraintType;
2289 /// If this is the result output operand or a clobber, this is null,
2290 /// otherwise it is the incoming operand to the CallInst. This gets
2291 /// modified as the asm is processed.
2292 Value *CallOperandVal;
2294 /// The ValueType for the operand value.
2297 /// Return true of this is an input operand that is a matching constraint
2299 bool isMatchingInputConstraint() const;
2301 /// If this is an input matching constraint, this method returns the output
2302 /// operand it matches.
2303 unsigned getMatchedOperand() const;
2305 /// Copy constructor for copying from a ConstraintInfo.
2306 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2307 : InlineAsm::ConstraintInfo(info),
2308 ConstraintType(TargetLowering::C_Unknown),
2309 CallOperandVal(0), ConstraintVT(MVT::Other) {
2313 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2315 /// Split up the constraint string from the inline assembly value into the
2316 /// specific constraints and their prefixes, and also tie in the associated
2317 /// operand values. If this returns an empty vector, and if the constraint
2318 /// string itself isn't empty, there was an error parsing.
2319 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2321 /// Examine constraint type and operand type and determine a weight value.
2322 /// The operand object must already have been set up with the operand type.
2323 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2324 AsmOperandInfo &info, int maIndex) const;
2326 /// Examine constraint string and operand type and determine a weight value.
2327 /// The operand object must already have been set up with the operand type.
2328 virtual ConstraintWeight getSingleConstraintMatchWeight(
2329 AsmOperandInfo &info, const char *constraint) const;
2331 /// Determines the constraint code and constraint type to use for the specific
2332 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2333 /// If the actual operand being passed in is available, it can be passed in as
2334 /// Op, otherwise an empty SDValue can be passed.
2335 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2337 SelectionDAG *DAG = 0) const;
2339 /// Given a constraint, return the type of constraint it is for this target.
2340 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2342 /// Given a physical register constraint (e.g. {edx}), return the register
2343 /// number and the register class for the register.
2345 /// Given a register class constraint, like 'r', if this corresponds directly
2346 /// to an LLVM register class, return a register of 0 and the register class
2349 /// This should only be used for C_Register constraints. On error, this
2350 /// returns a register number of 0 and a null register class pointer..
2351 virtual std::pair<unsigned, const TargetRegisterClass*>
2352 getRegForInlineAsmConstraint(const std::string &Constraint,
2355 /// Try to replace an X constraint, which matches anything, with another that
2356 /// has more specific requirements based on the type of the corresponding
2357 /// operand. This returns null if there is no replacement to make.
2358 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2360 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2361 /// add anything to Ops.
2362 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2363 std::vector<SDValue> &Ops,
2364 SelectionDAG &DAG) const;
2366 //===--------------------------------------------------------------------===//
2367 // Div utility functions
2369 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2370 SelectionDAG &DAG) const;
2371 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2372 std::vector<SDNode*> *Created) const;
2373 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2374 std::vector<SDNode*> *Created) const;
2376 //===--------------------------------------------------------------------===//
2377 // Instruction Emitting Hooks
2380 /// This method should be implemented by targets that mark instructions with
2381 /// the 'usesCustomInserter' flag. These instructions are special in various
2382 /// ways, which require special support to insert. The specified MachineInstr
2383 /// is created but not inserted into any basic blocks, and this method is
2384 /// called to expand it into a sequence of instructions, potentially also
2385 /// creating new basic blocks and control flow.
2386 virtual MachineBasicBlock *
2387 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2389 /// This method should be implemented by targets that mark instructions with
2390 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2391 /// instruction selection by target hooks. e.g. To fill in optional defs for
2392 /// ARM 's' setting instructions.
2394 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2397 /// Given an LLVM IR type and return type attributes, compute the return value
2398 /// EVTs and flags, and optionally also the offsets, if the return value is
2399 /// being lowered to memory.
2400 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2401 SmallVectorImpl<ISD::OutputArg> &Outs,
2402 const TargetLowering &TLI);
2404 } // end llvm namespace