1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
27 #include "llvm/ADT/APFloat.h"
28 #include "llvm/ADT/STLExtras.h"
37 class TargetRegisterClass;
41 class MachineBasicBlock;
44 class TargetSubtarget;
46 //===----------------------------------------------------------------------===//
47 /// TargetLowering - This class defines information used to lower LLVM code to
48 /// legal SelectionDAG operators that the target instruction selector can accept
51 /// This class also defines callbacks that targets must implement to lower
52 /// target-specific constructs to SelectionDAG operators.
54 class TargetLowering {
56 /// LegalizeAction - This enum indicates whether operations are valid for a
57 /// target, and if not, what action should be used to make them valid.
59 Legal, // The target natively supports this operation.
60 Promote, // This operation should be executed in a larger type.
61 Expand, // Try to expand this to other ops, otherwise use a libcall.
62 Custom // Use the LowerOperation hook to implement custom lowering.
65 enum OutOfRangeShiftAmount {
66 Undefined, // Oversized shift amounts are undefined (default).
67 Mask, // Shift amounts are auto masked (anded) to value size.
68 Extend // Oversized shift pulls in zeros or sign bits.
71 enum SetCCResultValue {
72 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
73 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
74 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
77 enum SchedPreference {
78 SchedulingForLatency, // Scheduling for shortest total latency.
79 SchedulingForRegPressure // Scheduling for lowest register pressure.
82 explicit TargetLowering(TargetMachine &TM);
83 virtual ~TargetLowering();
85 TargetMachine &getTargetMachine() const { return TM; }
86 const TargetData *getTargetData() const { return TD; }
88 bool isLittleEndian() const { return IsLittleEndian; }
89 MVT::ValueType getPointerTy() const { return PointerTy; }
90 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
91 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
93 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
95 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
97 /// isSelectExpensive - Return true if the select operation is expensive for
99 bool isSelectExpensive() const { return SelectIsExpensive; }
101 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
102 /// a sequence of several shifts, adds, and multiplies for this target.
103 bool isIntDivCheap() const { return IntDivIsCheap; }
105 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
107 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
109 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
111 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
113 /// getSetCCResultContents - For targets without boolean registers, this flag
114 /// returns information about the contents of the high-bits in the setcc
116 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
118 /// getSchedulingPreference - Return target scheduling preference.
119 SchedPreference getSchedulingPreference() const {
120 return SchedPreferenceInfo;
123 /// getRegClassFor - Return the register class that should be used for the
124 /// specified value type. This may only be called on legal types.
125 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
126 assert(VT < array_lengthof(RegClassForVT));
127 TargetRegisterClass *RC = RegClassForVT[VT];
128 assert(RC && "This value type is not natively supported!");
132 /// isTypeLegal - Return true if the target has native support for the
133 /// specified value type. This means that it has a register that directly
134 /// holds it without promotions or expansions.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT));
137 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
140 class ValueTypeActionImpl {
141 /// ValueTypeActions - This is a bitvector that contains two bits for each
142 /// value type, where the two bits correspond to the LegalizeAction enum.
143 /// This can be queried with "getTypeAction(VT)".
144 uint32_t ValueTypeActions[2];
146 ValueTypeActionImpl() {
147 ValueTypeActions[0] = ValueTypeActions[1] = 0;
149 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
150 ValueTypeActions[0] = RHS.ValueTypeActions[0];
151 ValueTypeActions[1] = RHS.ValueTypeActions[1];
154 LegalizeAction getTypeAction(MVT::ValueType VT) const {
155 if (MVT::isExtendedVT(VT)) {
156 if (MVT::isVector(VT)) return Expand;
157 if (MVT::isInteger(VT))
158 // First promote to a power-of-two size, then expand if necessary.
159 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
160 assert(0 && "Unsupported extended type!");
162 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
163 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
165 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
166 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
167 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
171 const ValueTypeActionImpl &getValueTypeActions() const {
172 return ValueTypeActions;
175 /// getTypeAction - Return how we should legalize values of this type, either
176 /// it is already legal (return 'Legal') or we need to promote it to a larger
177 /// type (return 'Promote'), or we need to expand it into multiple registers
178 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
179 LegalizeAction getTypeAction(MVT::ValueType VT) const {
180 return ValueTypeActions.getTypeAction(VT);
183 /// getTypeToTransformTo - For types supported by the target, this is an
184 /// identity function. For types that must be promoted to larger types, this
185 /// returns the larger type to promote to. For integer types that are larger
186 /// than the largest integer register, this contains one step in the expansion
187 /// to get to the smaller register. For illegal floating point types, this
188 /// returns the integer type to transform to.
189 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
190 if (!MVT::isExtendedVT(VT)) {
191 assert(VT < array_lengthof(TransformToType));
192 MVT::ValueType NVT = TransformToType[VT];
193 assert(getTypeAction(NVT) != Promote &&
194 "Promote may not follow Expand or Promote");
198 if (MVT::isVector(VT))
199 return MVT::getVectorType(MVT::getVectorElementType(VT),
200 MVT::getVectorNumElements(VT) / 2);
201 if (MVT::isInteger(VT)) {
202 MVT::ValueType NVT = MVT::RoundIntegerType(VT);
204 // Size is a power of two - expand to half the size.
205 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
207 // Promote to a power of two size, avoiding multi-step promotion.
208 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
210 assert(0 && "Unsupported extended type!");
213 /// getTypeToExpandTo - For types supported by the target, this is an
214 /// identity function. For types that must be expanded (i.e. integer types
215 /// that are larger than the largest integer register or illegal floating
216 /// point types), this returns the largest legal type it will be expanded to.
217 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
218 assert(!MVT::isVector(VT));
220 switch (getTypeAction(VT)) {
224 VT = getTypeToTransformTo(VT);
227 assert(false && "Type is not legal nor is it to be expanded!");
234 /// getVectorTypeBreakdown - Vector types are broken down into some number of
235 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
236 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
237 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
239 /// This method returns the number of registers needed, and the VT for each
240 /// register. It also returns the VT and quantity of the intermediate values
241 /// before they are promoted/expanded.
243 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
244 MVT::ValueType &IntermediateVT,
245 unsigned &NumIntermediates,
246 MVT::ValueType &RegisterVT) const;
248 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
249 legal_fpimm_iterator legal_fpimm_begin() const {
250 return LegalFPImmediates.begin();
252 legal_fpimm_iterator legal_fpimm_end() const {
253 return LegalFPImmediates.end();
256 /// isShuffleMaskLegal - Targets can use this to indicate that they only
257 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
258 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
259 /// are assumed to be legal.
260 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
264 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
265 /// used by Targets can use this to indicate if there is a suitable
266 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
268 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
270 SelectionDAG &DAG) const {
274 /// getOperationAction - Return how this operation should be treated: either
275 /// it is legal, needs to be promoted to a larger size, needs to be
276 /// expanded to some other code sequence, or the target has a custom expander
278 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
279 if (MVT::isExtendedVT(VT)) return Expand;
280 assert(Op < array_lengthof(OpActions) &&
281 VT < sizeof(OpActions[0])*4 && "Table isn't big enough!");
282 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
285 /// isOperationLegal - Return true if the specified operation is legal on this
287 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
288 return getOperationAction(Op, VT) == Legal ||
289 getOperationAction(Op, VT) == Custom;
292 /// getLoadXAction - Return how this load with extension should be treated:
293 /// either it is legal, needs to be promoted to a larger size, needs to be
294 /// expanded to some other code sequence, or the target has a custom expander
296 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
297 assert(LType < array_lengthof(LoadXActions) &&
298 VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!");
299 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
302 /// isLoadXLegal - Return true if the specified load with extension is legal
304 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
305 return !MVT::isExtendedVT(VT) &&
306 (getLoadXAction(LType, VT) == Legal ||
307 getLoadXAction(LType, VT) == Custom);
310 /// getTruncStoreAction - Return how this store with truncation should be
311 /// treated: either it is legal, needs to be promoted to a larger size, needs
312 /// to be expanded to some other code sequence, or the target has a custom
314 LegalizeAction getTruncStoreAction(MVT::ValueType ValVT,
315 MVT::ValueType MemVT) const {
316 assert(ValVT < array_lengthof(TruncStoreActions) &&
317 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
318 return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3);
321 /// isTruncStoreLegal - Return true if the specified store with truncation is
322 /// legal on this target.
323 bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const {
324 return !MVT::isExtendedVT(MemVT) &&
325 (getTruncStoreAction(ValVT, MemVT) == Legal ||
326 getTruncStoreAction(ValVT, MemVT) == Custom);
329 /// getIndexedLoadAction - Return how the indexed load should be treated:
330 /// either it is legal, needs to be promoted to a larger size, needs to be
331 /// expanded to some other code sequence, or the target has a custom expander
334 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
335 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
336 VT < sizeof(IndexedModeActions[0][0])*4 &&
337 "Table isn't big enough!");
338 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
341 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
343 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
344 return getIndexedLoadAction(IdxMode, VT) == Legal ||
345 getIndexedLoadAction(IdxMode, VT) == Custom;
348 /// getIndexedStoreAction - Return how the indexed store should be treated:
349 /// either it is legal, needs to be promoted to a larger size, needs to be
350 /// expanded to some other code sequence, or the target has a custom expander
353 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
354 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
355 VT < sizeof(IndexedModeActions[1][0])*4 &&
356 "Table isn't big enough!");
357 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
360 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
362 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
363 return getIndexedStoreAction(IdxMode, VT) == Legal ||
364 getIndexedStoreAction(IdxMode, VT) == Custom;
367 /// getConvertAction - Return how the conversion should be treated:
368 /// either it is legal, needs to be promoted to a larger size, needs to be
369 /// expanded to some other code sequence, or the target has a custom expander
372 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
373 assert(FromVT < array_lengthof(ConvertActions) &&
374 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
375 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
378 /// isConvertLegal - Return true if the specified conversion is legal
380 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
381 return getConvertAction(FromVT, ToVT) == Legal ||
382 getConvertAction(FromVT, ToVT) == Custom;
385 /// getTypeToPromoteTo - If the action for this operation is to promote, this
386 /// method returns the ValueType to promote to.
387 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
388 assert(getOperationAction(Op, VT) == Promote &&
389 "This operation isn't promoted!");
391 // See if this has an explicit type specified.
392 std::map<std::pair<unsigned, MVT::ValueType>,
393 MVT::ValueType>::const_iterator PTTI =
394 PromoteToType.find(std::make_pair(Op, VT));
395 if (PTTI != PromoteToType.end()) return PTTI->second;
397 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
398 "Cannot autopromote this type, add it with AddPromotedToType.");
400 MVT::ValueType NVT = VT;
402 NVT = (MVT::ValueType)(NVT+1);
403 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
404 "Didn't find type to promote to!");
405 } while (!isTypeLegal(NVT) ||
406 getOperationAction(Op, NVT) == Promote);
410 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
411 /// This is fixed by the LLVM operations except for the pointer size. If
412 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
413 /// counterpart (e.g. structs), otherwise it will assert.
414 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
415 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
416 return VT == MVT::iPTR ? PointerTy : VT;
419 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
420 /// function arguments in the caller parameter area.
421 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
423 /// getRegisterType - Return the type of registers that this ValueType will
424 /// eventually require.
425 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
426 if (!MVT::isExtendedVT(VT)) {
427 assert(VT < array_lengthof(RegisterTypeForVT));
428 return RegisterTypeForVT[VT];
430 if (MVT::isVector(VT)) {
431 MVT::ValueType VT1, RegisterVT;
432 unsigned NumIntermediates;
433 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
436 assert(0 && "Unsupported extended type!");
439 /// getNumRegisters - Return the number of registers that this ValueType will
440 /// eventually require. This is one for any types promoted to live in larger
441 /// registers, but may be more than one for types (like i64) that are split
443 unsigned getNumRegisters(MVT::ValueType VT) const {
444 if (!MVT::isExtendedVT(VT)) {
445 assert(VT < array_lengthof(NumRegistersForVT));
446 return NumRegistersForVT[VT];
448 if (MVT::isVector(VT)) {
449 MVT::ValueType VT1, VT2;
450 unsigned NumIntermediates;
451 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
453 assert(0 && "Unsupported extended type!");
456 /// hasTargetDAGCombine - If true, the target has custom DAG combine
457 /// transformations that it can perform for the specified node.
458 bool hasTargetDAGCombine(ISD::NodeType NT) const {
459 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
460 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
463 /// This function returns the maximum number of store operations permitted
464 /// to replace a call to llvm.memset. The value is set by the target at the
465 /// performance threshold for such a replacement.
466 /// @brief Get maximum # of store operations permitted for llvm.memset
467 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
469 /// This function returns the maximum number of store operations permitted
470 /// to replace a call to llvm.memcpy. The value is set by the target at the
471 /// performance threshold for such a replacement.
472 /// @brief Get maximum # of store operations permitted for llvm.memcpy
473 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
475 /// This function returns the maximum number of store operations permitted
476 /// to replace a call to llvm.memmove. The value is set by the target at the
477 /// performance threshold for such a replacement.
478 /// @brief Get maximum # of store operations permitted for llvm.memmove
479 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
481 /// This function returns true if the target allows unaligned memory accesses.
482 /// This is used, for example, in situations where an array copy/move/set is
483 /// converted to a sequence of store operations. It's use helps to ensure that
484 /// such replacements don't generate code that causes an alignment error
485 /// (trap) on the target machine.
486 /// @brief Determine if the target supports unaligned memory accesses.
487 bool allowsUnalignedMemoryAccesses() const {
488 return allowUnalignedMemoryAccesses;
491 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
492 /// to implement llvm.setjmp.
493 bool usesUnderscoreSetJmp() const {
494 return UseUnderscoreSetJmp;
497 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
498 /// to implement llvm.longjmp.
499 bool usesUnderscoreLongJmp() const {
500 return UseUnderscoreLongJmp;
503 /// getStackPointerRegisterToSaveRestore - If a physical register, this
504 /// specifies the register that llvm.savestack/llvm.restorestack should save
506 unsigned getStackPointerRegisterToSaveRestore() const {
507 return StackPointerRegisterToSaveRestore;
510 /// getExceptionAddressRegister - If a physical register, this returns
511 /// the register that receives the exception address on entry to a landing
513 unsigned getExceptionAddressRegister() const {
514 return ExceptionPointerRegister;
517 /// getExceptionSelectorRegister - If a physical register, this returns
518 /// the register that receives the exception typeid on entry to a landing
520 unsigned getExceptionSelectorRegister() const {
521 return ExceptionSelectorRegister;
524 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
525 /// set, the default is 200)
526 unsigned getJumpBufSize() const {
530 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
531 /// (if never set, the default is 0)
532 unsigned getJumpBufAlignment() const {
533 return JumpBufAlignment;
536 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
537 /// limit. Any block whose size is greater should not be predicated.
538 virtual unsigned getIfCvtBlockSizeLimit() const {
539 return IfCvtBlockSizeLimit;
542 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
543 /// block to be considered for duplication. Any block whose size is greater
544 /// should not be duplicated to facilitate its predication.
545 virtual unsigned getIfCvtDupBlockSizeLimit() const {
546 return IfCvtDupBlockSizeLimit;
549 /// getPreIndexedAddressParts - returns true by value, base pointer and
550 /// offset pointer and addressing mode by reference if the node's address
551 /// can be legally represented as pre-indexed load / store address.
552 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
554 ISD::MemIndexedMode &AM,
559 /// getPostIndexedAddressParts - returns true by value, base pointer and
560 /// offset pointer and addressing mode by reference if this node can be
561 /// combined with a load / store to form a post-indexed load / store.
562 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
563 SDOperand &Base, SDOperand &Offset,
564 ISD::MemIndexedMode &AM,
569 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
571 virtual SDOperand getPICJumpTableRelocBase(SDOperand Table,
572 SelectionDAG &DAG) const;
574 //===--------------------------------------------------------------------===//
575 // TargetLowering Optimization Methods
578 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
579 /// SDOperands for returning information from TargetLowering to its clients
580 /// that want to combine
581 struct TargetLoweringOpt {
587 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
588 : DAG(InDAG), AfterLegalize(afterLegalize) {}
590 bool CombineTo(SDOperand O, SDOperand N) {
596 /// ShrinkDemandedConstant - Check to see if the specified operand of the
597 /// specified instruction is a constant integer. If so, check to see if
598 /// there are any bits set in the constant that are not demanded. If so,
599 /// shrink the constant and return true.
600 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
603 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
604 /// DemandedMask bits of the result of Op are ever used downstream. If we can
605 /// use this information to simplify Op, create a new simplified DAG node and
606 /// return true, returning the original and new nodes in Old and New.
607 /// Otherwise, analyze the expression and return a mask of KnownOne and
608 /// KnownZero bits for the expression (used to simplify the caller).
609 /// The KnownZero/One bits may only be accurate for those bits in the
611 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
612 uint64_t &KnownZero, uint64_t &KnownOne,
613 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
615 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
616 /// Mask are known to be either zero or one and return them in the
617 /// KnownZero/KnownOne bitsets.
618 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
622 const SelectionDAG &DAG,
623 unsigned Depth = 0) const;
625 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
626 /// targets that want to expose additional information about sign bits to the
628 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
629 unsigned Depth = 0) const;
631 struct DAGCombinerInfo {
632 void *DC; // The DAG Combiner object.
634 bool CalledByLegalizer;
638 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
639 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
641 bool isBeforeLegalize() const { return BeforeLegalize; }
642 bool isCalledByLegalizer() const { return CalledByLegalizer; }
644 void AddToWorklist(SDNode *N);
645 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
646 SDOperand CombineTo(SDNode *N, SDOperand Res);
647 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
650 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
651 /// and cc. If it is unable to simplify it, return a null SDOperand.
652 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
653 ISD::CondCode Cond, bool foldBooleans,
654 DAGCombinerInfo &DCI) const;
656 /// PerformDAGCombine - This method will be invoked for all target nodes and
657 /// for any target-independent nodes that the target has registered with
660 /// The semantics are as follows:
662 /// SDOperand.Val == 0 - No change was made
663 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
664 /// otherwise - N should be replaced by the returned Operand.
666 /// In addition, methods provided by DAGCombinerInfo may be used to perform
667 /// more complex transformations.
669 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
671 //===--------------------------------------------------------------------===//
672 // TargetLowering Configuration Methods - These methods should be invoked by
673 // the derived class constructor to configure this object for the target.
677 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
678 /// GOT for PC-relative code.
679 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
681 /// setShiftAmountType - Describe the type that should be used for shift
682 /// amounts. This type defaults to the pointer type.
683 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
685 /// setSetCCResultType - Describe the type that shoudl be used as the result
686 /// of a setcc operation. This defaults to the pointer type.
687 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
689 /// setSetCCResultContents - Specify how the target extends the result of a
690 /// setcc operation in a register.
691 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
693 /// setSchedulingPreference - Specify the target scheduling preference.
694 void setSchedulingPreference(SchedPreference Pref) {
695 SchedPreferenceInfo = Pref;
698 /// setShiftAmountFlavor - Describe how the target handles out of range shift
700 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
701 ShiftAmtHandling = OORSA;
704 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
705 /// use _setjmp to implement llvm.setjmp or the non _ version.
706 /// Defaults to false.
707 void setUseUnderscoreSetJmp(bool Val) {
708 UseUnderscoreSetJmp = Val;
711 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
712 /// use _longjmp to implement llvm.longjmp or the non _ version.
713 /// Defaults to false.
714 void setUseUnderscoreLongJmp(bool Val) {
715 UseUnderscoreLongJmp = Val;
718 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
719 /// specifies the register that llvm.savestack/llvm.restorestack should save
721 void setStackPointerRegisterToSaveRestore(unsigned R) {
722 StackPointerRegisterToSaveRestore = R;
725 /// setExceptionPointerRegister - If set to a physical register, this sets
726 /// the register that receives the exception address on entry to a landing
728 void setExceptionPointerRegister(unsigned R) {
729 ExceptionPointerRegister = R;
732 /// setExceptionSelectorRegister - If set to a physical register, this sets
733 /// the register that receives the exception typeid on entry to a landing
735 void setExceptionSelectorRegister(unsigned R) {
736 ExceptionSelectorRegister = R;
739 /// SelectIsExpensive - Tells the code generator not to expand operations
740 /// into sequences that use the select operations if possible.
741 void setSelectIsExpensive() { SelectIsExpensive = true; }
743 /// setIntDivIsCheap - Tells the code generator that integer divide is
744 /// expensive, and if possible, should be replaced by an alternate sequence
745 /// of instructions not containing an integer divide.
746 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
748 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
749 /// srl/add/sra for a signed divide by power of two, and let the target handle
751 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
753 /// addRegisterClass - Add the specified register class as an available
754 /// regclass for the specified value type. This indicates the selector can
755 /// handle values of that class natively.
756 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
757 assert(VT < array_lengthof(RegClassForVT));
758 AvailableRegClasses.push_back(std::make_pair(VT, RC));
759 RegClassForVT[VT] = RC;
762 /// computeRegisterProperties - Once all of the register classes are added,
763 /// this allows us to compute derived properties we expose.
764 void computeRegisterProperties();
766 /// setOperationAction - Indicate that the specified operation does not work
767 /// with the specified type and indicate what to do about it.
768 void setOperationAction(unsigned Op, MVT::ValueType VT,
769 LegalizeAction Action) {
770 assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) &&
771 "Table isn't big enough!");
772 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
773 OpActions[Op] |= (uint64_t)Action << VT*2;
776 /// setLoadXAction - Indicate that the specified load with extension does not
777 /// work with the with specified type and indicate what to do about it.
778 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
779 LegalizeAction Action) {
780 assert(VT < sizeof(LoadXActions[0])*4 &&
781 ExtType < array_lengthof(LoadXActions) &&
782 "Table isn't big enough!");
783 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
784 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
787 /// setTruncStoreAction - Indicate that the specified truncating store does
788 /// not work with the with specified type and indicate what to do about it.
789 void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT,
790 LegalizeAction Action) {
791 assert(ValVT < array_lengthof(TruncStoreActions) &&
792 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
793 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
794 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
797 /// setIndexedLoadAction - Indicate that the specified indexed load does or
798 /// does not work with the with specified type and indicate what to do abort
799 /// it. NOTE: All indexed mode loads are initialized to Expand in
800 /// TargetLowering.cpp
801 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
802 LegalizeAction Action) {
803 assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode <
804 array_lengthof(IndexedModeActions[0]) &&
805 "Table isn't big enough!");
806 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
807 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
810 /// setIndexedStoreAction - Indicate that the specified indexed store does or
811 /// does not work with the with specified type and indicate what to do about
812 /// it. NOTE: All indexed mode stores are initialized to Expand in
813 /// TargetLowering.cpp
814 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
815 LegalizeAction Action) {
816 assert(VT < sizeof(IndexedModeActions[1][0])*4 &&
817 IdxMode < array_lengthof(IndexedModeActions[1]) &&
818 "Table isn't big enough!");
819 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
820 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
823 /// setConvertAction - Indicate that the specified conversion does or does
824 /// not work with the with specified type and indicate what to do about it.
825 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
826 LegalizeAction Action) {
827 assert(FromVT < array_lengthof(ConvertActions) &&
828 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
829 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
830 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
833 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
834 /// promotion code defaults to trying a larger integer/fp until it can find
835 /// one that works. If that default is insufficient, this method can be used
836 /// by the target to override the default.
837 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
838 MVT::ValueType DestVT) {
839 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
842 /// addLegalFPImmediate - Indicate that this target can instruction select
843 /// the specified FP immediate natively.
844 void addLegalFPImmediate(const APFloat& Imm) {
845 LegalFPImmediates.push_back(Imm);
848 /// setTargetDAGCombine - Targets should invoke this method for each target
849 /// independent node that they want to provide a custom DAG combiner for by
850 /// implementing the PerformDAGCombine virtual method.
851 void setTargetDAGCombine(ISD::NodeType NT) {
852 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
853 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
856 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
857 /// bytes); default is 200
858 void setJumpBufSize(unsigned Size) {
862 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
863 /// alignment (in bytes); default is 0
864 void setJumpBufAlignment(unsigned Align) {
865 JumpBufAlignment = Align;
868 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
869 /// limit (in number of instructions); default is 2.
870 void setIfCvtBlockSizeLimit(unsigned Limit) {
871 IfCvtBlockSizeLimit = Limit;
874 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
875 /// of instructions) to be considered for code duplication during
876 /// if-conversion; default is 2.
877 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
878 IfCvtDupBlockSizeLimit = Limit;
883 virtual const TargetSubtarget *getSubtarget() {
884 assert(0 && "Not Implemented");
885 return NULL; // this is here to silence compiler errors
887 //===--------------------------------------------------------------------===//
888 // Lowering methods - These methods must be implemented by targets so that
889 // the SelectionDAGLowering code knows how to lower these.
892 /// LowerArguments - This hook must be implemented to indicate how we should
893 /// lower the arguments for the specified function, into the specified DAG.
894 virtual std::vector<SDOperand>
895 LowerArguments(Function &F, SelectionDAG &DAG);
897 /// LowerCallTo - This hook lowers an abstract call to a function into an
898 /// actual call. This returns a pair of operands. The first element is the
899 /// return value for the function (if RetTy is not VoidTy). The second
900 /// element is the outgoing token chain.
901 struct ArgListEntry {
911 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
912 isSRet(false), isNest(false), isByVal(false) { }
914 typedef std::vector<ArgListEntry> ArgListTy;
915 virtual std::pair<SDOperand, SDOperand>
916 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
917 bool isVarArg, unsigned CallingConv, bool isTailCall,
918 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
921 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
922 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest,
923 SDOperand Source, SDOperand Count,
925 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
926 SDOperand Source, unsigned Size,
927 unsigned Align, SelectionDAG &DAG) {
928 assert(0 && "Not Implemented");
929 return SDOperand(); // this is here to silence compiler errors
933 /// LowerOperation - This callback is invoked for operations that are
934 /// unsupported by the target, which are registered to use 'custom' lowering,
935 /// and whose defined values are all legal.
936 /// If the target has no operations that require custom lowering, it need not
937 /// implement this. The default implementation of this aborts.
938 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
940 /// ExpandOperationResult - This callback is invoked for operations that are
941 /// unsupported by the target, which are registered to use 'custom' lowering,
942 /// and whose result type needs to be expanded. This must return a node whose
943 /// results precisely match the results of the input node. This typically
944 /// involves a MERGE_VALUES node and/or BUILD_PAIR.
946 /// If the target has no operations that require custom lowering, it need not
947 /// implement this. The default implementation of this aborts.
948 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
949 assert(0 && "ExpandOperationResult not implemented for this target!");
953 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
954 /// tail call optimization. Targets which want to do tail call optimization
955 /// should override this function.
956 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
958 SelectionDAG &DAG) const {
962 /// CustomPromoteOperation - This callback is invoked for operations that are
963 /// unsupported by the target, are registered to use 'custom' lowering, and
964 /// whose type needs to be promoted.
965 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
967 /// getTargetNodeName() - This method returns the name of a target specific
969 virtual const char *getTargetNodeName(unsigned Opcode) const;
971 //===--------------------------------------------------------------------===//
972 // Inline Asm Support hooks
975 enum ConstraintType {
976 C_Register, // Constraint represents a single register.
977 C_RegisterClass, // Constraint represents one or more registers.
978 C_Memory, // Memory constraint.
979 C_Other, // Something else.
980 C_Unknown // Unsupported constraint.
983 /// getConstraintType - Given a constraint, return the type of constraint it
984 /// is for this target.
985 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
988 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
989 /// return a list of registers that can be used to satisfy the constraint.
990 /// This should only be used for C_RegisterClass constraints.
991 virtual std::vector<unsigned>
992 getRegClassForInlineAsmConstraint(const std::string &Constraint,
993 MVT::ValueType VT) const;
995 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
996 /// {edx}), return the register number and the register class for the
999 /// Given a register class constraint, like 'r', if this corresponds directly
1000 /// to an LLVM register class, return a register of 0 and the register class
1003 /// This should only be used for C_Register constraints. On error,
1004 /// this returns a register number of 0 and a null register class pointer..
1005 virtual std::pair<unsigned, const TargetRegisterClass*>
1006 getRegForInlineAsmConstraint(const std::string &Constraint,
1007 MVT::ValueType VT) const;
1009 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1010 /// with another that has more specific requirements based on the type of the
1011 /// corresponding operand.
1012 virtual void lowerXConstraint(MVT::ValueType ConstraintVT,
1013 std::string&) const;
1015 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1016 /// vector. If it is invalid, don't add anything to Ops.
1017 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
1018 std::vector<SDOperand> &Ops,
1021 //===--------------------------------------------------------------------===//
1025 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
1026 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1027 // instructions are special in various ways, which require special support to
1028 // insert. The specified MachineInstr is created but not inserted into any
1029 // basic blocks, and the scheduler passes ownership of it to this method.
1030 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
1031 MachineBasicBlock *MBB);
1033 //===--------------------------------------------------------------------===//
1034 // Addressing mode description hooks (used by LSR etc).
1037 /// AddrMode - This represents an addressing mode of:
1038 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1039 /// If BaseGV is null, there is no BaseGV.
1040 /// If BaseOffs is zero, there is no base offset.
1041 /// If HasBaseReg is false, there is no base register.
1042 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1046 GlobalValue *BaseGV;
1050 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1053 /// isLegalAddressingMode - Return true if the addressing mode represented by
1054 /// AM is legal for this target, for a load/store of the specified type.
1055 /// TODO: Handle pre/postinc as well.
1056 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1058 /// isTruncateFree - Return true if it's free to truncate a value of
1059 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1060 /// register EAX to i16 by referencing its sub-register AX.
1061 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1065 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const {
1069 //===--------------------------------------------------------------------===//
1070 // Div utility functions
1072 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
1073 std::vector<SDNode*>* Created) const;
1074 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
1075 std::vector<SDNode*>* Created) const;
1078 //===--------------------------------------------------------------------===//
1079 // Runtime Library hooks
1082 /// setLibcallName - Rename the default libcall routine name for the specified
1084 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1085 LibcallRoutineNames[Call] = Name;
1088 /// getLibcallName - Get the libcall routine name for the specified libcall.
1090 const char *getLibcallName(RTLIB::Libcall Call) const {
1091 return LibcallRoutineNames[Call];
1094 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1095 /// result of the comparison libcall against zero.
1096 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1097 CmpLibcallCCs[Call] = CC;
1100 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1101 /// the comparison libcall against zero.
1102 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1103 return CmpLibcallCCs[Call];
1108 const TargetData *TD;
1110 /// IsLittleEndian - True if this is a little endian target.
1112 bool IsLittleEndian;
1114 /// PointerTy - The type to use for pointers, usually i32 or i64.
1116 MVT::ValueType PointerTy;
1118 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1120 bool UsesGlobalOffsetTable;
1122 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1124 MVT::ValueType ShiftAmountTy;
1126 OutOfRangeShiftAmount ShiftAmtHandling;
1128 /// SelectIsExpensive - Tells the code generator not to expand operations
1129 /// into sequences that use the select operations if possible.
1130 bool SelectIsExpensive;
1132 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1133 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1134 /// a real cost model is in place. If we ever optimize for size, this will be
1135 /// set to true unconditionally.
1138 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1139 /// srl/add/sra for a signed divide by power of two, and let the target handle
1141 bool Pow2DivIsCheap;
1143 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
1145 MVT::ValueType SetCCResultTy;
1147 /// SetCCResultContents - Information about the contents of the high-bits in
1148 /// the result of a setcc comparison operation.
1149 SetCCResultValue SetCCResultContents;
1151 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1152 /// total cycles or lowest register usage.
1153 SchedPreference SchedPreferenceInfo;
1155 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1156 /// llvm.setjmp. Defaults to false.
1157 bool UseUnderscoreSetJmp;
1159 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1160 /// llvm.longjmp. Defaults to false.
1161 bool UseUnderscoreLongJmp;
1163 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1164 unsigned JumpBufSize;
1166 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1168 unsigned JumpBufAlignment;
1170 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1172 unsigned IfCvtBlockSizeLimit;
1174 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1175 /// duplicated during if-conversion.
1176 unsigned IfCvtDupBlockSizeLimit;
1178 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1179 /// specifies the register that llvm.savestack/llvm.restorestack should save
1181 unsigned StackPointerRegisterToSaveRestore;
1183 /// ExceptionPointerRegister - If set to a physical register, this specifies
1184 /// the register that receives the exception address on entry to a landing
1186 unsigned ExceptionPointerRegister;
1188 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1189 /// the register that receives the exception typeid on entry to a landing
1191 unsigned ExceptionSelectorRegister;
1193 /// RegClassForVT - This indicates the default register class to use for
1194 /// each ValueType the target supports natively.
1195 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1196 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1197 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1199 /// TransformToType - For any value types we are promoting or expanding, this
1200 /// contains the value type that we are changing to. For Expanded types, this
1201 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1202 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1203 /// by the system, this holds the same type (e.g. i32 -> i32).
1204 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1206 /// OpActions - For each operation and each value type, keep a LegalizeAction
1207 /// that indicates how instruction selection should deal with the operation.
1208 /// Most operations are Legal (aka, supported natively by the target), but
1209 /// operations that are not should be described. Note that operations on
1210 /// non-legal value types are not described here.
1211 uint64_t OpActions[156];
1213 /// LoadXActions - For each load of load extension type and each value type,
1214 /// keep a LegalizeAction that indicates how instruction selection should deal
1216 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1218 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1219 /// indicates how instruction selection should deal with the store.
1220 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1222 /// IndexedModeActions - For each indexed mode and each value type, keep a
1223 /// pair of LegalizeAction that indicates how instruction selection should
1224 /// deal with the load / store.
1225 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1227 /// ConvertActions - For each conversion from source type to destination type,
1228 /// keep a LegalizeAction that indicates how instruction selection should
1229 /// deal with the conversion.
1230 /// Currently, this is used only for floating->floating conversions
1231 /// (FP_EXTEND and FP_ROUND).
1232 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1234 ValueTypeActionImpl ValueTypeActions;
1236 std::vector<APFloat> LegalFPImmediates;
1238 std::vector<std::pair<MVT::ValueType,
1239 TargetRegisterClass*> > AvailableRegClasses;
1241 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1242 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1243 /// which sets a bit in this array.
1244 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1246 /// PromoteToType - For operations that must be promoted to a specific type,
1247 /// this holds the destination type. This map should be sparse, so don't hold
1250 /// Targets add entries to this map with AddPromotedToType(..), clients access
1251 /// this with getTypeToPromoteTo(..).
1252 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1254 /// LibcallRoutineNames - Stores the name each libcall.
1256 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1258 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1259 /// of each of the comparison libcall against zero.
1260 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1263 /// When lowering %llvm.memset this field specifies the maximum number of
1264 /// store operations that may be substituted for the call to memset. Targets
1265 /// must set this value based on the cost threshold for that target. Targets
1266 /// should assume that the memset will be done using as many of the largest
1267 /// store operations first, followed by smaller ones, if necessary, per
1268 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1269 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1270 /// store. This only applies to setting a constant array of a constant size.
1271 /// @brief Specify maximum number of store instructions per memset call.
1272 unsigned maxStoresPerMemset;
1274 /// When lowering %llvm.memcpy this field specifies the maximum number of
1275 /// store operations that may be substituted for a call to memcpy. Targets
1276 /// must set this value based on the cost threshold for that target. Targets
1277 /// should assume that the memcpy will be done using as many of the largest
1278 /// store operations first, followed by smaller ones, if necessary, per
1279 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1280 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1281 /// and one 1-byte store. This only applies to copying a constant array of
1283 /// @brief Specify maximum bytes of store instructions per memcpy call.
1284 unsigned maxStoresPerMemcpy;
1286 /// When lowering %llvm.memmove this field specifies the maximum number of
1287 /// store instructions that may be substituted for a call to memmove. Targets
1288 /// must set this value based on the cost threshold for that target. Targets
1289 /// should assume that the memmove will be done using as many of the largest
1290 /// store operations first, followed by smaller ones, if necessary, per
1291 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1292 /// with 8-bit alignment would result in nine 1-byte stores. This only
1293 /// applies to copying a constant array of constant size.
1294 /// @brief Specify maximum bytes of store instructions per memmove call.
1295 unsigned maxStoresPerMemmove;
1297 /// This field specifies whether the target machine permits unaligned memory
1298 /// accesses. This is used, for example, to determine the size of store
1299 /// operations when copying small arrays and other similar tasks.
1300 /// @brief Indicate whether the target permits unaligned memory accesses.
1301 bool allowUnalignedMemoryAccesses;
1303 } // end llvm namespace