1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/DebugLoc.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFunction;
50 class MachineFrameInfo;
52 class MachineJumpTableInfo;
60 class TargetRegisterClass;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 /// NOTE: The constructor takes ownership of TLOF.
104 explicit TargetLowering(const TargetMachine &TM,
105 const TargetLoweringObjectFile *TLOF);
106 virtual ~TargetLowering();
108 const TargetMachine &getTargetMachine() const { return TM; }
109 const TargetData *getTargetData() const { return TD; }
110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT getPointerTy() const { return PointerTy; }
115 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 /// isSelectExpensive - Return true if the select operation is expensive for
119 bool isSelectExpensive() const { return SelectIsExpensive; }
121 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
122 /// a sequence of several shifts, adds, and multiplies for this target.
123 bool isIntDivCheap() const { return IntDivIsCheap; }
125 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
127 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
129 /// getSetCCResultType - Return the ValueType of the result of SETCC
130 /// operations. Also used to obtain the target's preferred type for
131 /// the condition operand of SELECT and BRCOND nodes. In the case of
132 /// BRCOND the argument passed is MVT::Other since there are no other
133 /// operands to get a type hint from.
135 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
137 /// getCmpLibcallReturnType - Return the ValueType for comparison
138 /// libcalls. Comparions libcalls include floating point comparion calls,
139 /// and Ordered/Unordered check calls on floating point numbers.
141 MVT::SimpleValueType getCmpLibcallReturnType() const;
143 /// getBooleanContents - For targets without i1 registers, this gives the
144 /// nature of the high-bits of boolean values held in types wider than i1.
145 /// "Boolean values" are special true/false values produced by nodes like
146 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
147 /// Not to be confused with general values promoted from i1.
148 BooleanContent getBooleanContents() const { return BooleanContents;}
150 /// getSchedulingPreference - Return target scheduling preference.
151 Sched::Preference getSchedulingPreference() const {
152 return SchedPreferenceInfo;
155 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
156 /// different scheduling heuristics for different nodes. This function returns
157 /// the preference (or none) for the given node.
158 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
162 /// getRegClassFor - Return the register class that should be used for the
163 /// specified value type.
164 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
165 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
166 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
167 assert(RC && "This value type is not natively supported!");
171 /// isTypeLegal - Return true if the target has native support for the
172 /// specified value type. This means that it has a register that directly
173 /// holds it without promotions or expansions.
174 bool isTypeLegal(EVT VT) const {
175 assert(!VT.isSimple() ||
176 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
177 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
180 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
181 /// new operations of this type. All Legal types are synthesizable except
182 /// MMX vector types on X86. Non-Legal types are not synthesizable.
183 bool isTypeSynthesizable(EVT VT) const {
184 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
187 class ValueTypeActionImpl {
188 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
189 /// that indicates how instruction selection should deal with the type.
190 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
192 ValueTypeActionImpl() {
193 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
195 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
196 if (VT.isExtended()) {
198 return VT.isPow2VectorType() ? Expand : Promote;
201 // First promote to a power-of-two size, then expand if necessary.
202 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
203 assert(0 && "Unsupported extended type!");
206 unsigned I = VT.getSimpleVT().SimpleTy;
207 return (LegalizeAction)ValueTypeActions[I];
209 void setTypeAction(EVT VT, LegalizeAction Action) {
210 unsigned I = VT.getSimpleVT().SimpleTy;
211 ValueTypeActions[I] = Action;
215 const ValueTypeActionImpl &getValueTypeActions() const {
216 return ValueTypeActions;
219 /// getTypeAction - Return how we should legalize values of this type, either
220 /// it is already legal (return 'Legal') or we need to promote it to a larger
221 /// type (return 'Promote'), or we need to expand it into multiple registers
222 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
223 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
224 return ValueTypeActions.getTypeAction(Context, VT);
227 /// getTypeToTransformTo - For types supported by the target, this is an
228 /// identity function. For types that must be promoted to larger types, this
229 /// returns the larger type to promote to. For integer types that are larger
230 /// than the largest integer register, this contains one step in the expansion
231 /// to get to the smaller register. For illegal floating point types, this
232 /// returns the integer type to transform to.
233 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
235 assert((unsigned)VT.getSimpleVT().SimpleTy <
236 array_lengthof(TransformToType));
237 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
238 assert(getTypeAction(Context, NVT) != Promote &&
239 "Promote may not follow Expand or Promote");
244 EVT NVT = VT.getPow2VectorType(Context);
246 // Vector length is a power of 2 - split to half the size.
247 unsigned NumElts = VT.getVectorNumElements();
248 EVT EltVT = VT.getVectorElementType();
249 return (NumElts == 1) ?
250 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
252 // Promote to a power of two size, avoiding multi-step promotion.
253 return getTypeAction(Context, NVT) == Promote ?
254 getTypeToTransformTo(Context, NVT) : NVT;
255 } else if (VT.isInteger()) {
256 EVT NVT = VT.getRoundIntegerType(Context);
258 // Size is a power of two - expand to half the size.
259 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
261 // Promote to a power of two size, avoiding multi-step promotion.
262 return getTypeAction(Context, NVT) == Promote ?
263 getTypeToTransformTo(Context, NVT) : NVT;
265 assert(0 && "Unsupported extended type!");
266 return MVT(MVT::Other); // Not reached
269 /// getTypeToExpandTo - For types supported by the target, this is an
270 /// identity function. For types that must be expanded (i.e. integer types
271 /// that are larger than the largest integer register or illegal floating
272 /// point types), this returns the largest legal type it will be expanded to.
273 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
274 assert(!VT.isVector());
276 switch (getTypeAction(Context, VT)) {
280 VT = getTypeToTransformTo(Context, VT);
283 assert(false && "Type is not legal nor is it to be expanded!");
290 /// getVectorTypeBreakdown - Vector types are broken down into some number of
291 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
292 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
293 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
295 /// This method returns the number of registers needed, and the VT for each
296 /// register. It also returns the VT and quantity of the intermediate values
297 /// before they are promoted/expanded.
299 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
301 unsigned &NumIntermediates,
302 EVT &RegisterVT) const;
304 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
305 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
306 /// this is the case, it returns true and store the intrinsic
307 /// information into the IntrinsicInfo that was passed to the function.
308 struct IntrinsicInfo {
309 unsigned opc; // target opcode
310 EVT memVT; // memory VT
311 const Value* ptrVal; // value representing memory location
312 int offset; // offset off of ptrVal
313 unsigned align; // alignment
314 bool vol; // is volatile?
315 bool readMem; // reads memory?
316 bool writeMem; // writes memory?
319 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
320 const CallInst &I, unsigned Intrinsic) const {
324 /// isFPImmLegal - Returns true if the target can instruction select the
325 /// specified FP immediate natively. If false, the legalizer will materialize
326 /// the FP immediate as a load from a constant pool.
327 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
331 /// isShuffleMaskLegal - Targets can use this to indicate that they only
332 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
333 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
334 /// are assumed to be legal.
335 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
340 /// canOpTrap - Returns true if the operation can trap for the value type.
341 /// VT must be a legal type. By default, we optimistically assume most
342 /// operations don't trap except for divide and remainder.
343 virtual bool canOpTrap(unsigned Op, EVT VT) const;
345 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
346 /// used by Targets can use this to indicate if there is a suitable
347 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
349 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
354 /// getOperationAction - Return how this operation should be treated: either
355 /// it is legal, needs to be promoted to a larger size, needs to be
356 /// expanded to some other code sequence, or the target has a custom expander
358 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
359 if (VT.isExtended()) return Expand;
360 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
361 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
362 return (LegalizeAction)OpActions[I][Op];
365 /// isOperationLegalOrCustom - Return true if the specified operation is
366 /// legal on this target or can be made legal with custom lowering. This
367 /// is used to help guide high-level lowering decisions.
368 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
369 return (VT == MVT::Other || isTypeLegal(VT)) &&
370 (getOperationAction(Op, VT) == Legal ||
371 getOperationAction(Op, VT) == Custom);
374 /// isOperationLegal - Return true if the specified operation is legal on this
376 bool isOperationLegal(unsigned Op, EVT VT) const {
377 return (VT == MVT::Other || isTypeLegal(VT)) &&
378 getOperationAction(Op, VT) == Legal;
381 /// getLoadExtAction - Return how this load with extension should be treated:
382 /// either it is legal, needs to be promoted to a larger size, needs to be
383 /// expanded to some other code sequence, or the target has a custom expander
385 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
386 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
387 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
388 "Table isn't big enough!");
389 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
392 /// isLoadExtLegal - Return true if the specified load with extension is legal
394 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
395 return VT.isSimple() &&
396 (getLoadExtAction(ExtType, VT) == Legal ||
397 getLoadExtAction(ExtType, VT) == Custom);
400 /// getTruncStoreAction - Return how this store with truncation should be
401 /// treated: either it is legal, needs to be promoted to a larger size, needs
402 /// to be expanded to some other code sequence, or the target has a custom
404 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
405 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
406 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
407 "Table isn't big enough!");
408 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
409 [MemVT.getSimpleVT().SimpleTy];
412 /// isTruncStoreLegal - Return true if the specified store with truncation is
413 /// legal on this target.
414 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
415 return isTypeLegal(ValVT) && MemVT.isSimple() &&
416 (getTruncStoreAction(ValVT, MemVT) == Legal ||
417 getTruncStoreAction(ValVT, MemVT) == Custom);
420 /// getIndexedLoadAction - Return how the indexed load should be treated:
421 /// either it is legal, needs to be promoted to a larger size, needs to be
422 /// expanded to some other code sequence, or the target has a custom expander
425 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
426 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
427 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
428 "Table isn't big enough!");
429 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
430 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
433 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
435 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
436 return VT.isSimple() &&
437 (getIndexedLoadAction(IdxMode, VT) == Legal ||
438 getIndexedLoadAction(IdxMode, VT) == Custom);
441 /// getIndexedStoreAction - Return how the indexed store should be treated:
442 /// either it is legal, needs to be promoted to a larger size, needs to be
443 /// expanded to some other code sequence, or the target has a custom expander
446 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
447 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
448 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
449 "Table isn't big enough!");
450 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
451 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
454 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
456 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
457 return VT.isSimple() &&
458 (getIndexedStoreAction(IdxMode, VT) == Legal ||
459 getIndexedStoreAction(IdxMode, VT) == Custom);
462 /// getCondCodeAction - Return how the condition code should be treated:
463 /// either it is legal, needs to be expanded to some other code sequence,
464 /// or the target has a custom expander for it.
466 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
467 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
468 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
469 "Table isn't big enough!");
470 LegalizeAction Action = (LegalizeAction)
471 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
472 assert(Action != Promote && "Can't promote condition code!");
476 /// isCondCodeLegal - Return true if the specified condition code is legal
478 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
479 return getCondCodeAction(CC, VT) == Legal ||
480 getCondCodeAction(CC, VT) == Custom;
484 /// getTypeToPromoteTo - If the action for this operation is to promote, this
485 /// method returns the ValueType to promote to.
486 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
487 assert(getOperationAction(Op, VT) == Promote &&
488 "This operation isn't promoted!");
490 // See if this has an explicit type specified.
491 std::map<std::pair<unsigned, MVT::SimpleValueType>,
492 MVT::SimpleValueType>::const_iterator PTTI =
493 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
494 if (PTTI != PromoteToType.end()) return PTTI->second;
496 assert((VT.isInteger() || VT.isFloatingPoint()) &&
497 "Cannot autopromote this type, add it with AddPromotedToType.");
501 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
502 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
503 "Didn't find type to promote to!");
504 } while (!isTypeLegal(NVT) ||
505 getOperationAction(Op, NVT) == Promote);
509 /// getValueType - Return the EVT corresponding to this LLVM type.
510 /// This is fixed by the LLVM operations except for the pointer size. If
511 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
512 /// counterpart (e.g. structs), otherwise it will assert.
513 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
514 EVT VT = EVT::getEVT(Ty, AllowUnknown);
515 return VT == MVT::iPTR ? PointerTy : VT;
518 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
519 /// function arguments in the caller parameter area. This is the actual
520 /// alignment, not its logarithm.
521 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
523 /// getRegisterType - Return the type of registers that this ValueType will
524 /// eventually require.
525 EVT getRegisterType(MVT VT) const {
526 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
527 return RegisterTypeForVT[VT.SimpleTy];
530 /// getRegisterType - Return the type of registers that this ValueType will
531 /// eventually require.
532 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
534 assert((unsigned)VT.getSimpleVT().SimpleTy <
535 array_lengthof(RegisterTypeForVT));
536 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
540 unsigned NumIntermediates;
541 (void)getVectorTypeBreakdown(Context, VT, VT1,
542 NumIntermediates, RegisterVT);
545 if (VT.isInteger()) {
546 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
548 assert(0 && "Unsupported extended type!");
549 return EVT(MVT::Other); // Not reached
552 /// getNumRegisters - Return the number of registers that this ValueType will
553 /// eventually require. This is one for any types promoted to live in larger
554 /// registers, but may be more than one for types (like i64) that are split
555 /// into pieces. For types like i140, which are first promoted then expanded,
556 /// it is the number of registers needed to hold all the bits of the original
557 /// type. For an i140 on a 32 bit machine this means 5 registers.
558 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
560 assert((unsigned)VT.getSimpleVT().SimpleTy <
561 array_lengthof(NumRegistersForVT));
562 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
566 unsigned NumIntermediates;
567 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
569 if (VT.isInteger()) {
570 unsigned BitWidth = VT.getSizeInBits();
571 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
572 return (BitWidth + RegWidth - 1) / RegWidth;
574 assert(0 && "Unsupported extended type!");
575 return 0; // Not reached
578 /// ShouldShrinkFPConstant - If true, then instruction selection should
579 /// seek to shrink the FP constant of the specified type to a smaller type
580 /// in order to save space and / or reduce runtime.
581 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
583 /// hasTargetDAGCombine - If true, the target has custom DAG combine
584 /// transformations that it can perform for the specified node.
585 bool hasTargetDAGCombine(ISD::NodeType NT) const {
586 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
587 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
590 /// This function returns the maximum number of store operations permitted
591 /// to replace a call to llvm.memset. The value is set by the target at the
592 /// performance threshold for such a replacement.
593 /// @brief Get maximum # of store operations permitted for llvm.memset
594 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
596 /// This function returns the maximum number of store operations permitted
597 /// to replace a call to llvm.memcpy. The value is set by the target at the
598 /// performance threshold for such a replacement.
599 /// @brief Get maximum # of store operations permitted for llvm.memcpy
600 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
602 /// This function returns the maximum number of store operations permitted
603 /// to replace a call to llvm.memmove. The value is set by the target at the
604 /// performance threshold for such a replacement.
605 /// @brief Get maximum # of store operations permitted for llvm.memmove
606 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
608 /// This function returns true if the target allows unaligned memory accesses.
609 /// of the specified type. This is used, for example, in situations where an
610 /// array copy/move/set is converted to a sequence of store operations. It's
611 /// use helps to ensure that such replacements don't generate code that causes
612 /// an alignment error (trap) on the target machine.
613 /// @brief Determine if the target supports unaligned memory accesses.
614 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
618 /// This function returns true if the target would benefit from code placement
620 /// @brief Determine if the target should perform code placement optimization.
621 bool shouldOptimizeCodePlacement() const {
622 return benefitFromCodePlacementOpt;
625 /// getOptimalMemOpType - Returns the target specific optimal type for load
626 /// and store operations as a result of memset, memcpy, and memmove
627 /// lowering. If DstAlign is zero that means it's safe to destination
628 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
629 /// means there isn't a need to check it against alignment requirement,
630 /// probably because the source does not need to be loaded. If
631 /// 'NonScalarIntSafe' is true, that means it's safe to return a
632 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
633 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
634 /// constant so it does not need to be loaded.
635 /// It returns EVT::Other if the type should be determined using generic
636 /// target-independent logic.
637 virtual EVT getOptimalMemOpType(uint64_t Size,
638 unsigned DstAlign, unsigned SrcAlign,
639 bool NonScalarIntSafe, bool MemcpyStrSrc,
640 MachineFunction &MF) const {
644 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
645 /// to implement llvm.setjmp.
646 bool usesUnderscoreSetJmp() const {
647 return UseUnderscoreSetJmp;
650 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
651 /// to implement llvm.longjmp.
652 bool usesUnderscoreLongJmp() const {
653 return UseUnderscoreLongJmp;
656 /// getStackPointerRegisterToSaveRestore - If a physical register, this
657 /// specifies the register that llvm.savestack/llvm.restorestack should save
659 unsigned getStackPointerRegisterToSaveRestore() const {
660 return StackPointerRegisterToSaveRestore;
663 /// getExceptionAddressRegister - If a physical register, this returns
664 /// the register that receives the exception address on entry to a landing
666 unsigned getExceptionAddressRegister() const {
667 return ExceptionPointerRegister;
670 /// getExceptionSelectorRegister - If a physical register, this returns
671 /// the register that receives the exception typeid on entry to a landing
673 unsigned getExceptionSelectorRegister() const {
674 return ExceptionSelectorRegister;
677 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
678 /// set, the default is 200)
679 unsigned getJumpBufSize() const {
683 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
684 /// (if never set, the default is 0)
685 unsigned getJumpBufAlignment() const {
686 return JumpBufAlignment;
689 /// getPrefLoopAlignment - return the preferred loop alignment.
691 unsigned getPrefLoopAlignment() const {
692 return PrefLoopAlignment;
695 /// getShouldFoldAtomicFences - return whether the combiner should fold
696 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
698 bool getShouldFoldAtomicFences() const {
699 return ShouldFoldAtomicFences;
702 /// getPreIndexedAddressParts - returns true by value, base pointer and
703 /// offset pointer and addressing mode by reference if the node's address
704 /// can be legally represented as pre-indexed load / store address.
705 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
707 ISD::MemIndexedMode &AM,
708 SelectionDAG &DAG) const {
712 /// getPostIndexedAddressParts - returns true by value, base pointer and
713 /// offset pointer and addressing mode by reference if this node can be
714 /// combined with a load / store to form a post-indexed load / store.
715 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
716 SDValue &Base, SDValue &Offset,
717 ISD::MemIndexedMode &AM,
718 SelectionDAG &DAG) const {
722 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
723 /// current function. The returned value is a member of the
724 /// MachineJumpTableInfo::JTEntryKind enum.
725 virtual unsigned getJumpTableEncoding() const;
727 virtual const MCExpr *
728 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
729 const MachineBasicBlock *MBB, unsigned uid,
730 MCContext &Ctx) const {
731 assert(0 && "Need to implement this hook if target has custom JTIs");
735 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
737 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
738 SelectionDAG &DAG) const;
740 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
741 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
743 virtual const MCExpr *
744 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
745 unsigned JTI, MCContext &Ctx) const;
747 /// isOffsetFoldingLegal - Return true if folding a constant offset
748 /// with the given GlobalAddress is legal. It is frequently not legal in
749 /// PIC relocation models.
750 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
752 /// getFunctionAlignment - Return the Log2 alignment of this function.
753 virtual unsigned getFunctionAlignment(const Function *) const = 0;
755 /// getStackCookieLocation - Return true if the target stores stack
756 /// protector cookies at a fixed offset in some non-standard address
757 /// space, and populates the address space and offset as
759 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
763 //===--------------------------------------------------------------------===//
764 // TargetLowering Optimization Methods
767 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
768 /// SDValues for returning information from TargetLowering to its clients
769 /// that want to combine
770 struct TargetLoweringOpt {
777 explicit TargetLoweringOpt(SelectionDAG &InDAG,
779 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
781 bool LegalTypes() const { return LegalTys; }
782 bool LegalOperations() const { return LegalOps; }
784 bool CombineTo(SDValue O, SDValue N) {
790 /// ShrinkDemandedConstant - Check to see if the specified operand of the
791 /// specified instruction is a constant integer. If so, check to see if
792 /// there are any bits set in the constant that are not demanded. If so,
793 /// shrink the constant and return true.
794 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
796 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
797 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
798 /// cast, but it could be generalized for targets with other types of
799 /// implicit widening casts.
800 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
804 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
805 /// DemandedMask bits of the result of Op are ever used downstream. If we can
806 /// use this information to simplify Op, create a new simplified DAG node and
807 /// return true, returning the original and new nodes in Old and New.
808 /// Otherwise, analyze the expression and return a mask of KnownOne and
809 /// KnownZero bits for the expression (used to simplify the caller).
810 /// The KnownZero/One bits may only be accurate for those bits in the
812 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
813 APInt &KnownZero, APInt &KnownOne,
814 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
816 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
817 /// Mask are known to be either zero or one and return them in the
818 /// KnownZero/KnownOne bitsets.
819 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
823 const SelectionDAG &DAG,
824 unsigned Depth = 0) const;
826 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
827 /// targets that want to expose additional information about sign bits to the
829 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
830 unsigned Depth = 0) const;
832 struct DAGCombinerInfo {
833 void *DC; // The DAG Combiner object.
835 bool BeforeLegalizeOps;
836 bool CalledByLegalizer;
840 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
841 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
842 CalledByLegalizer(cl), DAG(dag) {}
844 bool isBeforeLegalize() const { return BeforeLegalize; }
845 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
846 bool isCalledByLegalizer() const { return CalledByLegalizer; }
848 void AddToWorklist(SDNode *N);
849 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
851 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
852 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
854 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
857 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
858 /// and cc. If it is unable to simplify it, return a null SDValue.
859 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
860 ISD::CondCode Cond, bool foldBooleans,
861 DAGCombinerInfo &DCI, DebugLoc dl) const;
863 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
864 /// node is a GlobalAddress + offset.
866 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
868 /// PerformDAGCombine - This method will be invoked for all target nodes and
869 /// for any target-independent nodes that the target has registered with
872 /// The semantics are as follows:
874 /// SDValue.Val == 0 - No change was made
875 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
876 /// otherwise - N should be replaced by the returned Operand.
878 /// In addition, methods provided by DAGCombinerInfo may be used to perform
879 /// more complex transformations.
881 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
883 /// isTypeDesirableForOp - Return true if the target has native support for
884 /// the specified value type and it is 'desirable' to use the type for the
885 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
886 /// instruction encodings are longer and some i16 instructions are slow.
887 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
888 // By default, assume all legal types are desirable.
889 return isTypeLegal(VT);
892 /// IsDesirableToPromoteOp - This method query the target whether it is
893 /// beneficial for dag combiner to promote the specified node. If true, it
894 /// should return the desired promotion type by reference.
895 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
899 //===--------------------------------------------------------------------===//
900 // TargetLowering Configuration Methods - These methods should be invoked by
901 // the derived class constructor to configure this object for the target.
905 /// setShiftAmountType - Describe the type that should be used for shift
906 /// amounts. This type defaults to the pointer type.
907 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
909 /// setBooleanContents - Specify how the target extends the result of a
910 /// boolean value from i1 to a wider type. See getBooleanContents.
911 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
913 /// setSchedulingPreference - Specify the target scheduling preference.
914 void setSchedulingPreference(Sched::Preference Pref) {
915 SchedPreferenceInfo = Pref;
918 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
919 /// use _setjmp to implement llvm.setjmp or the non _ version.
920 /// Defaults to false.
921 void setUseUnderscoreSetJmp(bool Val) {
922 UseUnderscoreSetJmp = Val;
925 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
926 /// use _longjmp to implement llvm.longjmp or the non _ version.
927 /// Defaults to false.
928 void setUseUnderscoreLongJmp(bool Val) {
929 UseUnderscoreLongJmp = Val;
932 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
933 /// specifies the register that llvm.savestack/llvm.restorestack should save
935 void setStackPointerRegisterToSaveRestore(unsigned R) {
936 StackPointerRegisterToSaveRestore = R;
939 /// setExceptionPointerRegister - If set to a physical register, this sets
940 /// the register that receives the exception address on entry to a landing
942 void setExceptionPointerRegister(unsigned R) {
943 ExceptionPointerRegister = R;
946 /// setExceptionSelectorRegister - If set to a physical register, this sets
947 /// the register that receives the exception typeid on entry to a landing
949 void setExceptionSelectorRegister(unsigned R) {
950 ExceptionSelectorRegister = R;
953 /// SelectIsExpensive - Tells the code generator not to expand operations
954 /// into sequences that use the select operations if possible.
955 void setSelectIsExpensive() { SelectIsExpensive = true; }
957 /// setIntDivIsCheap - Tells the code generator that integer divide is
958 /// expensive, and if possible, should be replaced by an alternate sequence
959 /// of instructions not containing an integer divide.
960 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
962 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
963 /// srl/add/sra for a signed divide by power of two, and let the target handle
965 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
967 /// addRegisterClass - Add the specified register class as an available
968 /// regclass for the specified value type. This indicates the selector can
969 /// handle values of that class natively.
970 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
971 bool isSynthesizable = true) {
972 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
973 AvailableRegClasses.push_back(std::make_pair(VT, RC));
974 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
975 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
978 /// computeRegisterProperties - Once all of the register classes are added,
979 /// this allows us to compute derived properties we expose.
980 void computeRegisterProperties();
982 /// setOperationAction - Indicate that the specified operation does not work
983 /// with the specified type and indicate what to do about it.
984 void setOperationAction(unsigned Op, MVT VT,
985 LegalizeAction Action) {
986 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
987 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
990 /// setLoadExtAction - Indicate that the specified load with extension does
991 /// not work with the specified type and indicate what to do about it.
992 void setLoadExtAction(unsigned ExtType, MVT VT,
993 LegalizeAction Action) {
994 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
995 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
996 "Table isn't big enough!");
997 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1000 /// setTruncStoreAction - Indicate that the specified truncating store does
1001 /// not work with the specified type and indicate what to do about it.
1002 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1003 LegalizeAction Action) {
1004 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1005 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1006 "Table isn't big enough!");
1007 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1010 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1011 /// does not work with the specified type and indicate what to do abort
1012 /// it. NOTE: All indexed mode loads are initialized to Expand in
1013 /// TargetLowering.cpp
1014 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1015 LegalizeAction Action) {
1016 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1017 IdxMode < ISD::LAST_INDEXED_MODE &&
1018 (unsigned)Action < 0xf &&
1019 "Table isn't big enough!");
1020 // Load action are kept in the upper half.
1021 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1022 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1025 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1026 /// does not work with the specified type and indicate what to do about
1027 /// it. NOTE: All indexed mode stores are initialized to Expand in
1028 /// TargetLowering.cpp
1029 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1030 LegalizeAction Action) {
1031 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1032 IdxMode < ISD::LAST_INDEXED_MODE &&
1033 (unsigned)Action < 0xf &&
1034 "Table isn't big enough!");
1035 // Store action are kept in the lower half.
1036 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1037 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1040 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1041 /// supported on the target and indicate what to do about it.
1042 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1043 LegalizeAction Action) {
1044 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1045 (unsigned)CC < array_lengthof(CondCodeActions) &&
1046 "Table isn't big enough!");
1047 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1048 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1051 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1052 /// promotion code defaults to trying a larger integer/fp until it can find
1053 /// one that works. If that default is insufficient, this method can be used
1054 /// by the target to override the default.
1055 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1056 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1059 /// setTargetDAGCombine - Targets should invoke this method for each target
1060 /// independent node that they want to provide a custom DAG combiner for by
1061 /// implementing the PerformDAGCombine virtual method.
1062 void setTargetDAGCombine(ISD::NodeType NT) {
1063 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1064 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1067 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1068 /// bytes); default is 200
1069 void setJumpBufSize(unsigned Size) {
1073 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1074 /// alignment (in bytes); default is 0
1075 void setJumpBufAlignment(unsigned Align) {
1076 JumpBufAlignment = Align;
1079 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1080 /// alignment is zero, it means the target does not care about loop alignment.
1081 void setPrefLoopAlignment(unsigned Align) {
1082 PrefLoopAlignment = Align;
1085 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1086 /// atomic operation intrinsics includes locking. Default is false.
1087 void setShouldFoldAtomicFences(bool fold) {
1088 ShouldFoldAtomicFences = fold;
1092 //===--------------------------------------------------------------------===//
1093 // Lowering methods - These methods must be implemented by targets so that
1094 // the SelectionDAGLowering code knows how to lower these.
1097 /// LowerFormalArguments - This hook must be implemented to lower the
1098 /// incoming (formal) arguments, described by the Ins array, into the
1099 /// specified DAG. The implementation should fill in the InVals array
1100 /// with legal-type argument values, and return the resulting token
1104 LowerFormalArguments(SDValue Chain,
1105 CallingConv::ID CallConv, bool isVarArg,
1106 const SmallVectorImpl<ISD::InputArg> &Ins,
1107 DebugLoc dl, SelectionDAG &DAG,
1108 SmallVectorImpl<SDValue> &InVals) const {
1109 assert(0 && "Not Implemented");
1110 return SDValue(); // this is here to silence compiler errors
1113 /// LowerCallTo - This function lowers an abstract call to a function into an
1114 /// actual call. This returns a pair of operands. The first element is the
1115 /// return value for the function (if RetTy is not VoidTy). The second
1116 /// element is the outgoing token chain. It calls LowerCall to do the actual
1118 struct ArgListEntry {
1129 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1130 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1132 typedef std::vector<ArgListEntry> ArgListTy;
1133 std::pair<SDValue, SDValue>
1134 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1135 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1136 CallingConv::ID CallConv, bool isTailCall,
1137 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1138 SelectionDAG &DAG, DebugLoc dl) const;
1140 /// LowerCall - This hook must be implemented to lower calls into the
1141 /// the specified DAG. The outgoing arguments to the call are described
1142 /// by the Outs array, and the values to be returned by the call are
1143 /// described by the Ins array. The implementation should fill in the
1144 /// InVals array with legal-type return values from the call, and return
1145 /// the resulting token chain value.
1147 LowerCall(SDValue Chain, SDValue Callee,
1148 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1149 const SmallVectorImpl<ISD::OutputArg> &Outs,
1150 const SmallVectorImpl<SDValue> &OutVals,
1151 const SmallVectorImpl<ISD::InputArg> &Ins,
1152 DebugLoc dl, SelectionDAG &DAG,
1153 SmallVectorImpl<SDValue> &InVals) const {
1154 assert(0 && "Not Implemented");
1155 return SDValue(); // this is here to silence compiler errors
1158 /// CanLowerReturn - This hook should be implemented to check whether the
1159 /// return values described by the Outs array can fit into the return
1160 /// registers. If false is returned, an sret-demotion is performed.
1162 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1163 const SmallVectorImpl<ISD::OutputArg> &Outs,
1164 LLVMContext &Context) const
1166 // Return true by default to get preexisting behavior.
1170 /// LowerReturn - This hook must be implemented to lower outgoing
1171 /// return values, described by the Outs array, into the specified
1172 /// DAG. The implementation should return the resulting token chain
1176 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1177 const SmallVectorImpl<ISD::OutputArg> &Outs,
1178 const SmallVectorImpl<SDValue> &OutVals,
1179 DebugLoc dl, SelectionDAG &DAG) const {
1180 assert(0 && "Not Implemented");
1181 return SDValue(); // this is here to silence compiler errors
1184 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1185 /// to legalize nodes with an illegal operand type but legal result types.
1186 /// It replaces the LowerOperation callback in the type Legalizer.
1187 /// The reason we can not do away with LowerOperation entirely is that
1188 /// LegalizeDAG isn't yet ready to use this callback.
1189 /// TODO: Consider merging with ReplaceNodeResults.
1191 /// The target places new result values for the node in Results (their number
1192 /// and types must exactly match those of the original return values of
1193 /// the node), or leaves Results empty, which indicates that the node is not
1194 /// to be custom lowered after all.
1195 /// The default implementation calls LowerOperation.
1196 virtual void LowerOperationWrapper(SDNode *N,
1197 SmallVectorImpl<SDValue> &Results,
1198 SelectionDAG &DAG) const;
1200 /// LowerOperation - This callback is invoked for operations that are
1201 /// unsupported by the target, which are registered to use 'custom' lowering,
1202 /// and whose defined values are all legal.
1203 /// If the target has no operations that require custom lowering, it need not
1204 /// implement this. The default implementation of this aborts.
1205 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1207 /// ReplaceNodeResults - This callback is invoked when a node result type is
1208 /// illegal for the target, and the operation was registered to use 'custom'
1209 /// lowering for that result type. The target places new result values for
1210 /// the node in Results (their number and types must exactly match those of
1211 /// the original return values of the node), or leaves Results empty, which
1212 /// indicates that the node is not to be custom lowered after all.
1214 /// If the target has no operations that require custom lowering, it need not
1215 /// implement this. The default implementation aborts.
1216 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1217 SelectionDAG &DAG) const {
1218 assert(0 && "ReplaceNodeResults not implemented for this target!");
1221 /// getTargetNodeName() - This method returns the name of a target specific
1223 virtual const char *getTargetNodeName(unsigned Opcode) const;
1225 /// createFastISel - This method returns a target specific FastISel object,
1226 /// or null if the target does not support "fast" ISel.
1227 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1231 //===--------------------------------------------------------------------===//
1232 // Inline Asm Support hooks
1235 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1236 /// call to be explicit llvm code if it wants to. This is useful for
1237 /// turning simple inline asms into LLVM intrinsics, which gives the
1238 /// compiler more information about the behavior of the code.
1239 virtual bool ExpandInlineAsm(CallInst *CI) const {
1243 enum ConstraintType {
1244 C_Register, // Constraint represents specific register(s).
1245 C_RegisterClass, // Constraint represents any of register(s) in class.
1246 C_Memory, // Memory constraint.
1247 C_Other, // Something else.
1248 C_Unknown // Unsupported constraint.
1251 /// AsmOperandInfo - This contains information for each constraint that we are
1253 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1254 /// ConstraintCode - This contains the actual string for the code, like "m".
1255 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1256 /// most closely matches the operand.
1257 std::string ConstraintCode;
1259 /// ConstraintType - Information about the constraint code, e.g. Register,
1260 /// RegisterClass, Memory, Other, Unknown.
1261 TargetLowering::ConstraintType ConstraintType;
1263 /// CallOperandval - If this is the result output operand or a
1264 /// clobber, this is null, otherwise it is the incoming operand to the
1265 /// CallInst. This gets modified as the asm is processed.
1266 Value *CallOperandVal;
1268 /// ConstraintVT - The ValueType for the operand value.
1271 /// isMatchingInputConstraint - Return true of this is an input operand that
1272 /// is a matching constraint like "4".
1273 bool isMatchingInputConstraint() const;
1275 /// getMatchedOperand - If this is an input matching constraint, this method
1276 /// returns the output operand it matches.
1277 unsigned getMatchedOperand() const;
1279 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1280 : InlineAsm::ConstraintInfo(info),
1281 ConstraintType(TargetLowering::C_Unknown),
1282 CallOperandVal(0), ConstraintVT(MVT::Other) {
1286 /// ComputeConstraintToUse - Determines the constraint code and constraint
1287 /// type to use for the specific AsmOperandInfo, setting
1288 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1289 /// being passed in is available, it can be passed in as Op, otherwise an
1290 /// empty SDValue can be passed.
1291 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1293 SelectionDAG *DAG = 0) const;
1295 /// getConstraintType - Given a constraint, return the type of constraint it
1296 /// is for this target.
1297 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1299 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1300 /// return a list of registers that can be used to satisfy the constraint.
1301 /// This should only be used for C_RegisterClass constraints.
1302 virtual std::vector<unsigned>
1303 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1306 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1307 /// {edx}), return the register number and the register class for the
1310 /// Given a register class constraint, like 'r', if this corresponds directly
1311 /// to an LLVM register class, return a register of 0 and the register class
1314 /// This should only be used for C_Register constraints. On error,
1315 /// this returns a register number of 0 and a null register class pointer..
1316 virtual std::pair<unsigned, const TargetRegisterClass*>
1317 getRegForInlineAsmConstraint(const std::string &Constraint,
1320 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1321 /// with another that has more specific requirements based on the type of the
1322 /// corresponding operand. This returns null if there is no replacement to
1324 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1326 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1327 /// vector. If it is invalid, don't add anything to Ops.
1328 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1329 std::vector<SDValue> &Ops,
1330 SelectionDAG &DAG) const;
1332 //===--------------------------------------------------------------------===//
1333 // Instruction Emitting Hooks
1336 // EmitInstrWithCustomInserter - This method should be implemented by targets
1337 // that mark instructions with the 'usesCustomInserter' flag. These
1338 // instructions are special in various ways, which require special support to
1339 // insert. The specified MachineInstr is created but not inserted into any
1340 // basic blocks, and this method is called to expand it into a sequence of
1341 // instructions, potentially also creating new basic blocks and control flow.
1342 virtual MachineBasicBlock *
1343 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1345 //===--------------------------------------------------------------------===//
1346 // Addressing mode description hooks (used by LSR etc).
1349 /// AddrMode - This represents an addressing mode of:
1350 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1351 /// If BaseGV is null, there is no BaseGV.
1352 /// If BaseOffs is zero, there is no base offset.
1353 /// If HasBaseReg is false, there is no base register.
1354 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1358 GlobalValue *BaseGV;
1362 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1365 /// isLegalAddressingMode - Return true if the addressing mode represented by
1366 /// AM is legal for this target, for a load/store of the specified type.
1367 /// The type may be VoidTy, in which case only return true if the addressing
1368 /// mode is legal for a load/store of any legal type.
1369 /// TODO: Handle pre/postinc as well.
1370 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1372 /// isTruncateFree - Return true if it's free to truncate a value of
1373 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1374 /// register EAX to i16 by referencing its sub-register AX.
1375 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1379 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1383 /// isZExtFree - Return true if any actual instruction that defines a
1384 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1385 /// register. This does not necessarily include registers defined in
1386 /// unknown ways, such as incoming arguments, or copies from unknown
1387 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1388 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1389 /// all instructions that define 32-bit values implicit zero-extend the
1390 /// result out to 64 bits.
1391 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1395 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1399 /// isNarrowingProfitable - Return true if it's profitable to narrow
1400 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1401 /// from i32 to i8 but not from i32 to i16.
1402 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1406 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1407 /// icmp immediate, that is the target has icmp instructions which can compare
1408 /// a register against the immediate without having to materialize the
1409 /// immediate into a register.
1410 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1414 //===--------------------------------------------------------------------===//
1415 // Div utility functions
1417 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1418 std::vector<SDNode*>* Created) const;
1419 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1420 std::vector<SDNode*>* Created) const;
1423 //===--------------------------------------------------------------------===//
1424 // Runtime Library hooks
1427 /// setLibcallName - Rename the default libcall routine name for the specified
1429 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1430 LibcallRoutineNames[Call] = Name;
1433 /// getLibcallName - Get the libcall routine name for the specified libcall.
1435 const char *getLibcallName(RTLIB::Libcall Call) const {
1436 return LibcallRoutineNames[Call];
1439 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1440 /// result of the comparison libcall against zero.
1441 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1442 CmpLibcallCCs[Call] = CC;
1445 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1446 /// the comparison libcall against zero.
1447 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1448 return CmpLibcallCCs[Call];
1451 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1452 /// specified libcall.
1453 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1454 LibcallCallingConvs[Call] = CC;
1457 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1458 /// specified libcall.
1459 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1460 return LibcallCallingConvs[Call];
1464 const TargetMachine &TM;
1465 const TargetData *TD;
1466 const TargetLoweringObjectFile &TLOF;
1468 /// PointerTy - The type to use for pointers, usually i32 or i64.
1472 /// IsLittleEndian - True if this is a little endian target.
1474 bool IsLittleEndian;
1476 /// SelectIsExpensive - Tells the code generator not to expand operations
1477 /// into sequences that use the select operations if possible.
1478 bool SelectIsExpensive;
1480 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1481 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1482 /// a real cost model is in place. If we ever optimize for size, this will be
1483 /// set to true unconditionally.
1486 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1487 /// srl/add/sra for a signed divide by power of two, and let the target handle
1489 bool Pow2DivIsCheap;
1491 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1492 /// llvm.setjmp. Defaults to false.
1493 bool UseUnderscoreSetJmp;
1495 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1496 /// llvm.longjmp. Defaults to false.
1497 bool UseUnderscoreLongJmp;
1499 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1503 /// BooleanContents - Information about the contents of the high-bits in
1504 /// boolean values held in a type wider than i1. See getBooleanContents.
1505 BooleanContent BooleanContents;
1507 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1508 /// total cycles or lowest register usage.
1509 Sched::Preference SchedPreferenceInfo;
1511 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1512 unsigned JumpBufSize;
1514 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1516 unsigned JumpBufAlignment;
1518 /// PrefLoopAlignment - The perferred loop alignment.
1520 unsigned PrefLoopAlignment;
1522 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1523 /// be folded into the enclosed atomic intrinsic instruction by the
1525 bool ShouldFoldAtomicFences;
1527 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1528 /// specifies the register that llvm.savestack/llvm.restorestack should save
1530 unsigned StackPointerRegisterToSaveRestore;
1532 /// ExceptionPointerRegister - If set to a physical register, this specifies
1533 /// the register that receives the exception address on entry to a landing
1535 unsigned ExceptionPointerRegister;
1537 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1538 /// the register that receives the exception typeid on entry to a landing
1540 unsigned ExceptionSelectorRegister;
1542 /// RegClassForVT - This indicates the default register class to use for
1543 /// each ValueType the target supports natively.
1544 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1545 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1546 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1548 /// Synthesizable indicates whether it is OK for the compiler to create new
1549 /// operations using this type. All Legal types are Synthesizable except
1550 /// MMX types on X86. Non-Legal types are not Synthesizable.
1551 bool Synthesizable[MVT::LAST_VALUETYPE];
1553 /// TransformToType - For any value types we are promoting or expanding, this
1554 /// contains the value type that we are changing to. For Expanded types, this
1555 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1556 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1557 /// by the system, this holds the same type (e.g. i32 -> i32).
1558 EVT TransformToType[MVT::LAST_VALUETYPE];
1560 /// OpActions - For each operation and each value type, keep a LegalizeAction
1561 /// that indicates how instruction selection should deal with the operation.
1562 /// Most operations are Legal (aka, supported natively by the target), but
1563 /// operations that are not should be described. Note that operations on
1564 /// non-legal value types are not described here.
1565 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1567 /// LoadExtActions - For each load extension type and each value type,
1568 /// keep a LegalizeAction that indicates how instruction selection should deal
1569 /// with a load of a specific value type and extension type.
1570 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1572 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1573 /// indicates whether a truncating store of a specific value type and
1574 /// truncating type is legal.
1575 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1577 /// IndexedModeActions - For each indexed mode and each value type,
1578 /// keep a pair of LegalizeAction that indicates how instruction
1579 /// selection should deal with the load / store. The first dimension is the
1580 /// value_type for the reference. The second dimension represents the various
1581 /// modes for load store.
1582 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1584 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1585 /// LegalizeAction that indicates how instruction selection should
1586 /// deal with the condition code.
1587 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1589 ValueTypeActionImpl ValueTypeActions;
1591 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1593 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1594 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1595 /// which sets a bit in this array.
1597 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1599 /// PromoteToType - For operations that must be promoted to a specific type,
1600 /// this holds the destination type. This map should be sparse, so don't hold
1603 /// Targets add entries to this map with AddPromotedToType(..), clients access
1604 /// this with getTypeToPromoteTo(..).
1605 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1608 /// LibcallRoutineNames - Stores the name each libcall.
1610 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1612 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1613 /// of each of the comparison libcall against zero.
1614 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1616 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1618 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1621 /// When lowering \@llvm.memset this field specifies the maximum number of
1622 /// store operations that may be substituted for the call to memset. Targets
1623 /// must set this value based on the cost threshold for that target. Targets
1624 /// should assume that the memset will be done using as many of the largest
1625 /// store operations first, followed by smaller ones, if necessary, per
1626 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1627 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1628 /// store. This only applies to setting a constant array of a constant size.
1629 /// @brief Specify maximum number of store instructions per memset call.
1630 unsigned maxStoresPerMemset;
1632 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1633 /// store operations that may be substituted for a call to memcpy. Targets
1634 /// must set this value based on the cost threshold for that target. Targets
1635 /// should assume that the memcpy will be done using as many of the largest
1636 /// store operations first, followed by smaller ones, if necessary, per
1637 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1638 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1639 /// and one 1-byte store. This only applies to copying a constant array of
1641 /// @brief Specify maximum bytes of store instructions per memcpy call.
1642 unsigned maxStoresPerMemcpy;
1644 /// When lowering \@llvm.memmove this field specifies the maximum number of
1645 /// store instructions that may be substituted for a call to memmove. Targets
1646 /// must set this value based on the cost threshold for that target. Targets
1647 /// should assume that the memmove will be done using as many of the largest
1648 /// store operations first, followed by smaller ones, if necessary, per
1649 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1650 /// with 8-bit alignment would result in nine 1-byte stores. This only
1651 /// applies to copying a constant array of constant size.
1652 /// @brief Specify maximum bytes of store instructions per memmove call.
1653 unsigned maxStoresPerMemmove;
1655 /// This field specifies whether the target can benefit from code placement
1657 bool benefitFromCodePlacementOpt;
1660 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1661 /// compute the return value EVTs and flags, and optionally also
1662 /// the offsets, if the return value is being lowered to memory.
1663 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1664 SmallVectorImpl<ISD::OutputArg> &Outs,
1665 const TargetLowering &TLI,
1666 SmallVectorImpl<uint64_t> *Offsets = 0);
1668 } // end llvm namespace