1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/InlineAsm.h"
33 #include "llvm/Support/CallSite.h"
34 #include "llvm/Target/TargetCallingConv.h"
35 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
47 class MachineBasicBlock;
48 class MachineFunction;
50 class MachineJumpTableInfo;
53 template<typename T> class SmallVectorImpl;
55 class TargetRegisterClass;
56 class TargetLibraryInfo;
57 class TargetLoweringObjectFile;
62 None, // No preference
63 Source, // Follow source order.
64 RegPressure, // Scheduling for lowest register pressure.
65 Hybrid, // Scheduling for both latency and register pressure.
66 ILP, // Scheduling for ILP in low register pressure mode.
67 VLIW // Scheduling for VLIW targets.
71 /// This base class for TargetLowering contains the SelectionDAG-independent
72 /// parts that can be used from the rest of CodeGen.
73 class TargetLoweringBase {
74 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
75 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
78 /// This enum indicates whether operations are valid for a target, and if not,
79 /// what action should be used to make them valid.
81 Legal, // The target natively supports this operation.
82 Promote, // This operation should be executed in a larger type.
83 Expand, // Try to expand this to other ops, otherwise use a libcall.
84 Custom // Use the LowerOperation hook to implement custom lowering.
87 /// This enum indicates whether a types are legal for a target, and if not,
88 /// what action should be used to make them valid.
89 enum LegalizeTypeAction {
90 TypeLegal, // The target natively supports this type.
91 TypePromoteInteger, // Replace this integer with a larger one.
92 TypeExpandInteger, // Split this integer into two of half the size.
93 TypeSoftenFloat, // Convert this float to a same size integer type.
94 TypeExpandFloat, // Split this float into two of half the size.
95 TypeScalarizeVector, // Replace this one-element vector with its element.
96 TypeSplitVector, // Split this vector into two of half the size.
97 TypeWidenVector // This vector should be widened into a larger vector.
100 /// LegalizeKind holds the legalization kind that needs to happen to EVT
101 /// in order to type-legalize it.
102 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
104 /// Enum that describes how the target represents true/false values.
105 enum BooleanContent {
106 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
107 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
108 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
111 /// Enum that describes what type of support for selects the target has.
112 enum SelectSupportKind {
113 ScalarValSelect, // The target supports scalar selects (ex: cmov).
114 ScalarCondVectorVal, // The target supports selects with a scalar condition
115 // and vector values (ex: cmov).
116 VectorMaskSelect // The target supports vector selects with a vector
117 // mask (ex: x86 blends).
120 static ISD::NodeType getExtendForContent(BooleanContent Content) {
122 case UndefinedBooleanContent:
123 // Extend by adding rubbish bits.
124 return ISD::ANY_EXTEND;
125 case ZeroOrOneBooleanContent:
126 // Extend by adding zero bits.
127 return ISD::ZERO_EXTEND;
128 case ZeroOrNegativeOneBooleanContent:
129 // Extend by copying the sign bit.
130 return ISD::SIGN_EXTEND;
132 llvm_unreachable("Invalid content kind");
135 /// NOTE: The constructor takes ownership of TLOF.
136 explicit TargetLoweringBase(const TargetMachine &TM,
137 const TargetLoweringObjectFile *TLOF);
138 virtual ~TargetLoweringBase();
141 /// \brief Initialize all of the actions to default values.
145 const TargetMachine &getTargetMachine() const { return TM; }
146 const DataLayout *getDataLayout() const { return DL; }
147 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
149 bool isBigEndian() const { return !IsLittleEndian; }
150 bool isLittleEndian() const { return IsLittleEndian; }
152 /// Return the pointer type for the given address space, defaults to
153 /// the pointer type from the data layout.
154 /// FIXME: The default needs to be removed once all the code is updated.
155 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
156 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
157 unsigned getPointerTypeSizeInBits(Type *Ty) const;
158 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
160 EVT getShiftAmountTy(EVT LHSTy) const;
162 /// Returns the type to be used for the index operand of:
163 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
164 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
165 virtual MVT getVectorIdxTy() const {
166 return getPointerTy();
169 /// Return true if the select operation is expensive for this target.
170 bool isSelectExpensive() const { return SelectIsExpensive; }
172 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
176 /// Return true if multiple condition registers are available.
177 bool hasMultipleConditionRegisters() const {
178 return HasMultipleConditionRegisters;
181 /// Return true if a vector of the given type should be split
182 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
184 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
186 /// Return true if integer divide is usually cheaper than a sequence of
187 /// several shifts, adds, and multiplies for this target.
188 bool isIntDivCheap() const { return IntDivIsCheap; }
190 /// Returns true if target has indicated at least one type should be bypassed.
191 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
193 /// Returns map of slow types for division or remainder with corresponding
195 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
196 return BypassSlowDivWidths;
199 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
200 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
202 /// Return true if Flow Control is an expensive operation that should be
204 bool isJumpExpensive() const { return JumpIsExpensive; }
206 /// Return true if selects are only cheaper than branches if the branch is
207 /// unlikely to be predicted right.
208 bool isPredictableSelectExpensive() const {
209 return PredictableSelectIsExpensive;
212 /// isLoadBitCastBeneficial() - Return true if the following transform
214 /// fold (conv (load x)) -> (load (conv*)x)
215 /// On architectures that don't natively support some vector loads efficiently,
216 /// casting the load to a smaller vector of larger types and loading
217 /// is more efficient, however, this can be undone by optimizations in
219 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
223 /// Return the ValueType of the result of SETCC operations. Also used to
224 /// obtain the target's preferred type for the condition operand of SELECT and
225 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
226 /// since there are no other operands to get a type hint from.
227 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
229 /// Return the ValueType for comparison libcalls. Comparions libcalls include
230 /// floating point comparion calls, and Ordered/Unordered check calls on
231 /// floating point numbers.
233 MVT::SimpleValueType getCmpLibcallReturnType() const;
235 /// For targets without i1 registers, this gives the nature of the high-bits
236 /// of boolean values held in types wider than i1.
238 /// "Boolean values" are special true/false values produced by nodes like
239 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
240 /// Not to be confused with general values promoted from i1. Some cpus
241 /// distinguish between vectors of boolean and scalars; the isVec parameter
242 /// selects between the two kinds. For example on X86 a scalar boolean should
243 /// be zero extended from i1, while the elements of a vector of booleans
244 /// should be sign extended from i1.
245 BooleanContent getBooleanContents(bool isVec) const {
246 return isVec ? BooleanVectorContents : BooleanContents;
249 /// Return target scheduling preference.
250 Sched::Preference getSchedulingPreference() const {
251 return SchedPreferenceInfo;
254 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
255 /// for different nodes. This function returns the preference (or none) for
257 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
261 /// Return the register class that should be used for the specified value
263 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
264 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
265 assert(RC && "This value type is not natively supported!");
269 /// Return the 'representative' register class for the specified value
272 /// The 'representative' register class is the largest legal super-reg
273 /// register class for the register class of the value type. For example, on
274 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
275 /// register class is GR64 on x86_64.
276 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
277 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
281 /// Return the cost of the 'representative' register class for the specified
283 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
284 return RepRegClassCostForVT[VT.SimpleTy];
287 /// Return true if the target has native support for the specified value type.
288 /// This means that it has a register that directly holds it without
289 /// promotions or expansions.
290 bool isTypeLegal(EVT VT) const {
291 assert(!VT.isSimple() ||
292 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
293 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
296 class ValueTypeActionImpl {
297 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
298 /// that indicates how instruction selection should deal with the type.
299 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
302 ValueTypeActionImpl() {
303 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
306 LegalizeTypeAction getTypeAction(MVT VT) const {
307 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
310 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
311 unsigned I = VT.SimpleTy;
312 ValueTypeActions[I] = Action;
316 const ValueTypeActionImpl &getValueTypeActions() const {
317 return ValueTypeActions;
320 /// Return how we should legalize values of this type, either it is already
321 /// legal (return 'Legal') or we need to promote it to a larger type (return
322 /// 'Promote'), or we need to expand it into multiple registers of smaller
323 /// integer type (return 'Expand'). 'Custom' is not an option.
324 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
325 return getTypeConversion(Context, VT).first;
327 LegalizeTypeAction getTypeAction(MVT VT) const {
328 return ValueTypeActions.getTypeAction(VT);
331 /// For types supported by the target, this is an identity function. For
332 /// types that must be promoted to larger types, this returns the larger type
333 /// to promote to. For integer types that are larger than the largest integer
334 /// register, this contains one step in the expansion to get to the smaller
335 /// register. For illegal floating point types, this returns the integer type
337 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
338 return getTypeConversion(Context, VT).second;
341 /// For types supported by the target, this is an identity function. For
342 /// types that must be expanded (i.e. integer types that are larger than the
343 /// largest integer register or illegal floating point types), this returns
344 /// the largest legal type it will be expanded to.
345 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
346 assert(!VT.isVector());
348 switch (getTypeAction(Context, VT)) {
351 case TypeExpandInteger:
352 VT = getTypeToTransformTo(Context, VT);
355 llvm_unreachable("Type is not legal nor is it to be expanded!");
360 /// Vector types are broken down into some number of legal first class types.
361 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
362 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
363 /// turns into 4 EVT::i32 values with both PPC and X86.
365 /// This method returns the number of registers needed, and the VT for each
366 /// register. It also returns the VT and quantity of the intermediate values
367 /// before they are promoted/expanded.
368 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
370 unsigned &NumIntermediates,
371 MVT &RegisterVT) const;
373 struct IntrinsicInfo {
374 unsigned opc; // target opcode
375 EVT memVT; // memory VT
376 const Value* ptrVal; // value representing memory location
377 int offset; // offset off of ptrVal
378 unsigned align; // alignment
379 bool vol; // is volatile?
380 bool readMem; // reads memory?
381 bool writeMem; // writes memory?
384 /// Given an intrinsic, checks if on the target the intrinsic will need to map
385 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
386 /// true and store the intrinsic information into the IntrinsicInfo that was
387 /// passed to the function.
388 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
389 unsigned /*Intrinsic*/) const {
393 /// Returns true if the target can instruction select the specified FP
394 /// immediate natively. If false, the legalizer will materialize the FP
395 /// immediate as a load from a constant pool.
396 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
400 /// Targets can use this to indicate that they only support *some*
401 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
402 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
404 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
409 /// Returns true if the operation can trap for the value type.
411 /// VT must be a legal type. By default, we optimistically assume most
412 /// operations don't trap except for divide and remainder.
413 virtual bool canOpTrap(unsigned Op, EVT VT) const;
415 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
416 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
417 /// a VAND with a constant pool entry.
418 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
423 /// Return how this operation should be treated: either it is legal, needs to
424 /// be promoted to a larger size, needs to be expanded to some other code
425 /// sequence, or the target has a custom expander for it.
426 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
427 if (VT.isExtended()) return Expand;
428 // If a target-specific SDNode requires legalization, require the target
429 // to provide custom legalization for it.
430 if (Op > array_lengthof(OpActions[0])) return Custom;
431 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
432 return (LegalizeAction)OpActions[I][Op];
435 /// Return true if the specified operation is legal on this target or can be
436 /// made legal with custom lowering. This is used to help guide high-level
437 /// lowering decisions.
438 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
439 return (VT == MVT::Other || isTypeLegal(VT)) &&
440 (getOperationAction(Op, VT) == Legal ||
441 getOperationAction(Op, VT) == Custom);
444 /// Return true if the specified operation is legal on this target or can be
445 /// made legal using promotion. This is used to help guide high-level lowering
447 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
448 return (VT == MVT::Other || isTypeLegal(VT)) &&
449 (getOperationAction(Op, VT) == Legal ||
450 getOperationAction(Op, VT) == Promote);
453 /// Return true if the specified operation is illegal on this target or
454 /// unlikely to be made legal with custom lowering. This is used to help guide
455 /// high-level lowering decisions.
456 bool isOperationExpand(unsigned Op, EVT VT) const {
457 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
460 /// Return true if the specified operation is legal on this target.
461 bool isOperationLegal(unsigned Op, EVT VT) const {
462 return (VT == MVT::Other || isTypeLegal(VT)) &&
463 getOperationAction(Op, VT) == Legal;
466 /// Return how this load with extension should be treated: either it is legal,
467 /// needs to be promoted to a larger size, needs to be expanded to some other
468 /// code sequence, or the target has a custom expander for it.
469 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
470 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
471 "Table isn't big enough!");
472 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
475 /// Return true if the specified load with extension is legal on this target.
476 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
477 return VT.isSimple() &&
478 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
481 /// Return how this store with truncation should be treated: either it is
482 /// legal, needs to be promoted to a larger size, needs to be expanded to some
483 /// other code sequence, or the target has a custom expander for it.
484 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
485 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
486 "Table isn't big enough!");
487 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
491 /// Return true if the specified store with truncation is legal on this
493 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
494 return isTypeLegal(ValVT) && MemVT.isSimple() &&
495 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
498 /// Return how the indexed load should be treated: either it is legal, needs
499 /// to be promoted to a larger size, needs to be expanded to some other code
500 /// sequence, or the target has a custom expander for it.
502 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
503 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
504 "Table isn't big enough!");
505 unsigned Ty = (unsigned)VT.SimpleTy;
506 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
509 /// Return true if the specified indexed load is legal on this target.
510 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
511 return VT.isSimple() &&
512 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
513 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
516 /// Return how the indexed store should be treated: either it is legal, needs
517 /// to be promoted to a larger size, needs to be expanded to some other code
518 /// sequence, or the target has a custom expander for it.
520 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
521 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
522 "Table isn't big enough!");
523 unsigned Ty = (unsigned)VT.SimpleTy;
524 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
527 /// Return true if the specified indexed load is legal on this target.
528 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
529 return VT.isSimple() &&
530 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
531 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
534 /// Return how the condition code should be treated: either it is legal, needs
535 /// to be expanded to some other code sequence, or the target has a custom
538 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
539 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
540 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
541 "Table isn't big enough!");
542 // See setCondCodeAction for how this is encoded.
543 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
544 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
545 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
546 assert(Action != Promote && "Can't promote condition code!");
550 /// Return true if the specified condition code is legal on this target.
551 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
553 getCondCodeAction(CC, VT) == Legal ||
554 getCondCodeAction(CC, VT) == Custom;
558 /// If the action for this operation is to promote, this method returns the
559 /// ValueType to promote to.
560 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
561 assert(getOperationAction(Op, VT) == Promote &&
562 "This operation isn't promoted!");
564 // See if this has an explicit type specified.
565 std::map<std::pair<unsigned, MVT::SimpleValueType>,
566 MVT::SimpleValueType>::const_iterator PTTI =
567 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
568 if (PTTI != PromoteToType.end()) return PTTI->second;
570 assert((VT.isInteger() || VT.isFloatingPoint()) &&
571 "Cannot autopromote this type, add it with AddPromotedToType.");
575 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
576 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
577 "Didn't find type to promote to!");
578 } while (!isTypeLegal(NVT) ||
579 getOperationAction(Op, NVT) == Promote);
583 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
584 /// operations except for the pointer size. If AllowUnknown is true, this
585 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
586 /// otherwise it will assert.
587 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
588 // Lower scalar pointers to native pointer types.
589 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
590 return getPointerTy(PTy->getAddressSpace());
592 if (Ty->isVectorTy()) {
593 VectorType *VTy = cast<VectorType>(Ty);
594 Type *Elm = VTy->getElementType();
595 // Lower vectors of pointers to native pointer types.
596 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
597 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
598 Elm = PointerTy.getTypeForEVT(Ty->getContext());
601 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
602 VTy->getNumElements());
604 return EVT::getEVT(Ty, AllowUnknown);
607 /// Return the MVT corresponding to this LLVM type. See getValueType.
608 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
609 return getValueType(Ty, AllowUnknown).getSimpleVT();
612 /// Return the desired alignment for ByVal or InAlloca aggregate function
613 /// arguments in the caller parameter area. This is the actual alignment, not
615 virtual unsigned getByValTypeAlignment(Type *Ty) const;
617 /// Return the type of registers that this ValueType will eventually require.
618 MVT getRegisterType(MVT VT) const {
619 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
620 return RegisterTypeForVT[VT.SimpleTy];
623 /// Return the type of registers that this ValueType will eventually require.
624 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
626 assert((unsigned)VT.getSimpleVT().SimpleTy <
627 array_lengthof(RegisterTypeForVT));
628 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
633 unsigned NumIntermediates;
634 (void)getVectorTypeBreakdown(Context, VT, VT1,
635 NumIntermediates, RegisterVT);
638 if (VT.isInteger()) {
639 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
641 llvm_unreachable("Unsupported extended type!");
644 /// Return the number of registers that this ValueType will eventually
647 /// This is one for any types promoted to live in larger registers, but may be
648 /// more than one for types (like i64) that are split into pieces. For types
649 /// like i140, which are first promoted then expanded, it is the number of
650 /// registers needed to hold all the bits of the original type. For an i140
651 /// on a 32 bit machine this means 5 registers.
652 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
654 assert((unsigned)VT.getSimpleVT().SimpleTy <
655 array_lengthof(NumRegistersForVT));
656 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
661 unsigned NumIntermediates;
662 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
664 if (VT.isInteger()) {
665 unsigned BitWidth = VT.getSizeInBits();
666 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
667 return (BitWidth + RegWidth - 1) / RegWidth;
669 llvm_unreachable("Unsupported extended type!");
672 /// If true, then instruction selection should seek to shrink the FP constant
673 /// of the specified type to a smaller type in order to save space and / or
675 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
677 /// If true, the target has custom DAG combine transformations that it can
678 /// perform for the specified node.
679 bool hasTargetDAGCombine(ISD::NodeType NT) const {
680 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
681 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
684 /// \brief Get maximum # of store operations permitted for llvm.memset
686 /// This function returns the maximum number of store operations permitted
687 /// to replace a call to llvm.memset. The value is set by the target at the
688 /// performance threshold for such a replacement. If OptSize is true,
689 /// return the limit for functions that have OptSize attribute.
690 unsigned getMaxStoresPerMemset(bool OptSize) const {
691 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
694 /// \brief Get maximum # of store operations permitted for llvm.memcpy
696 /// This function returns the maximum number of store operations permitted
697 /// to replace a call to llvm.memcpy. The value is set by the target at the
698 /// performance threshold for such a replacement. If OptSize is true,
699 /// return the limit for functions that have OptSize attribute.
700 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
701 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
704 /// \brief Get maximum # of store operations permitted for llvm.memmove
706 /// This function returns the maximum number of store operations permitted
707 /// to replace a call to llvm.memmove. The value is set by the target at the
708 /// performance threshold for such a replacement. If OptSize is true,
709 /// return the limit for functions that have OptSize attribute.
710 unsigned getMaxStoresPerMemmove(bool OptSize) const {
711 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
714 /// \brief Determine if the target supports unaligned memory accesses.
716 /// This function returns true if the target allows unaligned memory accesses
717 /// of the specified type in the given address space. If true, it also returns
718 /// whether the unaligned memory access is "fast" in the third argument by
719 /// reference. This is used, for example, in situations where an array
720 /// copy/move/set is converted to a sequence of store operations. Its use
721 /// helps to ensure that such replacements don't generate code that causes an
722 /// alignment error (trap) on the target machine.
723 virtual bool allowsUnalignedMemoryAccesses(EVT,
724 unsigned AddrSpace = 0,
725 bool * /*Fast*/ = 0) const {
729 /// Returns the target specific optimal type for load and store operations as
730 /// a result of memset, memcpy, and memmove lowering.
732 /// If DstAlign is zero that means it's safe to destination alignment can
733 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
734 /// a need to check it against alignment requirement, probably because the
735 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
736 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
737 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
738 /// does not need to be loaded. It returns EVT::Other if the type should be
739 /// determined using generic target-independent logic.
740 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
741 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
744 bool /*MemcpyStrSrc*/,
745 MachineFunction &/*MF*/) const {
749 /// Returns true if it's safe to use load / store of the specified type to
750 /// expand memcpy / memset inline.
752 /// This is mostly true for all types except for some special cases. For
753 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
754 /// fstpl which also does type conversion. Note the specified type doesn't
755 /// have to be legal as the hook is used before type legalization.
756 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
758 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
759 bool usesUnderscoreSetJmp() const {
760 return UseUnderscoreSetJmp;
763 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
764 bool usesUnderscoreLongJmp() const {
765 return UseUnderscoreLongJmp;
768 /// Return whether the target can generate code for jump tables.
769 bool supportJumpTables() const {
770 return SupportJumpTables;
773 /// Return integer threshold on number of blocks to use jump tables rather
774 /// than if sequence.
775 int getMinimumJumpTableEntries() const {
776 return MinimumJumpTableEntries;
779 /// If a physical register, this specifies the register that
780 /// llvm.savestack/llvm.restorestack should save and restore.
781 unsigned getStackPointerRegisterToSaveRestore() const {
782 return StackPointerRegisterToSaveRestore;
785 /// If a physical register, this returns the register that receives the
786 /// exception address on entry to a landing pad.
787 unsigned getExceptionPointerRegister() const {
788 return ExceptionPointerRegister;
791 /// If a physical register, this returns the register that receives the
792 /// exception typeid on entry to a landing pad.
793 unsigned getExceptionSelectorRegister() const {
794 return ExceptionSelectorRegister;
797 /// Returns the target's jmp_buf size in bytes (if never set, the default is
799 unsigned getJumpBufSize() const {
803 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
805 unsigned getJumpBufAlignment() const {
806 return JumpBufAlignment;
809 /// Return the minimum stack alignment of an argument.
810 unsigned getMinStackArgumentAlignment() const {
811 return MinStackArgumentAlignment;
814 /// Return the minimum function alignment.
815 unsigned getMinFunctionAlignment() const {
816 return MinFunctionAlignment;
819 /// Return the preferred function alignment.
820 unsigned getPrefFunctionAlignment() const {
821 return PrefFunctionAlignment;
824 /// Return the preferred loop alignment.
825 unsigned getPrefLoopAlignment() const {
826 return PrefLoopAlignment;
829 /// Return whether the DAG builder should automatically insert fences and
830 /// reduce ordering for atomics.
831 bool getInsertFencesForAtomic() const {
832 return InsertFencesForAtomic;
835 /// Return true if the target stores stack protector cookies at a fixed offset
836 /// in some non-standard address space, and populates the address space and
837 /// offset as appropriate.
838 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
839 unsigned &/*Offset*/) const {
843 /// Returns the maximal possible offset which can be used for loads / stores
845 virtual unsigned getMaximalGlobalOffset() const {
849 /// Returns true if a cast between SrcAS and DestAS is a noop.
850 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
854 //===--------------------------------------------------------------------===//
855 /// \name Helpers for TargetTransformInfo implementations
858 /// Get the ISD node that corresponds to the Instruction class opcode.
859 int InstructionOpcodeToISD(unsigned Opcode) const;
861 /// Estimate the cost of type-legalization and the legalized type.
862 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
866 //===--------------------------------------------------------------------===//
867 // TargetLowering Configuration Methods - These methods should be invoked by
868 // the derived class constructor to configure this object for the target.
871 /// \brief Reset the operation actions based on target options.
872 virtual void resetOperationActions() {}
875 /// Specify how the target extends the result of a boolean value from i1 to a
876 /// wider type. See getBooleanContents.
877 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
879 /// Specify how the target extends the result of a vector boolean value from a
880 /// vector of i1 to a wider type. See getBooleanContents.
881 void setBooleanVectorContents(BooleanContent Ty) {
882 BooleanVectorContents = Ty;
885 /// Specify the target scheduling preference.
886 void setSchedulingPreference(Sched::Preference Pref) {
887 SchedPreferenceInfo = Pref;
890 /// Indicate whether this target prefers to use _setjmp to implement
891 /// llvm.setjmp or the version without _. Defaults to false.
892 void setUseUnderscoreSetJmp(bool Val) {
893 UseUnderscoreSetJmp = Val;
896 /// Indicate whether this target prefers to use _longjmp to implement
897 /// llvm.longjmp or the version without _. Defaults to false.
898 void setUseUnderscoreLongJmp(bool Val) {
899 UseUnderscoreLongJmp = Val;
902 /// Indicate whether the target can generate code for jump tables.
903 void setSupportJumpTables(bool Val) {
904 SupportJumpTables = Val;
907 /// Indicate the number of blocks to generate jump tables rather than if
909 void setMinimumJumpTableEntries(int Val) {
910 MinimumJumpTableEntries = Val;
913 /// If set to a physical register, this specifies the register that
914 /// llvm.savestack/llvm.restorestack should save and restore.
915 void setStackPointerRegisterToSaveRestore(unsigned R) {
916 StackPointerRegisterToSaveRestore = R;
919 /// If set to a physical register, this sets the register that receives the
920 /// exception address on entry to a landing pad.
921 void setExceptionPointerRegister(unsigned R) {
922 ExceptionPointerRegister = R;
925 /// If set to a physical register, this sets the register that receives the
926 /// exception typeid on entry to a landing pad.
927 void setExceptionSelectorRegister(unsigned R) {
928 ExceptionSelectorRegister = R;
931 /// Tells the code generator not to expand operations into sequences that use
932 /// the select operations if possible.
933 void setSelectIsExpensive(bool isExpensive = true) {
934 SelectIsExpensive = isExpensive;
937 /// Tells the code generator that the target has multiple (allocatable)
938 /// condition registers that can be used to store the results of comparisons
939 /// for use by selects and conditional branches. With multiple condition
940 /// registers, the code generator will not aggressively sink comparisons into
941 /// the blocks of their users.
942 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
943 HasMultipleConditionRegisters = hasManyRegs;
946 /// Tells the code generator not to expand sequence of operations into a
947 /// separate sequences that increases the amount of flow control.
948 void setJumpIsExpensive(bool isExpensive = true) {
949 JumpIsExpensive = isExpensive;
952 /// Tells the code generator that integer divide is expensive, and if
953 /// possible, should be replaced by an alternate sequence of instructions not
954 /// containing an integer divide.
955 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
957 /// Tells the code generator which bitwidths to bypass.
958 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
959 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
962 /// Tells the code generator that it shouldn't generate srl/add/sra for a
963 /// signed divide by power of two, and let the target handle it.
964 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
966 /// Add the specified register class as an available regclass for the
967 /// specified value type. This indicates the selector can handle values of
968 /// that class natively.
969 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
970 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
971 AvailableRegClasses.push_back(std::make_pair(VT, RC));
972 RegClassForVT[VT.SimpleTy] = RC;
975 /// Remove all register classes.
976 void clearRegisterClasses() {
977 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
979 AvailableRegClasses.clear();
982 /// \brief Remove all operation actions.
983 void clearOperationActions() {
986 /// Return the largest legal super-reg register class of the register class
987 /// for the specified type and its associated "cost".
988 virtual std::pair<const TargetRegisterClass*, uint8_t>
989 findRepresentativeClass(MVT VT) const;
991 /// Once all of the register classes are added, this allows us to compute
992 /// derived properties we expose.
993 void computeRegisterProperties();
995 /// Indicate that the specified operation does not work with the specified
996 /// type and indicate what to do about it.
997 void setOperationAction(unsigned Op, MVT VT,
998 LegalizeAction Action) {
999 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1000 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1003 /// Indicate that the specified load with extension does not work with the
1004 /// specified type and indicate what to do about it.
1005 void setLoadExtAction(unsigned ExtType, MVT VT,
1006 LegalizeAction Action) {
1007 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1008 "Table isn't big enough!");
1009 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1012 /// Indicate that the specified truncating store does not work with the
1013 /// specified type and indicate what to do about it.
1014 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1015 LegalizeAction Action) {
1016 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1017 "Table isn't big enough!");
1018 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1021 /// Indicate that the specified indexed load does or does not work with the
1022 /// specified type and indicate what to do abort it.
1024 /// NOTE: All indexed mode loads are initialized to Expand in
1025 /// TargetLowering.cpp
1026 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1027 LegalizeAction Action) {
1028 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1029 (unsigned)Action < 0xf && "Table isn't big enough!");
1030 // Load action are kept in the upper half.
1031 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1032 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1035 /// Indicate that the specified indexed store does or does not work with the
1036 /// specified type and indicate what to do about it.
1038 /// NOTE: All indexed mode stores are initialized to Expand in
1039 /// TargetLowering.cpp
1040 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1041 LegalizeAction Action) {
1042 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1043 (unsigned)Action < 0xf && "Table isn't big enough!");
1044 // Store action are kept in the lower half.
1045 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1046 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1049 /// Indicate that the specified condition code is or isn't supported on the
1050 /// target and indicate what to do about it.
1051 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1052 LegalizeAction Action) {
1053 assert(VT < MVT::LAST_VALUETYPE &&
1054 (unsigned)CC < array_lengthof(CondCodeActions) &&
1055 "Table isn't big enough!");
1056 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1057 /// value and the upper 27 bits index into the second dimension of the array
1058 /// to select what 32-bit value to use.
1059 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1060 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1061 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1064 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1065 /// to trying a larger integer/fp until it can find one that works. If that
1066 /// default is insufficient, this method can be used by the target to override
1068 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1069 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1072 /// Targets should invoke this method for each target independent node that
1073 /// they want to provide a custom DAG combiner for by implementing the
1074 /// PerformDAGCombine virtual method.
1075 void setTargetDAGCombine(ISD::NodeType NT) {
1076 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1077 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1080 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1081 void setJumpBufSize(unsigned Size) {
1085 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1087 void setJumpBufAlignment(unsigned Align) {
1088 JumpBufAlignment = Align;
1091 /// Set the target's minimum function alignment (in log2(bytes))
1092 void setMinFunctionAlignment(unsigned Align) {
1093 MinFunctionAlignment = Align;
1096 /// Set the target's preferred function alignment. This should be set if
1097 /// there is a performance benefit to higher-than-minimum alignment (in
1099 void setPrefFunctionAlignment(unsigned Align) {
1100 PrefFunctionAlignment = Align;
1103 /// Set the target's preferred loop alignment. Default alignment is zero, it
1104 /// means the target does not care about loop alignment. The alignment is
1105 /// specified in log2(bytes).
1106 void setPrefLoopAlignment(unsigned Align) {
1107 PrefLoopAlignment = Align;
1110 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1111 void setMinStackArgumentAlignment(unsigned Align) {
1112 MinStackArgumentAlignment = Align;
1115 /// Set if the DAG builder should automatically insert fences and reduce the
1116 /// order of atomic memory operations to Monotonic.
1117 void setInsertFencesForAtomic(bool fence) {
1118 InsertFencesForAtomic = fence;
1122 //===--------------------------------------------------------------------===//
1123 // Addressing mode description hooks (used by LSR etc).
1126 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1127 /// instructions reading the address. This allows as much computation as
1128 /// possible to be done in the address mode for that operand. This hook lets
1129 /// targets also pass back when this should be done on intrinsics which
1131 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1132 SmallVectorImpl<Value*> &/*Ops*/,
1133 Type *&/*AccessTy*/) const {
1137 /// This represents an addressing mode of:
1138 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1139 /// If BaseGV is null, there is no BaseGV.
1140 /// If BaseOffs is zero, there is no base offset.
1141 /// If HasBaseReg is false, there is no base register.
1142 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1145 GlobalValue *BaseGV;
1149 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1152 /// Return true if the addressing mode represented by AM is legal for this
1153 /// target, for a load/store of the specified type.
1155 /// The type may be VoidTy, in which case only return true if the addressing
1156 /// mode is legal for a load/store of any legal type. TODO: Handle
1157 /// pre/postinc as well.
1158 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1160 /// \brief Return the cost of the scaling factor used in the addressing mode
1161 /// represented by AM for this target, for a load/store of the specified type.
1163 /// If the AM is supported, the return value must be >= 0.
1164 /// If the AM is not supported, it returns a negative value.
1165 /// TODO: Handle pre/postinc as well.
1166 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1167 // Default: assume that any scaling factor used in a legal AM is free.
1168 if (isLegalAddressingMode(AM, Ty)) return 0;
1172 /// Return true if the specified immediate is legal icmp immediate, that is
1173 /// the target has icmp instructions which can compare a register against the
1174 /// immediate without having to materialize the immediate into a register.
1175 virtual bool isLegalICmpImmediate(int64_t) const {
1179 /// Return true if the specified immediate is legal add immediate, that is the
1180 /// target has add instructions which can add a register with the immediate
1181 /// without having to materialize the immediate into a register.
1182 virtual bool isLegalAddImmediate(int64_t) const {
1186 /// Return true if it's free to truncate a value of type Ty1 to type
1187 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1188 /// by referencing its sub-register AX.
1189 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1193 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1194 /// whether a call is in tail position. Typically this means that both results
1195 /// would be assigned to the same register or stack slot, but it could mean
1196 /// the target performs adequate checks of its own before proceeding with the
1198 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1202 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1206 /// Return true if any actual instruction that defines a value of type Ty1
1207 /// implicitly zero-extends the value to Ty2 in the result register.
1209 /// This does not necessarily include registers defined in unknown ways, such
1210 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1211 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1212 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1213 /// values implicit zero-extend the result out to 64 bits.
1214 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1218 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1222 /// Return true if the target supplies and combines to a paired load
1223 /// two loaded values of type LoadedType next to each other in memory.
1224 /// RequiredAlignment gives the minimal alignment constraints that must be met
1225 /// to be able to select this paired load.
1227 /// This information is *not* used to generate actual paired loads, but it is
1228 /// used to generate a sequence of loads that is easier to combine into a
1230 /// For instance, something like this:
1231 /// a = load i64* addr
1232 /// b = trunc i64 a to i32
1233 /// c = lshr i64 a, 32
1234 /// d = trunc i64 c to i32
1235 /// will be optimized into:
1236 /// b = load i32* addr1
1237 /// d = load i32* addr2
1238 /// Where addr1 = addr2 +/- sizeof(i32).
1240 /// In other words, unless the target performs a post-isel load combining,
1241 /// this information should not be provided because it will generate more
1243 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1244 unsigned & /*RequiredAligment*/) const {
1248 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1249 unsigned & /*RequiredAligment*/) const {
1253 /// Return true if zero-extending the specific node Val to type VT2 is free
1254 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1255 /// because it's folded such as X86 zero-extending loads).
1256 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1257 return isZExtFree(Val.getValueType(), VT2);
1260 /// Return true if an fneg operation is free to the point where it is never
1261 /// worthwhile to replace it with a bitwise operation.
1262 virtual bool isFNegFree(EVT VT) const {
1263 assert(VT.isFloatingPoint());
1267 /// Return true if an fabs operation is free to the point where it is never
1268 /// worthwhile to replace it with a bitwise operation.
1269 virtual bool isFAbsFree(EVT VT) const {
1270 assert(VT.isFloatingPoint());
1274 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1275 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1276 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1278 /// NOTE: This may be called before legalization on types for which FMAs are
1279 /// not legal, but should return true if those types will eventually legalize
1280 /// to types that support FMAs. After legalization, it will only be called on
1281 /// types that support FMAs (via Legal or Custom actions)
1282 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1286 /// Return true if it's profitable to narrow operations of type VT1 to
1287 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1289 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1293 /// \brief Return true if it is beneficial to convert a load of a constant to
1294 /// just the constant itself.
1295 /// On some targets it might be more efficient to use a combination of
1296 /// arithmetic instructions to materialize the constant instead of loading it
1297 /// from a constant pool.
1298 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1302 //===--------------------------------------------------------------------===//
1303 // Runtime Library hooks
1306 /// Rename the default libcall routine name for the specified libcall.
1307 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1308 LibcallRoutineNames[Call] = Name;
1311 /// Get the libcall routine name for the specified libcall.
1312 const char *getLibcallName(RTLIB::Libcall Call) const {
1313 return LibcallRoutineNames[Call];
1316 /// Override the default CondCode to be used to test the result of the
1317 /// comparison libcall against zero.
1318 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1319 CmpLibcallCCs[Call] = CC;
1322 /// Get the CondCode that's to be used to test the result of the comparison
1323 /// libcall against zero.
1324 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1325 return CmpLibcallCCs[Call];
1328 /// Set the CallingConv that should be used for the specified libcall.
1329 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1330 LibcallCallingConvs[Call] = CC;
1333 /// Get the CallingConv that should be used for the specified libcall.
1334 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1335 return LibcallCallingConvs[Call];
1339 const TargetMachine &TM;
1340 const DataLayout *DL;
1341 const TargetLoweringObjectFile &TLOF;
1343 /// True if this is a little endian target.
1344 bool IsLittleEndian;
1346 /// Tells the code generator not to expand operations into sequences that use
1347 /// the select operations if possible.
1348 bool SelectIsExpensive;
1350 /// Tells the code generator that the target has multiple (allocatable)
1351 /// condition registers that can be used to store the results of comparisons
1352 /// for use by selects and conditional branches. With multiple condition
1353 /// registers, the code generator will not aggressively sink comparisons into
1354 /// the blocks of their users.
1355 bool HasMultipleConditionRegisters;
1357 /// Tells the code generator not to expand integer divides by constants into a
1358 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1359 /// model is in place. If we ever optimize for size, this will be set to true
1360 /// unconditionally.
1363 /// Tells the code generator to bypass slow divide or remainder
1364 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1365 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1366 /// div/rem when the operands are positive and less than 256.
1367 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1369 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1370 /// signed divide by power of two, and let the target handle it.
1371 bool Pow2DivIsCheap;
1373 /// Tells the code generator that it shouldn't generate extra flow control
1374 /// instructions and should attempt to combine flow control instructions via
1376 bool JumpIsExpensive;
1378 /// This target prefers to use _setjmp to implement llvm.setjmp.
1380 /// Defaults to false.
1381 bool UseUnderscoreSetJmp;
1383 /// This target prefers to use _longjmp to implement llvm.longjmp.
1385 /// Defaults to false.
1386 bool UseUnderscoreLongJmp;
1388 /// Whether the target can generate code for jumptables. If it's not true,
1389 /// then each jumptable must be lowered into if-then-else's.
1390 bool SupportJumpTables;
1392 /// Number of blocks threshold to use jump tables.
1393 int MinimumJumpTableEntries;
1395 /// Information about the contents of the high-bits in boolean values held in
1396 /// a type wider than i1. See getBooleanContents.
1397 BooleanContent BooleanContents;
1399 /// Information about the contents of the high-bits in boolean vector values
1400 /// when the element type is wider than i1. See getBooleanContents.
1401 BooleanContent BooleanVectorContents;
1403 /// The target scheduling preference: shortest possible total cycles or lowest
1405 Sched::Preference SchedPreferenceInfo;
1407 /// The size, in bytes, of the target's jmp_buf buffers
1408 unsigned JumpBufSize;
1410 /// The alignment, in bytes, of the target's jmp_buf buffers
1411 unsigned JumpBufAlignment;
1413 /// The minimum alignment that any argument on the stack needs to have.
1414 unsigned MinStackArgumentAlignment;
1416 /// The minimum function alignment (used when optimizing for size, and to
1417 /// prevent explicitly provided alignment from leading to incorrect code).
1418 unsigned MinFunctionAlignment;
1420 /// The preferred function alignment (used when alignment unspecified and
1421 /// optimizing for speed).
1422 unsigned PrefFunctionAlignment;
1424 /// The preferred loop alignment.
1425 unsigned PrefLoopAlignment;
1427 /// Whether the DAG builder should automatically insert fences and reduce
1428 /// ordering for atomics. (This will be set for for most architectures with
1429 /// weak memory ordering.)
1430 bool InsertFencesForAtomic;
1432 /// If set to a physical register, this specifies the register that
1433 /// llvm.savestack/llvm.restorestack should save and restore.
1434 unsigned StackPointerRegisterToSaveRestore;
1436 /// If set to a physical register, this specifies the register that receives
1437 /// the exception address on entry to a landing pad.
1438 unsigned ExceptionPointerRegister;
1440 /// If set to a physical register, this specifies the register that receives
1441 /// the exception typeid on entry to a landing pad.
1442 unsigned ExceptionSelectorRegister;
1444 /// This indicates the default register class to use for each ValueType the
1445 /// target supports natively.
1446 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1447 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1448 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1450 /// This indicates the "representative" register class to use for each
1451 /// ValueType the target supports natively. This information is used by the
1452 /// scheduler to track register pressure. By default, the representative
1453 /// register class is the largest legal super-reg register class of the
1454 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1455 /// representative class would be GR32.
1456 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1458 /// This indicates the "cost" of the "representative" register class for each
1459 /// ValueType. The cost is used by the scheduler to approximate register
1461 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1463 /// For any value types we are promoting or expanding, this contains the value
1464 /// type that we are changing to. For Expanded types, this contains one step
1465 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1466 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1467 /// the same type (e.g. i32 -> i32).
1468 MVT TransformToType[MVT::LAST_VALUETYPE];
1470 /// For each operation and each value type, keep a LegalizeAction that
1471 /// indicates how instruction selection should deal with the operation. Most
1472 /// operations are Legal (aka, supported natively by the target), but
1473 /// operations that are not should be described. Note that operations on
1474 /// non-legal value types are not described here.
1475 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1477 /// For each load extension type and each value type, keep a LegalizeAction
1478 /// that indicates how instruction selection should deal with a load of a
1479 /// specific value type and extension type.
1480 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1482 /// For each value type pair keep a LegalizeAction that indicates whether a
1483 /// truncating store of a specific value type and truncating type is legal.
1484 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1486 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1487 /// that indicates how instruction selection should deal with the load /
1490 /// The first dimension is the value_type for the reference. The second
1491 /// dimension represents the various modes for load store.
1492 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1494 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1495 /// indicates how instruction selection should deal with the condition code.
1497 /// Because each CC action takes up 2 bits, we need to have the array size be
1498 /// large enough to fit all of the value types. This can be done by rounding
1499 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1500 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1502 ValueTypeActionImpl ValueTypeActions;
1506 getTypeConversion(LLVMContext &Context, EVT VT) const {
1507 // If this is a simple type, use the ComputeRegisterProp mechanism.
1508 if (VT.isSimple()) {
1509 MVT SVT = VT.getSimpleVT();
1510 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1511 MVT NVT = TransformToType[SVT.SimpleTy];
1512 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1516 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1517 && "Promote may not follow Expand or Promote");
1519 if (LA == TypeSplitVector)
1520 return LegalizeKind(LA, EVT::getVectorVT(Context,
1521 SVT.getVectorElementType(),
1522 SVT.getVectorNumElements()/2));
1523 if (LA == TypeScalarizeVector)
1524 return LegalizeKind(LA, SVT.getVectorElementType());
1525 return LegalizeKind(LA, NVT);
1528 // Handle Extended Scalar Types.
1529 if (!VT.isVector()) {
1530 assert(VT.isInteger() && "Float types must be simple");
1531 unsigned BitSize = VT.getSizeInBits();
1532 // First promote to a power-of-two size, then expand if necessary.
1533 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1534 EVT NVT = VT.getRoundIntegerType(Context);
1535 assert(NVT != VT && "Unable to round integer VT");
1536 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1537 // Avoid multi-step promotion.
1538 if (NextStep.first == TypePromoteInteger) return NextStep;
1539 // Return rounded integer type.
1540 return LegalizeKind(TypePromoteInteger, NVT);
1543 return LegalizeKind(TypeExpandInteger,
1544 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1547 // Handle vector types.
1548 unsigned NumElts = VT.getVectorNumElements();
1549 EVT EltVT = VT.getVectorElementType();
1551 // Vectors with only one element are always scalarized.
1553 return LegalizeKind(TypeScalarizeVector, EltVT);
1555 // Try to widen vector elements until the element type is a power of two and
1556 // promote it to a legal type later on, for example:
1557 // <3 x i8> -> <4 x i8> -> <4 x i32>
1558 if (EltVT.isInteger()) {
1559 // Vectors with a number of elements that is not a power of two are always
1560 // widened, for example <3 x i8> -> <4 x i8>.
1561 if (!VT.isPow2VectorType()) {
1562 NumElts = (unsigned)NextPowerOf2(NumElts);
1563 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1564 return LegalizeKind(TypeWidenVector, NVT);
1567 // Examine the element type.
1568 LegalizeKind LK = getTypeConversion(Context, EltVT);
1570 // If type is to be expanded, split the vector.
1571 // <4 x i140> -> <2 x i140>
1572 if (LK.first == TypeExpandInteger)
1573 return LegalizeKind(TypeSplitVector,
1574 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1576 // Promote the integer element types until a legal vector type is found
1577 // or until the element integer type is too big. If a legal type was not
1578 // found, fallback to the usual mechanism of widening/splitting the
1580 EVT OldEltVT = EltVT;
1582 // Increase the bitwidth of the element to the next pow-of-two
1583 // (which is greater than 8 bits).
1584 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1585 ).getRoundIntegerType(Context);
1587 // Stop trying when getting a non-simple element type.
1588 // Note that vector elements may be greater than legal vector element
1589 // types. Example: X86 XMM registers hold 64bit element on 32bit
1591 if (!EltVT.isSimple()) break;
1593 // Build a new vector type and check if it is legal.
1594 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1595 // Found a legal promoted vector type.
1596 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1597 return LegalizeKind(TypePromoteInteger,
1598 EVT::getVectorVT(Context, EltVT, NumElts));
1601 // Reset the type to the unexpanded type if we did not find a legal vector
1602 // type with a promoted vector element type.
1606 // Try to widen the vector until a legal type is found.
1607 // If there is no wider legal type, split the vector.
1609 // Round up to the next power of 2.
1610 NumElts = (unsigned)NextPowerOf2(NumElts);
1612 // If there is no simple vector type with this many elements then there
1613 // cannot be a larger legal vector type. Note that this assumes that
1614 // there are no skipped intermediate vector types in the simple types.
1615 if (!EltVT.isSimple()) break;
1616 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1617 if (LargerVector == MVT()) break;
1619 // If this type is legal then widen the vector.
1620 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1621 return LegalizeKind(TypeWidenVector, LargerVector);
1624 // Widen odd vectors to next power of two.
1625 if (!VT.isPow2VectorType()) {
1626 EVT NVT = VT.getPow2VectorType(Context);
1627 return LegalizeKind(TypeWidenVector, NVT);
1630 // Vectors with illegal element types are expanded.
1631 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1632 return LegalizeKind(TypeSplitVector, NVT);
1636 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1638 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1639 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1642 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1644 /// For operations that must be promoted to a specific type, this holds the
1645 /// destination type. This map should be sparse, so don't hold it as an
1648 /// Targets add entries to this map with AddPromotedToType(..), clients access
1649 /// this with getTypeToPromoteTo(..).
1650 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1653 /// Stores the name each libcall.
1654 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1656 /// The ISD::CondCode that should be used to test the result of each of the
1657 /// comparison libcall against zero.
1658 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1660 /// Stores the CallingConv that should be used for each libcall.
1661 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1664 /// \brief Specify maximum number of store instructions per memset call.
1666 /// When lowering \@llvm.memset this field specifies the maximum number of
1667 /// store operations that may be substituted for the call to memset. Targets
1668 /// must set this value based on the cost threshold for that target. Targets
1669 /// should assume that the memset will be done using as many of the largest
1670 /// store operations first, followed by smaller ones, if necessary, per
1671 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1672 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1673 /// store. This only applies to setting a constant array of a constant size.
1674 unsigned MaxStoresPerMemset;
1676 /// Maximum number of stores operations that may be substituted for the call
1677 /// to memset, used for functions with OptSize attribute.
1678 unsigned MaxStoresPerMemsetOptSize;
1680 /// \brief Specify maximum bytes of store instructions per memcpy call.
1682 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1683 /// store operations that may be substituted for a call to memcpy. Targets
1684 /// must set this value based on the cost threshold for that target. Targets
1685 /// should assume that the memcpy will be done using as many of the largest
1686 /// store operations first, followed by smaller ones, if necessary, per
1687 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1688 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1689 /// and one 1-byte store. This only applies to copying a constant array of
1691 unsigned MaxStoresPerMemcpy;
1693 /// Maximum number of store operations that may be substituted for a call to
1694 /// memcpy, used for functions with OptSize attribute.
1695 unsigned MaxStoresPerMemcpyOptSize;
1697 /// \brief Specify maximum bytes of store instructions per memmove call.
1699 /// When lowering \@llvm.memmove this field specifies the maximum number of
1700 /// store instructions that may be substituted for a call to memmove. Targets
1701 /// must set this value based on the cost threshold for that target. Targets
1702 /// should assume that the memmove will be done using as many of the largest
1703 /// store operations first, followed by smaller ones, if necessary, per
1704 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1705 /// with 8-bit alignment would result in nine 1-byte stores. This only
1706 /// applies to copying a constant array of constant size.
1707 unsigned MaxStoresPerMemmove;
1709 /// Maximum number of store instructions that may be substituted for a call to
1710 /// memmove, used for functions with OpSize attribute.
1711 unsigned MaxStoresPerMemmoveOptSize;
1713 /// Tells the code generator that select is more expensive than a branch if
1714 /// the branch is usually predicted right.
1715 bool PredictableSelectIsExpensive;
1718 /// Return true if the value types that can be represented by the specified
1719 /// register class are all legal.
1720 bool isLegalRC(const TargetRegisterClass *RC) const;
1722 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1723 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1724 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1727 /// This class defines information used to lower LLVM code to legal SelectionDAG
1728 /// operators that the target instruction selector can accept natively.
1730 /// This class also defines callbacks that targets must implement to lower
1731 /// target-specific constructs to SelectionDAG operators.
1732 class TargetLowering : public TargetLoweringBase {
1733 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1734 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1737 /// NOTE: The constructor takes ownership of TLOF.
1738 explicit TargetLowering(const TargetMachine &TM,
1739 const TargetLoweringObjectFile *TLOF);
1741 /// Returns true by value, base pointer and offset pointer and addressing mode
1742 /// by reference if the node's address can be legally represented as
1743 /// pre-indexed load / store address.
1744 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1745 SDValue &/*Offset*/,
1746 ISD::MemIndexedMode &/*AM*/,
1747 SelectionDAG &/*DAG*/) const {
1751 /// Returns true by value, base pointer and offset pointer and addressing mode
1752 /// by reference if this node can be combined with a load / store to form a
1753 /// post-indexed load / store.
1754 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1756 SDValue &/*Offset*/,
1757 ISD::MemIndexedMode &/*AM*/,
1758 SelectionDAG &/*DAG*/) const {
1762 /// Return the entry encoding for a jump table in the current function. The
1763 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1764 virtual unsigned getJumpTableEncoding() const;
1766 virtual const MCExpr *
1767 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1768 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1769 MCContext &/*Ctx*/) const {
1770 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1773 /// Returns relocation base for the given PIC jumptable.
1774 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1775 SelectionDAG &DAG) const;
1777 /// This returns the relocation base for the given PIC jumptable, the same as
1778 /// getPICJumpTableRelocBase, but as an MCExpr.
1779 virtual const MCExpr *
1780 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1781 unsigned JTI, MCContext &Ctx) const;
1783 /// Return true if folding a constant offset with the given GlobalAddress is
1784 /// legal. It is frequently not legal in PIC relocation models.
1785 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1787 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1788 SDValue &Chain) const;
1790 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1791 SDValue &NewLHS, SDValue &NewRHS,
1792 ISD::CondCode &CCCode, SDLoc DL) const;
1794 /// Returns a pair of (return value, chain).
1795 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1796 EVT RetVT, const SDValue *Ops,
1797 unsigned NumOps, bool isSigned,
1798 SDLoc dl, bool doesNotReturn = false,
1799 bool isReturnValueUsed = true) const;
1801 //===--------------------------------------------------------------------===//
1802 // TargetLowering Optimization Methods
1805 /// A convenience struct that encapsulates a DAG, and two SDValues for
1806 /// returning information from TargetLowering to its clients that want to
1808 struct TargetLoweringOpt {
1815 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1817 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1819 bool LegalTypes() const { return LegalTys; }
1820 bool LegalOperations() const { return LegalOps; }
1822 bool CombineTo(SDValue O, SDValue N) {
1828 /// Check to see if the specified operand of the specified instruction is a
1829 /// constant integer. If so, check to see if there are any bits set in the
1830 /// constant that are not demanded. If so, shrink the constant and return
1832 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1834 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1835 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1836 /// generalized for targets with other types of implicit widening casts.
1837 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1841 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1842 /// result of Op are ever used downstream. If we can use this information to
1843 /// simplify Op, create a new simplified DAG node and return true, returning
1844 /// the original and new nodes in Old and New. Otherwise, analyze the
1845 /// expression and return a mask of KnownOne and KnownZero bits for the
1846 /// expression (used to simplify the caller). The KnownZero/One bits may only
1847 /// be accurate for those bits in the DemandedMask.
1848 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1849 APInt &KnownZero, APInt &KnownOne,
1850 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1852 /// Determine which of the bits specified in Mask are known to be either zero
1853 /// or one and return them in the KnownZero/KnownOne bitsets.
1854 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1857 const SelectionDAG &DAG,
1858 unsigned Depth = 0) const;
1860 /// This method can be implemented by targets that want to expose additional
1861 /// information about sign bits to the DAG Combiner.
1862 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1863 unsigned Depth = 0) const;
1865 struct DAGCombinerInfo {
1866 void *DC; // The DAG Combiner object.
1868 bool CalledByLegalizer;
1872 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1873 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1875 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1876 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1877 bool isAfterLegalizeVectorOps() const {
1878 return Level == AfterLegalizeDAG;
1880 CombineLevel getDAGCombineLevel() { return Level; }
1881 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1883 void AddToWorklist(SDNode *N);
1884 void RemoveFromWorklist(SDNode *N);
1885 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1887 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1888 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1890 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1893 /// Try to simplify a setcc built with the specified operands and cc. If it is
1894 /// unable to simplify it, return a null SDValue.
1895 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1896 ISD::CondCode Cond, bool foldBooleans,
1897 DAGCombinerInfo &DCI, SDLoc dl) const;
1899 /// Returns true (and the GlobalValue and the offset) if the node is a
1900 /// GlobalAddress + offset.
1902 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1904 /// This method will be invoked for all target nodes and for any
1905 /// target-independent nodes that the target has registered with invoke it
1908 /// The semantics are as follows:
1910 /// SDValue.Val == 0 - No change was made
1911 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1912 /// otherwise - N should be replaced by the returned Operand.
1914 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1915 /// more complex transformations.
1917 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1919 /// Return true if the target has native support for the specified value type
1920 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
1921 /// i16 is legal, but undesirable since i16 instruction encodings are longer
1922 /// and some i16 instructions are slow.
1923 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1924 // By default, assume all legal types are desirable.
1925 return isTypeLegal(VT);
1928 /// Return true if it is profitable for dag combiner to transform a floating
1929 /// point op of specified opcode to a equivalent op of an integer
1930 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
1931 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1936 /// This method query the target whether it is beneficial for dag combiner to
1937 /// promote the specified node. If true, it should return the desired
1938 /// promotion type by reference.
1939 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1943 //===--------------------------------------------------------------------===//
1944 // Lowering methods - These methods must be implemented by targets so that
1945 // the SelectionDAGBuilder code knows how to lower these.
1948 /// This hook must be implemented to lower the incoming (formal) arguments,
1949 /// described by the Ins array, into the specified DAG. The implementation
1950 /// should fill in the InVals array with legal-type argument values, and
1951 /// return the resulting token chain value.
1954 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1956 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1957 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
1958 SmallVectorImpl<SDValue> &/*InVals*/) const {
1959 llvm_unreachable("Not Implemented");
1962 struct ArgListEntry {
1971 bool isInAlloca : 1;
1972 bool isReturned : 1;
1975 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1976 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
1977 isReturned(false), Alignment(0) { }
1979 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
1981 typedef std::vector<ArgListEntry> ArgListTy;
1983 /// This structure contains all information that is necessary for lowering
1984 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
1985 /// needs to lower a call, and targets will see this struct in their LowerCall
1987 struct CallLoweringInfo {
1994 bool DoesNotReturn : 1;
1995 bool IsReturnValueUsed : 1;
1997 // IsTailCall should be modified by implementations of
1998 // TargetLowering::LowerCall that perform tail call conversions.
2001 unsigned NumFixedArgs;
2002 CallingConv::ID CallConv;
2007 ImmutableCallSite *CS;
2008 SmallVector<ISD::OutputArg, 32> Outs;
2009 SmallVector<SDValue, 32> OutVals;
2010 SmallVector<ISD::InputArg, 32> Ins;
2013 /// Constructs a call lowering context based on the ImmutableCallSite \p cs.
2014 CallLoweringInfo(SDValue chain, Type *retTy,
2015 FunctionType *FTy, bool isTailCall, SDValue callee,
2016 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
2017 ImmutableCallSite &cs)
2018 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
2019 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
2020 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
2021 DoesNotReturn(cs.doesNotReturn()),
2022 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
2023 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
2024 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
2027 /// Constructs a call lowering context based on the provided call
2029 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
2030 bool isVarArg, bool isInReg, unsigned numFixedArgs,
2031 CallingConv::ID callConv, bool isTailCall,
2032 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
2033 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
2034 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
2035 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
2036 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
2037 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
2038 Args(args), DAG(dag), DL(dl), CS(NULL) {}
2041 /// This function lowers an abstract call to a function into an actual call.
2042 /// This returns a pair of operands. The first element is the return value
2043 /// for the function (if RetTy is not VoidTy). The second element is the
2044 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2045 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2047 /// This hook must be implemented to lower calls into the the specified
2048 /// DAG. The outgoing arguments to the call are described by the Outs array,
2049 /// and the values to be returned by the call are described by the Ins
2050 /// array. The implementation should fill in the InVals array with legal-type
2051 /// return values from the call, and return the resulting token chain value.
2053 LowerCall(CallLoweringInfo &/*CLI*/,
2054 SmallVectorImpl<SDValue> &/*InVals*/) const {
2055 llvm_unreachable("Not Implemented");
2058 /// Target-specific cleanup for formal ByVal parameters.
2059 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2061 /// This hook should be implemented to check whether the return values
2062 /// described by the Outs array can fit into the return registers. If false
2063 /// is returned, an sret-demotion is performed.
2064 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2065 MachineFunction &/*MF*/, bool /*isVarArg*/,
2066 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2067 LLVMContext &/*Context*/) const
2069 // Return true by default to get preexisting behavior.
2073 /// This hook must be implemented to lower outgoing return values, described
2074 /// by the Outs array, into the specified DAG. The implementation should
2075 /// return the resulting token chain value.
2077 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2079 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2080 const SmallVectorImpl<SDValue> &/*OutVals*/,
2081 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2082 llvm_unreachable("Not Implemented");
2085 /// Return true if result of the specified node is used by a return node
2086 /// only. It also compute and return the input chain for the tail call.
2088 /// This is used to determine whether it is possible to codegen a libcall as
2089 /// tail call at legalization time.
2090 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2094 /// Return true if the target may be able emit the call instruction as a tail
2095 /// call. This is used by optimization passes to determine if it's profitable
2096 /// to duplicate return instructions to enable tailcall optimization.
2097 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2101 /// Return the type that should be used to zero or sign extend a
2102 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2103 /// convention requires the return type to be promoted, but this is not true
2104 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2105 /// calling conventions. The frontend should handle this and include all of
2106 /// the necessary information.
2107 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2108 ISD::NodeType /*ExtendKind*/) const {
2109 MVT MinVT = getRegisterType(MVT::i32);
2110 return VT.bitsLT(MinVT) ? MinVT : VT;
2113 /// Returns a 0 terminated array of registers that can be safely used as
2114 /// scratch registers.
2115 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const {
2119 /// This callback is used to prepare for a volatile or atomic load.
2120 /// It takes a chain node as input and returns the chain for the load itself.
2122 /// Having a callback like this is necessary for targets like SystemZ,
2123 /// which allows a CPU to reuse the result of a previous load indefinitely,
2124 /// even if a cache-coherent store is performed by another CPU. The default
2125 /// implementation does nothing.
2126 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2127 SelectionDAG &DAG) const {
2131 /// This callback is invoked by the type legalizer to legalize nodes with an
2132 /// illegal operand type but legal result types. It replaces the
2133 /// LowerOperation callback in the type Legalizer. The reason we can not do
2134 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2135 /// use this callback.
2137 /// TODO: Consider merging with ReplaceNodeResults.
2139 /// The target places new result values for the node in Results (their number
2140 /// and types must exactly match those of the original return values of
2141 /// the node), or leaves Results empty, which indicates that the node is not
2142 /// to be custom lowered after all.
2143 /// The default implementation calls LowerOperation.
2144 virtual void LowerOperationWrapper(SDNode *N,
2145 SmallVectorImpl<SDValue> &Results,
2146 SelectionDAG &DAG) const;
2148 /// This callback is invoked for operations that are unsupported by the
2149 /// target, which are registered to use 'custom' lowering, and whose defined
2150 /// values are all legal. If the target has no operations that require custom
2151 /// lowering, it need not implement this. The default implementation of this
2153 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2155 /// This callback is invoked when a node result type is illegal for the
2156 /// target, and the operation was registered to use 'custom' lowering for that
2157 /// result type. The target places new result values for the node in Results
2158 /// (their number and types must exactly match those of the original return
2159 /// values of the node), or leaves Results empty, which indicates that the
2160 /// node is not to be custom lowered after all.
2162 /// If the target has no operations that require custom lowering, it need not
2163 /// implement this. The default implementation aborts.
2164 virtual void ReplaceNodeResults(SDNode * /*N*/,
2165 SmallVectorImpl<SDValue> &/*Results*/,
2166 SelectionDAG &/*DAG*/) const {
2167 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2170 /// This method returns the name of a target specific DAG node.
2171 virtual const char *getTargetNodeName(unsigned Opcode) const;
2173 /// This method returns a target specific FastISel object, or null if the
2174 /// target does not support "fast" ISel.
2175 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2176 const TargetLibraryInfo *) const {
2181 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2182 SelectionDAG &DAG) const;
2184 //===--------------------------------------------------------------------===//
2185 // Inline Asm Support hooks
2188 /// This hook allows the target to expand an inline asm call to be explicit
2189 /// llvm code if it wants to. This is useful for turning simple inline asms
2190 /// into LLVM intrinsics, which gives the compiler more information about the
2191 /// behavior of the code.
2192 virtual bool ExpandInlineAsm(CallInst *) const {
2196 enum ConstraintType {
2197 C_Register, // Constraint represents specific register(s).
2198 C_RegisterClass, // Constraint represents any of register(s) in class.
2199 C_Memory, // Memory constraint.
2200 C_Other, // Something else.
2201 C_Unknown // Unsupported constraint.
2204 enum ConstraintWeight {
2206 CW_Invalid = -1, // No match.
2207 CW_Okay = 0, // Acceptable.
2208 CW_Good = 1, // Good weight.
2209 CW_Better = 2, // Better weight.
2210 CW_Best = 3, // Best weight.
2212 // Well-known weights.
2213 CW_SpecificReg = CW_Okay, // Specific register operands.
2214 CW_Register = CW_Good, // Register operands.
2215 CW_Memory = CW_Better, // Memory operands.
2216 CW_Constant = CW_Best, // Constant operand.
2217 CW_Default = CW_Okay // Default or don't know type.
2220 /// This contains information for each constraint that we are lowering.
2221 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2222 /// This contains the actual string for the code, like "m". TargetLowering
2223 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2224 /// matches the operand.
2225 std::string ConstraintCode;
2227 /// Information about the constraint code, e.g. Register, RegisterClass,
2228 /// Memory, Other, Unknown.
2229 TargetLowering::ConstraintType ConstraintType;
2231 /// If this is the result output operand or a clobber, this is null,
2232 /// otherwise it is the incoming operand to the CallInst. This gets
2233 /// modified as the asm is processed.
2234 Value *CallOperandVal;
2236 /// The ValueType for the operand value.
2239 /// Return true of this is an input operand that is a matching constraint
2241 bool isMatchingInputConstraint() const;
2243 /// If this is an input matching constraint, this method returns the output
2244 /// operand it matches.
2245 unsigned getMatchedOperand() const;
2247 /// Copy constructor for copying from an AsmOperandInfo.
2248 AsmOperandInfo(const AsmOperandInfo &info)
2249 : InlineAsm::ConstraintInfo(info),
2250 ConstraintCode(info.ConstraintCode),
2251 ConstraintType(info.ConstraintType),
2252 CallOperandVal(info.CallOperandVal),
2253 ConstraintVT(info.ConstraintVT) {
2256 /// Copy constructor for copying from a ConstraintInfo.
2257 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2258 : InlineAsm::ConstraintInfo(info),
2259 ConstraintType(TargetLowering::C_Unknown),
2260 CallOperandVal(0), ConstraintVT(MVT::Other) {
2264 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2266 /// Split up the constraint string from the inline assembly value into the
2267 /// specific constraints and their prefixes, and also tie in the associated
2268 /// operand values. If this returns an empty vector, and if the constraint
2269 /// string itself isn't empty, there was an error parsing.
2270 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2272 /// Examine constraint type and operand type and determine a weight value.
2273 /// The operand object must already have been set up with the operand type.
2274 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2275 AsmOperandInfo &info, int maIndex) const;
2277 /// Examine constraint string and operand type and determine a weight value.
2278 /// The operand object must already have been set up with the operand type.
2279 virtual ConstraintWeight getSingleConstraintMatchWeight(
2280 AsmOperandInfo &info, const char *constraint) const;
2282 /// Determines the constraint code and constraint type to use for the specific
2283 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2284 /// If the actual operand being passed in is available, it can be passed in as
2285 /// Op, otherwise an empty SDValue can be passed.
2286 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2288 SelectionDAG *DAG = 0) const;
2290 /// Given a constraint, return the type of constraint it is for this target.
2291 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2293 /// Given a physical register constraint (e.g. {edx}), return the register
2294 /// number and the register class for the register.
2296 /// Given a register class constraint, like 'r', if this corresponds directly
2297 /// to an LLVM register class, return a register of 0 and the register class
2300 /// This should only be used for C_Register constraints. On error, this
2301 /// returns a register number of 0 and a null register class pointer..
2302 virtual std::pair<unsigned, const TargetRegisterClass*>
2303 getRegForInlineAsmConstraint(const std::string &Constraint,
2306 /// Try to replace an X constraint, which matches anything, with another that
2307 /// has more specific requirements based on the type of the corresponding
2308 /// operand. This returns null if there is no replacement to make.
2309 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2311 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2312 /// add anything to Ops.
2313 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2314 std::vector<SDValue> &Ops,
2315 SelectionDAG &DAG) const;
2317 //===--------------------------------------------------------------------===//
2318 // Div utility functions
2320 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2321 SelectionDAG &DAG) const;
2322 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2323 std::vector<SDNode*> *Created) const;
2324 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2325 std::vector<SDNode*> *Created) const;
2327 //===--------------------------------------------------------------------===//
2328 // Instruction Emitting Hooks
2331 /// This method should be implemented by targets that mark instructions with
2332 /// the 'usesCustomInserter' flag. These instructions are special in various
2333 /// ways, which require special support to insert. The specified MachineInstr
2334 /// is created but not inserted into any basic blocks, and this method is
2335 /// called to expand it into a sequence of instructions, potentially also
2336 /// creating new basic blocks and control flow.
2337 virtual MachineBasicBlock *
2338 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2340 /// This method should be implemented by targets that mark instructions with
2341 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2342 /// instruction selection by target hooks. e.g. To fill in optional defs for
2343 /// ARM 's' setting instructions.
2345 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2348 /// Given an LLVM IR type and return type attributes, compute the return value
2349 /// EVTs and flags, and optionally also the offsets, if the return value is
2350 /// being lowered to memory.
2351 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2352 SmallVectorImpl<ISD::OutputArg> &Outs,
2353 const TargetLowering &TLI);
2355 } // end llvm namespace