1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they
130 /// should expand to.
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
164 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
166 bool isBigEndian() const { return !IsLittleEndian; }
167 bool isLittleEndian() const { return IsLittleEndian; }
168 virtual bool useSoftFloat() const { return false; }
170 /// Return the pointer type for the given address space, defaults to
171 /// the pointer type from the data layout.
172 /// FIXME: The default needs to be removed once all the code is updated.
173 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
174 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
175 unsigned getPointerTypeSizeInBits(Type *Ty) const;
176 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
178 EVT getShiftAmountTy(EVT LHSTy) const;
180 /// Returns the type to be used for the index operand of:
181 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
182 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
183 virtual MVT getVectorIdxTy() const {
184 return getPointerTy();
187 /// Return true if the select operation is expensive for this target.
188 bool isSelectExpensive() const { return SelectIsExpensive; }
190 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
194 /// Return true if multiple condition registers are available.
195 bool hasMultipleConditionRegisters() const {
196 return HasMultipleConditionRegisters;
199 /// Return true if the target has BitExtract instructions.
200 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
202 /// Return the preferred vector type legalization action.
203 virtual TargetLoweringBase::LegalizeTypeAction
204 getPreferredVectorAction(EVT VT) const {
205 // The default action for one element vectors is to scalarize
206 if (VT.getVectorNumElements() == 1)
207 return TypeScalarizeVector;
208 // The default action for other vectors is to promote
209 return TypePromoteInteger;
212 // There are two general methods for expanding a BUILD_VECTOR node:
213 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
215 // 2. Build the vector on the stack and then load it.
216 // If this function returns true, then method (1) will be used, subject to
217 // the constraint that all of the necessary shuffles are legal (as determined
218 // by isShuffleMaskLegal). If this function returns false, then method (2) is
219 // always used. The vector type, and the number of defined values, are
222 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
223 unsigned DefinedValues) const {
224 return DefinedValues < 3;
227 /// Return true if integer divide is usually cheaper than a sequence of
228 /// several shifts, adds, and multiplies for this target.
229 bool isIntDivCheap() const { return IntDivIsCheap; }
231 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
232 bool isFsqrtCheap() const {
236 /// Returns true if target has indicated at least one type should be bypassed.
237 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
239 /// Returns map of slow types for division or remainder with corresponding
241 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
242 return BypassSlowDivWidths;
245 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
246 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
248 /// Return true if Flow Control is an expensive operation that should be
250 bool isJumpExpensive() const { return JumpIsExpensive; }
252 /// Return true if selects are only cheaper than branches if the branch is
253 /// unlikely to be predicted right.
254 bool isPredictableSelectExpensive() const {
255 return PredictableSelectIsExpensive;
258 /// isLoadBitCastBeneficial() - Return true if the following transform
260 /// fold (conv (load x)) -> (load (conv*)x)
261 /// On architectures that don't natively support some vector loads
262 /// efficiently, casting the load to a smaller vector of larger types and
263 /// loading is more efficient, however, this can be undone by optimizations in
265 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
266 EVT /* Bitcast */) const {
270 /// Return true if it is expected to be cheaper to do a store of a non-zero
271 /// vector constant with the given size and type for the address space than to
272 /// store the individual scalar element constants.
273 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
275 unsigned AddrSpace) const {
279 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
280 virtual bool isCheapToSpeculateCttz() const {
284 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
285 virtual bool isCheapToSpeculateCtlz() const {
289 /// \brief Return if the target supports combining a
292 /// %andResult = and %val1, #imm-with-one-bit-set;
293 /// %icmpResult = icmp %andResult, 0
294 /// br i1 %icmpResult, label %dest1, label %dest2
296 /// into a single machine instruction of a form like:
298 /// brOnBitSet %register, #bitNumber, dest
300 bool isMaskAndBranchFoldingLegal() const {
301 return MaskAndBranchFoldingIsLegal;
304 /// \brief Return true if the target wants to use the optimization that
305 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
306 /// promotedInst1(...(promotedInstN(ext(load)))).
307 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
309 /// Return true if the target can combine store(extractelement VectorTy,
311 /// \p Cost[out] gives the cost of that transformation when this is true.
312 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
313 unsigned &Cost) const {
317 /// Return true if target supports floating point exceptions.
318 bool hasFloatingPointExceptions() const {
319 return HasFloatingPointExceptions;
322 /// Return true if target always beneficiates from combining into FMA for a
323 /// given value type. This must typically return false on targets where FMA
324 /// takes more cycles to execute than FADD.
325 virtual bool enableAggressiveFMAFusion(EVT VT) const {
329 /// Return the ValueType of the result of SETCC operations.
330 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
332 /// Return the ValueType for comparison libcalls. Comparions libcalls include
333 /// floating point comparion calls, and Ordered/Unordered check calls on
334 /// floating point numbers.
336 MVT::SimpleValueType getCmpLibcallReturnType() const;
338 /// For targets without i1 registers, this gives the nature of the high-bits
339 /// of boolean values held in types wider than i1.
341 /// "Boolean values" are special true/false values produced by nodes like
342 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
343 /// Not to be confused with general values promoted from i1. Some cpus
344 /// distinguish between vectors of boolean and scalars; the isVec parameter
345 /// selects between the two kinds. For example on X86 a scalar boolean should
346 /// be zero extended from i1, while the elements of a vector of booleans
347 /// should be sign extended from i1.
349 /// Some cpus also treat floating point types the same way as they treat
350 /// vectors instead of the way they treat scalars.
351 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
353 return BooleanVectorContents;
354 return isFloat ? BooleanFloatContents : BooleanContents;
357 BooleanContent getBooleanContents(EVT Type) const {
358 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
361 /// Return target scheduling preference.
362 Sched::Preference getSchedulingPreference() const {
363 return SchedPreferenceInfo;
366 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
367 /// for different nodes. This function returns the preference (or none) for
369 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
373 /// Return the register class that should be used for the specified value
375 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
376 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
377 assert(RC && "This value type is not natively supported!");
381 /// Return the 'representative' register class for the specified value
384 /// The 'representative' register class is the largest legal super-reg
385 /// register class for the register class of the value type. For example, on
386 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
387 /// register class is GR64 on x86_64.
388 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
389 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
393 /// Return the cost of the 'representative' register class for the specified
395 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
396 return RepRegClassCostForVT[VT.SimpleTy];
399 /// Return true if the target has native support for the specified value type.
400 /// This means that it has a register that directly holds it without
401 /// promotions or expansions.
402 bool isTypeLegal(EVT VT) const {
403 assert(!VT.isSimple() ||
404 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
405 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
408 class ValueTypeActionImpl {
409 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
410 /// that indicates how instruction selection should deal with the type.
411 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
414 ValueTypeActionImpl() {
415 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
418 LegalizeTypeAction getTypeAction(MVT VT) const {
419 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
422 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
423 unsigned I = VT.SimpleTy;
424 ValueTypeActions[I] = Action;
428 const ValueTypeActionImpl &getValueTypeActions() const {
429 return ValueTypeActions;
432 /// Return how we should legalize values of this type, either it is already
433 /// legal (return 'Legal') or we need to promote it to a larger type (return
434 /// 'Promote'), or we need to expand it into multiple registers of smaller
435 /// integer type (return 'Expand'). 'Custom' is not an option.
436 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
437 return getTypeConversion(Context, VT).first;
439 LegalizeTypeAction getTypeAction(MVT VT) const {
440 return ValueTypeActions.getTypeAction(VT);
443 /// For types supported by the target, this is an identity function. For
444 /// types that must be promoted to larger types, this returns the larger type
445 /// to promote to. For integer types that are larger than the largest integer
446 /// register, this contains one step in the expansion to get to the smaller
447 /// register. For illegal floating point types, this returns the integer type
449 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
450 return getTypeConversion(Context, VT).second;
453 /// For types supported by the target, this is an identity function. For
454 /// types that must be expanded (i.e. integer types that are larger than the
455 /// largest integer register or illegal floating point types), this returns
456 /// the largest legal type it will be expanded to.
457 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
458 assert(!VT.isVector());
460 switch (getTypeAction(Context, VT)) {
463 case TypeExpandInteger:
464 VT = getTypeToTransformTo(Context, VT);
467 llvm_unreachable("Type is not legal nor is it to be expanded!");
472 /// Vector types are broken down into some number of legal first class types.
473 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
474 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
475 /// turns into 4 EVT::i32 values with both PPC and X86.
477 /// This method returns the number of registers needed, and the VT for each
478 /// register. It also returns the VT and quantity of the intermediate values
479 /// before they are promoted/expanded.
480 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
482 unsigned &NumIntermediates,
483 MVT &RegisterVT) const;
485 struct IntrinsicInfo {
486 unsigned opc; // target opcode
487 EVT memVT; // memory VT
488 const Value* ptrVal; // value representing memory location
489 int offset; // offset off of ptrVal
490 unsigned size; // the size of the memory location
491 // (taken from memVT if zero)
492 unsigned align; // alignment
493 bool vol; // is volatile?
494 bool readMem; // reads memory?
495 bool writeMem; // writes memory?
497 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
498 vol(false), readMem(false), writeMem(false) {}
501 /// Given an intrinsic, checks if on the target the intrinsic will need to map
502 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
503 /// true and store the intrinsic information into the IntrinsicInfo that was
504 /// passed to the function.
505 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
506 unsigned /*Intrinsic*/) const {
510 /// Returns true if the target can instruction select the specified FP
511 /// immediate natively. If false, the legalizer will materialize the FP
512 /// immediate as a load from a constant pool.
513 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
517 /// Targets can use this to indicate that they only support *some*
518 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
519 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
521 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
526 /// Returns true if the operation can trap for the value type.
528 /// VT must be a legal type. By default, we optimistically assume most
529 /// operations don't trap except for divide and remainder.
530 virtual bool canOpTrap(unsigned Op, EVT VT) const;
532 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
533 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
534 /// a VAND with a constant pool entry.
535 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
540 /// Return how this operation should be treated: either it is legal, needs to
541 /// be promoted to a larger size, needs to be expanded to some other code
542 /// sequence, or the target has a custom expander for it.
543 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
544 if (VT.isExtended()) return Expand;
545 // If a target-specific SDNode requires legalization, require the target
546 // to provide custom legalization for it.
547 if (Op > array_lengthof(OpActions[0])) return Custom;
548 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
549 return (LegalizeAction)OpActions[I][Op];
552 /// Return true if the specified operation is legal on this target or can be
553 /// made legal with custom lowering. This is used to help guide high-level
554 /// lowering decisions.
555 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
556 return (VT == MVT::Other || isTypeLegal(VT)) &&
557 (getOperationAction(Op, VT) == Legal ||
558 getOperationAction(Op, VT) == Custom);
561 /// Return true if the specified operation is legal on this target or can be
562 /// made legal using promotion. This is used to help guide high-level lowering
564 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
565 return (VT == MVT::Other || isTypeLegal(VT)) &&
566 (getOperationAction(Op, VT) == Legal ||
567 getOperationAction(Op, VT) == Promote);
570 /// Return true if the specified operation is illegal on this target or
571 /// unlikely to be made legal with custom lowering. This is used to help guide
572 /// high-level lowering decisions.
573 bool isOperationExpand(unsigned Op, EVT VT) const {
574 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
577 /// Return true if the specified operation is legal on this target.
578 bool isOperationLegal(unsigned Op, EVT VT) const {
579 return (VT == MVT::Other || isTypeLegal(VT)) &&
580 getOperationAction(Op, VT) == Legal;
583 /// Return how this load with extension should be treated: either it is legal,
584 /// needs to be promoted to a larger size, needs to be expanded to some other
585 /// code sequence, or the target has a custom expander for it.
586 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
588 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
589 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
590 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
591 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
592 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
593 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
596 /// Return true if the specified load with extension is legal on this target.
597 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
598 return ValVT.isSimple() && MemVT.isSimple() &&
599 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
602 /// Return true if the specified load with extension is legal or custom
604 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
605 return ValVT.isSimple() && MemVT.isSimple() &&
606 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
607 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
610 /// Return how this store with truncation should be treated: either it is
611 /// legal, needs to be promoted to a larger size, needs to be expanded to some
612 /// other code sequence, or the target has a custom expander for it.
613 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
614 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
615 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
616 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
617 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
618 "Table isn't big enough!");
619 return (LegalizeAction)TruncStoreActions[ValI][MemI];
622 /// Return true if the specified store with truncation is legal on this
624 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
625 return isTypeLegal(ValVT) && MemVT.isSimple() &&
626 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
629 /// Return how the indexed load should be treated: either it is legal, needs
630 /// to be promoted to a larger size, needs to be expanded to some other code
631 /// sequence, or the target has a custom expander for it.
633 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
634 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
635 "Table isn't big enough!");
636 unsigned Ty = (unsigned)VT.SimpleTy;
637 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
640 /// Return true if the specified indexed load is legal on this target.
641 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
642 return VT.isSimple() &&
643 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
644 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
647 /// Return how the indexed store should be treated: either it is legal, needs
648 /// to be promoted to a larger size, needs to be expanded to some other code
649 /// sequence, or the target has a custom expander for it.
651 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
652 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
653 "Table isn't big enough!");
654 unsigned Ty = (unsigned)VT.SimpleTy;
655 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
658 /// Return true if the specified indexed load is legal on this target.
659 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
660 return VT.isSimple() &&
661 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
662 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
665 /// Return how the condition code should be treated: either it is legal, needs
666 /// to be expanded to some other code sequence, or the target has a custom
669 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
670 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
671 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
672 "Table isn't big enough!");
673 // See setCondCodeAction for how this is encoded.
674 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
675 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
676 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
677 assert(Action != Promote && "Can't promote condition code!");
681 /// Return true if the specified condition code is legal on this target.
682 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
684 getCondCodeAction(CC, VT) == Legal ||
685 getCondCodeAction(CC, VT) == Custom;
689 /// If the action for this operation is to promote, this method returns the
690 /// ValueType to promote to.
691 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
692 assert(getOperationAction(Op, VT) == Promote &&
693 "This operation isn't promoted!");
695 // See if this has an explicit type specified.
696 std::map<std::pair<unsigned, MVT::SimpleValueType>,
697 MVT::SimpleValueType>::const_iterator PTTI =
698 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
699 if (PTTI != PromoteToType.end()) return PTTI->second;
701 assert((VT.isInteger() || VT.isFloatingPoint()) &&
702 "Cannot autopromote this type, add it with AddPromotedToType.");
706 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
707 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
708 "Didn't find type to promote to!");
709 } while (!isTypeLegal(NVT) ||
710 getOperationAction(Op, NVT) == Promote);
714 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
715 /// operations except for the pointer size. If AllowUnknown is true, this
716 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
717 /// otherwise it will assert.
718 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
719 // Lower scalar pointers to native pointer types.
720 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
721 return getPointerTy(PTy->getAddressSpace());
723 if (Ty->isVectorTy()) {
724 VectorType *VTy = cast<VectorType>(Ty);
725 Type *Elm = VTy->getElementType();
726 // Lower vectors of pointers to native pointer types.
727 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
728 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
729 Elm = PointerTy.getTypeForEVT(Ty->getContext());
732 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
733 VTy->getNumElements());
735 return EVT::getEVT(Ty, AllowUnknown);
738 /// Return the MVT corresponding to this LLVM type. See getValueType.
739 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
740 return getValueType(Ty, AllowUnknown).getSimpleVT();
743 /// Return the desired alignment for ByVal or InAlloca aggregate function
744 /// arguments in the caller parameter area. This is the actual alignment, not
746 virtual unsigned getByValTypeAlignment(Type *Ty) const;
748 /// Return the type of registers that this ValueType will eventually require.
749 MVT getRegisterType(MVT VT) const {
750 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
751 return RegisterTypeForVT[VT.SimpleTy];
754 /// Return the type of registers that this ValueType will eventually require.
755 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
757 assert((unsigned)VT.getSimpleVT().SimpleTy <
758 array_lengthof(RegisterTypeForVT));
759 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
764 unsigned NumIntermediates;
765 (void)getVectorTypeBreakdown(Context, VT, VT1,
766 NumIntermediates, RegisterVT);
769 if (VT.isInteger()) {
770 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
772 llvm_unreachable("Unsupported extended type!");
775 /// Return the number of registers that this ValueType will eventually
778 /// This is one for any types promoted to live in larger registers, but may be
779 /// more than one for types (like i64) that are split into pieces. For types
780 /// like i140, which are first promoted then expanded, it is the number of
781 /// registers needed to hold all the bits of the original type. For an i140
782 /// on a 32 bit machine this means 5 registers.
783 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
785 assert((unsigned)VT.getSimpleVT().SimpleTy <
786 array_lengthof(NumRegistersForVT));
787 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
792 unsigned NumIntermediates;
793 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
795 if (VT.isInteger()) {
796 unsigned BitWidth = VT.getSizeInBits();
797 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
798 return (BitWidth + RegWidth - 1) / RegWidth;
800 llvm_unreachable("Unsupported extended type!");
803 /// If true, then instruction selection should seek to shrink the FP constant
804 /// of the specified type to a smaller type in order to save space and / or
806 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
808 // Return true if it is profitable to reduce the given load node to a smaller
811 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
812 virtual bool shouldReduceLoadWidth(SDNode *Load,
813 ISD::LoadExtType ExtTy,
818 /// When splitting a value of the specified type into parts, does the Lo
819 /// or Hi part come first? This usually follows the endianness, except
820 /// for ppcf128, where the Hi part always comes first.
821 bool hasBigEndianPartOrdering(EVT VT) const {
822 return isBigEndian() || VT == MVT::ppcf128;
825 /// If true, the target has custom DAG combine transformations that it can
826 /// perform for the specified node.
827 bool hasTargetDAGCombine(ISD::NodeType NT) const {
828 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
829 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
832 /// \brief Get maximum # of store operations permitted for llvm.memset
834 /// This function returns the maximum number of store operations permitted
835 /// to replace a call to llvm.memset. The value is set by the target at the
836 /// performance threshold for such a replacement. If OptSize is true,
837 /// return the limit for functions that have OptSize attribute.
838 unsigned getMaxStoresPerMemset(bool OptSize) const {
839 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
842 /// \brief Get maximum # of store operations permitted for llvm.memcpy
844 /// This function returns the maximum number of store operations permitted
845 /// to replace a call to llvm.memcpy. The value is set by the target at the
846 /// performance threshold for such a replacement. If OptSize is true,
847 /// return the limit for functions that have OptSize attribute.
848 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
849 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
852 /// \brief Get maximum # of store operations permitted for llvm.memmove
854 /// This function returns the maximum number of store operations permitted
855 /// to replace a call to llvm.memmove. The value is set by the target at the
856 /// performance threshold for such a replacement. If OptSize is true,
857 /// return the limit for functions that have OptSize attribute.
858 unsigned getMaxStoresPerMemmove(bool OptSize) const {
859 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
862 /// \brief Determine if the target supports unaligned memory accesses.
864 /// This function returns true if the target allows unaligned memory accesses
865 /// of the specified type in the given address space. If true, it also returns
866 /// whether the unaligned memory access is "fast" in the last argument by
867 /// reference. This is used, for example, in situations where an array
868 /// copy/move/set is converted to a sequence of store operations. Its use
869 /// helps to ensure that such replacements don't generate code that causes an
870 /// alignment error (trap) on the target machine.
871 virtual bool allowsMisalignedMemoryAccesses(EVT,
872 unsigned AddrSpace = 0,
874 bool * /*Fast*/ = nullptr) const {
878 /// Returns the target specific optimal type for load and store operations as
879 /// a result of memset, memcpy, and memmove lowering.
881 /// If DstAlign is zero that means it's safe to destination alignment can
882 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
883 /// a need to check it against alignment requirement, probably because the
884 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
885 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
886 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
887 /// does not need to be loaded. It returns EVT::Other if the type should be
888 /// determined using generic target-independent logic.
889 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
890 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
893 bool /*MemcpyStrSrc*/,
894 MachineFunction &/*MF*/) const {
898 /// Returns true if it's safe to use load / store of the specified type to
899 /// expand memcpy / memset inline.
901 /// This is mostly true for all types except for some special cases. For
902 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
903 /// fstpl which also does type conversion. Note the specified type doesn't
904 /// have to be legal as the hook is used before type legalization.
905 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
907 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
908 bool usesUnderscoreSetJmp() const {
909 return UseUnderscoreSetJmp;
912 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
913 bool usesUnderscoreLongJmp() const {
914 return UseUnderscoreLongJmp;
917 /// Return integer threshold on number of blocks to use jump tables rather
918 /// than if sequence.
919 int getMinimumJumpTableEntries() const {
920 return MinimumJumpTableEntries;
923 /// If a physical register, this specifies the register that
924 /// llvm.savestack/llvm.restorestack should save and restore.
925 unsigned getStackPointerRegisterToSaveRestore() const {
926 return StackPointerRegisterToSaveRestore;
929 /// If a physical register, this returns the register that receives the
930 /// exception address on entry to a landing pad.
931 unsigned getExceptionPointerRegister() const {
932 return ExceptionPointerRegister;
935 /// If a physical register, this returns the register that receives the
936 /// exception typeid on entry to a landing pad.
937 unsigned getExceptionSelectorRegister() const {
938 return ExceptionSelectorRegister;
941 /// Returns the target's jmp_buf size in bytes (if never set, the default is
943 unsigned getJumpBufSize() const {
947 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
949 unsigned getJumpBufAlignment() const {
950 return JumpBufAlignment;
953 /// Return the minimum stack alignment of an argument.
954 unsigned getMinStackArgumentAlignment() const {
955 return MinStackArgumentAlignment;
958 /// Return the minimum function alignment.
959 unsigned getMinFunctionAlignment() const {
960 return MinFunctionAlignment;
963 /// Return the preferred function alignment.
964 unsigned getPrefFunctionAlignment() const {
965 return PrefFunctionAlignment;
968 /// Return the preferred loop alignment.
969 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
970 return PrefLoopAlignment;
973 /// Return whether the DAG builder should automatically insert fences and
974 /// reduce ordering for atomics.
975 bool getInsertFencesForAtomic() const {
976 return InsertFencesForAtomic;
979 /// Return true if the target stores stack protector cookies at a fixed offset
980 /// in some non-standard address space, and populates the address space and
981 /// offset as appropriate.
982 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
983 unsigned &/*Offset*/) const {
987 /// Returns true if a cast between SrcAS and DestAS is a noop.
988 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
992 /// Return true if the pointer arguments to CI should be aligned by aligning
993 /// the object whose address is being passed. If so then MinSize is set to the
994 /// minimum size the object must be to be aligned and PrefAlign is set to the
995 /// preferred alignment.
996 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
997 unsigned & /*PrefAlign*/) const {
1001 //===--------------------------------------------------------------------===//
1002 /// \name Helpers for TargetTransformInfo implementations
1005 /// Get the ISD node that corresponds to the Instruction class opcode.
1006 int InstructionOpcodeToISD(unsigned Opcode) const;
1008 /// Estimate the cost of type-legalization and the legalized type.
1009 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
1013 //===--------------------------------------------------------------------===//
1014 /// \name Helpers for atomic expansion.
1017 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1018 /// and expand AtomicCmpXchgInst.
1019 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1021 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1022 /// corresponding pointee type. This may entail some non-trivial operations to
1023 /// truncate or reconstruct types that will be illegal in the backend. See
1024 /// ARMISelLowering for an example implementation.
1025 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1026 AtomicOrdering Ord) const {
1027 llvm_unreachable("Load linked unimplemented on this target");
1030 /// Perform a store-conditional operation to Addr. Return the status of the
1031 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1032 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1033 Value *Addr, AtomicOrdering Ord) const {
1034 llvm_unreachable("Store conditional unimplemented on this target");
1037 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1038 /// It is called by AtomicExpandPass before expanding an
1039 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1040 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1041 /// This function should either return a nullptr, or a pointer to an IR-level
1042 /// Instruction*. Even complex fence sequences can be represented by a
1043 /// single Instruction* through an intrinsic to be lowered later.
1044 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1045 /// Backends should override this method to produce target-specific intrinsic
1046 /// for their fences.
1047 /// FIXME: Please note that the default implementation here in terms of
1048 /// IR-level fences exists for historical/compatibility reasons and is
1049 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1050 /// consistency. For example, consider the following example:
1051 /// atomic<int> x = y = 0;
1052 /// int r1, r2, r3, r4;
1063 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1064 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1065 /// IR-level fences can prevent it.
1067 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1068 AtomicOrdering Ord, bool IsStore,
1069 bool IsLoad) const {
1070 if (!getInsertFencesForAtomic())
1073 if (isAtLeastRelease(Ord) && IsStore)
1074 return Builder.CreateFence(Ord);
1079 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1080 AtomicOrdering Ord, bool IsStore,
1081 bool IsLoad) const {
1082 if (!getInsertFencesForAtomic())
1085 if (isAtLeastAcquire(Ord))
1086 return Builder.CreateFence(Ord);
1092 /// Returns true if the given (atomic) store should be expanded by the
1093 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1094 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1098 /// Returns true if arguments should be sign-extended in lib calls.
1099 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1103 /// Returns true if the given (atomic) load should be expanded by the
1104 /// IR-level AtomicExpand pass into a load-linked instruction
1105 /// (through emitLoadLinked()).
1106 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1108 /// Returns how the IR-level AtomicExpand pass should expand the given
1109 /// AtomicRMW, if at all. Default is to never expand.
1110 virtual AtomicRMWExpansionKind
1111 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1112 return AtomicRMWExpansionKind::None;
1115 /// On some platforms, an AtomicRMW that never actually modifies the value
1116 /// (such as fetch_add of 0) can be turned into a fence followed by an
1117 /// atomic load. This may sound useless, but it makes it possible for the
1118 /// processor to keep the cacheline shared, dramatically improving
1119 /// performance. And such idempotent RMWs are useful for implementing some
1120 /// kinds of locks, see for example (justification + benchmarks):
1121 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1122 /// This method tries doing that transformation, returning the atomic load if
1123 /// it succeeds, and nullptr otherwise.
1124 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1125 /// another round of expansion.
1127 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1131 /// Returns true if we should normalize
1132 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1133 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1134 /// that it saves us from materializing N0 and N1 in an integer register.
1135 /// Targets that are able to perform and/or on flags should return false here.
1136 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1138 // If a target has multiple condition registers, then it likely has logical
1139 // operations on those registers.
1140 if (hasMultipleConditionRegisters())
1142 // Only do the transform if the value won't be split into multiple
1144 LegalizeTypeAction Action = getTypeAction(Context, VT);
1145 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1146 Action != TypeSplitVector;
1149 //===--------------------------------------------------------------------===//
1150 // TargetLowering Configuration Methods - These methods should be invoked by
1151 // the derived class constructor to configure this object for the target.
1154 /// Specify how the target extends the result of integer and floating point
1155 /// boolean values from i1 to a wider type. See getBooleanContents.
1156 void setBooleanContents(BooleanContent Ty) {
1157 BooleanContents = Ty;
1158 BooleanFloatContents = Ty;
1161 /// Specify how the target extends the result of integer and floating point
1162 /// boolean values from i1 to a wider type. See getBooleanContents.
1163 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1164 BooleanContents = IntTy;
1165 BooleanFloatContents = FloatTy;
1168 /// Specify how the target extends the result of a vector boolean value from a
1169 /// vector of i1 to a wider type. See getBooleanContents.
1170 void setBooleanVectorContents(BooleanContent Ty) {
1171 BooleanVectorContents = Ty;
1174 /// Specify the target scheduling preference.
1175 void setSchedulingPreference(Sched::Preference Pref) {
1176 SchedPreferenceInfo = Pref;
1179 /// Indicate whether this target prefers to use _setjmp to implement
1180 /// llvm.setjmp or the version without _. Defaults to false.
1181 void setUseUnderscoreSetJmp(bool Val) {
1182 UseUnderscoreSetJmp = Val;
1185 /// Indicate whether this target prefers to use _longjmp to implement
1186 /// llvm.longjmp or the version without _. Defaults to false.
1187 void setUseUnderscoreLongJmp(bool Val) {
1188 UseUnderscoreLongJmp = Val;
1191 /// Indicate the number of blocks to generate jump tables rather than if
1193 void setMinimumJumpTableEntries(int Val) {
1194 MinimumJumpTableEntries = Val;
1197 /// If set to a physical register, this specifies the register that
1198 /// llvm.savestack/llvm.restorestack should save and restore.
1199 void setStackPointerRegisterToSaveRestore(unsigned R) {
1200 StackPointerRegisterToSaveRestore = R;
1203 /// If set to a physical register, this sets the register that receives the
1204 /// exception address on entry to a landing pad.
1205 void setExceptionPointerRegister(unsigned R) {
1206 ExceptionPointerRegister = R;
1209 /// If set to a physical register, this sets the register that receives the
1210 /// exception typeid on entry to a landing pad.
1211 void setExceptionSelectorRegister(unsigned R) {
1212 ExceptionSelectorRegister = R;
1215 /// Tells the code generator not to expand operations into sequences that use
1216 /// the select operations if possible.
1217 void setSelectIsExpensive(bool isExpensive = true) {
1218 SelectIsExpensive = isExpensive;
1221 /// Tells the code generator that the target has multiple (allocatable)
1222 /// condition registers that can be used to store the results of comparisons
1223 /// for use by selects and conditional branches. With multiple condition
1224 /// registers, the code generator will not aggressively sink comparisons into
1225 /// the blocks of their users.
1226 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1227 HasMultipleConditionRegisters = hasManyRegs;
1230 /// Tells the code generator that the target has BitExtract instructions.
1231 /// The code generator will aggressively sink "shift"s into the blocks of
1232 /// their users if the users will generate "and" instructions which can be
1233 /// combined with "shift" to BitExtract instructions.
1234 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1235 HasExtractBitsInsn = hasExtractInsn;
1238 /// Tells the code generator not to expand sequence of operations into a
1239 /// separate sequences that increases the amount of flow control.
1240 void setJumpIsExpensive(bool isExpensive = true) {
1241 JumpIsExpensive = isExpensive;
1244 /// Tells the code generator that integer divide is expensive, and if
1245 /// possible, should be replaced by an alternate sequence of instructions not
1246 /// containing an integer divide.
1247 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1249 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1250 /// with an alternative sequence of instructions.
1251 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1253 /// Tells the code generator that this target supports floating point
1254 /// exceptions and cares about preserving floating point exception behavior.
1255 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1256 HasFloatingPointExceptions = FPExceptions;
1259 /// Tells the code generator which bitwidths to bypass.
1260 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1261 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1264 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1265 /// signed divide by power of two; let the target handle it.
1266 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1268 /// Add the specified register class as an available regclass for the
1269 /// specified value type. This indicates the selector can handle values of
1270 /// that class natively.
1271 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1272 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1273 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1274 RegClassForVT[VT.SimpleTy] = RC;
1277 /// Remove all register classes.
1278 void clearRegisterClasses() {
1279 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1281 AvailableRegClasses.clear();
1284 /// \brief Remove all operation actions.
1285 void clearOperationActions() {
1288 /// Return the largest legal super-reg register class of the register class
1289 /// for the specified type and its associated "cost".
1290 virtual std::pair<const TargetRegisterClass *, uint8_t>
1291 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1293 /// Once all of the register classes are added, this allows us to compute
1294 /// derived properties we expose.
1295 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1297 /// Indicate that the specified operation does not work with the specified
1298 /// type and indicate what to do about it.
1299 void setOperationAction(unsigned Op, MVT VT,
1300 LegalizeAction Action) {
1301 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1302 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1305 /// Indicate that the specified load with extension does not work with the
1306 /// specified type and indicate what to do about it.
1307 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1308 LegalizeAction Action) {
1309 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1310 MemVT.isValid() && "Table isn't big enough!");
1311 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1314 /// Indicate that the specified truncating store does not work with the
1315 /// specified type and indicate what to do about it.
1316 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1317 LegalizeAction Action) {
1318 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1319 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1322 /// Indicate that the specified indexed load does or does not work with the
1323 /// specified type and indicate what to do abort it.
1325 /// NOTE: All indexed mode loads are initialized to Expand in
1326 /// TargetLowering.cpp
1327 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1328 LegalizeAction Action) {
1329 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1330 (unsigned)Action < 0xf && "Table isn't big enough!");
1331 // Load action are kept in the upper half.
1332 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1333 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1336 /// Indicate that the specified indexed store does or does not work with the
1337 /// specified type and indicate what to do about it.
1339 /// NOTE: All indexed mode stores are initialized to Expand in
1340 /// TargetLowering.cpp
1341 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1342 LegalizeAction Action) {
1343 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1344 (unsigned)Action < 0xf && "Table isn't big enough!");
1345 // Store action are kept in the lower half.
1346 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1347 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1350 /// Indicate that the specified condition code is or isn't supported on the
1351 /// target and indicate what to do about it.
1352 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1353 LegalizeAction Action) {
1354 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1355 "Table isn't big enough!");
1356 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1357 /// value and the upper 27 bits index into the second dimension of the array
1358 /// to select what 32-bit value to use.
1359 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1360 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1361 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1364 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1365 /// to trying a larger integer/fp until it can find one that works. If that
1366 /// default is insufficient, this method can be used by the target to override
1368 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1369 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1372 /// Targets should invoke this method for each target independent node that
1373 /// they want to provide a custom DAG combiner for by implementing the
1374 /// PerformDAGCombine virtual method.
1375 void setTargetDAGCombine(ISD::NodeType NT) {
1376 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1377 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1380 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1381 void setJumpBufSize(unsigned Size) {
1385 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1387 void setJumpBufAlignment(unsigned Align) {
1388 JumpBufAlignment = Align;
1391 /// Set the target's minimum function alignment (in log2(bytes))
1392 void setMinFunctionAlignment(unsigned Align) {
1393 MinFunctionAlignment = Align;
1396 /// Set the target's preferred function alignment. This should be set if
1397 /// there is a performance benefit to higher-than-minimum alignment (in
1399 void setPrefFunctionAlignment(unsigned Align) {
1400 PrefFunctionAlignment = Align;
1403 /// Set the target's preferred loop alignment. Default alignment is zero, it
1404 /// means the target does not care about loop alignment. The alignment is
1405 /// specified in log2(bytes). The target may also override
1406 /// getPrefLoopAlignment to provide per-loop values.
1407 void setPrefLoopAlignment(unsigned Align) {
1408 PrefLoopAlignment = Align;
1411 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1412 void setMinStackArgumentAlignment(unsigned Align) {
1413 MinStackArgumentAlignment = Align;
1416 /// Set if the DAG builder should automatically insert fences and reduce the
1417 /// order of atomic memory operations to Monotonic.
1418 void setInsertFencesForAtomic(bool fence) {
1419 InsertFencesForAtomic = fence;
1423 //===--------------------------------------------------------------------===//
1424 // Addressing mode description hooks (used by LSR etc).
1427 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1428 /// instructions reading the address. This allows as much computation as
1429 /// possible to be done in the address mode for that operand. This hook lets
1430 /// targets also pass back when this should be done on intrinsics which
1432 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1433 SmallVectorImpl<Value*> &/*Ops*/,
1434 Type *&/*AccessTy*/,
1435 unsigned AddrSpace = 0) const {
1439 /// This represents an addressing mode of:
1440 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1441 /// If BaseGV is null, there is no BaseGV.
1442 /// If BaseOffs is zero, there is no base offset.
1443 /// If HasBaseReg is false, there is no base register.
1444 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1447 GlobalValue *BaseGV;
1451 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1454 /// Return true if the addressing mode represented by AM is legal for this
1455 /// target, for a load/store of the specified type.
1457 /// The type may be VoidTy, in which case only return true if the addressing
1458 /// mode is legal for a load/store of any legal type. TODO: Handle
1459 /// pre/postinc as well.
1461 /// If the address space cannot be determined, it will be -1.
1463 /// TODO: Remove default argument
1464 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
1465 unsigned AddrSpace) const;
1467 /// \brief Return the cost of the scaling factor used in the addressing mode
1468 /// represented by AM for this target, for a load/store of the specified type.
1470 /// If the AM is supported, the return value must be >= 0.
1471 /// If the AM is not supported, it returns a negative value.
1472 /// TODO: Handle pre/postinc as well.
1473 /// TODO: Remove default argument
1474 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty,
1475 unsigned AS = 0) const {
1476 // Default: assume that any scaling factor used in a legal AM is free.
1477 if (isLegalAddressingMode(AM, Ty, AS))
1482 /// Return true if the specified immediate is legal icmp immediate, that is
1483 /// the target has icmp instructions which can compare a register against the
1484 /// immediate without having to materialize the immediate into a register.
1485 virtual bool isLegalICmpImmediate(int64_t) const {
1489 /// Return true if the specified immediate is legal add immediate, that is the
1490 /// target has add instructions which can add a register with the immediate
1491 /// without having to materialize the immediate into a register.
1492 virtual bool isLegalAddImmediate(int64_t) const {
1496 /// Return true if it's significantly cheaper to shift a vector by a uniform
1497 /// scalar than by an amount which will vary across each lane. On x86, for
1498 /// example, there is a "psllw" instruction for the former case, but no simple
1499 /// instruction for a general "a << b" operation on vectors.
1500 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1504 /// Return true if it's free to truncate a value of type Ty1 to type
1505 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1506 /// by referencing its sub-register AX.
1507 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1511 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1512 /// whether a call is in tail position. Typically this means that both results
1513 /// would be assigned to the same register or stack slot, but it could mean
1514 /// the target performs adequate checks of its own before proceeding with the
1516 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1520 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1524 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1526 /// Return true if the extension represented by \p I is free.
1527 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1528 /// this method can use the context provided by \p I to decide
1529 /// whether or not \p I is free.
1530 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1531 /// In other words, if is[Z|FP]Free returns true, then this method
1532 /// returns true as well. The converse is not true.
1533 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1534 /// \pre \p I must be a sign, zero, or fp extension.
1535 bool isExtFree(const Instruction *I) const {
1536 switch (I->getOpcode()) {
1537 case Instruction::FPExt:
1538 if (isFPExtFree(EVT::getEVT(I->getType())))
1541 case Instruction::ZExt:
1542 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1545 case Instruction::SExt:
1548 llvm_unreachable("Instruction is not an extension");
1550 return isExtFreeImpl(I);
1553 /// Return true if any actual instruction that defines a value of type Ty1
1554 /// implicitly zero-extends the value to Ty2 in the result register.
1556 /// This does not necessarily include registers defined in unknown ways, such
1557 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1558 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1559 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1560 /// values implicit zero-extend the result out to 64 bits.
1561 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1565 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1569 /// Return true if the target supplies and combines to a paired load
1570 /// two loaded values of type LoadedType next to each other in memory.
1571 /// RequiredAlignment gives the minimal alignment constraints that must be met
1572 /// to be able to select this paired load.
1574 /// This information is *not* used to generate actual paired loads, but it is
1575 /// used to generate a sequence of loads that is easier to combine into a
1577 /// For instance, something like this:
1578 /// a = load i64* addr
1579 /// b = trunc i64 a to i32
1580 /// c = lshr i64 a, 32
1581 /// d = trunc i64 c to i32
1582 /// will be optimized into:
1583 /// b = load i32* addr1
1584 /// d = load i32* addr2
1585 /// Where addr1 = addr2 +/- sizeof(i32).
1587 /// In other words, unless the target performs a post-isel load combining,
1588 /// this information should not be provided because it will generate more
1590 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1591 unsigned & /*RequiredAligment*/) const {
1595 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1596 unsigned & /*RequiredAligment*/) const {
1600 /// Return true if zero-extending the specific node Val to type VT2 is free
1601 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1602 /// because it's folded such as X86 zero-extending loads).
1603 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1604 return isZExtFree(Val.getValueType(), VT2);
1607 /// Return true if an fpext operation is free (for instance, because
1608 /// single-precision floating-point numbers are implicitly extended to
1609 /// double-precision).
1610 virtual bool isFPExtFree(EVT VT) const {
1611 assert(VT.isFloatingPoint());
1615 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1616 /// extend node) is profitable.
1617 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1619 /// Return true if an fneg operation is free to the point where it is never
1620 /// worthwhile to replace it with a bitwise operation.
1621 virtual bool isFNegFree(EVT VT) const {
1622 assert(VT.isFloatingPoint());
1626 /// Return true if an fabs operation is free to the point where it is never
1627 /// worthwhile to replace it with a bitwise operation.
1628 virtual bool isFAbsFree(EVT VT) const {
1629 assert(VT.isFloatingPoint());
1633 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1634 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1635 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1637 /// NOTE: This may be called before legalization on types for which FMAs are
1638 /// not legal, but should return true if those types will eventually legalize
1639 /// to types that support FMAs. After legalization, it will only be called on
1640 /// types that support FMAs (via Legal or Custom actions)
1641 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1645 /// Return true if it's profitable to narrow operations of type VT1 to
1646 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1648 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1652 /// \brief Return true if it is beneficial to convert a load of a constant to
1653 /// just the constant itself.
1654 /// On some targets it might be more efficient to use a combination of
1655 /// arithmetic instructions to materialize the constant instead of loading it
1656 /// from a constant pool.
1657 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1662 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1663 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1664 /// has custom lowering that depends on the index of the first element,
1665 /// and only the target knows which lowering is cheap.
1666 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1670 //===--------------------------------------------------------------------===//
1671 // Runtime Library hooks
1674 /// Rename the default libcall routine name for the specified libcall.
1675 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1676 LibcallRoutineNames[Call] = Name;
1679 /// Get the libcall routine name for the specified libcall.
1680 const char *getLibcallName(RTLIB::Libcall Call) const {
1681 return LibcallRoutineNames[Call];
1684 /// Override the default CondCode to be used to test the result of the
1685 /// comparison libcall against zero.
1686 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1687 CmpLibcallCCs[Call] = CC;
1690 /// Get the CondCode that's to be used to test the result of the comparison
1691 /// libcall against zero.
1692 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1693 return CmpLibcallCCs[Call];
1696 /// Set the CallingConv that should be used for the specified libcall.
1697 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1698 LibcallCallingConvs[Call] = CC;
1701 /// Get the CallingConv that should be used for the specified libcall.
1702 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1703 return LibcallCallingConvs[Call];
1707 const TargetMachine &TM;
1709 /// True if this is a little endian target.
1710 bool IsLittleEndian;
1712 /// Tells the code generator not to expand operations into sequences that use
1713 /// the select operations if possible.
1714 bool SelectIsExpensive;
1716 /// Tells the code generator that the target has multiple (allocatable)
1717 /// condition registers that can be used to store the results of comparisons
1718 /// for use by selects and conditional branches. With multiple condition
1719 /// registers, the code generator will not aggressively sink comparisons into
1720 /// the blocks of their users.
1721 bool HasMultipleConditionRegisters;
1723 /// Tells the code generator that the target has BitExtract instructions.
1724 /// The code generator will aggressively sink "shift"s into the blocks of
1725 /// their users if the users will generate "and" instructions which can be
1726 /// combined with "shift" to BitExtract instructions.
1727 bool HasExtractBitsInsn;
1729 /// Tells the code generator not to expand integer divides by constants into a
1730 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1731 /// model is in place. If we ever optimize for size, this will be set to true
1732 /// unconditionally.
1735 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1738 /// Tells the code generator to bypass slow divide or remainder
1739 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1740 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1741 /// div/rem when the operands are positive and less than 256.
1742 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1744 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1745 /// signed divide by power of two; let the target handle it.
1746 bool Pow2SDivIsCheap;
1748 /// Tells the code generator that it shouldn't generate extra flow control
1749 /// instructions and should attempt to combine flow control instructions via
1751 bool JumpIsExpensive;
1753 /// Whether the target supports or cares about preserving floating point
1754 /// exception behavior.
1755 bool HasFloatingPointExceptions;
1757 /// This target prefers to use _setjmp to implement llvm.setjmp.
1759 /// Defaults to false.
1760 bool UseUnderscoreSetJmp;
1762 /// This target prefers to use _longjmp to implement llvm.longjmp.
1764 /// Defaults to false.
1765 bool UseUnderscoreLongJmp;
1767 /// Number of blocks threshold to use jump tables.
1768 int MinimumJumpTableEntries;
1770 /// Information about the contents of the high-bits in boolean values held in
1771 /// a type wider than i1. See getBooleanContents.
1772 BooleanContent BooleanContents;
1774 /// Information about the contents of the high-bits in boolean values held in
1775 /// a type wider than i1. See getBooleanContents.
1776 BooleanContent BooleanFloatContents;
1778 /// Information about the contents of the high-bits in boolean vector values
1779 /// when the element type is wider than i1. See getBooleanContents.
1780 BooleanContent BooleanVectorContents;
1782 /// The target scheduling preference: shortest possible total cycles or lowest
1784 Sched::Preference SchedPreferenceInfo;
1786 /// The size, in bytes, of the target's jmp_buf buffers
1787 unsigned JumpBufSize;
1789 /// The alignment, in bytes, of the target's jmp_buf buffers
1790 unsigned JumpBufAlignment;
1792 /// The minimum alignment that any argument on the stack needs to have.
1793 unsigned MinStackArgumentAlignment;
1795 /// The minimum function alignment (used when optimizing for size, and to
1796 /// prevent explicitly provided alignment from leading to incorrect code).
1797 unsigned MinFunctionAlignment;
1799 /// The preferred function alignment (used when alignment unspecified and
1800 /// optimizing for speed).
1801 unsigned PrefFunctionAlignment;
1803 /// The preferred loop alignment.
1804 unsigned PrefLoopAlignment;
1806 /// Whether the DAG builder should automatically insert fences and reduce
1807 /// ordering for atomics. (This will be set for for most architectures with
1808 /// weak memory ordering.)
1809 bool InsertFencesForAtomic;
1811 /// If set to a physical register, this specifies the register that
1812 /// llvm.savestack/llvm.restorestack should save and restore.
1813 unsigned StackPointerRegisterToSaveRestore;
1815 /// If set to a physical register, this specifies the register that receives
1816 /// the exception address on entry to a landing pad.
1817 unsigned ExceptionPointerRegister;
1819 /// If set to a physical register, this specifies the register that receives
1820 /// the exception typeid on entry to a landing pad.
1821 unsigned ExceptionSelectorRegister;
1823 /// This indicates the default register class to use for each ValueType the
1824 /// target supports natively.
1825 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1826 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1827 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1829 /// This indicates the "representative" register class to use for each
1830 /// ValueType the target supports natively. This information is used by the
1831 /// scheduler to track register pressure. By default, the representative
1832 /// register class is the largest legal super-reg register class of the
1833 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1834 /// representative class would be GR32.
1835 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1837 /// This indicates the "cost" of the "representative" register class for each
1838 /// ValueType. The cost is used by the scheduler to approximate register
1840 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1842 /// For any value types we are promoting or expanding, this contains the value
1843 /// type that we are changing to. For Expanded types, this contains one step
1844 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1845 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1846 /// the same type (e.g. i32 -> i32).
1847 MVT TransformToType[MVT::LAST_VALUETYPE];
1849 /// For each operation and each value type, keep a LegalizeAction that
1850 /// indicates how instruction selection should deal with the operation. Most
1851 /// operations are Legal (aka, supported natively by the target), but
1852 /// operations that are not should be described. Note that operations on
1853 /// non-legal value types are not described here.
1854 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1856 /// For each load extension type and each value type, keep a LegalizeAction
1857 /// that indicates how instruction selection should deal with a load of a
1858 /// specific value type and extension type.
1859 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1860 [ISD::LAST_LOADEXT_TYPE];
1862 /// For each value type pair keep a LegalizeAction that indicates whether a
1863 /// truncating store of a specific value type and truncating type is legal.
1864 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1866 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1867 /// that indicates how instruction selection should deal with the load /
1870 /// The first dimension is the value_type for the reference. The second
1871 /// dimension represents the various modes for load store.
1872 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1874 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1875 /// indicates how instruction selection should deal with the condition code.
1877 /// Because each CC action takes up 2 bits, we need to have the array size be
1878 /// large enough to fit all of the value types. This can be done by rounding
1879 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1880 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1882 ValueTypeActionImpl ValueTypeActions;
1885 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1888 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1890 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1891 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1894 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1896 /// For operations that must be promoted to a specific type, this holds the
1897 /// destination type. This map should be sparse, so don't hold it as an
1900 /// Targets add entries to this map with AddPromotedToType(..), clients access
1901 /// this with getTypeToPromoteTo(..).
1902 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1905 /// Stores the name each libcall.
1906 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1908 /// The ISD::CondCode that should be used to test the result of each of the
1909 /// comparison libcall against zero.
1910 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1912 /// Stores the CallingConv that should be used for each libcall.
1913 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1916 /// Return true if the extension represented by \p I is free.
1917 /// \pre \p I is a sign, zero, or fp extension and
1918 /// is[Z|FP]ExtFree of the related types is not true.
1919 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1921 /// \brief Specify maximum number of store instructions per memset call.
1923 /// When lowering \@llvm.memset this field specifies the maximum number of
1924 /// store operations that may be substituted for the call to memset. Targets
1925 /// must set this value based on the cost threshold for that target. Targets
1926 /// should assume that the memset will be done using as many of the largest
1927 /// store operations first, followed by smaller ones, if necessary, per
1928 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1929 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1930 /// store. This only applies to setting a constant array of a constant size.
1931 unsigned MaxStoresPerMemset;
1933 /// Maximum number of stores operations that may be substituted for the call
1934 /// to memset, used for functions with OptSize attribute.
1935 unsigned MaxStoresPerMemsetOptSize;
1937 /// \brief Specify maximum bytes of store instructions per memcpy call.
1939 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1940 /// store operations that may be substituted for a call to memcpy. Targets
1941 /// must set this value based on the cost threshold for that target. Targets
1942 /// should assume that the memcpy will be done using as many of the largest
1943 /// store operations first, followed by smaller ones, if necessary, per
1944 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1945 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1946 /// and one 1-byte store. This only applies to copying a constant array of
1948 unsigned MaxStoresPerMemcpy;
1950 /// Maximum number of store operations that may be substituted for a call to
1951 /// memcpy, used for functions with OptSize attribute.
1952 unsigned MaxStoresPerMemcpyOptSize;
1954 /// \brief Specify maximum bytes of store instructions per memmove call.
1956 /// When lowering \@llvm.memmove this field specifies the maximum number of
1957 /// store instructions that may be substituted for a call to memmove. Targets
1958 /// must set this value based on the cost threshold for that target. Targets
1959 /// should assume that the memmove will be done using as many of the largest
1960 /// store operations first, followed by smaller ones, if necessary, per
1961 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1962 /// with 8-bit alignment would result in nine 1-byte stores. This only
1963 /// applies to copying a constant array of constant size.
1964 unsigned MaxStoresPerMemmove;
1966 /// Maximum number of store instructions that may be substituted for a call to
1967 /// memmove, used for functions with OpSize attribute.
1968 unsigned MaxStoresPerMemmoveOptSize;
1970 /// Tells the code generator that select is more expensive than a branch if
1971 /// the branch is usually predicted right.
1972 bool PredictableSelectIsExpensive;
1974 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1975 /// a mask of a single bit, a compare, and a branch into a single instruction.
1976 bool MaskAndBranchFoldingIsLegal;
1978 /// \see enableExtLdPromotion.
1979 bool EnableExtLdPromotion;
1982 /// Return true if the value types that can be represented by the specified
1983 /// register class are all legal.
1984 bool isLegalRC(const TargetRegisterClass *RC) const;
1986 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1987 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1988 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
1989 MachineBasicBlock *MBB) const;
1992 /// This class defines information used to lower LLVM code to legal SelectionDAG
1993 /// operators that the target instruction selector can accept natively.
1995 /// This class also defines callbacks that targets must implement to lower
1996 /// target-specific constructs to SelectionDAG operators.
1997 class TargetLowering : public TargetLoweringBase {
1998 TargetLowering(const TargetLowering&) = delete;
1999 void operator=(const TargetLowering&) = delete;
2002 /// NOTE: The TargetMachine owns TLOF.
2003 explicit TargetLowering(const TargetMachine &TM);
2005 /// Returns true by value, base pointer and offset pointer and addressing mode
2006 /// by reference if the node's address can be legally represented as
2007 /// pre-indexed load / store address.
2008 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2009 SDValue &/*Offset*/,
2010 ISD::MemIndexedMode &/*AM*/,
2011 SelectionDAG &/*DAG*/) const {
2015 /// Returns true by value, base pointer and offset pointer and addressing mode
2016 /// by reference if this node can be combined with a load / store to form a
2017 /// post-indexed load / store.
2018 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2020 SDValue &/*Offset*/,
2021 ISD::MemIndexedMode &/*AM*/,
2022 SelectionDAG &/*DAG*/) const {
2026 /// Return the entry encoding for a jump table in the current function. The
2027 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2028 virtual unsigned getJumpTableEncoding() const;
2030 virtual const MCExpr *
2031 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2032 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2033 MCContext &/*Ctx*/) const {
2034 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2037 /// Returns relocation base for the given PIC jumptable.
2038 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2039 SelectionDAG &DAG) const;
2041 /// This returns the relocation base for the given PIC jumptable, the same as
2042 /// getPICJumpTableRelocBase, but as an MCExpr.
2043 virtual const MCExpr *
2044 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2045 unsigned JTI, MCContext &Ctx) const;
2047 /// Return true if folding a constant offset with the given GlobalAddress is
2048 /// legal. It is frequently not legal in PIC relocation models.
2049 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2051 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2052 SDValue &Chain) const;
2054 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2055 SDValue &NewLHS, SDValue &NewRHS,
2056 ISD::CondCode &CCCode, SDLoc DL) const;
2058 /// Returns a pair of (return value, chain).
2059 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2060 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2061 EVT RetVT, const SDValue *Ops,
2062 unsigned NumOps, bool isSigned,
2063 SDLoc dl, bool doesNotReturn = false,
2064 bool isReturnValueUsed = true) const;
2066 //===--------------------------------------------------------------------===//
2067 // TargetLowering Optimization Methods
2070 /// A convenience struct that encapsulates a DAG, and two SDValues for
2071 /// returning information from TargetLowering to its clients that want to
2073 struct TargetLoweringOpt {
2080 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2082 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2084 bool LegalTypes() const { return LegalTys; }
2085 bool LegalOperations() const { return LegalOps; }
2087 bool CombineTo(SDValue O, SDValue N) {
2093 /// Check to see if the specified operand of the specified instruction is a
2094 /// constant integer. If so, check to see if there are any bits set in the
2095 /// constant that are not demanded. If so, shrink the constant and return
2097 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2099 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2100 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2101 /// generalized for targets with other types of implicit widening casts.
2102 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2106 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2107 /// result of Op are ever used downstream. If we can use this information to
2108 /// simplify Op, create a new simplified DAG node and return true, returning
2109 /// the original and new nodes in Old and New. Otherwise, analyze the
2110 /// expression and return a mask of KnownOne and KnownZero bits for the
2111 /// expression (used to simplify the caller). The KnownZero/One bits may only
2112 /// be accurate for those bits in the DemandedMask.
2113 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2114 APInt &KnownZero, APInt &KnownOne,
2115 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2117 /// Determine which of the bits specified in Mask are known to be either zero
2118 /// or one and return them in the KnownZero/KnownOne bitsets.
2119 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2122 const SelectionDAG &DAG,
2123 unsigned Depth = 0) const;
2125 /// This method can be implemented by targets that want to expose additional
2126 /// information about sign bits to the DAG Combiner.
2127 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2128 const SelectionDAG &DAG,
2129 unsigned Depth = 0) const;
2131 struct DAGCombinerInfo {
2132 void *DC; // The DAG Combiner object.
2134 bool CalledByLegalizer;
2138 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2139 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2141 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2142 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2143 bool isAfterLegalizeVectorOps() const {
2144 return Level == AfterLegalizeDAG;
2146 CombineLevel getDAGCombineLevel() { return Level; }
2147 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2149 void AddToWorklist(SDNode *N);
2150 void RemoveFromWorklist(SDNode *N);
2151 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2152 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2153 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2155 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2158 /// Return if the N is a constant or constant vector equal to the true value
2159 /// from getBooleanContents().
2160 bool isConstTrueVal(const SDNode *N) const;
2162 /// Return if the N is a constant or constant vector equal to the false value
2163 /// from getBooleanContents().
2164 bool isConstFalseVal(const SDNode *N) const;
2166 /// Try to simplify a setcc built with the specified operands and cc. If it is
2167 /// unable to simplify it, return a null SDValue.
2168 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2169 ISD::CondCode Cond, bool foldBooleans,
2170 DAGCombinerInfo &DCI, SDLoc dl) const;
2172 /// Returns true (and the GlobalValue and the offset) if the node is a
2173 /// GlobalAddress + offset.
2175 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2177 /// This method will be invoked for all target nodes and for any
2178 /// target-independent nodes that the target has registered with invoke it
2181 /// The semantics are as follows:
2183 /// SDValue.Val == 0 - No change was made
2184 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2185 /// otherwise - N should be replaced by the returned Operand.
2187 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2188 /// more complex transformations.
2190 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2192 /// Return true if it is profitable to move a following shift through this
2193 // node, adjusting any immediate operands as necessary to preserve semantics.
2194 // This transformation may not be desirable if it disrupts a particularly
2195 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2196 // By default, it returns true.
2197 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2201 /// Return true if the target has native support for the specified value type
2202 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2203 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2204 /// and some i16 instructions are slow.
2205 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2206 // By default, assume all legal types are desirable.
2207 return isTypeLegal(VT);
2210 /// Return true if it is profitable for dag combiner to transform a floating
2211 /// point op of specified opcode to a equivalent op of an integer
2212 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2213 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2218 /// This method query the target whether it is beneficial for dag combiner to
2219 /// promote the specified node. If true, it should return the desired
2220 /// promotion type by reference.
2221 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2225 //===--------------------------------------------------------------------===//
2226 // Lowering methods - These methods must be implemented by targets so that
2227 // the SelectionDAGBuilder code knows how to lower these.
2230 /// This hook must be implemented to lower the incoming (formal) arguments,
2231 /// described by the Ins array, into the specified DAG. The implementation
2232 /// should fill in the InVals array with legal-type argument values, and
2233 /// return the resulting token chain value.
2236 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2238 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2239 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2240 SmallVectorImpl<SDValue> &/*InVals*/) const {
2241 llvm_unreachable("Not Implemented");
2244 struct ArgListEntry {
2253 bool isInAlloca : 1;
2254 bool isReturned : 1;
2257 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2258 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2259 isReturned(false), Alignment(0) { }
2261 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2263 typedef std::vector<ArgListEntry> ArgListTy;
2265 /// This structure contains all information that is necessary for lowering
2266 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2267 /// needs to lower a call, and targets will see this struct in their LowerCall
2269 struct CallLoweringInfo {
2276 bool DoesNotReturn : 1;
2277 bool IsReturnValueUsed : 1;
2279 // IsTailCall should be modified by implementations of
2280 // TargetLowering::LowerCall that perform tail call conversions.
2283 unsigned NumFixedArgs;
2284 CallingConv::ID CallConv;
2289 ImmutableCallSite *CS;
2291 SmallVector<ISD::OutputArg, 32> Outs;
2292 SmallVector<SDValue, 32> OutVals;
2293 SmallVector<ISD::InputArg, 32> Ins;
2295 CallLoweringInfo(SelectionDAG &DAG)
2296 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2297 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2298 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2299 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2301 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2306 CallLoweringInfo &setChain(SDValue InChain) {
2311 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2312 SDValue Target, ArgListTy &&ArgsList,
2313 unsigned FixedArgs = -1) {
2318 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2319 Args = std::move(ArgsList);
2323 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2324 SDValue Target, ArgListTy &&ArgsList,
2325 ImmutableCallSite &Call) {
2328 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2329 DoesNotReturn = Call.doesNotReturn();
2330 IsVarArg = FTy->isVarArg();
2331 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2332 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2333 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2337 CallConv = Call.getCallingConv();
2338 NumFixedArgs = FTy->getNumParams();
2339 Args = std::move(ArgsList);
2346 CallLoweringInfo &setInRegister(bool Value = true) {
2351 CallLoweringInfo &setNoReturn(bool Value = true) {
2352 DoesNotReturn = Value;
2356 CallLoweringInfo &setVarArg(bool Value = true) {
2361 CallLoweringInfo &setTailCall(bool Value = true) {
2366 CallLoweringInfo &setDiscardResult(bool Value = true) {
2367 IsReturnValueUsed = !Value;
2371 CallLoweringInfo &setSExtResult(bool Value = true) {
2376 CallLoweringInfo &setZExtResult(bool Value = true) {
2381 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2382 IsPatchPoint = Value;
2386 ArgListTy &getArgs() {
2391 /// This function lowers an abstract call to a function into an actual call.
2392 /// This returns a pair of operands. The first element is the return value
2393 /// for the function (if RetTy is not VoidTy). The second element is the
2394 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2395 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2397 /// This hook must be implemented to lower calls into the the specified
2398 /// DAG. The outgoing arguments to the call are described by the Outs array,
2399 /// and the values to be returned by the call are described by the Ins
2400 /// array. The implementation should fill in the InVals array with legal-type
2401 /// return values from the call, and return the resulting token chain value.
2403 LowerCall(CallLoweringInfo &/*CLI*/,
2404 SmallVectorImpl<SDValue> &/*InVals*/) const {
2405 llvm_unreachable("Not Implemented");
2408 /// Target-specific cleanup for formal ByVal parameters.
2409 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2411 /// This hook should be implemented to check whether the return values
2412 /// described by the Outs array can fit into the return registers. If false
2413 /// is returned, an sret-demotion is performed.
2414 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2415 MachineFunction &/*MF*/, bool /*isVarArg*/,
2416 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2417 LLVMContext &/*Context*/) const
2419 // Return true by default to get preexisting behavior.
2423 /// This hook must be implemented to lower outgoing return values, described
2424 /// by the Outs array, into the specified DAG. The implementation should
2425 /// return the resulting token chain value.
2427 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2429 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2430 const SmallVectorImpl<SDValue> &/*OutVals*/,
2431 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2432 llvm_unreachable("Not Implemented");
2435 /// Return true if result of the specified node is used by a return node
2436 /// only. It also compute and return the input chain for the tail call.
2438 /// This is used to determine whether it is possible to codegen a libcall as
2439 /// tail call at legalization time.
2440 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2444 /// Return true if the target may be able emit the call instruction as a tail
2445 /// call. This is used by optimization passes to determine if it's profitable
2446 /// to duplicate return instructions to enable tailcall optimization.
2447 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2451 /// Return the builtin name for the __builtin___clear_cache intrinsic
2452 /// Default is to invoke the clear cache library call
2453 virtual const char * getClearCacheBuiltinName() const {
2454 return "__clear_cache";
2457 /// Return the register ID of the name passed in. Used by named register
2458 /// global variables extension. There is no target-independent behaviour
2459 /// so the default action is to bail.
2460 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2461 report_fatal_error("Named registers not implemented for this target");
2464 /// Return the type that should be used to zero or sign extend a
2465 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2466 /// convention requires the return type to be promoted, but this is not true
2467 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2468 /// calling conventions. The frontend should handle this and include all of
2469 /// the necessary information.
2470 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2471 ISD::NodeType /*ExtendKind*/) const {
2472 EVT MinVT = getRegisterType(Context, MVT::i32);
2473 return VT.bitsLT(MinVT) ? MinVT : VT;
2476 /// For some targets, an LLVM struct type must be broken down into multiple
2477 /// simple types, but the calling convention specifies that the entire struct
2478 /// must be passed in a block of consecutive registers.
2480 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2481 bool isVarArg) const {
2485 /// Returns a 0 terminated array of registers that can be safely used as
2486 /// scratch registers.
2487 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2491 /// This callback is used to prepare for a volatile or atomic load.
2492 /// It takes a chain node as input and returns the chain for the load itself.
2494 /// Having a callback like this is necessary for targets like SystemZ,
2495 /// which allows a CPU to reuse the result of a previous load indefinitely,
2496 /// even if a cache-coherent store is performed by another CPU. The default
2497 /// implementation does nothing.
2498 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2499 SelectionDAG &DAG) const {
2503 /// This callback is invoked by the type legalizer to legalize nodes with an
2504 /// illegal operand type but legal result types. It replaces the
2505 /// LowerOperation callback in the type Legalizer. The reason we can not do
2506 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2507 /// use this callback.
2509 /// TODO: Consider merging with ReplaceNodeResults.
2511 /// The target places new result values for the node in Results (their number
2512 /// and types must exactly match those of the original return values of
2513 /// the node), or leaves Results empty, which indicates that the node is not
2514 /// to be custom lowered after all.
2515 /// The default implementation calls LowerOperation.
2516 virtual void LowerOperationWrapper(SDNode *N,
2517 SmallVectorImpl<SDValue> &Results,
2518 SelectionDAG &DAG) const;
2520 /// This callback is invoked for operations that are unsupported by the
2521 /// target, which are registered to use 'custom' lowering, and whose defined
2522 /// values are all legal. If the target has no operations that require custom
2523 /// lowering, it need not implement this. The default implementation of this
2525 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2527 /// This callback is invoked when a node result type is illegal for the
2528 /// target, and the operation was registered to use 'custom' lowering for that
2529 /// result type. The target places new result values for the node in Results
2530 /// (their number and types must exactly match those of the original return
2531 /// values of the node), or leaves Results empty, which indicates that the
2532 /// node is not to be custom lowered after all.
2534 /// If the target has no operations that require custom lowering, it need not
2535 /// implement this. The default implementation aborts.
2536 virtual void ReplaceNodeResults(SDNode * /*N*/,
2537 SmallVectorImpl<SDValue> &/*Results*/,
2538 SelectionDAG &/*DAG*/) const {
2539 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2542 /// This method returns the name of a target specific DAG node.
2543 virtual const char *getTargetNodeName(unsigned Opcode) const;
2545 /// This method returns a target specific FastISel object, or null if the
2546 /// target does not support "fast" ISel.
2547 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2548 const TargetLibraryInfo *) const {
2553 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2554 SelectionDAG &DAG) const;
2556 //===--------------------------------------------------------------------===//
2557 // Inline Asm Support hooks
2560 /// This hook allows the target to expand an inline asm call to be explicit
2561 /// llvm code if it wants to. This is useful for turning simple inline asms
2562 /// into LLVM intrinsics, which gives the compiler more information about the
2563 /// behavior of the code.
2564 virtual bool ExpandInlineAsm(CallInst *) const {
2568 enum ConstraintType {
2569 C_Register, // Constraint represents specific register(s).
2570 C_RegisterClass, // Constraint represents any of register(s) in class.
2571 C_Memory, // Memory constraint.
2572 C_Other, // Something else.
2573 C_Unknown // Unsupported constraint.
2576 enum ConstraintWeight {
2578 CW_Invalid = -1, // No match.
2579 CW_Okay = 0, // Acceptable.
2580 CW_Good = 1, // Good weight.
2581 CW_Better = 2, // Better weight.
2582 CW_Best = 3, // Best weight.
2584 // Well-known weights.
2585 CW_SpecificReg = CW_Okay, // Specific register operands.
2586 CW_Register = CW_Good, // Register operands.
2587 CW_Memory = CW_Better, // Memory operands.
2588 CW_Constant = CW_Best, // Constant operand.
2589 CW_Default = CW_Okay // Default or don't know type.
2592 /// This contains information for each constraint that we are lowering.
2593 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2594 /// This contains the actual string for the code, like "m". TargetLowering
2595 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2596 /// matches the operand.
2597 std::string ConstraintCode;
2599 /// Information about the constraint code, e.g. Register, RegisterClass,
2600 /// Memory, Other, Unknown.
2601 TargetLowering::ConstraintType ConstraintType;
2603 /// If this is the result output operand or a clobber, this is null,
2604 /// otherwise it is the incoming operand to the CallInst. This gets
2605 /// modified as the asm is processed.
2606 Value *CallOperandVal;
2608 /// The ValueType for the operand value.
2611 /// Return true of this is an input operand that is a matching constraint
2613 bool isMatchingInputConstraint() const;
2615 /// If this is an input matching constraint, this method returns the output
2616 /// operand it matches.
2617 unsigned getMatchedOperand() const;
2619 /// Copy constructor for copying from a ConstraintInfo.
2620 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2621 : InlineAsm::ConstraintInfo(std::move(Info)),
2622 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2623 ConstraintVT(MVT::Other) {}
2626 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2628 /// Split up the constraint string from the inline assembly value into the
2629 /// specific constraints and their prefixes, and also tie in the associated
2630 /// operand values. If this returns an empty vector, and if the constraint
2631 /// string itself isn't empty, there was an error parsing.
2632 virtual AsmOperandInfoVector ParseConstraints(const TargetRegisterInfo *TRI,
2633 ImmutableCallSite CS) const;
2635 /// Examine constraint type and operand type and determine a weight value.
2636 /// The operand object must already have been set up with the operand type.
2637 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2638 AsmOperandInfo &info, int maIndex) const;
2640 /// Examine constraint string and operand type and determine a weight value.
2641 /// The operand object must already have been set up with the operand type.
2642 virtual ConstraintWeight getSingleConstraintMatchWeight(
2643 AsmOperandInfo &info, const char *constraint) const;
2645 /// Determines the constraint code and constraint type to use for the specific
2646 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2647 /// If the actual operand being passed in is available, it can be passed in as
2648 /// Op, otherwise an empty SDValue can be passed.
2649 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2651 SelectionDAG *DAG = nullptr) const;
2653 /// Given a constraint, return the type of constraint it is for this target.
2654 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2656 /// Given a physical register constraint (e.g. {edx}), return the register
2657 /// number and the register class for the register.
2659 /// Given a register class constraint, like 'r', if this corresponds directly
2660 /// to an LLVM register class, return a register of 0 and the register class
2663 /// This should only be used for C_Register constraints. On error, this
2664 /// returns a register number of 0 and a null register class pointer.
2665 virtual std::pair<unsigned, const TargetRegisterClass *>
2666 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2667 const std::string &Constraint, MVT VT) const;
2670 getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
2671 if (ConstraintCode == "i")
2672 return InlineAsm::Constraint_i;
2673 else if (ConstraintCode == "m")
2674 return InlineAsm::Constraint_m;
2675 return InlineAsm::Constraint_Unknown;
2678 /// Try to replace an X constraint, which matches anything, with another that
2679 /// has more specific requirements based on the type of the corresponding
2680 /// operand. This returns null if there is no replacement to make.
2681 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2683 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2684 /// add anything to Ops.
2685 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2686 std::vector<SDValue> &Ops,
2687 SelectionDAG &DAG) const;
2689 //===--------------------------------------------------------------------===//
2690 // Div utility functions
2692 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2693 SelectionDAG &DAG) const;
2694 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2695 bool IsAfterLegalization,
2696 std::vector<SDNode *> *Created) const;
2697 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2698 bool IsAfterLegalization,
2699 std::vector<SDNode *> *Created) const;
2700 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2702 std::vector<SDNode *> *Created) const {
2706 /// Indicate whether this target prefers to combine the given number of FDIVs
2707 /// with the same divisor.
2708 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2712 /// Hooks for building estimates in place of slower divisions and square
2715 /// Return a reciprocal square root estimate value for the input operand.
2716 /// The RefinementSteps output is the number of Newton-Raphson refinement
2717 /// iterations required to generate a sufficient (though not necessarily
2718 /// IEEE-754 compliant) estimate for the value type.
2719 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2720 /// algorithm implementation that uses one constant or two constants.
2721 /// A target may choose to implement its own refinement within this function.
2722 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2723 /// any further refinement of the estimate.
2724 /// An empty SDValue return means no estimate sequence can be created.
2725 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2726 unsigned &RefinementSteps,
2727 bool &UseOneConstNR) const {
2731 /// Return a reciprocal estimate value for the input operand.
2732 /// The RefinementSteps output is the number of Newton-Raphson refinement
2733 /// iterations required to generate a sufficient (though not necessarily
2734 /// IEEE-754 compliant) estimate for the value type.
2735 /// A target may choose to implement its own refinement within this function.
2736 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2737 /// any further refinement of the estimate.
2738 /// An empty SDValue return means no estimate sequence can be created.
2739 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2740 unsigned &RefinementSteps) const {
2744 //===--------------------------------------------------------------------===//
2745 // Legalization utility functions
2748 /// Expand a MUL into two nodes. One that computes the high bits of
2749 /// the result and one that computes the low bits.
2750 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2751 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2752 /// if you want to control how low bits are extracted from the LHS.
2753 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2754 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2755 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2756 /// \returns true if the node has been expanded. false if it has not
2757 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2758 SelectionDAG &DAG, SDValue LL = SDValue(),
2759 SDValue LH = SDValue(), SDValue RL = SDValue(),
2760 SDValue RH = SDValue()) const;
2762 /// Expand float(f32) to SINT(i64) conversion
2763 /// \param N Node to expand
2764 /// \param Result output after conversion
2765 /// \returns True, if the expansion was successful, false otherwise
2766 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2768 //===--------------------------------------------------------------------===//
2769 // Instruction Emitting Hooks
2772 /// This method should be implemented by targets that mark instructions with
2773 /// the 'usesCustomInserter' flag. These instructions are special in various
2774 /// ways, which require special support to insert. The specified MachineInstr
2775 /// is created but not inserted into any basic blocks, and this method is
2776 /// called to expand it into a sequence of instructions, potentially also
2777 /// creating new basic blocks and control flow.
2778 /// As long as the returned basic block is different (i.e., we created a new
2779 /// one), the custom inserter is free to modify the rest of \p MBB.
2780 virtual MachineBasicBlock *
2781 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2783 /// This method should be implemented by targets that mark instructions with
2784 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2785 /// instruction selection by target hooks. e.g. To fill in optional defs for
2786 /// ARM 's' setting instructions.
2788 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2790 /// If this function returns true, SelectionDAGBuilder emits a
2791 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2792 virtual bool useLoadStackGuardNode() const {
2797 /// Given an LLVM IR type and return type attributes, compute the return value
2798 /// EVTs and flags, and optionally also the offsets, if the return value is
2799 /// being lowered to memory.
2800 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2801 SmallVectorImpl<ISD::OutputArg> &Outs,
2802 const TargetLowering &TLI);
2804 } // end llvm namespace