1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/CodeGen/DAGCombine.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/InlineAsm.h"
32 #include "llvm/Support/CallSite.h"
33 #include "llvm/Target/TargetCallingConv.h"
34 #include "llvm/Target/TargetMachine.h"
43 class FunctionLoweringInfo;
44 class ImmutableCallSite;
46 class MachineBasicBlock;
47 class MachineFunction;
49 class MachineJumpTableInfo;
52 template<typename T> class SmallVectorImpl;
54 class TargetRegisterClass;
55 class TargetLibraryInfo;
56 class TargetLoweringObjectFile;
61 None, // No preference
62 Source, // Follow source order.
63 RegPressure, // Scheduling for lowest register pressure.
64 Hybrid, // Scheduling for both latency and register pressure.
65 ILP, // Scheduling for ILP in low register pressure mode.
66 VLIW // Scheduling for VLIW targets.
70 /// TargetLoweringBase - This base class for TargetLowering contains the
71 /// SelectionDAG-independent parts that can be used from the rest of CodeGen.
72 class TargetLoweringBase {
73 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
74 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
77 /// LegalizeAction - This enum indicates whether operations are valid for a
78 /// target, and if not, what action should be used to make them valid.
80 Legal, // The target natively supports this operation.
81 Promote, // This operation should be executed in a larger type.
82 Expand, // Try to expand this to other ops, otherwise use a libcall.
83 Custom // Use the LowerOperation hook to implement custom lowering.
86 /// LegalizeTypeAction - This enum indicates whether a types are legal for a
87 /// target, and if not, what action should be used to make them valid.
88 enum LegalizeTypeAction {
89 TypeLegal, // The target natively supports this type.
90 TypePromoteInteger, // Replace this integer with a larger one.
91 TypeExpandInteger, // Split this integer into two of half the size.
92 TypeSoftenFloat, // Convert this float to a same size integer type.
93 TypeExpandFloat, // Split this float into two of half the size.
94 TypeScalarizeVector, // Replace this one-element vector with its element.
95 TypeSplitVector, // Split this vector into two of half the size.
96 TypeWidenVector // This vector should be widened into a larger vector.
99 /// LegalizeKind holds the legalization kind that needs to happen to EVT
100 /// in order to type-legalize it.
101 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
103 enum BooleanContent { // How the target represents true/false values.
104 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
105 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
106 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
109 enum SelectSupportKind {
110 ScalarValSelect, // The target supports scalar selects (ex: cmov).
111 ScalarCondVectorVal, // The target supports selects with a scalar condition
112 // and vector values (ex: cmov).
113 VectorMaskSelect // The target supports vector selects with a vector
114 // mask (ex: x86 blends).
117 static ISD::NodeType getExtendForContent(BooleanContent Content) {
119 case UndefinedBooleanContent:
120 // Extend by adding rubbish bits.
121 return ISD::ANY_EXTEND;
122 case ZeroOrOneBooleanContent:
123 // Extend by adding zero bits.
124 return ISD::ZERO_EXTEND;
125 case ZeroOrNegativeOneBooleanContent:
126 // Extend by copying the sign bit.
127 return ISD::SIGN_EXTEND;
129 llvm_unreachable("Invalid content kind");
132 /// NOTE: The constructor takes ownership of TLOF.
133 explicit TargetLoweringBase(const TargetMachine &TM,
134 const TargetLoweringObjectFile *TLOF);
135 virtual ~TargetLoweringBase();
138 /// \brief Initialize all of the actions to default values.
142 const TargetMachine &getTargetMachine() const { return TM; }
143 const DataLayout *getDataLayout() const { return TD; }
144 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
146 bool isBigEndian() const { return !IsLittleEndian; }
147 bool isLittleEndian() const { return IsLittleEndian; }
148 // Return the pointer type for the given address space, defaults to
149 // the pointer type from the data layout.
150 // FIXME: The default needs to be removed once all the code is updated.
151 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const { return PointerTy; }
152 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
154 EVT getShiftAmountTy(EVT LHSTy) const;
156 /// isSelectExpensive - Return true if the select operation is expensive for
158 bool isSelectExpensive() const { return SelectIsExpensive; }
160 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
164 /// shouldSplitVectorElementType - Return true if a vector of the given type
165 /// should be split (TypeSplitVector) instead of promoted
166 /// (TypePromoteInteger) during type legalization.
167 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
169 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
170 /// a sequence of several shifts, adds, and multiplies for this target.
171 bool isIntDivCheap() const { return IntDivIsCheap; }
173 /// isSlowDivBypassed - Returns true if target has indicated at least one
174 /// type should be bypassed.
175 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
177 /// getBypassSlowDivTypes - Returns map of slow types for division or
178 /// remainder with corresponding fast types
179 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
180 return BypassSlowDivWidths;
183 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
185 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
187 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
188 /// that should be avoided.
189 bool isJumpExpensive() const { return JumpIsExpensive; }
191 /// isPredictableSelectExpensive - Return true if selects are only cheaper
192 /// than branches if the branch is unlikely to be predicted right.
193 bool isPredictableSelectExpensive() const {
194 return PredictableSelectIsExpensive;
197 /// getSetCCResultType - Return the ValueType of the result of SETCC
198 /// operations. Also used to obtain the target's preferred type for
199 /// the condition operand of SELECT and BRCOND nodes. In the case of
200 /// BRCOND the argument passed is MVT::Other since there are no other
201 /// operands to get a type hint from.
202 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
204 /// getCmpLibcallReturnType - Return the ValueType for comparison
205 /// libcalls. Comparions libcalls include floating point comparion calls,
206 /// and Ordered/Unordered check calls on floating point numbers.
208 MVT::SimpleValueType getCmpLibcallReturnType() const;
210 /// getBooleanContents - For targets without i1 registers, this gives the
211 /// nature of the high-bits of boolean values held in types wider than i1.
212 /// "Boolean values" are special true/false values produced by nodes like
213 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
214 /// Not to be confused with general values promoted from i1.
215 /// Some cpus distinguish between vectors of boolean and scalars; the isVec
216 /// parameter selects between the two kinds. For example on X86 a scalar
217 /// boolean should be zero extended from i1, while the elements of a vector
218 /// of booleans should be sign extended from i1.
219 BooleanContent getBooleanContents(bool isVec) const {
220 return isVec ? BooleanVectorContents : BooleanContents;
223 /// getSchedulingPreference - Return target scheduling preference.
224 Sched::Preference getSchedulingPreference() const {
225 return SchedPreferenceInfo;
228 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
229 /// different scheduling heuristics for different nodes. This function returns
230 /// the preference (or none) for the given node.
231 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
235 /// getRegClassFor - Return the register class that should be used for the
236 /// specified value type.
237 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
238 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
239 assert(RC && "This value type is not natively supported!");
243 /// getRepRegClassFor - Return the 'representative' register class for the
244 /// specified value type. The 'representative' register class is the largest
245 /// legal super-reg register class for the register class of the value type.
246 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
247 /// while the rep register class is GR64 on x86_64.
248 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
249 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
253 /// getRepRegClassCostFor - Return the cost of the 'representative' register
254 /// class for the specified value type.
255 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
256 return RepRegClassCostForVT[VT.SimpleTy];
259 /// isTypeLegal - Return true if the target has native support for the
260 /// specified value type. This means that it has a register that directly
261 /// holds it without promotions or expansions.
262 bool isTypeLegal(EVT VT) const {
263 assert(!VT.isSimple() ||
264 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
265 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
268 class ValueTypeActionImpl {
269 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
270 /// that indicates how instruction selection should deal with the type.
271 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
274 ValueTypeActionImpl() {
275 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
278 LegalizeTypeAction getTypeAction(MVT VT) const {
279 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
282 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
283 unsigned I = VT.SimpleTy;
284 ValueTypeActions[I] = Action;
288 const ValueTypeActionImpl &getValueTypeActions() const {
289 return ValueTypeActions;
292 /// getTypeAction - Return how we should legalize values of this type, either
293 /// it is already legal (return 'Legal') or we need to promote it to a larger
294 /// type (return 'Promote'), or we need to expand it into multiple registers
295 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
296 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
297 return getTypeConversion(Context, VT).first;
299 LegalizeTypeAction getTypeAction(MVT VT) const {
300 return ValueTypeActions.getTypeAction(VT);
303 /// getTypeToTransformTo - For types supported by the target, this is an
304 /// identity function. For types that must be promoted to larger types, this
305 /// returns the larger type to promote to. For integer types that are larger
306 /// than the largest integer register, this contains one step in the expansion
307 /// to get to the smaller register. For illegal floating point types, this
308 /// returns the integer type to transform to.
309 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
310 return getTypeConversion(Context, VT).second;
313 /// getTypeToExpandTo - For types supported by the target, this is an
314 /// identity function. For types that must be expanded (i.e. integer types
315 /// that are larger than the largest integer register or illegal floating
316 /// point types), this returns the largest legal type it will be expanded to.
317 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
318 assert(!VT.isVector());
320 switch (getTypeAction(Context, VT)) {
323 case TypeExpandInteger:
324 VT = getTypeToTransformTo(Context, VT);
327 llvm_unreachable("Type is not legal nor is it to be expanded!");
332 /// getVectorTypeBreakdown - Vector types are broken down into some number of
333 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
334 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
335 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
337 /// This method returns the number of registers needed, and the VT for each
338 /// register. It also returns the VT and quantity of the intermediate values
339 /// before they are promoted/expanded.
341 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
343 unsigned &NumIntermediates,
344 MVT &RegisterVT) const;
346 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
347 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
348 /// this is the case, it returns true and store the intrinsic
349 /// information into the IntrinsicInfo that was passed to the function.
350 struct IntrinsicInfo {
351 unsigned opc; // target opcode
352 EVT memVT; // memory VT
353 const Value* ptrVal; // value representing memory location
354 int offset; // offset off of ptrVal
355 unsigned align; // alignment
356 bool vol; // is volatile?
357 bool readMem; // reads memory?
358 bool writeMem; // writes memory?
361 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
362 unsigned /*Intrinsic*/) const {
366 /// isFPImmLegal - Returns true if the target can instruction select the
367 /// specified FP immediate natively. If false, the legalizer will materialize
368 /// the FP immediate as a load from a constant pool.
369 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
373 /// isShuffleMaskLegal - Targets can use this to indicate that they only
374 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
375 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
376 /// are assumed to be legal.
377 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
382 /// canOpTrap - Returns true if the operation can trap for the value type.
383 /// VT must be a legal type. By default, we optimistically assume most
384 /// operations don't trap except for divide and remainder.
385 virtual bool canOpTrap(unsigned Op, EVT VT) const;
387 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
388 /// used by Targets can use this to indicate if there is a suitable
389 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
391 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
396 /// getOperationAction - Return how this operation should be treated: either
397 /// it is legal, needs to be promoted to a larger size, needs to be
398 /// expanded to some other code sequence, or the target has a custom expander
400 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
401 if (VT.isExtended()) return Expand;
402 // If a target-specific SDNode requires legalization, require the target
403 // to provide custom legalization for it.
404 if (Op > array_lengthof(OpActions[0])) return Custom;
405 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
406 return (LegalizeAction)OpActions[I][Op];
409 /// isOperationLegalOrCustom - Return true if the specified operation is
410 /// legal on this target or can be made legal with custom lowering. This
411 /// is used to help guide high-level lowering decisions.
412 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
413 return (VT == MVT::Other || isTypeLegal(VT)) &&
414 (getOperationAction(Op, VT) == Legal ||
415 getOperationAction(Op, VT) == Custom);
418 /// isOperationLegalOrPromote - Return true if the specified operation is
419 /// legal on this target or can be made legal using promotion. This
420 /// is used to help guide high-level lowering decisions.
421 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
422 return (VT == MVT::Other || isTypeLegal(VT)) &&
423 (getOperationAction(Op, VT) == Legal ||
424 getOperationAction(Op, VT) == Promote);
427 /// isOperationExpand - Return true if the specified operation is illegal on
428 /// this target or unlikely to be made legal with custom lowering. This is
429 /// used to help guide high-level lowering decisions.
430 bool isOperationExpand(unsigned Op, EVT VT) const {
431 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
434 /// isOperationLegal - Return true if the specified operation is legal on this
436 bool isOperationLegal(unsigned Op, EVT VT) const {
437 return (VT == MVT::Other || isTypeLegal(VT)) &&
438 getOperationAction(Op, VT) == Legal;
441 /// getLoadExtAction - Return how this load with extension should be treated:
442 /// either it is legal, needs to be promoted to a larger size, needs to be
443 /// expanded to some other code sequence, or the target has a custom expander
445 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
446 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
447 "Table isn't big enough!");
448 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
451 /// isLoadExtLegal - Return true if the specified load with extension is legal
453 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
454 return VT.isSimple() &&
455 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
458 /// getTruncStoreAction - Return how this store with truncation should be
459 /// treated: either it is legal, needs to be promoted to a larger size, needs
460 /// to be expanded to some other code sequence, or the target has a custom
462 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
463 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
464 "Table isn't big enough!");
465 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
469 /// isTruncStoreLegal - Return true if the specified store with truncation is
470 /// legal on this target.
471 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
472 return isTypeLegal(ValVT) && MemVT.isSimple() &&
473 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
476 /// getIndexedLoadAction - Return how the indexed load should be treated:
477 /// either it is legal, needs to be promoted to a larger size, needs to be
478 /// expanded to some other code sequence, or the target has a custom expander
481 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
482 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
483 "Table isn't big enough!");
484 unsigned Ty = (unsigned)VT.SimpleTy;
485 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
488 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
490 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
491 return VT.isSimple() &&
492 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
493 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
496 /// getIndexedStoreAction - Return how the indexed store should be treated:
497 /// either it is legal, needs to be promoted to a larger size, needs to be
498 /// expanded to some other code sequence, or the target has a custom expander
501 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
502 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
503 "Table isn't big enough!");
504 unsigned Ty = (unsigned)VT.SimpleTy;
505 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
508 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
510 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
511 return VT.isSimple() &&
512 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
513 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
516 /// getCondCodeAction - Return how the condition code should be treated:
517 /// either it is legal, needs to be expanded to some other code sequence,
518 /// or the target has a custom expander for it.
520 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
521 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
522 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
523 "Table isn't big enough!");
524 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
525 /// value and the upper 27 bits index into the second dimension of the
526 /// array to select what 64bit value to use.
527 LegalizeAction Action = (LegalizeAction)
528 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3);
529 assert(Action != Promote && "Can't promote condition code!");
533 /// isCondCodeLegal - Return true if the specified condition code is legal
535 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
537 getCondCodeAction(CC, VT) == Legal ||
538 getCondCodeAction(CC, VT) == Custom;
542 /// getTypeToPromoteTo - If the action for this operation is to promote, this
543 /// method returns the ValueType to promote to.
544 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
545 assert(getOperationAction(Op, VT) == Promote &&
546 "This operation isn't promoted!");
548 // See if this has an explicit type specified.
549 std::map<std::pair<unsigned, MVT::SimpleValueType>,
550 MVT::SimpleValueType>::const_iterator PTTI =
551 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
552 if (PTTI != PromoteToType.end()) return PTTI->second;
554 assert((VT.isInteger() || VT.isFloatingPoint()) &&
555 "Cannot autopromote this type, add it with AddPromotedToType.");
559 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
560 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
561 "Didn't find type to promote to!");
562 } while (!isTypeLegal(NVT) ||
563 getOperationAction(Op, NVT) == Promote);
567 /// getValueType - Return the EVT corresponding to this LLVM type.
568 /// This is fixed by the LLVM operations except for the pointer size. If
569 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
570 /// counterpart (e.g. structs), otherwise it will assert.
571 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
572 // Lower scalar pointers to native pointer types.
573 if (Ty->isPointerTy()) return PointerTy;
575 if (Ty->isVectorTy()) {
576 VectorType *VTy = cast<VectorType>(Ty);
577 Type *Elm = VTy->getElementType();
578 // Lower vectors of pointers to native pointer types.
579 if (Elm->isPointerTy())
580 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
581 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
582 VTy->getNumElements());
584 return EVT::getEVT(Ty, AllowUnknown);
587 /// Return the MVT corresponding to this LLVM type. See getValueType.
588 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
589 return getValueType(Ty, AllowUnknown).getSimpleVT();
592 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
593 /// function arguments in the caller parameter area. This is the actual
594 /// alignment, not its logarithm.
595 virtual unsigned getByValTypeAlignment(Type *Ty) const;
597 /// getRegisterType - Return the type of registers that this ValueType will
598 /// eventually require.
599 MVT getRegisterType(MVT VT) const {
600 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
601 return RegisterTypeForVT[VT.SimpleTy];
604 /// getRegisterType - Return the type of registers that this ValueType will
605 /// eventually require.
606 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
608 assert((unsigned)VT.getSimpleVT().SimpleTy <
609 array_lengthof(RegisterTypeForVT));
610 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
615 unsigned NumIntermediates;
616 (void)getVectorTypeBreakdown(Context, VT, VT1,
617 NumIntermediates, RegisterVT);
620 if (VT.isInteger()) {
621 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
623 llvm_unreachable("Unsupported extended type!");
626 /// getNumRegisters - Return the number of registers that this ValueType will
627 /// eventually require. This is one for any types promoted to live in larger
628 /// registers, but may be more than one for types (like i64) that are split
629 /// into pieces. For types like i140, which are first promoted then expanded,
630 /// it is the number of registers needed to hold all the bits of the original
631 /// type. For an i140 on a 32 bit machine this means 5 registers.
632 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
634 assert((unsigned)VT.getSimpleVT().SimpleTy <
635 array_lengthof(NumRegistersForVT));
636 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
641 unsigned NumIntermediates;
642 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
644 if (VT.isInteger()) {
645 unsigned BitWidth = VT.getSizeInBits();
646 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
647 return (BitWidth + RegWidth - 1) / RegWidth;
649 llvm_unreachable("Unsupported extended type!");
652 /// ShouldShrinkFPConstant - If true, then instruction selection should
653 /// seek to shrink the FP constant of the specified type to a smaller type
654 /// in order to save space and / or reduce runtime.
655 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
657 /// hasTargetDAGCombine - If true, the target has custom DAG combine
658 /// transformations that it can perform for the specified node.
659 bool hasTargetDAGCombine(ISD::NodeType NT) const {
660 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
661 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
664 /// This function returns the maximum number of store operations permitted
665 /// to replace a call to llvm.memset. The value is set by the target at the
666 /// performance threshold for such a replacement. If OptSize is true,
667 /// return the limit for functions that have OptSize attribute.
668 /// @brief Get maximum # of store operations permitted for llvm.memset
669 unsigned getMaxStoresPerMemset(bool OptSize) const {
670 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
673 /// This function returns the maximum number of store operations permitted
674 /// to replace a call to llvm.memcpy. The value is set by the target at the
675 /// performance threshold for such a replacement. If OptSize is true,
676 /// return the limit for functions that have OptSize attribute.
677 /// @brief Get maximum # of store operations permitted for llvm.memcpy
678 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
679 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
682 /// This function returns the maximum number of store operations permitted
683 /// to replace a call to llvm.memmove. The value is set by the target at the
684 /// performance threshold for such a replacement. If OptSize is true,
685 /// return the limit for functions that have OptSize attribute.
686 /// @brief Get maximum # of store operations permitted for llvm.memmove
687 unsigned getMaxStoresPerMemmove(bool OptSize) const {
688 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
691 /// This function returns true if the target allows unaligned memory accesses.
692 /// of the specified type. If true, it also returns whether the unaligned
693 /// memory access is "fast" in the second argument by reference. This is used,
694 /// for example, in situations where an array copy/move/set is converted to a
695 /// sequence of store operations. It's use helps to ensure that such
696 /// replacements don't generate code that causes an alignment error (trap) on
697 /// the target machine.
698 /// @brief Determine if the target supports unaligned memory accesses.
699 virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) const {
703 /// getOptimalMemOpType - Returns the target specific optimal type for load
704 /// and store operations as a result of memset, memcpy, and memmove
705 /// lowering. If DstAlign is zero that means it's safe to destination
706 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
707 /// means there isn't a need to check it against alignment requirement,
708 /// probably because the source does not need to be loaded. If 'IsMemset' is
709 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
710 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
711 /// source is constant so it does not need to be loaded.
712 /// It returns EVT::Other if the type should be determined using generic
713 /// target-independent logic.
714 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
715 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
718 bool /*MemcpyStrSrc*/,
719 MachineFunction &/*MF*/) const {
723 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
724 /// specified type to expand memcpy / memset inline. This is mostly true
725 /// for all types except for some special cases. For example, on X86
726 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
727 /// also does type conversion. Note the specified type doesn't have to be
728 /// legal as the hook is used before type legalization.
729 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
731 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
732 /// to implement llvm.setjmp.
733 bool usesUnderscoreSetJmp() const {
734 return UseUnderscoreSetJmp;
737 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
738 /// to implement llvm.longjmp.
739 bool usesUnderscoreLongJmp() const {
740 return UseUnderscoreLongJmp;
743 /// supportJumpTables - return whether the target can generate code for
745 bool supportJumpTables() const {
746 return SupportJumpTables;
749 /// getMinimumJumpTableEntries - return integer threshold on number of
750 /// blocks to use jump tables rather than if sequence.
751 int getMinimumJumpTableEntries() const {
752 return MinimumJumpTableEntries;
755 /// getStackPointerRegisterToSaveRestore - If a physical register, this
756 /// specifies the register that llvm.savestack/llvm.restorestack should save
758 unsigned getStackPointerRegisterToSaveRestore() const {
759 return StackPointerRegisterToSaveRestore;
762 /// getExceptionPointerRegister - If a physical register, this returns
763 /// the register that receives the exception address on entry to a landing
765 unsigned getExceptionPointerRegister() const {
766 return ExceptionPointerRegister;
769 /// getExceptionSelectorRegister - If a physical register, this returns
770 /// the register that receives the exception typeid on entry to a landing
772 unsigned getExceptionSelectorRegister() const {
773 return ExceptionSelectorRegister;
776 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
777 /// set, the default is 200)
778 unsigned getJumpBufSize() const {
782 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
783 /// (if never set, the default is 0)
784 unsigned getJumpBufAlignment() const {
785 return JumpBufAlignment;
788 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
790 unsigned getMinStackArgumentAlignment() const {
791 return MinStackArgumentAlignment;
794 /// getMinFunctionAlignment - return the minimum function alignment.
796 unsigned getMinFunctionAlignment() const {
797 return MinFunctionAlignment;
800 /// getPrefFunctionAlignment - return the preferred function alignment.
802 unsigned getPrefFunctionAlignment() const {
803 return PrefFunctionAlignment;
806 /// getPrefLoopAlignment - return the preferred loop alignment.
808 unsigned getPrefLoopAlignment() const {
809 return PrefLoopAlignment;
812 /// getInsertFencesFor - return whether the DAG builder should automatically
813 /// insert fences and reduce ordering for atomics.
815 bool getInsertFencesForAtomic() const {
816 return InsertFencesForAtomic;
819 /// getStackCookieLocation - Return true if the target stores stack
820 /// protector cookies at a fixed offset in some non-standard address
821 /// space, and populates the address space and offset as
823 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
824 unsigned &/*Offset*/) const {
828 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
829 /// used for loads / stores from the global.
830 virtual unsigned getMaximalGlobalOffset() const {
834 //===--------------------------------------------------------------------===//
835 /// \name Helpers for TargetTransformInfo implementations
838 /// Get the ISD node that corresponds to the Instruction class opcode.
839 int InstructionOpcodeToISD(unsigned Opcode) const;
841 /// Estimate the cost of type-legalization and the legalized type.
842 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
846 //===--------------------------------------------------------------------===//
847 // TargetLowering Configuration Methods - These methods should be invoked by
848 // the derived class constructor to configure this object for the target.
851 /// \brief Reset the operation actions based on target options.
852 virtual void resetOperationActions() {}
855 /// setBooleanContents - Specify how the target extends the result of a
856 /// boolean value from i1 to a wider type. See getBooleanContents.
857 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
858 /// setBooleanVectorContents - Specify how the target extends the result
859 /// of a vector boolean value from a vector of i1 to a wider type. See
860 /// getBooleanContents.
861 void setBooleanVectorContents(BooleanContent Ty) {
862 BooleanVectorContents = Ty;
865 /// setSchedulingPreference - Specify the target scheduling preference.
866 void setSchedulingPreference(Sched::Preference Pref) {
867 SchedPreferenceInfo = Pref;
870 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
871 /// use _setjmp to implement llvm.setjmp or the non _ version.
872 /// Defaults to false.
873 void setUseUnderscoreSetJmp(bool Val) {
874 UseUnderscoreSetJmp = Val;
877 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
878 /// use _longjmp to implement llvm.longjmp or the non _ version.
879 /// Defaults to false.
880 void setUseUnderscoreLongJmp(bool Val) {
881 UseUnderscoreLongJmp = Val;
884 /// setSupportJumpTables - Indicate whether the target can generate code for
886 void setSupportJumpTables(bool Val) {
887 SupportJumpTables = Val;
890 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate
891 /// jump tables rather than if sequence.
892 void setMinimumJumpTableEntries(int Val) {
893 MinimumJumpTableEntries = Val;
896 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
897 /// specifies the register that llvm.savestack/llvm.restorestack should save
899 void setStackPointerRegisterToSaveRestore(unsigned R) {
900 StackPointerRegisterToSaveRestore = R;
903 /// setExceptionPointerRegister - If set to a physical register, this sets
904 /// the register that receives the exception address on entry to a landing
906 void setExceptionPointerRegister(unsigned R) {
907 ExceptionPointerRegister = R;
910 /// setExceptionSelectorRegister - If set to a physical register, this sets
911 /// the register that receives the exception typeid on entry to a landing
913 void setExceptionSelectorRegister(unsigned R) {
914 ExceptionSelectorRegister = R;
917 /// SelectIsExpensive - Tells the code generator not to expand operations
918 /// into sequences that use the select operations if possible.
919 void setSelectIsExpensive(bool isExpensive = true) {
920 SelectIsExpensive = isExpensive;
923 /// JumpIsExpensive - Tells the code generator not to expand sequence of
924 /// operations into a separate sequences that increases the amount of
926 void setJumpIsExpensive(bool isExpensive = true) {
927 JumpIsExpensive = isExpensive;
930 /// setIntDivIsCheap - Tells the code generator that integer divide is
931 /// expensive, and if possible, should be replaced by an alternate sequence
932 /// of instructions not containing an integer divide.
933 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
935 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass.
936 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
937 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
940 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
941 /// srl/add/sra for a signed divide by power of two, and let the target handle
943 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
945 /// addRegisterClass - Add the specified register class as an available
946 /// regclass for the specified value type. This indicates the selector can
947 /// handle values of that class natively.
948 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
949 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
950 AvailableRegClasses.push_back(std::make_pair(VT, RC));
951 RegClassForVT[VT.SimpleTy] = RC;
954 /// clearRegisterClasses - Remove all register classes.
955 void clearRegisterClasses() {
956 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
958 AvailableRegClasses.clear();
961 /// \brief Remove all operation actions.
962 void clearOperationActions() {
965 /// findRepresentativeClass - Return the largest legal super-reg register class
966 /// of the register class for the specified type and its associated "cost".
967 virtual std::pair<const TargetRegisterClass*, uint8_t>
968 findRepresentativeClass(MVT VT) const;
970 /// computeRegisterProperties - Once all of the register classes are added,
971 /// this allows us to compute derived properties we expose.
972 void computeRegisterProperties();
974 /// setOperationAction - Indicate that the specified operation does not work
975 /// with the specified type and indicate what to do about it.
976 void setOperationAction(unsigned Op, MVT VT,
977 LegalizeAction Action) {
978 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
979 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
982 /// setLoadExtAction - Indicate that the specified load with extension does
983 /// not work with the specified type and indicate what to do about it.
984 void setLoadExtAction(unsigned ExtType, MVT VT,
985 LegalizeAction Action) {
986 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
987 "Table isn't big enough!");
988 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
991 /// setTruncStoreAction - Indicate that the specified truncating store does
992 /// not work with the specified type and indicate what to do about it.
993 void setTruncStoreAction(MVT ValVT, MVT MemVT,
994 LegalizeAction Action) {
995 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
996 "Table isn't big enough!");
997 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1000 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1001 /// does not work with the specified type and indicate what to do abort
1002 /// it. NOTE: All indexed mode loads are initialized to Expand in
1003 /// TargetLowering.cpp
1004 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1005 LegalizeAction Action) {
1006 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1007 (unsigned)Action < 0xf && "Table isn't big enough!");
1008 // Load action are kept in the upper half.
1009 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1010 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1013 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1014 /// does not work with the specified type and indicate what to do about
1015 /// it. NOTE: All indexed mode stores are initialized to Expand in
1016 /// TargetLowering.cpp
1017 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1018 LegalizeAction Action) {
1019 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1020 (unsigned)Action < 0xf && "Table isn't big enough!");
1021 // Store action are kept in the lower half.
1022 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1023 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1026 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1027 /// supported on the target and indicate what to do about it.
1028 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1029 LegalizeAction Action) {
1030 assert(VT < MVT::LAST_VALUETYPE &&
1031 (unsigned)CC < array_lengthof(CondCodeActions) &&
1032 "Table isn't big enough!");
1033 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
1034 /// value and the upper 27 bits index into the second dimension of the
1035 /// array to select what 64bit value to use.
1036 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1037 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);
1038 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1039 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
1042 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1043 /// promotion code defaults to trying a larger integer/fp until it can find
1044 /// one that works. If that default is insufficient, this method can be used
1045 /// by the target to override the default.
1046 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1047 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1050 /// setTargetDAGCombine - Targets should invoke this method for each target
1051 /// independent node that they want to provide a custom DAG combiner for by
1052 /// implementing the PerformDAGCombine virtual method.
1053 void setTargetDAGCombine(ISD::NodeType NT) {
1054 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1055 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1058 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1059 /// bytes); default is 200
1060 void setJumpBufSize(unsigned Size) {
1064 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1065 /// alignment (in bytes); default is 0
1066 void setJumpBufAlignment(unsigned Align) {
1067 JumpBufAlignment = Align;
1070 /// setMinFunctionAlignment - Set the target's minimum function alignment (in
1072 void setMinFunctionAlignment(unsigned Align) {
1073 MinFunctionAlignment = Align;
1076 /// setPrefFunctionAlignment - Set the target's preferred function alignment.
1077 /// This should be set if there is a performance benefit to
1078 /// higher-than-minimum alignment (in log2(bytes))
1079 void setPrefFunctionAlignment(unsigned Align) {
1080 PrefFunctionAlignment = Align;
1083 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1084 /// alignment is zero, it means the target does not care about loop alignment.
1085 /// The alignment is specified in log2(bytes).
1086 void setPrefLoopAlignment(unsigned Align) {
1087 PrefLoopAlignment = Align;
1090 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1091 /// argument (in log2(bytes)).
1092 void setMinStackArgumentAlignment(unsigned Align) {
1093 MinStackArgumentAlignment = Align;
1096 /// setInsertFencesForAtomic - Set if the DAG builder should
1097 /// automatically insert fences and reduce the order of atomic memory
1098 /// operations to Monotonic.
1099 void setInsertFencesForAtomic(bool fence) {
1100 InsertFencesForAtomic = fence;
1104 //===--------------------------------------------------------------------===//
1105 // Addressing mode description hooks (used by LSR etc).
1108 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1109 /// same BB as Load/Store instructions reading the address. This allows as
1110 /// much computation as possible to be done in the address mode for that
1111 /// operand. This hook lets targets also pass back when this should be done
1112 /// on intrinsics which load/store.
1113 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1114 SmallVectorImpl<Value*> &/*Ops*/,
1115 Type *&/*AccessTy*/) const {
1119 /// AddrMode - This represents an addressing mode of:
1120 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1121 /// If BaseGV is null, there is no BaseGV.
1122 /// If BaseOffs is zero, there is no base offset.
1123 /// If HasBaseReg is false, there is no base register.
1124 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1128 GlobalValue *BaseGV;
1132 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1135 /// isLegalAddressingMode - Return true if the addressing mode represented by
1136 /// AM is legal for this target, for a load/store of the specified type.
1137 /// The type may be VoidTy, in which case only return true if the addressing
1138 /// mode is legal for a load/store of any legal type.
1139 /// TODO: Handle pre/postinc as well.
1140 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1142 /// \brief Return the cost of the scaling factor used in the addressing
1143 /// mode represented by AM for this target, for a load/store
1144 /// of the specified type.
1145 /// If the AM is supported, the return value must be >= 0.
1146 /// If the AM is not supported, it returns a negative value.
1147 /// TODO: Handle pre/postinc as well.
1148 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1149 // Default: assume that any scaling factor used in a legal AM is free.
1150 if (isLegalAddressingMode(AM, Ty)) return 0;
1154 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1155 /// icmp immediate, that is the target has icmp instructions which can compare
1156 /// a register against the immediate without having to materialize the
1157 /// immediate into a register.
1158 virtual bool isLegalICmpImmediate(int64_t) const {
1162 /// isLegalAddImmediate - Return true if the specified immediate is legal
1163 /// add immediate, that is the target has add instructions which can add
1164 /// a register with the immediate without having to materialize the
1165 /// immediate into a register.
1166 virtual bool isLegalAddImmediate(int64_t) const {
1170 /// isTruncateFree - Return true if it's free to truncate a value of
1171 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1172 /// register EAX to i16 by referencing its sub-register AX.
1173 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1177 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1181 /// isZExtFree - Return true if any actual instruction that defines a
1182 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1183 /// register. This does not necessarily include registers defined in
1184 /// unknown ways, such as incoming arguments, or copies from unknown
1185 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1186 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1187 /// all instructions that define 32-bit values implicit zero-extend the
1188 /// result out to 64 bits.
1189 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1193 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1197 /// isZExtFree - Return true if zero-extending the specific node Val to type
1198 /// VT2 is free (either because it's implicitly zero-extended such as ARM
1199 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
1200 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1201 return isZExtFree(Val.getValueType(), VT2);
1204 /// isFNegFree - Return true if an fneg operation is free to the point where
1205 /// it is never worthwhile to replace it with a bitwise operation.
1206 virtual bool isFNegFree(EVT) const {
1210 /// isFAbsFree - Return true if an fneg operation is free to the point where
1211 /// it is never worthwhile to replace it with a bitwise operation.
1212 virtual bool isFAbsFree(EVT) const {
1216 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1217 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1218 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1219 /// is expanded to mul + add.
1220 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1224 /// isNarrowingProfitable - Return true if it's profitable to narrow
1225 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1226 /// from i32 to i8 but not from i32 to i16.
1227 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1231 //===--------------------------------------------------------------------===//
1232 // Runtime Library hooks
1235 /// setLibcallName - Rename the default libcall routine name for the specified
1237 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1238 LibcallRoutineNames[Call] = Name;
1241 /// getLibcallName - Get the libcall routine name for the specified libcall.
1243 const char *getLibcallName(RTLIB::Libcall Call) const {
1244 return LibcallRoutineNames[Call];
1247 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1248 /// result of the comparison libcall against zero.
1249 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1250 CmpLibcallCCs[Call] = CC;
1253 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1254 /// the comparison libcall against zero.
1255 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1256 return CmpLibcallCCs[Call];
1259 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1260 /// specified libcall.
1261 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1262 LibcallCallingConvs[Call] = CC;
1265 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1266 /// specified libcall.
1267 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1268 return LibcallCallingConvs[Call];
1272 const TargetMachine &TM;
1273 const DataLayout *TD;
1274 const TargetLoweringObjectFile &TLOF;
1276 /// PointerTy - The type to use for pointers for the default address space,
1277 /// usually i32 or i64.
1281 /// IsLittleEndian - True if this is a little endian target.
1283 bool IsLittleEndian;
1285 /// SelectIsExpensive - Tells the code generator not to expand operations
1286 /// into sequences that use the select operations if possible.
1287 bool SelectIsExpensive;
1289 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1290 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1291 /// a real cost model is in place. If we ever optimize for size, this will be
1292 /// set to true unconditionally.
1295 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1296 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1297 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1298 /// integer div/rem when the operands are positive and less than 256.
1299 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1301 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1302 /// srl/add/sra for a signed divide by power of two, and let the target handle
1304 bool Pow2DivIsCheap;
1306 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1307 /// extra flow control instructions and should attempt to combine flow
1308 /// control instructions via predication.
1309 bool JumpIsExpensive;
1311 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1312 /// llvm.setjmp. Defaults to false.
1313 bool UseUnderscoreSetJmp;
1315 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1316 /// llvm.longjmp. Defaults to false.
1317 bool UseUnderscoreLongJmp;
1319 /// SupportJumpTables - Whether the target can generate code for jumptables.
1320 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1321 bool SupportJumpTables;
1323 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1324 int MinimumJumpTableEntries;
1326 /// BooleanContents - Information about the contents of the high-bits in
1327 /// boolean values held in a type wider than i1. See getBooleanContents.
1328 BooleanContent BooleanContents;
1329 /// BooleanVectorContents - Information about the contents of the high-bits
1330 /// in boolean vector values when the element type is wider than i1. See
1331 /// getBooleanContents.
1332 BooleanContent BooleanVectorContents;
1334 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1335 /// total cycles or lowest register usage.
1336 Sched::Preference SchedPreferenceInfo;
1338 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1339 unsigned JumpBufSize;
1341 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1343 unsigned JumpBufAlignment;
1345 /// MinStackArgumentAlignment - The minimum alignment that any argument
1346 /// on the stack needs to have.
1348 unsigned MinStackArgumentAlignment;
1350 /// MinFunctionAlignment - The minimum function alignment (used when
1351 /// optimizing for size, and to prevent explicitly provided alignment
1352 /// from leading to incorrect code).
1354 unsigned MinFunctionAlignment;
1356 /// PrefFunctionAlignment - The preferred function alignment (used when
1357 /// alignment unspecified and optimizing for speed).
1359 unsigned PrefFunctionAlignment;
1361 /// PrefLoopAlignment - The preferred loop alignment.
1363 unsigned PrefLoopAlignment;
1365 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1366 /// insert fences and reduce ordering for atomics. (This will be set for
1367 /// for most architectures with weak memory ordering.)
1368 bool InsertFencesForAtomic;
1370 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1371 /// specifies the register that llvm.savestack/llvm.restorestack should save
1373 unsigned StackPointerRegisterToSaveRestore;
1375 /// ExceptionPointerRegister - If set to a physical register, this specifies
1376 /// the register that receives the exception address on entry to a landing
1378 unsigned ExceptionPointerRegister;
1380 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1381 /// the register that receives the exception typeid on entry to a landing
1383 unsigned ExceptionSelectorRegister;
1385 /// RegClassForVT - This indicates the default register class to use for
1386 /// each ValueType the target supports natively.
1387 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1388 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1389 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1391 /// RepRegClassForVT - This indicates the "representative" register class to
1392 /// use for each ValueType the target supports natively. This information is
1393 /// used by the scheduler to track register pressure. By default, the
1394 /// representative register class is the largest legal super-reg register
1395 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1396 /// and i32's representative class would be GR32.
1397 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1399 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1400 /// register class for each ValueType. The cost is used by the scheduler to
1401 /// approximate register pressure.
1402 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1404 /// TransformToType - For any value types we are promoting or expanding, this
1405 /// contains the value type that we are changing to. For Expanded types, this
1406 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1407 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1408 /// by the system, this holds the same type (e.g. i32 -> i32).
1409 MVT TransformToType[MVT::LAST_VALUETYPE];
1411 /// OpActions - For each operation and each value type, keep a LegalizeAction
1412 /// that indicates how instruction selection should deal with the operation.
1413 /// Most operations are Legal (aka, supported natively by the target), but
1414 /// operations that are not should be described. Note that operations on
1415 /// non-legal value types are not described here.
1416 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1418 /// LoadExtActions - For each load extension type and each value type,
1419 /// keep a LegalizeAction that indicates how instruction selection should deal
1420 /// with a load of a specific value type and extension type.
1421 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1423 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1424 /// indicates whether a truncating store of a specific value type and
1425 /// truncating type is legal.
1426 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1428 /// IndexedModeActions - For each indexed mode and each value type,
1429 /// keep a pair of LegalizeAction that indicates how instruction
1430 /// selection should deal with the load / store. The first dimension is the
1431 /// value_type for the reference. The second dimension represents the various
1432 /// modes for load store.
1433 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1435 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1436 /// LegalizeAction that indicates how instruction selection should
1437 /// deal with the condition code.
1438 /// Because each CC action takes up 2 bits, we need to have the array size
1439 /// be large enough to fit all of the value types. This can be done by
1440 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
1441 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
1443 ValueTypeActionImpl ValueTypeActions;
1447 getTypeConversion(LLVMContext &Context, EVT VT) const {
1448 // If this is a simple type, use the ComputeRegisterProp mechanism.
1449 if (VT.isSimple()) {
1450 MVT SVT = VT.getSimpleVT();
1451 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1452 MVT NVT = TransformToType[SVT.SimpleTy];
1453 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1457 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1458 && "Promote may not follow Expand or Promote");
1460 if (LA == TypeSplitVector)
1461 return LegalizeKind(LA, EVT::getVectorVT(Context,
1462 SVT.getVectorElementType(),
1463 SVT.getVectorNumElements()/2));
1464 if (LA == TypeScalarizeVector)
1465 return LegalizeKind(LA, SVT.getVectorElementType());
1466 return LegalizeKind(LA, NVT);
1469 // Handle Extended Scalar Types.
1470 if (!VT.isVector()) {
1471 assert(VT.isInteger() && "Float types must be simple");
1472 unsigned BitSize = VT.getSizeInBits();
1473 // First promote to a power-of-two size, then expand if necessary.
1474 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1475 EVT NVT = VT.getRoundIntegerType(Context);
1476 assert(NVT != VT && "Unable to round integer VT");
1477 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1478 // Avoid multi-step promotion.
1479 if (NextStep.first == TypePromoteInteger) return NextStep;
1480 // Return rounded integer type.
1481 return LegalizeKind(TypePromoteInteger, NVT);
1484 return LegalizeKind(TypeExpandInteger,
1485 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1488 // Handle vector types.
1489 unsigned NumElts = VT.getVectorNumElements();
1490 EVT EltVT = VT.getVectorElementType();
1492 // Vectors with only one element are always scalarized.
1494 return LegalizeKind(TypeScalarizeVector, EltVT);
1496 // Try to widen vector elements until a legal type is found.
1497 if (EltVT.isInteger()) {
1498 // Vectors with a number of elements that is not a power of two are always
1499 // widened, for example <3 x float> -> <4 x float>.
1500 if (!VT.isPow2VectorType()) {
1501 NumElts = (unsigned)NextPowerOf2(NumElts);
1502 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1503 return LegalizeKind(TypeWidenVector, NVT);
1506 // Examine the element type.
1507 LegalizeKind LK = getTypeConversion(Context, EltVT);
1509 // If type is to be expanded, split the vector.
1510 // <4 x i140> -> <2 x i140>
1511 if (LK.first == TypeExpandInteger)
1512 return LegalizeKind(TypeSplitVector,
1513 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1515 // Promote the integer element types until a legal vector type is found
1516 // or until the element integer type is too big. If a legal type was not
1517 // found, fallback to the usual mechanism of widening/splitting the
1519 EVT OldEltVT = EltVT;
1521 // Increase the bitwidth of the element to the next pow-of-two
1522 // (which is greater than 8 bits).
1523 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1524 ).getRoundIntegerType(Context);
1526 // Stop trying when getting a non-simple element type.
1527 // Note that vector elements may be greater than legal vector element
1528 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
1529 if (!EltVT.isSimple()) break;
1531 // Build a new vector type and check if it is legal.
1532 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1533 // Found a legal promoted vector type.
1534 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1535 return LegalizeKind(TypePromoteInteger,
1536 EVT::getVectorVT(Context, EltVT, NumElts));
1539 // Reset the type to the unexpanded type if we did not find a legal vector
1540 // type with a promoted vector element type.
1544 // Try to widen the vector until a legal type is found.
1545 // If there is no wider legal type, split the vector.
1547 // Round up to the next power of 2.
1548 NumElts = (unsigned)NextPowerOf2(NumElts);
1550 // If there is no simple vector type with this many elements then there
1551 // cannot be a larger legal vector type. Note that this assumes that
1552 // there are no skipped intermediate vector types in the simple types.
1553 if (!EltVT.isSimple()) break;
1554 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1555 if (LargerVector == MVT()) break;
1557 // If this type is legal then widen the vector.
1558 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1559 return LegalizeKind(TypeWidenVector, LargerVector);
1562 // Widen odd vectors to next power of two.
1563 if (!VT.isPow2VectorType()) {
1564 EVT NVT = VT.getPow2VectorType(Context);
1565 return LegalizeKind(TypeWidenVector, NVT);
1568 // Vectors with illegal element types are expanded.
1569 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1570 return LegalizeKind(TypeSplitVector, NVT);
1574 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1576 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1577 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1578 /// which sets a bit in this array.
1580 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1582 /// PromoteToType - For operations that must be promoted to a specific type,
1583 /// this holds the destination type. This map should be sparse, so don't hold
1586 /// Targets add entries to this map with AddPromotedToType(..), clients access
1587 /// this with getTypeToPromoteTo(..).
1588 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1591 /// LibcallRoutineNames - Stores the name each libcall.
1593 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1595 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1596 /// of each of the comparison libcall against zero.
1597 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1599 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1601 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1604 /// When lowering \@llvm.memset this field specifies the maximum number of
1605 /// store operations that may be substituted for the call to memset. Targets
1606 /// must set this value based on the cost threshold for that target. Targets
1607 /// should assume that the memset will be done using as many of the largest
1608 /// store operations first, followed by smaller ones, if necessary, per
1609 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1610 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1611 /// store. This only applies to setting a constant array of a constant size.
1612 /// @brief Specify maximum number of store instructions per memset call.
1613 unsigned MaxStoresPerMemset;
1615 /// Maximum number of stores operations that may be substituted for the call
1616 /// to memset, used for functions with OptSize attribute.
1617 unsigned MaxStoresPerMemsetOptSize;
1619 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1620 /// store operations that may be substituted for a call to memcpy. Targets
1621 /// must set this value based on the cost threshold for that target. Targets
1622 /// should assume that the memcpy will be done using as many of the largest
1623 /// store operations first, followed by smaller ones, if necessary, per
1624 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1625 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1626 /// and one 1-byte store. This only applies to copying a constant array of
1628 /// @brief Specify maximum bytes of store instructions per memcpy call.
1629 unsigned MaxStoresPerMemcpy;
1631 /// Maximum number of store operations that may be substituted for a call
1632 /// to memcpy, used for functions with OptSize attribute.
1633 unsigned MaxStoresPerMemcpyOptSize;
1635 /// When lowering \@llvm.memmove this field specifies the maximum number of
1636 /// store instructions that may be substituted for a call to memmove. Targets
1637 /// must set this value based on the cost threshold for that target. Targets
1638 /// should assume that the memmove will be done using as many of the largest
1639 /// store operations first, followed by smaller ones, if necessary, per
1640 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1641 /// with 8-bit alignment would result in nine 1-byte stores. This only
1642 /// applies to copying a constant array of constant size.
1643 /// @brief Specify maximum bytes of store instructions per memmove call.
1644 unsigned MaxStoresPerMemmove;
1646 /// Maximum number of store instructions that may be substituted for a call
1647 /// to memmove, used for functions with OpSize attribute.
1648 unsigned MaxStoresPerMemmoveOptSize;
1650 /// PredictableSelectIsExpensive - Tells the code generator that select is
1651 /// more expensive than a branch if the branch is usually predicted right.
1652 bool PredictableSelectIsExpensive;
1655 /// isLegalRC - Return true if the value types that can be represented by the
1656 /// specified register class are all legal.
1657 bool isLegalRC(const TargetRegisterClass *RC) const;
1660 //===----------------------------------------------------------------------===//
1661 /// TargetLowering - This class defines information used to lower LLVM code to
1662 /// legal SelectionDAG operators that the target instruction selector can accept
1665 /// This class also defines callbacks that targets must implement to lower
1666 /// target-specific constructs to SelectionDAG operators.
1668 class TargetLowering : public TargetLoweringBase {
1669 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1670 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1673 /// NOTE: The constructor takes ownership of TLOF.
1674 explicit TargetLowering(const TargetMachine &TM,
1675 const TargetLoweringObjectFile *TLOF);
1677 /// getPreIndexedAddressParts - returns true by value, base pointer and
1678 /// offset pointer and addressing mode by reference if the node's address
1679 /// can be legally represented as pre-indexed load / store address.
1680 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1681 SDValue &/*Offset*/,
1682 ISD::MemIndexedMode &/*AM*/,
1683 SelectionDAG &/*DAG*/) const {
1687 /// getPostIndexedAddressParts - returns true by value, base pointer and
1688 /// offset pointer and addressing mode by reference if this node can be
1689 /// combined with a load / store to form a post-indexed load / store.
1690 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1691 SDValue &/*Base*/, SDValue &/*Offset*/,
1692 ISD::MemIndexedMode &/*AM*/,
1693 SelectionDAG &/*DAG*/) const {
1697 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1698 /// current function. The returned value is a member of the
1699 /// MachineJumpTableInfo::JTEntryKind enum.
1700 virtual unsigned getJumpTableEncoding() const;
1702 virtual const MCExpr *
1703 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1704 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1705 MCContext &/*Ctx*/) const {
1706 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1709 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1711 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1712 SelectionDAG &DAG) const;
1714 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1715 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1717 virtual const MCExpr *
1718 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1719 unsigned JTI, MCContext &Ctx) const;
1721 /// isOffsetFoldingLegal - Return true if folding a constant offset
1722 /// with the given GlobalAddress is legal. It is frequently not legal in
1723 /// PIC relocation models.
1724 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1726 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1727 SDValue &Chain) const;
1729 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1730 SDValue &NewLHS, SDValue &NewRHS,
1731 ISD::CondCode &CCCode, SDLoc DL) const;
1733 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
1734 const SDValue *Ops, unsigned NumOps,
1735 bool isSigned, SDLoc dl) const;
1737 //===--------------------------------------------------------------------===//
1738 // TargetLowering Optimization Methods
1741 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
1742 /// SDValues for returning information from TargetLowering to its clients
1743 /// that want to combine
1744 struct TargetLoweringOpt {
1751 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1753 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1755 bool LegalTypes() const { return LegalTys; }
1756 bool LegalOperations() const { return LegalOps; }
1758 bool CombineTo(SDValue O, SDValue N) {
1764 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1765 /// specified instruction is a constant integer. If so, check to see if
1766 /// there are any bits set in the constant that are not demanded. If so,
1767 /// shrink the constant and return true.
1768 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1770 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1771 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1772 /// cast, but it could be generalized for targets with other types of
1773 /// implicit widening casts.
1774 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1778 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1779 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1780 /// use this information to simplify Op, create a new simplified DAG node and
1781 /// return true, returning the original and new nodes in Old and New.
1782 /// Otherwise, analyze the expression and return a mask of KnownOne and
1783 /// KnownZero bits for the expression (used to simplify the caller).
1784 /// The KnownZero/One bits may only be accurate for those bits in the
1786 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1787 APInt &KnownZero, APInt &KnownOne,
1788 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1790 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
1791 /// Mask are known to be either zero or one and return them in the
1792 /// KnownZero/KnownOne bitsets.
1793 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1796 const SelectionDAG &DAG,
1797 unsigned Depth = 0) const;
1799 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1800 /// targets that want to expose additional information about sign bits to the
1802 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1803 unsigned Depth = 0) const;
1805 struct DAGCombinerInfo {
1806 void *DC; // The DAG Combiner object.
1808 bool CalledByLegalizer;
1812 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1813 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1815 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1816 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1817 bool isAfterLegalizeVectorOps() const {
1818 return Level == AfterLegalizeDAG;
1820 CombineLevel getDAGCombineLevel() { return Level; }
1821 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1823 void AddToWorklist(SDNode *N);
1824 void RemoveFromWorklist(SDNode *N);
1825 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1827 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1828 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1830 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1833 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1834 /// and cc. If it is unable to simplify it, return a null SDValue.
1835 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1836 ISD::CondCode Cond, bool foldBooleans,
1837 DAGCombinerInfo &DCI, SDLoc dl) const;
1839 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1840 /// node is a GlobalAddress + offset.
1842 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1844 /// PerformDAGCombine - This method will be invoked for all target nodes and
1845 /// for any target-independent nodes that the target has registered with
1848 /// The semantics are as follows:
1850 /// SDValue.Val == 0 - No change was made
1851 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1852 /// otherwise - N should be replaced by the returned Operand.
1854 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1855 /// more complex transformations.
1857 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1859 /// isTypeDesirableForOp - Return true if the target has native support for
1860 /// the specified value type and it is 'desirable' to use the type for the
1861 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1862 /// instruction encodings are longer and some i16 instructions are slow.
1863 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1864 // By default, assume all legal types are desirable.
1865 return isTypeLegal(VT);
1868 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
1869 /// to transform a floating point op of specified opcode to a equivalent op of
1870 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
1871 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1876 /// IsDesirableToPromoteOp - This method query the target whether it is
1877 /// beneficial for dag combiner to promote the specified node. If true, it
1878 /// should return the desired promotion type by reference.
1879 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1883 //===--------------------------------------------------------------------===//
1884 // Lowering methods - These methods must be implemented by targets so that
1885 // the SelectionDAGBuilder code knows how to lower these.
1888 /// LowerFormalArguments - This hook must be implemented to lower the
1889 /// incoming (formal) arguments, described by the Ins array, into the
1890 /// specified DAG. The implementation should fill in the InVals array
1891 /// with legal-type argument values, and return the resulting token
1895 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1897 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1898 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
1899 SmallVectorImpl<SDValue> &/*InVals*/) const {
1900 llvm_unreachable("Not Implemented");
1903 struct ArgListEntry {
1912 bool isReturned : 1;
1915 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1916 isSRet(false), isNest(false), isByVal(false), isReturned(false),
1919 typedef std::vector<ArgListEntry> ArgListTy;
1921 /// CallLoweringInfo - This structure contains all information that is
1922 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the
1923 /// SelectionDAG builder needs to lower a call, and targets will see this
1924 /// struct in their LowerCall implementation.
1925 struct CallLoweringInfo {
1932 bool DoesNotReturn : 1;
1933 bool IsReturnValueUsed : 1;
1935 // IsTailCall should be modified by implementations of
1936 // TargetLowering::LowerCall that perform tail call conversions.
1939 unsigned NumFixedArgs;
1940 CallingConv::ID CallConv;
1945 ImmutableCallSite *CS;
1946 SmallVector<ISD::OutputArg, 32> Outs;
1947 SmallVector<SDValue, 32> OutVals;
1948 SmallVector<ISD::InputArg, 32> Ins;
1951 /// CallLoweringInfo - Constructs a call lowering context based on the
1952 /// ImmutableCallSite \p cs.
1953 CallLoweringInfo(SDValue chain, Type *retTy,
1954 FunctionType *FTy, bool isTailCall, SDValue callee,
1955 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
1956 ImmutableCallSite &cs)
1957 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
1958 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
1959 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
1960 DoesNotReturn(cs.doesNotReturn()),
1961 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
1962 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
1963 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
1966 /// CallLoweringInfo - Constructs a call lowering context based on the
1967 /// provided call information.
1968 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
1969 bool isVarArg, bool isInReg, unsigned numFixedArgs,
1970 CallingConv::ID callConv, bool isTailCall,
1971 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
1972 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
1973 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
1974 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
1975 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
1976 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
1977 Args(args), DAG(dag), DL(dl), CS(NULL) {}
1980 /// LowerCallTo - This function lowers an abstract call to a function into an
1981 /// actual call. This returns a pair of operands. The first element is the
1982 /// return value for the function (if RetTy is not VoidTy). The second
1983 /// element is the outgoing token chain. It calls LowerCall to do the actual
1985 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
1987 /// LowerCall - This hook must be implemented to lower calls into the
1988 /// the specified DAG. The outgoing arguments to the call are described
1989 /// by the Outs array, and the values to be returned by the call are
1990 /// described by the Ins array. The implementation should fill in the
1991 /// InVals array with legal-type return values from the call, and return
1992 /// the resulting token chain value.
1994 LowerCall(CallLoweringInfo &/*CLI*/,
1995 SmallVectorImpl<SDValue> &/*InVals*/) const {
1996 llvm_unreachable("Not Implemented");
1999 /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
2000 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2002 /// CanLowerReturn - This hook should be implemented to check whether the
2003 /// return values described by the Outs array can fit into the return
2004 /// registers. If false is returned, an sret-demotion is performed.
2006 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2007 MachineFunction &/*MF*/, bool /*isVarArg*/,
2008 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2009 LLVMContext &/*Context*/) const
2011 // Return true by default to get preexisting behavior.
2015 /// LowerReturn - This hook must be implemented to lower outgoing
2016 /// return values, described by the Outs array, into the specified
2017 /// DAG. The implementation should return the resulting token chain
2021 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2023 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2024 const SmallVectorImpl<SDValue> &/*OutVals*/,
2025 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2026 llvm_unreachable("Not Implemented");
2029 /// isUsedByReturnOnly - Return true if result of the specified node is used
2030 /// by a return node only. It also compute and return the input chain for the
2032 /// This is used to determine whether it is possible
2033 /// to codegen a libcall as tail call at legalization time.
2034 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2038 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the
2039 /// call instruction as a tail call. This is used by optimization passes to
2040 /// determine if it's profitable to duplicate return instructions to enable
2041 /// tailcall optimization.
2042 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2046 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or
2047 /// sign extend a zeroext/signext integer argument or return value.
2048 /// FIXME: Most C calling convention requires the return type to be promoted,
2049 /// but this is not true all the time, e.g. i1 on x86-64. It is also not
2050 /// necessary for non-C calling conventions. The frontend should handle this
2051 /// and include all of the necessary information.
2052 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2053 ISD::NodeType /*ExtendKind*/) const {
2054 MVT MinVT = getRegisterType(MVT::i32);
2055 return VT.bitsLT(MinVT) ? MinVT : VT;
2058 /// LowerOperationWrapper - This callback is invoked by the type legalizer
2059 /// to legalize nodes with an illegal operand type but legal result types.
2060 /// It replaces the LowerOperation callback in the type Legalizer.
2061 /// The reason we can not do away with LowerOperation entirely is that
2062 /// LegalizeDAG isn't yet ready to use this callback.
2063 /// TODO: Consider merging with ReplaceNodeResults.
2065 /// The target places new result values for the node in Results (their number
2066 /// and types must exactly match those of the original return values of
2067 /// the node), or leaves Results empty, which indicates that the node is not
2068 /// to be custom lowered after all.
2069 /// The default implementation calls LowerOperation.
2070 virtual void LowerOperationWrapper(SDNode *N,
2071 SmallVectorImpl<SDValue> &Results,
2072 SelectionDAG &DAG) const;
2074 /// LowerOperation - This callback is invoked for operations that are
2075 /// unsupported by the target, which are registered to use 'custom' lowering,
2076 /// and whose defined values are all legal.
2077 /// If the target has no operations that require custom lowering, it need not
2078 /// implement this. The default implementation of this aborts.
2079 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2081 /// ReplaceNodeResults - This callback is invoked when a node result type is
2082 /// illegal for the target, and the operation was registered to use 'custom'
2083 /// lowering for that result type. The target places new result values for
2084 /// the node in Results (their number and types must exactly match those of
2085 /// the original return values of the node), or leaves Results empty, which
2086 /// indicates that the node is not to be custom lowered after all.
2088 /// If the target has no operations that require custom lowering, it need not
2089 /// implement this. The default implementation aborts.
2090 virtual void ReplaceNodeResults(SDNode * /*N*/,
2091 SmallVectorImpl<SDValue> &/*Results*/,
2092 SelectionDAG &/*DAG*/) const {
2093 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2096 /// getTargetNodeName() - This method returns the name of a target specific
2098 virtual const char *getTargetNodeName(unsigned Opcode) const;
2100 /// createFastISel - This method returns a target specific FastISel object,
2101 /// or null if the target does not support "fast" ISel.
2102 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2103 const TargetLibraryInfo *) const {
2107 //===--------------------------------------------------------------------===//
2108 // Inline Asm Support hooks
2111 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
2112 /// call to be explicit llvm code if it wants to. This is useful for
2113 /// turning simple inline asms into LLVM intrinsics, which gives the
2114 /// compiler more information about the behavior of the code.
2115 virtual bool ExpandInlineAsm(CallInst *) const {
2119 enum ConstraintType {
2120 C_Register, // Constraint represents specific register(s).
2121 C_RegisterClass, // Constraint represents any of register(s) in class.
2122 C_Memory, // Memory constraint.
2123 C_Other, // Something else.
2124 C_Unknown // Unsupported constraint.
2127 enum ConstraintWeight {
2129 CW_Invalid = -1, // No match.
2130 CW_Okay = 0, // Acceptable.
2131 CW_Good = 1, // Good weight.
2132 CW_Better = 2, // Better weight.
2133 CW_Best = 3, // Best weight.
2135 // Well-known weights.
2136 CW_SpecificReg = CW_Okay, // Specific register operands.
2137 CW_Register = CW_Good, // Register operands.
2138 CW_Memory = CW_Better, // Memory operands.
2139 CW_Constant = CW_Best, // Constant operand.
2140 CW_Default = CW_Okay // Default or don't know type.
2143 /// AsmOperandInfo - This contains information for each constraint that we are
2145 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2146 /// ConstraintCode - This contains the actual string for the code, like "m".
2147 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
2148 /// most closely matches the operand.
2149 std::string ConstraintCode;
2151 /// ConstraintType - Information about the constraint code, e.g. Register,
2152 /// RegisterClass, Memory, Other, Unknown.
2153 TargetLowering::ConstraintType ConstraintType;
2155 /// CallOperandval - If this is the result output operand or a
2156 /// clobber, this is null, otherwise it is the incoming operand to the
2157 /// CallInst. This gets modified as the asm is processed.
2158 Value *CallOperandVal;
2160 /// ConstraintVT - The ValueType for the operand value.
2163 /// isMatchingInputConstraint - Return true of this is an input operand that
2164 /// is a matching constraint like "4".
2165 bool isMatchingInputConstraint() const;
2167 /// getMatchedOperand - If this is an input matching constraint, this method
2168 /// returns the output operand it matches.
2169 unsigned getMatchedOperand() const;
2171 /// Copy constructor for copying from an AsmOperandInfo.
2172 AsmOperandInfo(const AsmOperandInfo &info)
2173 : InlineAsm::ConstraintInfo(info),
2174 ConstraintCode(info.ConstraintCode),
2175 ConstraintType(info.ConstraintType),
2176 CallOperandVal(info.CallOperandVal),
2177 ConstraintVT(info.ConstraintVT) {
2180 /// Copy constructor for copying from a ConstraintInfo.
2181 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2182 : InlineAsm::ConstraintInfo(info),
2183 ConstraintType(TargetLowering::C_Unknown),
2184 CallOperandVal(0), ConstraintVT(MVT::Other) {
2188 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2190 /// ParseConstraints - Split up the constraint string from the inline
2191 /// assembly value into the specific constraints and their prefixes,
2192 /// and also tie in the associated operand values.
2193 /// If this returns an empty vector, and if the constraint string itself
2194 /// isn't empty, there was an error parsing.
2195 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2197 /// Examine constraint type and operand type and determine a weight value.
2198 /// The operand object must already have been set up with the operand type.
2199 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2200 AsmOperandInfo &info, int maIndex) const;
2202 /// Examine constraint string and operand type and determine a weight value.
2203 /// The operand object must already have been set up with the operand type.
2204 virtual ConstraintWeight getSingleConstraintMatchWeight(
2205 AsmOperandInfo &info, const char *constraint) const;
2207 /// ComputeConstraintToUse - Determines the constraint code and constraint
2208 /// type to use for the specific AsmOperandInfo, setting
2209 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
2210 /// being passed in is available, it can be passed in as Op, otherwise an
2211 /// empty SDValue can be passed.
2212 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2214 SelectionDAG *DAG = 0) const;
2216 /// getConstraintType - Given a constraint, return the type of constraint it
2217 /// is for this target.
2218 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2220 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
2221 /// {edx}), return the register number and the register class for the
2224 /// Given a register class constraint, like 'r', if this corresponds directly
2225 /// to an LLVM register class, return a register of 0 and the register class
2228 /// This should only be used for C_Register constraints. On error,
2229 /// this returns a register number of 0 and a null register class pointer..
2230 virtual std::pair<unsigned, const TargetRegisterClass*>
2231 getRegForInlineAsmConstraint(const std::string &Constraint,
2234 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2235 /// with another that has more specific requirements based on the type of the
2236 /// corresponding operand. This returns null if there is no replacement to
2238 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2240 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2241 /// vector. If it is invalid, don't add anything to Ops.
2242 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2243 std::vector<SDValue> &Ops,
2244 SelectionDAG &DAG) const;
2246 //===--------------------------------------------------------------------===//
2247 // Div utility functions
2249 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2250 SelectionDAG &DAG) const;
2251 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2252 std::vector<SDNode*> *Created) const;
2253 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2254 std::vector<SDNode*> *Created) const;
2256 //===--------------------------------------------------------------------===//
2257 // Instruction Emitting Hooks
2260 // EmitInstrWithCustomInserter - This method should be implemented by targets
2261 // that mark instructions with the 'usesCustomInserter' flag. These
2262 // instructions are special in various ways, which require special support to
2263 // insert. The specified MachineInstr is created but not inserted into any
2264 // basic blocks, and this method is called to expand it into a sequence of
2265 // instructions, potentially also creating new basic blocks and control flow.
2266 virtual MachineBasicBlock *
2267 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2269 /// AdjustInstrPostInstrSelection - This method should be implemented by
2270 /// targets that mark instructions with the 'hasPostISelHook' flag. These
2271 /// instructions must be adjusted after instruction selection by target hooks.
2272 /// e.g. To fill in optional defs for ARM 's' setting instructions.
2274 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2277 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
2278 /// compute the return value EVTs and flags, and optionally also
2279 /// the offsets, if the return value is being lowered to memory.
2280 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2281 SmallVectorImpl<ISD::OutputArg> &Outs,
2282 const TargetLowering &TLI);
2284 } // end llvm namespace