1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IRBuilder.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
81 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector // This vector should be widened into a larger vector.
106 /// LegalizeKind holds the legalization kind that needs to happen to EVT
107 /// in order to type-legalize it.
108 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
110 /// Enum that describes how the target represents true/false values.
111 enum BooleanContent {
112 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
113 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
114 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
117 /// Enum that describes what type of support for selects the target has.
118 enum SelectSupportKind {
119 ScalarValSelect, // The target supports scalar selects (ex: cmov).
120 ScalarCondVectorVal, // The target supports selects with a scalar condition
121 // and vector values (ex: cmov).
122 VectorMaskSelect // The target supports vector selects with a vector
123 // mask (ex: x86 blends).
126 static ISD::NodeType getExtendForContent(BooleanContent Content) {
128 case UndefinedBooleanContent:
129 // Extend by adding rubbish bits.
130 return ISD::ANY_EXTEND;
131 case ZeroOrOneBooleanContent:
132 // Extend by adding zero bits.
133 return ISD::ZERO_EXTEND;
134 case ZeroOrNegativeOneBooleanContent:
135 // Extend by copying the sign bit.
136 return ISD::SIGN_EXTEND;
138 llvm_unreachable("Invalid content kind");
141 /// NOTE: The TargetMachine owns TLOF.
142 explicit TargetLoweringBase(const TargetMachine &TM);
143 virtual ~TargetLoweringBase() {}
146 /// \brief Initialize all of the actions to default values.
150 const TargetMachine &getTargetMachine() const { return TM; }
151 const DataLayout *getDataLayout() const { return DL; }
152 const TargetLoweringObjectFile &getObjFileLowering() const {
153 return *TM.getObjFileLowering();
156 bool isBigEndian() const { return !IsLittleEndian; }
157 bool isLittleEndian() const { return IsLittleEndian; }
159 /// Return the pointer type for the given address space, defaults to
160 /// the pointer type from the data layout.
161 /// FIXME: The default needs to be removed once all the code is updated.
162 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
163 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
164 unsigned getPointerTypeSizeInBits(Type *Ty) const;
165 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
167 EVT getShiftAmountTy(EVT LHSTy) const;
169 /// Returns the type to be used for the index operand of:
170 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
171 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
172 virtual MVT getVectorIdxTy() const {
173 return getPointerTy();
176 /// Return true if the select operation is expensive for this target.
177 bool isSelectExpensive() const { return SelectIsExpensive; }
179 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
183 /// Return true if multiple condition registers are available.
184 bool hasMultipleConditionRegisters() const {
185 return HasMultipleConditionRegisters;
188 /// Return true if the target has BitExtract instructions.
189 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
191 /// Return the preferred vector type legalization action.
192 virtual TargetLoweringBase::LegalizeTypeAction
193 getPreferredVectorAction(EVT VT) const {
194 // The default action for one element vectors is to scalarize
195 if (VT.getVectorNumElements() == 1)
196 return TypeScalarizeVector;
197 // The default action for other vectors is to promote
198 return TypePromoteInteger;
201 // There are two general methods for expanding a BUILD_VECTOR node:
202 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
204 // 2. Build the vector on the stack and then load it.
205 // If this function returns true, then method (1) will be used, subject to
206 // the constraint that all of the necessary shuffles are legal (as determined
207 // by isShuffleMaskLegal). If this function returns false, then method (2) is
208 // always used. The vector type, and the number of defined values, are
211 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
212 unsigned DefinedValues) const {
213 return DefinedValues < 3;
216 /// Return true if integer divide is usually cheaper than a sequence of
217 /// several shifts, adds, and multiplies for this target.
218 bool isIntDivCheap() const { return IntDivIsCheap; }
220 /// Returns true if target has indicated at least one type should be bypassed.
221 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
223 /// Returns map of slow types for division or remainder with corresponding
225 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
226 return BypassSlowDivWidths;
229 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
230 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
232 /// Return true if Flow Control is an expensive operation that should be
234 bool isJumpExpensive() const { return JumpIsExpensive; }
236 /// Return true if selects are only cheaper than branches if the branch is
237 /// unlikely to be predicted right.
238 bool isPredictableSelectExpensive() const {
239 return PredictableSelectIsExpensive;
242 /// isLoadBitCastBeneficial() - Return true if the following transform
244 /// fold (conv (load x)) -> (load (conv*)x)
245 /// On architectures that don't natively support some vector loads efficiently,
246 /// casting the load to a smaller vector of larger types and loading
247 /// is more efficient, however, this can be undone by optimizations in
249 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
253 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
254 virtual bool isCheapToSpeculateCttz() const {
258 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
259 virtual bool isCheapToSpeculateCtlz() const {
263 /// \brief Return if the target supports combining a
266 /// %andResult = and %val1, #imm-with-one-bit-set;
267 /// %icmpResult = icmp %andResult, 0
268 /// br i1 %icmpResult, label %dest1, label %dest2
270 /// into a single machine instruction of a form like:
272 /// brOnBitSet %register, #bitNumber, dest
274 bool isMaskAndBranchFoldingLegal() const {
275 return MaskAndBranchFoldingIsLegal;
278 /// \brief Return true if the target wants to use the optimization that
279 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
280 /// promotedInst1(...(promotedInstN(ext(load)))).
281 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
283 /// Return true if the target can combine store(extractelement VectorTy,
285 /// \p Cost[out] gives the cost of that transformation when this is true.
286 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
287 unsigned &Cost) const {
291 /// Return true if target supports floating point exceptions.
292 bool hasFloatingPointExceptions() const {
293 return HasFloatingPointExceptions;
296 /// Return true if target always beneficiates from combining into FMA for a
297 /// given value type. This must typically return false on targets where FMA
298 /// takes more cycles to execute than FADD.
299 virtual bool enableAggressiveFMAFusion(EVT VT) const {
303 /// Return the ValueType of the result of SETCC operations.
304 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
306 /// Return the ValueType for comparison libcalls. Comparions libcalls include
307 /// floating point comparion calls, and Ordered/Unordered check calls on
308 /// floating point numbers.
310 MVT::SimpleValueType getCmpLibcallReturnType() const;
312 /// For targets without i1 registers, this gives the nature of the high-bits
313 /// of boolean values held in types wider than i1.
315 /// "Boolean values" are special true/false values produced by nodes like
316 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
317 /// Not to be confused with general values promoted from i1. Some cpus
318 /// distinguish between vectors of boolean and scalars; the isVec parameter
319 /// selects between the two kinds. For example on X86 a scalar boolean should
320 /// be zero extended from i1, while the elements of a vector of booleans
321 /// should be sign extended from i1.
323 /// Some cpus also treat floating point types the same way as they treat
324 /// vectors instead of the way they treat scalars.
325 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
327 return BooleanVectorContents;
328 return isFloat ? BooleanFloatContents : BooleanContents;
331 BooleanContent getBooleanContents(EVT Type) const {
332 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
335 /// Return target scheduling preference.
336 Sched::Preference getSchedulingPreference() const {
337 return SchedPreferenceInfo;
340 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
341 /// for different nodes. This function returns the preference (or none) for
343 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
347 /// Return the register class that should be used for the specified value
349 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
350 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
351 assert(RC && "This value type is not natively supported!");
355 /// Return the 'representative' register class for the specified value
358 /// The 'representative' register class is the largest legal super-reg
359 /// register class for the register class of the value type. For example, on
360 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
361 /// register class is GR64 on x86_64.
362 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
363 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
367 /// Return the cost of the 'representative' register class for the specified
369 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
370 return RepRegClassCostForVT[VT.SimpleTy];
373 /// Return true if the target has native support for the specified value type.
374 /// This means that it has a register that directly holds it without
375 /// promotions or expansions.
376 bool isTypeLegal(EVT VT) const {
377 assert(!VT.isSimple() ||
378 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
379 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
382 class ValueTypeActionImpl {
383 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
384 /// that indicates how instruction selection should deal with the type.
385 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
388 ValueTypeActionImpl() {
389 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
392 LegalizeTypeAction getTypeAction(MVT VT) const {
393 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
396 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
397 unsigned I = VT.SimpleTy;
398 ValueTypeActions[I] = Action;
402 const ValueTypeActionImpl &getValueTypeActions() const {
403 return ValueTypeActions;
406 /// Return how we should legalize values of this type, either it is already
407 /// legal (return 'Legal') or we need to promote it to a larger type (return
408 /// 'Promote'), or we need to expand it into multiple registers of smaller
409 /// integer type (return 'Expand'). 'Custom' is not an option.
410 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
411 return getTypeConversion(Context, VT).first;
413 LegalizeTypeAction getTypeAction(MVT VT) const {
414 return ValueTypeActions.getTypeAction(VT);
417 /// For types supported by the target, this is an identity function. For
418 /// types that must be promoted to larger types, this returns the larger type
419 /// to promote to. For integer types that are larger than the largest integer
420 /// register, this contains one step in the expansion to get to the smaller
421 /// register. For illegal floating point types, this returns the integer type
423 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
424 return getTypeConversion(Context, VT).second;
427 /// For types supported by the target, this is an identity function. For
428 /// types that must be expanded (i.e. integer types that are larger than the
429 /// largest integer register or illegal floating point types), this returns
430 /// the largest legal type it will be expanded to.
431 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
432 assert(!VT.isVector());
434 switch (getTypeAction(Context, VT)) {
437 case TypeExpandInteger:
438 VT = getTypeToTransformTo(Context, VT);
441 llvm_unreachable("Type is not legal nor is it to be expanded!");
446 /// Vector types are broken down into some number of legal first class types.
447 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
448 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
449 /// turns into 4 EVT::i32 values with both PPC and X86.
451 /// This method returns the number of registers needed, and the VT for each
452 /// register. It also returns the VT and quantity of the intermediate values
453 /// before they are promoted/expanded.
454 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
456 unsigned &NumIntermediates,
457 MVT &RegisterVT) const;
459 struct IntrinsicInfo {
460 unsigned opc; // target opcode
461 EVT memVT; // memory VT
462 const Value* ptrVal; // value representing memory location
463 int offset; // offset off of ptrVal
464 unsigned size; // the size of the memory location
465 // (taken from memVT if zero)
466 unsigned align; // alignment
467 bool vol; // is volatile?
468 bool readMem; // reads memory?
469 bool writeMem; // writes memory?
471 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
472 vol(false), readMem(false), writeMem(false) {}
475 /// Given an intrinsic, checks if on the target the intrinsic will need to map
476 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
477 /// true and store the intrinsic information into the IntrinsicInfo that was
478 /// passed to the function.
479 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
480 unsigned /*Intrinsic*/) const {
484 /// Returns true if the target can instruction select the specified FP
485 /// immediate natively. If false, the legalizer will materialize the FP
486 /// immediate as a load from a constant pool.
487 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
491 /// Targets can use this to indicate that they only support *some*
492 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
493 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
495 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
500 /// Returns true if the operation can trap for the value type.
502 /// VT must be a legal type. By default, we optimistically assume most
503 /// operations don't trap except for divide and remainder.
504 virtual bool canOpTrap(unsigned Op, EVT VT) const;
506 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
507 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
508 /// a VAND with a constant pool entry.
509 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
514 /// Return how this operation should be treated: either it is legal, needs to
515 /// be promoted to a larger size, needs to be expanded to some other code
516 /// sequence, or the target has a custom expander for it.
517 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
518 if (VT.isExtended()) return Expand;
519 // If a target-specific SDNode requires legalization, require the target
520 // to provide custom legalization for it.
521 if (Op > array_lengthof(OpActions[0])) return Custom;
522 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
523 return (LegalizeAction)OpActions[I][Op];
526 /// Return true if the specified operation is legal on this target or can be
527 /// made legal with custom lowering. This is used to help guide high-level
528 /// lowering decisions.
529 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
530 return (VT == MVT::Other || isTypeLegal(VT)) &&
531 (getOperationAction(Op, VT) == Legal ||
532 getOperationAction(Op, VT) == Custom);
535 /// Return true if the specified operation is legal on this target or can be
536 /// made legal using promotion. This is used to help guide high-level lowering
538 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
539 return (VT == MVT::Other || isTypeLegal(VT)) &&
540 (getOperationAction(Op, VT) == Legal ||
541 getOperationAction(Op, VT) == Promote);
544 /// Return true if the specified operation is illegal on this target or
545 /// unlikely to be made legal with custom lowering. This is used to help guide
546 /// high-level lowering decisions.
547 bool isOperationExpand(unsigned Op, EVT VT) const {
548 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
551 /// Return true if the specified operation is legal on this target.
552 bool isOperationLegal(unsigned Op, EVT VT) const {
553 return (VT == MVT::Other || isTypeLegal(VT)) &&
554 getOperationAction(Op, VT) == Legal;
557 /// Return how this load with extension should be treated: either it is legal,
558 /// needs to be promoted to a larger size, needs to be expanded to some other
559 /// code sequence, or the target has a custom expander for it.
560 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const {
561 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
562 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
563 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
564 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
565 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
566 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
569 /// Return true if the specified load with extension is legal on this target.
570 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
571 return ValVT.isSimple() && MemVT.isSimple() &&
572 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
575 /// Return how this store with truncation should be treated: either it is
576 /// legal, needs to be promoted to a larger size, needs to be expanded to some
577 /// other code sequence, or the target has a custom expander for it.
578 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
579 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
580 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
581 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
582 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
583 "Table isn't big enough!");
584 return (LegalizeAction)TruncStoreActions[ValI][MemI];
587 /// Return true if the specified store with truncation is legal on this
589 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
590 return isTypeLegal(ValVT) && MemVT.isSimple() &&
591 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
594 /// Return how the indexed load should be treated: either it is legal, needs
595 /// to be promoted to a larger size, needs to be expanded to some other code
596 /// sequence, or the target has a custom expander for it.
598 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
599 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
600 "Table isn't big enough!");
601 unsigned Ty = (unsigned)VT.SimpleTy;
602 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
605 /// Return true if the specified indexed load is legal on this target.
606 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
607 return VT.isSimple() &&
608 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
609 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
612 /// Return how the indexed store should be treated: either it is legal, needs
613 /// to be promoted to a larger size, needs to be expanded to some other code
614 /// sequence, or the target has a custom expander for it.
616 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
617 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
618 "Table isn't big enough!");
619 unsigned Ty = (unsigned)VT.SimpleTy;
620 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
623 /// Return true if the specified indexed load is legal on this target.
624 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
625 return VT.isSimple() &&
626 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
627 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
630 /// Return how the condition code should be treated: either it is legal, needs
631 /// to be expanded to some other code sequence, or the target has a custom
634 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
635 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
636 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
637 "Table isn't big enough!");
638 // See setCondCodeAction for how this is encoded.
639 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
640 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
641 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
642 assert(Action != Promote && "Can't promote condition code!");
646 /// Return true if the specified condition code is legal on this target.
647 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
649 getCondCodeAction(CC, VT) == Legal ||
650 getCondCodeAction(CC, VT) == Custom;
654 /// If the action for this operation is to promote, this method returns the
655 /// ValueType to promote to.
656 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
657 assert(getOperationAction(Op, VT) == Promote &&
658 "This operation isn't promoted!");
660 // See if this has an explicit type specified.
661 std::map<std::pair<unsigned, MVT::SimpleValueType>,
662 MVT::SimpleValueType>::const_iterator PTTI =
663 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
664 if (PTTI != PromoteToType.end()) return PTTI->second;
666 assert((VT.isInteger() || VT.isFloatingPoint()) &&
667 "Cannot autopromote this type, add it with AddPromotedToType.");
671 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
672 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
673 "Didn't find type to promote to!");
674 } while (!isTypeLegal(NVT) ||
675 getOperationAction(Op, NVT) == Promote);
679 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
680 /// operations except for the pointer size. If AllowUnknown is true, this
681 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
682 /// otherwise it will assert.
683 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
684 // Lower scalar pointers to native pointer types.
685 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
686 return getPointerTy(PTy->getAddressSpace());
688 if (Ty->isVectorTy()) {
689 VectorType *VTy = cast<VectorType>(Ty);
690 Type *Elm = VTy->getElementType();
691 // Lower vectors of pointers to native pointer types.
692 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
693 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
694 Elm = PointerTy.getTypeForEVT(Ty->getContext());
697 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
698 VTy->getNumElements());
700 return EVT::getEVT(Ty, AllowUnknown);
703 /// Return the MVT corresponding to this LLVM type. See getValueType.
704 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
705 return getValueType(Ty, AllowUnknown).getSimpleVT();
708 /// Return the desired alignment for ByVal or InAlloca aggregate function
709 /// arguments in the caller parameter area. This is the actual alignment, not
711 virtual unsigned getByValTypeAlignment(Type *Ty) const;
713 /// Return the type of registers that this ValueType will eventually require.
714 MVT getRegisterType(MVT VT) const {
715 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
716 return RegisterTypeForVT[VT.SimpleTy];
719 /// Return the type of registers that this ValueType will eventually require.
720 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
722 assert((unsigned)VT.getSimpleVT().SimpleTy <
723 array_lengthof(RegisterTypeForVT));
724 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
729 unsigned NumIntermediates;
730 (void)getVectorTypeBreakdown(Context, VT, VT1,
731 NumIntermediates, RegisterVT);
734 if (VT.isInteger()) {
735 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
737 llvm_unreachable("Unsupported extended type!");
740 /// Return the number of registers that this ValueType will eventually
743 /// This is one for any types promoted to live in larger registers, but may be
744 /// more than one for types (like i64) that are split into pieces. For types
745 /// like i140, which are first promoted then expanded, it is the number of
746 /// registers needed to hold all the bits of the original type. For an i140
747 /// on a 32 bit machine this means 5 registers.
748 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
750 assert((unsigned)VT.getSimpleVT().SimpleTy <
751 array_lengthof(NumRegistersForVT));
752 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
757 unsigned NumIntermediates;
758 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
760 if (VT.isInteger()) {
761 unsigned BitWidth = VT.getSizeInBits();
762 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
763 return (BitWidth + RegWidth - 1) / RegWidth;
765 llvm_unreachable("Unsupported extended type!");
768 /// If true, then instruction selection should seek to shrink the FP constant
769 /// of the specified type to a smaller type in order to save space and / or
771 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
773 // Return true if it is profitable to reduce the given load node to a smaller
776 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
777 virtual bool shouldReduceLoadWidth(SDNode *Load,
778 ISD::LoadExtType ExtTy,
783 /// When splitting a value of the specified type into parts, does the Lo
784 /// or Hi part come first? This usually follows the endianness, except
785 /// for ppcf128, where the Hi part always comes first.
786 bool hasBigEndianPartOrdering(EVT VT) const {
787 return isBigEndian() || VT == MVT::ppcf128;
790 /// If true, the target has custom DAG combine transformations that it can
791 /// perform for the specified node.
792 bool hasTargetDAGCombine(ISD::NodeType NT) const {
793 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
794 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
797 /// \brief Get maximum # of store operations permitted for llvm.memset
799 /// This function returns the maximum number of store operations permitted
800 /// to replace a call to llvm.memset. The value is set by the target at the
801 /// performance threshold for such a replacement. If OptSize is true,
802 /// return the limit for functions that have OptSize attribute.
803 unsigned getMaxStoresPerMemset(bool OptSize) const {
804 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
807 /// \brief Get maximum # of store operations permitted for llvm.memcpy
809 /// This function returns the maximum number of store operations permitted
810 /// to replace a call to llvm.memcpy. The value is set by the target at the
811 /// performance threshold for such a replacement. If OptSize is true,
812 /// return the limit for functions that have OptSize attribute.
813 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
814 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
817 /// \brief Get maximum # of store operations permitted for llvm.memmove
819 /// This function returns the maximum number of store operations permitted
820 /// to replace a call to llvm.memmove. The value is set by the target at the
821 /// performance threshold for such a replacement. If OptSize is true,
822 /// return the limit for functions that have OptSize attribute.
823 unsigned getMaxStoresPerMemmove(bool OptSize) const {
824 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
827 /// \brief Determine if the target supports unaligned memory accesses.
829 /// This function returns true if the target allows unaligned memory accesses
830 /// of the specified type in the given address space. If true, it also returns
831 /// whether the unaligned memory access is "fast" in the last argument by
832 /// reference. This is used, for example, in situations where an array
833 /// copy/move/set is converted to a sequence of store operations. Its use
834 /// helps to ensure that such replacements don't generate code that causes an
835 /// alignment error (trap) on the target machine.
836 virtual bool allowsMisalignedMemoryAccesses(EVT,
837 unsigned AddrSpace = 0,
839 bool * /*Fast*/ = nullptr) const {
843 /// Returns the target specific optimal type for load and store operations as
844 /// a result of memset, memcpy, and memmove lowering.
846 /// If DstAlign is zero that means it's safe to destination alignment can
847 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
848 /// a need to check it against alignment requirement, probably because the
849 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
850 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
851 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
852 /// does not need to be loaded. It returns EVT::Other if the type should be
853 /// determined using generic target-independent logic.
854 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
855 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
858 bool /*MemcpyStrSrc*/,
859 MachineFunction &/*MF*/) const {
863 /// Returns true if it's safe to use load / store of the specified type to
864 /// expand memcpy / memset inline.
866 /// This is mostly true for all types except for some special cases. For
867 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
868 /// fstpl which also does type conversion. Note the specified type doesn't
869 /// have to be legal as the hook is used before type legalization.
870 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
872 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
873 bool usesUnderscoreSetJmp() const {
874 return UseUnderscoreSetJmp;
877 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
878 bool usesUnderscoreLongJmp() const {
879 return UseUnderscoreLongJmp;
882 /// Return integer threshold on number of blocks to use jump tables rather
883 /// than if sequence.
884 int getMinimumJumpTableEntries() const {
885 return MinimumJumpTableEntries;
888 /// If a physical register, this specifies the register that
889 /// llvm.savestack/llvm.restorestack should save and restore.
890 unsigned getStackPointerRegisterToSaveRestore() const {
891 return StackPointerRegisterToSaveRestore;
894 /// If a physical register, this returns the register that receives the
895 /// exception address on entry to a landing pad.
896 unsigned getExceptionPointerRegister() const {
897 return ExceptionPointerRegister;
900 /// If a physical register, this returns the register that receives the
901 /// exception typeid on entry to a landing pad.
902 unsigned getExceptionSelectorRegister() const {
903 return ExceptionSelectorRegister;
906 /// Returns the target's jmp_buf size in bytes (if never set, the default is
908 unsigned getJumpBufSize() const {
912 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
914 unsigned getJumpBufAlignment() const {
915 return JumpBufAlignment;
918 /// Return the minimum stack alignment of an argument.
919 unsigned getMinStackArgumentAlignment() const {
920 return MinStackArgumentAlignment;
923 /// Return the minimum function alignment.
924 unsigned getMinFunctionAlignment() const {
925 return MinFunctionAlignment;
928 /// Return the preferred function alignment.
929 unsigned getPrefFunctionAlignment() const {
930 return PrefFunctionAlignment;
933 /// Return the preferred loop alignment.
934 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
935 return PrefLoopAlignment;
938 /// Return whether the DAG builder should automatically insert fences and
939 /// reduce ordering for atomics.
940 bool getInsertFencesForAtomic() const {
941 return InsertFencesForAtomic;
944 /// Return true if the target stores stack protector cookies at a fixed offset
945 /// in some non-standard address space, and populates the address space and
946 /// offset as appropriate.
947 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
948 unsigned &/*Offset*/) const {
952 /// Returns the maximal possible offset which can be used for loads / stores
954 virtual unsigned getMaximalGlobalOffset() const {
958 /// Returns true if a cast between SrcAS and DestAS is a noop.
959 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
963 //===--------------------------------------------------------------------===//
964 /// \name Helpers for TargetTransformInfo implementations
967 /// Get the ISD node that corresponds to the Instruction class opcode.
968 int InstructionOpcodeToISD(unsigned Opcode) const;
970 /// Estimate the cost of type-legalization and the legalized type.
971 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
975 //===--------------------------------------------------------------------===//
976 /// \name Helpers for atomic expansion.
979 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
980 /// and expand AtomicCmpXchgInst.
981 virtual bool hasLoadLinkedStoreConditional() const { return false; }
983 /// Perform a load-linked operation on Addr, returning a "Value *" with the
984 /// corresponding pointee type. This may entail some non-trivial operations to
985 /// truncate or reconstruct types that will be illegal in the backend. See
986 /// ARMISelLowering for an example implementation.
987 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
988 AtomicOrdering Ord) const {
989 llvm_unreachable("Load linked unimplemented on this target");
992 /// Perform a store-conditional operation to Addr. Return the status of the
993 /// store. This should be 0 if the store succeeded, non-zero otherwise.
994 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
995 Value *Addr, AtomicOrdering Ord) const {
996 llvm_unreachable("Store conditional unimplemented on this target");
999 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1000 /// It is called by AtomicExpandPass before expanding an
1001 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1002 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1003 /// This function should either return a nullptr, or a pointer to an IR-level
1004 /// Instruction*. Even complex fence sequences can be represented by a
1005 /// single Instruction* through an intrinsic to be lowered later.
1006 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1007 /// Backends should override this method to produce target-specific intrinsic
1008 /// for their fences.
1009 /// FIXME: Please note that the default implementation here in terms of
1010 /// IR-level fences exists for historical/compatibility reasons and is
1011 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1012 /// consistency. For example, consider the following example:
1013 /// atomic<int> x = y = 0;
1014 /// int r1, r2, r3, r4;
1025 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1026 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1027 /// IR-level fences can prevent it.
1029 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1030 bool IsStore, bool IsLoad) const {
1031 if (!getInsertFencesForAtomic())
1034 if (isAtLeastRelease(Ord) && IsStore)
1035 return Builder.CreateFence(Ord);
1040 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1041 bool IsStore, bool IsLoad) const {
1042 if (!getInsertFencesForAtomic())
1045 if (isAtLeastAcquire(Ord))
1046 return Builder.CreateFence(Ord);
1052 /// Returns true if the given (atomic) store should be expanded by the
1053 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1054 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1058 /// Returns true if the given (atomic) load should be expanded by the
1059 /// IR-level AtomicExpand pass into a load-linked instruction
1060 /// (through emitLoadLinked()).
1061 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1063 /// Returns true if the given AtomicRMW should be expanded by the
1064 /// IR-level AtomicExpand pass into a loop using LoadLinked/StoreConditional.
1065 virtual bool shouldExpandAtomicRMWInIR(AtomicRMWInst *RMWI) const {
1069 /// On some platforms, an AtomicRMW that never actually modifies the value
1070 /// (such as fetch_add of 0) can be turned into a fence followed by an
1071 /// atomic load. This may sound useless, but it makes it possible for the
1072 /// processor to keep the cacheline shared, dramatically improving
1073 /// performance. And such idempotent RMWs are useful for implementing some
1074 /// kinds of locks, see for example (justification + benchmarks):
1075 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1076 /// This method tries doing that transformation, returning the atomic load if
1077 /// it succeeds, and nullptr otherwise.
1078 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1079 /// another round of expansion.
1080 virtual LoadInst *lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1083 //===--------------------------------------------------------------------===//
1084 // TargetLowering Configuration Methods - These methods should be invoked by
1085 // the derived class constructor to configure this object for the target.
1088 /// \brief Reset the operation actions based on target options.
1089 virtual void resetOperationActions() {}
1092 /// Specify how the target extends the result of integer and floating point
1093 /// boolean values from i1 to a wider type. See getBooleanContents.
1094 void setBooleanContents(BooleanContent Ty) {
1095 BooleanContents = Ty;
1096 BooleanFloatContents = Ty;
1099 /// Specify how the target extends the result of integer and floating point
1100 /// boolean values from i1 to a wider type. See getBooleanContents.
1101 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1102 BooleanContents = IntTy;
1103 BooleanFloatContents = FloatTy;
1106 /// Specify how the target extends the result of a vector boolean value from a
1107 /// vector of i1 to a wider type. See getBooleanContents.
1108 void setBooleanVectorContents(BooleanContent Ty) {
1109 BooleanVectorContents = Ty;
1112 /// Specify the target scheduling preference.
1113 void setSchedulingPreference(Sched::Preference Pref) {
1114 SchedPreferenceInfo = Pref;
1117 /// Indicate whether this target prefers to use _setjmp to implement
1118 /// llvm.setjmp or the version without _. Defaults to false.
1119 void setUseUnderscoreSetJmp(bool Val) {
1120 UseUnderscoreSetJmp = Val;
1123 /// Indicate whether this target prefers to use _longjmp to implement
1124 /// llvm.longjmp or the version without _. Defaults to false.
1125 void setUseUnderscoreLongJmp(bool Val) {
1126 UseUnderscoreLongJmp = Val;
1129 /// Indicate the number of blocks to generate jump tables rather than if
1131 void setMinimumJumpTableEntries(int Val) {
1132 MinimumJumpTableEntries = Val;
1135 /// If set to a physical register, this specifies the register that
1136 /// llvm.savestack/llvm.restorestack should save and restore.
1137 void setStackPointerRegisterToSaveRestore(unsigned R) {
1138 StackPointerRegisterToSaveRestore = R;
1141 /// If set to a physical register, this sets the register that receives the
1142 /// exception address on entry to a landing pad.
1143 void setExceptionPointerRegister(unsigned R) {
1144 ExceptionPointerRegister = R;
1147 /// If set to a physical register, this sets the register that receives the
1148 /// exception typeid on entry to a landing pad.
1149 void setExceptionSelectorRegister(unsigned R) {
1150 ExceptionSelectorRegister = R;
1153 /// Tells the code generator not to expand operations into sequences that use
1154 /// the select operations if possible.
1155 void setSelectIsExpensive(bool isExpensive = true) {
1156 SelectIsExpensive = isExpensive;
1159 /// Tells the code generator that the target has multiple (allocatable)
1160 /// condition registers that can be used to store the results of comparisons
1161 /// for use by selects and conditional branches. With multiple condition
1162 /// registers, the code generator will not aggressively sink comparisons into
1163 /// the blocks of their users.
1164 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1165 HasMultipleConditionRegisters = hasManyRegs;
1168 /// Tells the code generator that the target has BitExtract instructions.
1169 /// The code generator will aggressively sink "shift"s into the blocks of
1170 /// their users if the users will generate "and" instructions which can be
1171 /// combined with "shift" to BitExtract instructions.
1172 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1173 HasExtractBitsInsn = hasExtractInsn;
1176 /// Tells the code generator not to expand sequence of operations into a
1177 /// separate sequences that increases the amount of flow control.
1178 void setJumpIsExpensive(bool isExpensive = true) {
1179 JumpIsExpensive = isExpensive;
1182 /// Tells the code generator that integer divide is expensive, and if
1183 /// possible, should be replaced by an alternate sequence of instructions not
1184 /// containing an integer divide.
1185 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1187 /// Tells the code generator that this target supports floating point
1188 /// exceptions and cares about preserving floating point exception behavior.
1189 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1190 HasFloatingPointExceptions = FPExceptions;
1193 /// Tells the code generator which bitwidths to bypass.
1194 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1195 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1198 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1199 /// signed divide by power of two; let the target handle it.
1200 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1202 /// Add the specified register class as an available regclass for the
1203 /// specified value type. This indicates the selector can handle values of
1204 /// that class natively.
1205 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1206 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1207 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1208 RegClassForVT[VT.SimpleTy] = RC;
1211 /// Remove all register classes.
1212 void clearRegisterClasses() {
1213 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1215 AvailableRegClasses.clear();
1218 /// \brief Remove all operation actions.
1219 void clearOperationActions() {
1222 /// Return the largest legal super-reg register class of the register class
1223 /// for the specified type and its associated "cost".
1224 virtual std::pair<const TargetRegisterClass*, uint8_t>
1225 findRepresentativeClass(MVT VT) const;
1227 /// Once all of the register classes are added, this allows us to compute
1228 /// derived properties we expose.
1229 void computeRegisterProperties();
1231 /// Indicate that the specified operation does not work with the specified
1232 /// type and indicate what to do about it.
1233 void setOperationAction(unsigned Op, MVT VT,
1234 LegalizeAction Action) {
1235 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1236 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1239 /// Indicate that the specified load with extension does not work with the
1240 /// specified type and indicate what to do about it.
1241 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1242 LegalizeAction Action) {
1243 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1244 MemVT.isValid() && "Table isn't big enough!");
1245 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1248 /// Indicate that the specified truncating store does not work with the
1249 /// specified type and indicate what to do about it.
1250 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1251 LegalizeAction Action) {
1252 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1253 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1256 /// Indicate that the specified indexed load does or does not work with the
1257 /// specified type and indicate what to do abort it.
1259 /// NOTE: All indexed mode loads are initialized to Expand in
1260 /// TargetLowering.cpp
1261 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1262 LegalizeAction Action) {
1263 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1264 (unsigned)Action < 0xf && "Table isn't big enough!");
1265 // Load action are kept in the upper half.
1266 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1267 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1270 /// Indicate that the specified indexed store does or does not work with the
1271 /// specified type and indicate what to do about it.
1273 /// NOTE: All indexed mode stores are initialized to Expand in
1274 /// TargetLowering.cpp
1275 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1276 LegalizeAction Action) {
1277 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1278 (unsigned)Action < 0xf && "Table isn't big enough!");
1279 // Store action are kept in the lower half.
1280 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1281 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1284 /// Indicate that the specified condition code is or isn't supported on the
1285 /// target and indicate what to do about it.
1286 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1287 LegalizeAction Action) {
1288 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1289 "Table isn't big enough!");
1290 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1291 /// value and the upper 27 bits index into the second dimension of the array
1292 /// to select what 32-bit value to use.
1293 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1294 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1295 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1298 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1299 /// to trying a larger integer/fp until it can find one that works. If that
1300 /// default is insufficient, this method can be used by the target to override
1302 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1303 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1306 /// Targets should invoke this method for each target independent node that
1307 /// they want to provide a custom DAG combiner for by implementing the
1308 /// PerformDAGCombine virtual method.
1309 void setTargetDAGCombine(ISD::NodeType NT) {
1310 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1311 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1314 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1315 void setJumpBufSize(unsigned Size) {
1319 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1321 void setJumpBufAlignment(unsigned Align) {
1322 JumpBufAlignment = Align;
1325 /// Set the target's minimum function alignment (in log2(bytes))
1326 void setMinFunctionAlignment(unsigned Align) {
1327 MinFunctionAlignment = Align;
1330 /// Set the target's preferred function alignment. This should be set if
1331 /// there is a performance benefit to higher-than-minimum alignment (in
1333 void setPrefFunctionAlignment(unsigned Align) {
1334 PrefFunctionAlignment = Align;
1337 /// Set the target's preferred loop alignment. Default alignment is zero, it
1338 /// means the target does not care about loop alignment. The alignment is
1339 /// specified in log2(bytes). The target may also override
1340 /// getPrefLoopAlignment to provide per-loop values.
1341 void setPrefLoopAlignment(unsigned Align) {
1342 PrefLoopAlignment = Align;
1345 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1346 void setMinStackArgumentAlignment(unsigned Align) {
1347 MinStackArgumentAlignment = Align;
1350 /// Set if the DAG builder should automatically insert fences and reduce the
1351 /// order of atomic memory operations to Monotonic.
1352 void setInsertFencesForAtomic(bool fence) {
1353 InsertFencesForAtomic = fence;
1357 //===--------------------------------------------------------------------===//
1358 // Addressing mode description hooks (used by LSR etc).
1361 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1362 /// instructions reading the address. This allows as much computation as
1363 /// possible to be done in the address mode for that operand. This hook lets
1364 /// targets also pass back when this should be done on intrinsics which
1366 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1367 SmallVectorImpl<Value*> &/*Ops*/,
1368 Type *&/*AccessTy*/) const {
1372 /// This represents an addressing mode of:
1373 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1374 /// If BaseGV is null, there is no BaseGV.
1375 /// If BaseOffs is zero, there is no base offset.
1376 /// If HasBaseReg is false, there is no base register.
1377 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1380 GlobalValue *BaseGV;
1384 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1387 /// Return true if the addressing mode represented by AM is legal for this
1388 /// target, for a load/store of the specified type.
1390 /// The type may be VoidTy, in which case only return true if the addressing
1391 /// mode is legal for a load/store of any legal type. TODO: Handle
1392 /// pre/postinc as well.
1393 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1395 /// \brief Return the cost of the scaling factor used in the addressing mode
1396 /// represented by AM for this target, for a load/store of the specified type.
1398 /// If the AM is supported, the return value must be >= 0.
1399 /// If the AM is not supported, it returns a negative value.
1400 /// TODO: Handle pre/postinc as well.
1401 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1402 // Default: assume that any scaling factor used in a legal AM is free.
1403 if (isLegalAddressingMode(AM, Ty)) return 0;
1407 /// Return true if the specified immediate is legal icmp immediate, that is
1408 /// the target has icmp instructions which can compare a register against the
1409 /// immediate without having to materialize the immediate into a register.
1410 virtual bool isLegalICmpImmediate(int64_t) const {
1414 /// Return true if the specified immediate is legal add immediate, that is the
1415 /// target has add instructions which can add a register with the immediate
1416 /// without having to materialize the immediate into a register.
1417 virtual bool isLegalAddImmediate(int64_t) const {
1421 /// Return true if it's significantly cheaper to shift a vector by a uniform
1422 /// scalar than by an amount which will vary across each lane. On x86, for
1423 /// example, there is a "psllw" instruction for the former case, but no simple
1424 /// instruction for a general "a << b" operation on vectors.
1425 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1429 /// Return true if it's free to truncate a value of type Ty1 to type
1430 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1431 /// by referencing its sub-register AX.
1432 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1436 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1437 /// whether a call is in tail position. Typically this means that both results
1438 /// would be assigned to the same register or stack slot, but it could mean
1439 /// the target performs adequate checks of its own before proceeding with the
1441 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1445 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1449 /// Return true if any actual instruction that defines a value of type Ty1
1450 /// implicitly zero-extends the value to Ty2 in the result register.
1452 /// This does not necessarily include registers defined in unknown ways, such
1453 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1454 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1455 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1456 /// values implicit zero-extend the result out to 64 bits.
1457 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1461 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1465 /// Return true if the target supplies and combines to a paired load
1466 /// two loaded values of type LoadedType next to each other in memory.
1467 /// RequiredAlignment gives the minimal alignment constraints that must be met
1468 /// to be able to select this paired load.
1470 /// This information is *not* used to generate actual paired loads, but it is
1471 /// used to generate a sequence of loads that is easier to combine into a
1473 /// For instance, something like this:
1474 /// a = load i64* addr
1475 /// b = trunc i64 a to i32
1476 /// c = lshr i64 a, 32
1477 /// d = trunc i64 c to i32
1478 /// will be optimized into:
1479 /// b = load i32* addr1
1480 /// d = load i32* addr2
1481 /// Where addr1 = addr2 +/- sizeof(i32).
1483 /// In other words, unless the target performs a post-isel load combining,
1484 /// this information should not be provided because it will generate more
1486 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1487 unsigned & /*RequiredAligment*/) const {
1491 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1492 unsigned & /*RequiredAligment*/) const {
1496 /// Return true if zero-extending the specific node Val to type VT2 is free
1497 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1498 /// because it's folded such as X86 zero-extending loads).
1499 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1500 return isZExtFree(Val.getValueType(), VT2);
1503 /// Return true if an fpext operation is free (for instance, because
1504 /// single-precision floating-point numbers are implicitly extended to
1505 /// double-precision).
1506 virtual bool isFPExtFree(EVT VT) const {
1507 assert(VT.isFloatingPoint());
1511 /// Return true if an fneg operation is free to the point where it is never
1512 /// worthwhile to replace it with a bitwise operation.
1513 virtual bool isFNegFree(EVT VT) const {
1514 assert(VT.isFloatingPoint());
1518 /// Return true if an fabs operation is free to the point where it is never
1519 /// worthwhile to replace it with a bitwise operation.
1520 virtual bool isFAbsFree(EVT VT) const {
1521 assert(VT.isFloatingPoint());
1525 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1526 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1527 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1529 /// NOTE: This may be called before legalization on types for which FMAs are
1530 /// not legal, but should return true if those types will eventually legalize
1531 /// to types that support FMAs. After legalization, it will only be called on
1532 /// types that support FMAs (via Legal or Custom actions)
1533 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1537 /// Return true if it's profitable to narrow operations of type VT1 to
1538 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1540 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1544 /// \brief Return true if it is beneficial to convert a load of a constant to
1545 /// just the constant itself.
1546 /// On some targets it might be more efficient to use a combination of
1547 /// arithmetic instructions to materialize the constant instead of loading it
1548 /// from a constant pool.
1549 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1554 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1555 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1556 /// has custom lowering that depends on the index of the first element,
1557 /// and only the target knows which lowering is cheap.
1558 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1562 //===--------------------------------------------------------------------===//
1563 // Runtime Library hooks
1566 /// Rename the default libcall routine name for the specified libcall.
1567 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1568 LibcallRoutineNames[Call] = Name;
1571 /// Get the libcall routine name for the specified libcall.
1572 const char *getLibcallName(RTLIB::Libcall Call) const {
1573 return LibcallRoutineNames[Call];
1576 /// Override the default CondCode to be used to test the result of the
1577 /// comparison libcall against zero.
1578 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1579 CmpLibcallCCs[Call] = CC;
1582 /// Get the CondCode that's to be used to test the result of the comparison
1583 /// libcall against zero.
1584 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1585 return CmpLibcallCCs[Call];
1588 /// Set the CallingConv that should be used for the specified libcall.
1589 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1590 LibcallCallingConvs[Call] = CC;
1593 /// Get the CallingConv that should be used for the specified libcall.
1594 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1595 return LibcallCallingConvs[Call];
1599 const TargetMachine &TM;
1600 const DataLayout *DL;
1602 /// True if this is a little endian target.
1603 bool IsLittleEndian;
1605 /// Tells the code generator not to expand operations into sequences that use
1606 /// the select operations if possible.
1607 bool SelectIsExpensive;
1609 /// Tells the code generator that the target has multiple (allocatable)
1610 /// condition registers that can be used to store the results of comparisons
1611 /// for use by selects and conditional branches. With multiple condition
1612 /// registers, the code generator will not aggressively sink comparisons into
1613 /// the blocks of their users.
1614 bool HasMultipleConditionRegisters;
1616 /// Tells the code generator that the target has BitExtract instructions.
1617 /// The code generator will aggressively sink "shift"s into the blocks of
1618 /// their users if the users will generate "and" instructions which can be
1619 /// combined with "shift" to BitExtract instructions.
1620 bool HasExtractBitsInsn;
1622 /// Tells the code generator not to expand integer divides by constants into a
1623 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1624 /// model is in place. If we ever optimize for size, this will be set to true
1625 /// unconditionally.
1628 /// Tells the code generator to bypass slow divide or remainder
1629 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1630 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1631 /// div/rem when the operands are positive and less than 256.
1632 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1634 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1635 /// signed divide by power of two; let the target handle it.
1636 bool Pow2SDivIsCheap;
1638 /// Tells the code generator that it shouldn't generate extra flow control
1639 /// instructions and should attempt to combine flow control instructions via
1641 bool JumpIsExpensive;
1643 /// Whether the target supports or cares about preserving floating point
1644 /// exception behavior.
1645 bool HasFloatingPointExceptions;
1647 /// This target prefers to use _setjmp to implement llvm.setjmp.
1649 /// Defaults to false.
1650 bool UseUnderscoreSetJmp;
1652 /// This target prefers to use _longjmp to implement llvm.longjmp.
1654 /// Defaults to false.
1655 bool UseUnderscoreLongJmp;
1657 /// Number of blocks threshold to use jump tables.
1658 int MinimumJumpTableEntries;
1660 /// Information about the contents of the high-bits in boolean values held in
1661 /// a type wider than i1. See getBooleanContents.
1662 BooleanContent BooleanContents;
1664 /// Information about the contents of the high-bits in boolean values held in
1665 /// a type wider than i1. See getBooleanContents.
1666 BooleanContent BooleanFloatContents;
1668 /// Information about the contents of the high-bits in boolean vector values
1669 /// when the element type is wider than i1. See getBooleanContents.
1670 BooleanContent BooleanVectorContents;
1672 /// The target scheduling preference: shortest possible total cycles or lowest
1674 Sched::Preference SchedPreferenceInfo;
1676 /// The size, in bytes, of the target's jmp_buf buffers
1677 unsigned JumpBufSize;
1679 /// The alignment, in bytes, of the target's jmp_buf buffers
1680 unsigned JumpBufAlignment;
1682 /// The minimum alignment that any argument on the stack needs to have.
1683 unsigned MinStackArgumentAlignment;
1685 /// The minimum function alignment (used when optimizing for size, and to
1686 /// prevent explicitly provided alignment from leading to incorrect code).
1687 unsigned MinFunctionAlignment;
1689 /// The preferred function alignment (used when alignment unspecified and
1690 /// optimizing for speed).
1691 unsigned PrefFunctionAlignment;
1693 /// The preferred loop alignment.
1694 unsigned PrefLoopAlignment;
1696 /// Whether the DAG builder should automatically insert fences and reduce
1697 /// ordering for atomics. (This will be set for for most architectures with
1698 /// weak memory ordering.)
1699 bool InsertFencesForAtomic;
1701 /// If set to a physical register, this specifies the register that
1702 /// llvm.savestack/llvm.restorestack should save and restore.
1703 unsigned StackPointerRegisterToSaveRestore;
1705 /// If set to a physical register, this specifies the register that receives
1706 /// the exception address on entry to a landing pad.
1707 unsigned ExceptionPointerRegister;
1709 /// If set to a physical register, this specifies the register that receives
1710 /// the exception typeid on entry to a landing pad.
1711 unsigned ExceptionSelectorRegister;
1713 /// This indicates the default register class to use for each ValueType the
1714 /// target supports natively.
1715 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1716 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1717 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1719 /// This indicates the "representative" register class to use for each
1720 /// ValueType the target supports natively. This information is used by the
1721 /// scheduler to track register pressure. By default, the representative
1722 /// register class is the largest legal super-reg register class of the
1723 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1724 /// representative class would be GR32.
1725 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1727 /// This indicates the "cost" of the "representative" register class for each
1728 /// ValueType. The cost is used by the scheduler to approximate register
1730 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1732 /// For any value types we are promoting or expanding, this contains the value
1733 /// type that we are changing to. For Expanded types, this contains one step
1734 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1735 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1736 /// the same type (e.g. i32 -> i32).
1737 MVT TransformToType[MVT::LAST_VALUETYPE];
1739 /// For each operation and each value type, keep a LegalizeAction that
1740 /// indicates how instruction selection should deal with the operation. Most
1741 /// operations are Legal (aka, supported natively by the target), but
1742 /// operations that are not should be described. Note that operations on
1743 /// non-legal value types are not described here.
1744 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1746 /// For each load extension type and each value type, keep a LegalizeAction
1747 /// that indicates how instruction selection should deal with a load of a
1748 /// specific value type and extension type.
1749 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1750 [ISD::LAST_LOADEXT_TYPE];
1752 /// For each value type pair keep a LegalizeAction that indicates whether a
1753 /// truncating store of a specific value type and truncating type is legal.
1754 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1756 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1757 /// that indicates how instruction selection should deal with the load /
1760 /// The first dimension is the value_type for the reference. The second
1761 /// dimension represents the various modes for load store.
1762 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1764 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1765 /// indicates how instruction selection should deal with the condition code.
1767 /// Because each CC action takes up 2 bits, we need to have the array size be
1768 /// large enough to fit all of the value types. This can be done by rounding
1769 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1770 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1772 ValueTypeActionImpl ValueTypeActions;
1776 getTypeConversion(LLVMContext &Context, EVT VT) const {
1777 // If this is a simple type, use the ComputeRegisterProp mechanism.
1778 if (VT.isSimple()) {
1779 MVT SVT = VT.getSimpleVT();
1780 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1781 MVT NVT = TransformToType[SVT.SimpleTy];
1782 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1785 (LA == TypeLegal || LA == TypeSoftenFloat ||
1786 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1787 && "Promote may not follow Expand or Promote");
1789 if (LA == TypeSplitVector)
1790 return LegalizeKind(LA, EVT::getVectorVT(Context,
1791 SVT.getVectorElementType(),
1792 SVT.getVectorNumElements()/2));
1793 if (LA == TypeScalarizeVector)
1794 return LegalizeKind(LA, SVT.getVectorElementType());
1795 return LegalizeKind(LA, NVT);
1798 // Handle Extended Scalar Types.
1799 if (!VT.isVector()) {
1800 assert(VT.isInteger() && "Float types must be simple");
1801 unsigned BitSize = VT.getSizeInBits();
1802 // First promote to a power-of-two size, then expand if necessary.
1803 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1804 EVT NVT = VT.getRoundIntegerType(Context);
1805 assert(NVT != VT && "Unable to round integer VT");
1806 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1807 // Avoid multi-step promotion.
1808 if (NextStep.first == TypePromoteInteger) return NextStep;
1809 // Return rounded integer type.
1810 return LegalizeKind(TypePromoteInteger, NVT);
1813 return LegalizeKind(TypeExpandInteger,
1814 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1817 // Handle vector types.
1818 unsigned NumElts = VT.getVectorNumElements();
1819 EVT EltVT = VT.getVectorElementType();
1821 // Vectors with only one element are always scalarized.
1823 return LegalizeKind(TypeScalarizeVector, EltVT);
1825 // Try to widen vector elements until the element type is a power of two and
1826 // promote it to a legal type later on, for example:
1827 // <3 x i8> -> <4 x i8> -> <4 x i32>
1828 if (EltVT.isInteger()) {
1829 // Vectors with a number of elements that is not a power of two are always
1830 // widened, for example <3 x i8> -> <4 x i8>.
1831 if (!VT.isPow2VectorType()) {
1832 NumElts = (unsigned)NextPowerOf2(NumElts);
1833 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1834 return LegalizeKind(TypeWidenVector, NVT);
1837 // Examine the element type.
1838 LegalizeKind LK = getTypeConversion(Context, EltVT);
1840 // If type is to be expanded, split the vector.
1841 // <4 x i140> -> <2 x i140>
1842 if (LK.first == TypeExpandInteger)
1843 return LegalizeKind(TypeSplitVector,
1844 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1846 // Promote the integer element types until a legal vector type is found
1847 // or until the element integer type is too big. If a legal type was not
1848 // found, fallback to the usual mechanism of widening/splitting the
1850 EVT OldEltVT = EltVT;
1852 // Increase the bitwidth of the element to the next pow-of-two
1853 // (which is greater than 8 bits).
1854 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1855 ).getRoundIntegerType(Context);
1857 // Stop trying when getting a non-simple element type.
1858 // Note that vector elements may be greater than legal vector element
1859 // types. Example: X86 XMM registers hold 64bit element on 32bit
1861 if (!EltVT.isSimple()) break;
1863 // Build a new vector type and check if it is legal.
1864 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1865 // Found a legal promoted vector type.
1866 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1867 return LegalizeKind(TypePromoteInteger,
1868 EVT::getVectorVT(Context, EltVT, NumElts));
1871 // Reset the type to the unexpanded type if we did not find a legal vector
1872 // type with a promoted vector element type.
1876 // Try to widen the vector until a legal type is found.
1877 // If there is no wider legal type, split the vector.
1879 // Round up to the next power of 2.
1880 NumElts = (unsigned)NextPowerOf2(NumElts);
1882 // If there is no simple vector type with this many elements then there
1883 // cannot be a larger legal vector type. Note that this assumes that
1884 // there are no skipped intermediate vector types in the simple types.
1885 if (!EltVT.isSimple()) break;
1886 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1887 if (LargerVector == MVT()) break;
1889 // If this type is legal then widen the vector.
1890 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1891 return LegalizeKind(TypeWidenVector, LargerVector);
1894 // Widen odd vectors to next power of two.
1895 if (!VT.isPow2VectorType()) {
1896 EVT NVT = VT.getPow2VectorType(Context);
1897 return LegalizeKind(TypeWidenVector, NVT);
1900 // Vectors with illegal element types are expanded.
1901 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1902 return LegalizeKind(TypeSplitVector, NVT);
1906 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1908 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1909 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1912 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1914 /// For operations that must be promoted to a specific type, this holds the
1915 /// destination type. This map should be sparse, so don't hold it as an
1918 /// Targets add entries to this map with AddPromotedToType(..), clients access
1919 /// this with getTypeToPromoteTo(..).
1920 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1923 /// Stores the name each libcall.
1924 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1926 /// The ISD::CondCode that should be used to test the result of each of the
1927 /// comparison libcall against zero.
1928 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1930 /// Stores the CallingConv that should be used for each libcall.
1931 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1934 /// \brief Specify maximum number of store instructions per memset call.
1936 /// When lowering \@llvm.memset this field specifies the maximum number of
1937 /// store operations that may be substituted for the call to memset. Targets
1938 /// must set this value based on the cost threshold for that target. Targets
1939 /// should assume that the memset will be done using as many of the largest
1940 /// store operations first, followed by smaller ones, if necessary, per
1941 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1942 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1943 /// store. This only applies to setting a constant array of a constant size.
1944 unsigned MaxStoresPerMemset;
1946 /// Maximum number of stores operations that may be substituted for the call
1947 /// to memset, used for functions with OptSize attribute.
1948 unsigned MaxStoresPerMemsetOptSize;
1950 /// \brief Specify maximum bytes of store instructions per memcpy call.
1952 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1953 /// store operations that may be substituted for a call to memcpy. Targets
1954 /// must set this value based on the cost threshold for that target. Targets
1955 /// should assume that the memcpy will be done using as many of the largest
1956 /// store operations first, followed by smaller ones, if necessary, per
1957 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1958 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1959 /// and one 1-byte store. This only applies to copying a constant array of
1961 unsigned MaxStoresPerMemcpy;
1963 /// Maximum number of store operations that may be substituted for a call to
1964 /// memcpy, used for functions with OptSize attribute.
1965 unsigned MaxStoresPerMemcpyOptSize;
1967 /// \brief Specify maximum bytes of store instructions per memmove call.
1969 /// When lowering \@llvm.memmove this field specifies the maximum number of
1970 /// store instructions that may be substituted for a call to memmove. Targets
1971 /// must set this value based on the cost threshold for that target. Targets
1972 /// should assume that the memmove will be done using as many of the largest
1973 /// store operations first, followed by smaller ones, if necessary, per
1974 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1975 /// with 8-bit alignment would result in nine 1-byte stores. This only
1976 /// applies to copying a constant array of constant size.
1977 unsigned MaxStoresPerMemmove;
1979 /// Maximum number of store instructions that may be substituted for a call to
1980 /// memmove, used for functions with OpSize attribute.
1981 unsigned MaxStoresPerMemmoveOptSize;
1983 /// Tells the code generator that select is more expensive than a branch if
1984 /// the branch is usually predicted right.
1985 bool PredictableSelectIsExpensive;
1987 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1988 /// a mask of a single bit, a compare, and a branch into a single instruction.
1989 bool MaskAndBranchFoldingIsLegal;
1991 /// \see enableExtLdPromotion.
1992 bool EnableExtLdPromotion;
1995 /// Return true if the value types that can be represented by the specified
1996 /// register class are all legal.
1997 bool isLegalRC(const TargetRegisterClass *RC) const;
1999 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2000 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2001 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
2004 /// This class defines information used to lower LLVM code to legal SelectionDAG
2005 /// operators that the target instruction selector can accept natively.
2007 /// This class also defines callbacks that targets must implement to lower
2008 /// target-specific constructs to SelectionDAG operators.
2009 class TargetLowering : public TargetLoweringBase {
2010 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
2011 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
2014 /// NOTE: The TargetMachine owns TLOF.
2015 explicit TargetLowering(const TargetMachine &TM);
2017 /// Returns true by value, base pointer and offset pointer and addressing mode
2018 /// by reference if the node's address can be legally represented as
2019 /// pre-indexed load / store address.
2020 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2021 SDValue &/*Offset*/,
2022 ISD::MemIndexedMode &/*AM*/,
2023 SelectionDAG &/*DAG*/) const {
2027 /// Returns true by value, base pointer and offset pointer and addressing mode
2028 /// by reference if this node can be combined with a load / store to form a
2029 /// post-indexed load / store.
2030 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2032 SDValue &/*Offset*/,
2033 ISD::MemIndexedMode &/*AM*/,
2034 SelectionDAG &/*DAG*/) const {
2038 /// Return the entry encoding for a jump table in the current function. The
2039 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2040 virtual unsigned getJumpTableEncoding() const;
2042 virtual const MCExpr *
2043 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2044 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2045 MCContext &/*Ctx*/) const {
2046 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2049 /// Returns relocation base for the given PIC jumptable.
2050 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2051 SelectionDAG &DAG) const;
2053 /// This returns the relocation base for the given PIC jumptable, the same as
2054 /// getPICJumpTableRelocBase, but as an MCExpr.
2055 virtual const MCExpr *
2056 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2057 unsigned JTI, MCContext &Ctx) const;
2059 /// Return true if folding a constant offset with the given GlobalAddress is
2060 /// legal. It is frequently not legal in PIC relocation models.
2061 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2063 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2064 SDValue &Chain) const;
2066 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2067 SDValue &NewLHS, SDValue &NewRHS,
2068 ISD::CondCode &CCCode, SDLoc DL) const;
2070 /// Returns a pair of (return value, chain).
2071 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2072 EVT RetVT, const SDValue *Ops,
2073 unsigned NumOps, bool isSigned,
2074 SDLoc dl, bool doesNotReturn = false,
2075 bool isReturnValueUsed = true) const;
2077 //===--------------------------------------------------------------------===//
2078 // TargetLowering Optimization Methods
2081 /// A convenience struct that encapsulates a DAG, and two SDValues for
2082 /// returning information from TargetLowering to its clients that want to
2084 struct TargetLoweringOpt {
2091 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2093 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2095 bool LegalTypes() const { return LegalTys; }
2096 bool LegalOperations() const { return LegalOps; }
2098 bool CombineTo(SDValue O, SDValue N) {
2104 /// Check to see if the specified operand of the specified instruction is a
2105 /// constant integer. If so, check to see if there are any bits set in the
2106 /// constant that are not demanded. If so, shrink the constant and return
2108 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2110 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2111 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2112 /// generalized for targets with other types of implicit widening casts.
2113 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2117 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2118 /// result of Op are ever used downstream. If we can use this information to
2119 /// simplify Op, create a new simplified DAG node and return true, returning
2120 /// the original and new nodes in Old and New. Otherwise, analyze the
2121 /// expression and return a mask of KnownOne and KnownZero bits for the
2122 /// expression (used to simplify the caller). The KnownZero/One bits may only
2123 /// be accurate for those bits in the DemandedMask.
2124 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2125 APInt &KnownZero, APInt &KnownOne,
2126 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2128 /// Determine which of the bits specified in Mask are known to be either zero
2129 /// or one and return them in the KnownZero/KnownOne bitsets.
2130 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2133 const SelectionDAG &DAG,
2134 unsigned Depth = 0) const;
2136 /// This method can be implemented by targets that want to expose additional
2137 /// information about sign bits to the DAG Combiner.
2138 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2139 const SelectionDAG &DAG,
2140 unsigned Depth = 0) const;
2142 struct DAGCombinerInfo {
2143 void *DC; // The DAG Combiner object.
2145 bool CalledByLegalizer;
2149 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2150 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2152 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2153 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2154 bool isAfterLegalizeVectorOps() const {
2155 return Level == AfterLegalizeDAG;
2157 CombineLevel getDAGCombineLevel() { return Level; }
2158 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2160 void AddToWorklist(SDNode *N);
2161 void RemoveFromWorklist(SDNode *N);
2162 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2164 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2165 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2167 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2170 /// Return if the N is a constant or constant vector equal to the true value
2171 /// from getBooleanContents().
2172 bool isConstTrueVal(const SDNode *N) const;
2174 /// Return if the N is a constant or constant vector equal to the false value
2175 /// from getBooleanContents().
2176 bool isConstFalseVal(const SDNode *N) const;
2178 /// Try to simplify a setcc built with the specified operands and cc. If it is
2179 /// unable to simplify it, return a null SDValue.
2180 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2181 ISD::CondCode Cond, bool foldBooleans,
2182 DAGCombinerInfo &DCI, SDLoc dl) const;
2184 /// Returns true (and the GlobalValue and the offset) if the node is a
2185 /// GlobalAddress + offset.
2187 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2189 /// This method will be invoked for all target nodes and for any
2190 /// target-independent nodes that the target has registered with invoke it
2193 /// The semantics are as follows:
2195 /// SDValue.Val == 0 - No change was made
2196 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2197 /// otherwise - N should be replaced by the returned Operand.
2199 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2200 /// more complex transformations.
2202 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2204 /// Return true if it is profitable to move a following shift through this
2205 // node, adjusting any immediate operands as necessary to preserve semantics.
2206 // This transformation may not be desirable if it disrupts a particularly
2207 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2208 // By default, it returns true.
2209 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2213 /// Return true if the target has native support for the specified value type
2214 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2215 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2216 /// and some i16 instructions are slow.
2217 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2218 // By default, assume all legal types are desirable.
2219 return isTypeLegal(VT);
2222 /// Return true if it is profitable for dag combiner to transform a floating
2223 /// point op of specified opcode to a equivalent op of an integer
2224 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2225 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2230 /// This method query the target whether it is beneficial for dag combiner to
2231 /// promote the specified node. If true, it should return the desired
2232 /// promotion type by reference.
2233 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2237 //===--------------------------------------------------------------------===//
2238 // Lowering methods - These methods must be implemented by targets so that
2239 // the SelectionDAGBuilder code knows how to lower these.
2242 /// This hook must be implemented to lower the incoming (formal) arguments,
2243 /// described by the Ins array, into the specified DAG. The implementation
2244 /// should fill in the InVals array with legal-type argument values, and
2245 /// return the resulting token chain value.
2248 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2250 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2251 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2252 SmallVectorImpl<SDValue> &/*InVals*/) const {
2253 llvm_unreachable("Not Implemented");
2256 struct ArgListEntry {
2265 bool isInAlloca : 1;
2266 bool isReturned : 1;
2269 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2270 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2271 isReturned(false), Alignment(0) { }
2273 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2275 typedef std::vector<ArgListEntry> ArgListTy;
2277 /// This structure contains all information that is necessary for lowering
2278 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2279 /// needs to lower a call, and targets will see this struct in their LowerCall
2281 struct CallLoweringInfo {
2288 bool DoesNotReturn : 1;
2289 bool IsReturnValueUsed : 1;
2291 // IsTailCall should be modified by implementations of
2292 // TargetLowering::LowerCall that perform tail call conversions.
2295 unsigned NumFixedArgs;
2296 CallingConv::ID CallConv;
2301 ImmutableCallSite *CS;
2302 SmallVector<ISD::OutputArg, 32> Outs;
2303 SmallVector<SDValue, 32> OutVals;
2304 SmallVector<ISD::InputArg, 32> Ins;
2306 CallLoweringInfo(SelectionDAG &DAG)
2307 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2308 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2309 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2310 DAG(DAG), CS(nullptr) {}
2312 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2317 CallLoweringInfo &setChain(SDValue InChain) {
2322 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2323 SDValue Target, ArgListTy &&ArgsList,
2324 unsigned FixedArgs = -1) {
2329 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2330 Args = std::move(ArgsList);
2334 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2335 SDValue Target, ArgListTy &&ArgsList,
2336 ImmutableCallSite &Call) {
2339 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2340 DoesNotReturn = Call.doesNotReturn();
2341 IsVarArg = FTy->isVarArg();
2342 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2343 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2344 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2348 CallConv = Call.getCallingConv();
2349 NumFixedArgs = FTy->getNumParams();
2350 Args = std::move(ArgsList);
2357 CallLoweringInfo &setInRegister(bool Value = true) {
2362 CallLoweringInfo &setNoReturn(bool Value = true) {
2363 DoesNotReturn = Value;
2367 CallLoweringInfo &setVarArg(bool Value = true) {
2372 CallLoweringInfo &setTailCall(bool Value = true) {
2377 CallLoweringInfo &setDiscardResult(bool Value = true) {
2378 IsReturnValueUsed = !Value;
2382 CallLoweringInfo &setSExtResult(bool Value = true) {
2387 CallLoweringInfo &setZExtResult(bool Value = true) {
2392 ArgListTy &getArgs() {
2397 /// This function lowers an abstract call to a function into an actual call.
2398 /// This returns a pair of operands. The first element is the return value
2399 /// for the function (if RetTy is not VoidTy). The second element is the
2400 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2401 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2403 /// This hook must be implemented to lower calls into the the specified
2404 /// DAG. The outgoing arguments to the call are described by the Outs array,
2405 /// and the values to be returned by the call are described by the Ins
2406 /// array. The implementation should fill in the InVals array with legal-type
2407 /// return values from the call, and return the resulting token chain value.
2409 LowerCall(CallLoweringInfo &/*CLI*/,
2410 SmallVectorImpl<SDValue> &/*InVals*/) const {
2411 llvm_unreachable("Not Implemented");
2414 /// Target-specific cleanup for formal ByVal parameters.
2415 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2417 /// This hook should be implemented to check whether the return values
2418 /// described by the Outs array can fit into the return registers. If false
2419 /// is returned, an sret-demotion is performed.
2420 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2421 MachineFunction &/*MF*/, bool /*isVarArg*/,
2422 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2423 LLVMContext &/*Context*/) const
2425 // Return true by default to get preexisting behavior.
2429 /// This hook must be implemented to lower outgoing return values, described
2430 /// by the Outs array, into the specified DAG. The implementation should
2431 /// return the resulting token chain value.
2433 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2435 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2436 const SmallVectorImpl<SDValue> &/*OutVals*/,
2437 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2438 llvm_unreachable("Not Implemented");
2441 /// Return true if result of the specified node is used by a return node
2442 /// only. It also compute and return the input chain for the tail call.
2444 /// This is used to determine whether it is possible to codegen a libcall as
2445 /// tail call at legalization time.
2446 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2450 /// Return true if the target may be able emit the call instruction as a tail
2451 /// call. This is used by optimization passes to determine if it's profitable
2452 /// to duplicate return instructions to enable tailcall optimization.
2453 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2457 /// Return the builtin name for the __builtin___clear_cache intrinsic
2458 /// Default is to invoke the clear cache library call
2459 virtual const char * getClearCacheBuiltinName() const {
2460 return "__clear_cache";
2463 /// Return the register ID of the name passed in. Used by named register
2464 /// global variables extension. There is no target-independent behaviour
2465 /// so the default action is to bail.
2466 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2467 report_fatal_error("Named registers not implemented for this target");
2470 /// Return the type that should be used to zero or sign extend a
2471 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2472 /// convention requires the return type to be promoted, but this is not true
2473 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2474 /// calling conventions. The frontend should handle this and include all of
2475 /// the necessary information.
2476 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2477 ISD::NodeType /*ExtendKind*/) const {
2478 EVT MinVT = getRegisterType(Context, MVT::i32);
2479 return VT.bitsLT(MinVT) ? MinVT : VT;
2482 /// For some targets, an LLVM struct type must be broken down into multiple
2483 /// simple types, but the calling convention specifies that the entire struct
2484 /// must be passed in a block of consecutive registers.
2486 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2487 bool isVarArg) const {
2491 /// Returns a 0 terminated array of registers that can be safely used as
2492 /// scratch registers.
2493 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2497 /// This callback is used to prepare for a volatile or atomic load.
2498 /// It takes a chain node as input and returns the chain for the load itself.
2500 /// Having a callback like this is necessary for targets like SystemZ,
2501 /// which allows a CPU to reuse the result of a previous load indefinitely,
2502 /// even if a cache-coherent store is performed by another CPU. The default
2503 /// implementation does nothing.
2504 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2505 SelectionDAG &DAG) const {
2509 /// This callback is invoked by the type legalizer to legalize nodes with an
2510 /// illegal operand type but legal result types. It replaces the
2511 /// LowerOperation callback in the type Legalizer. The reason we can not do
2512 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2513 /// use this callback.
2515 /// TODO: Consider merging with ReplaceNodeResults.
2517 /// The target places new result values for the node in Results (their number
2518 /// and types must exactly match those of the original return values of
2519 /// the node), or leaves Results empty, which indicates that the node is not
2520 /// to be custom lowered after all.
2521 /// The default implementation calls LowerOperation.
2522 virtual void LowerOperationWrapper(SDNode *N,
2523 SmallVectorImpl<SDValue> &Results,
2524 SelectionDAG &DAG) const;
2526 /// This callback is invoked for operations that are unsupported by the
2527 /// target, which are registered to use 'custom' lowering, and whose defined
2528 /// values are all legal. If the target has no operations that require custom
2529 /// lowering, it need not implement this. The default implementation of this
2531 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2533 /// This callback is invoked when a node result type is illegal for the
2534 /// target, and the operation was registered to use 'custom' lowering for that
2535 /// result type. The target places new result values for the node in Results
2536 /// (their number and types must exactly match those of the original return
2537 /// values of the node), or leaves Results empty, which indicates that the
2538 /// node is not to be custom lowered after all.
2540 /// If the target has no operations that require custom lowering, it need not
2541 /// implement this. The default implementation aborts.
2542 virtual void ReplaceNodeResults(SDNode * /*N*/,
2543 SmallVectorImpl<SDValue> &/*Results*/,
2544 SelectionDAG &/*DAG*/) const {
2545 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2548 /// This method returns the name of a target specific DAG node.
2549 virtual const char *getTargetNodeName(unsigned Opcode) const;
2551 /// This method returns a target specific FastISel object, or null if the
2552 /// target does not support "fast" ISel.
2553 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2554 const TargetLibraryInfo *) const {
2559 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2560 SelectionDAG &DAG) const;
2562 //===--------------------------------------------------------------------===//
2563 // Inline Asm Support hooks
2566 /// This hook allows the target to expand an inline asm call to be explicit
2567 /// llvm code if it wants to. This is useful for turning simple inline asms
2568 /// into LLVM intrinsics, which gives the compiler more information about the
2569 /// behavior of the code.
2570 virtual bool ExpandInlineAsm(CallInst *) const {
2574 enum ConstraintType {
2575 C_Register, // Constraint represents specific register(s).
2576 C_RegisterClass, // Constraint represents any of register(s) in class.
2577 C_Memory, // Memory constraint.
2578 C_Other, // Something else.
2579 C_Unknown // Unsupported constraint.
2582 enum ConstraintWeight {
2584 CW_Invalid = -1, // No match.
2585 CW_Okay = 0, // Acceptable.
2586 CW_Good = 1, // Good weight.
2587 CW_Better = 2, // Better weight.
2588 CW_Best = 3, // Best weight.
2590 // Well-known weights.
2591 CW_SpecificReg = CW_Okay, // Specific register operands.
2592 CW_Register = CW_Good, // Register operands.
2593 CW_Memory = CW_Better, // Memory operands.
2594 CW_Constant = CW_Best, // Constant operand.
2595 CW_Default = CW_Okay // Default or don't know type.
2598 /// This contains information for each constraint that we are lowering.
2599 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2600 /// This contains the actual string for the code, like "m". TargetLowering
2601 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2602 /// matches the operand.
2603 std::string ConstraintCode;
2605 /// Information about the constraint code, e.g. Register, RegisterClass,
2606 /// Memory, Other, Unknown.
2607 TargetLowering::ConstraintType ConstraintType;
2609 /// If this is the result output operand or a clobber, this is null,
2610 /// otherwise it is the incoming operand to the CallInst. This gets
2611 /// modified as the asm is processed.
2612 Value *CallOperandVal;
2614 /// The ValueType for the operand value.
2617 /// Return true of this is an input operand that is a matching constraint
2619 bool isMatchingInputConstraint() const;
2621 /// If this is an input matching constraint, this method returns the output
2622 /// operand it matches.
2623 unsigned getMatchedOperand() const;
2625 /// Copy constructor for copying from a ConstraintInfo.
2626 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2627 : InlineAsm::ConstraintInfo(std::move(Info)),
2628 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2629 ConstraintVT(MVT::Other) {}
2632 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2634 /// Split up the constraint string from the inline assembly value into the
2635 /// specific constraints and their prefixes, and also tie in the associated
2636 /// operand values. If this returns an empty vector, and if the constraint
2637 /// string itself isn't empty, there was an error parsing.
2638 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2640 /// Examine constraint type and operand type and determine a weight value.
2641 /// The operand object must already have been set up with the operand type.
2642 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2643 AsmOperandInfo &info, int maIndex) const;
2645 /// Examine constraint string and operand type and determine a weight value.
2646 /// The operand object must already have been set up with the operand type.
2647 virtual ConstraintWeight getSingleConstraintMatchWeight(
2648 AsmOperandInfo &info, const char *constraint) const;
2650 /// Determines the constraint code and constraint type to use for the specific
2651 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2652 /// If the actual operand being passed in is available, it can be passed in as
2653 /// Op, otherwise an empty SDValue can be passed.
2654 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2656 SelectionDAG *DAG = nullptr) const;
2658 /// Given a constraint, return the type of constraint it is for this target.
2659 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2661 /// Given a physical register constraint (e.g. {edx}), return the register
2662 /// number and the register class for the register.
2664 /// Given a register class constraint, like 'r', if this corresponds directly
2665 /// to an LLVM register class, return a register of 0 and the register class
2668 /// This should only be used for C_Register constraints. On error, this
2669 /// returns a register number of 0 and a null register class pointer..
2670 virtual std::pair<unsigned, const TargetRegisterClass*>
2671 getRegForInlineAsmConstraint(const std::string &Constraint,
2674 /// Try to replace an X constraint, which matches anything, with another that
2675 /// has more specific requirements based on the type of the corresponding
2676 /// operand. This returns null if there is no replacement to make.
2677 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2679 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2680 /// add anything to Ops.
2681 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2682 std::vector<SDValue> &Ops,
2683 SelectionDAG &DAG) const;
2685 //===--------------------------------------------------------------------===//
2686 // Div utility functions
2688 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2689 SelectionDAG &DAG) const;
2690 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2691 bool IsAfterLegalization,
2692 std::vector<SDNode *> *Created) const;
2693 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2694 bool IsAfterLegalization,
2695 std::vector<SDNode *> *Created) const;
2696 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2698 std::vector<SDNode *> *Created) const {
2702 /// Indicate whether this target prefers to combine the given number of FDIVs
2703 /// with the same divisor.
2704 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2708 /// Hooks for building estimates in place of slower divisions and square
2711 /// Return a reciprocal square root estimate value for the input operand.
2712 /// The RefinementSteps output is the number of Newton-Raphson refinement
2713 /// iterations required to generate a sufficient (though not necessarily
2714 /// IEEE-754 compliant) estimate for the value type.
2715 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2716 /// algorithm implementation that uses one constant or two constants.
2717 /// A target may choose to implement its own refinement within this function.
2718 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2719 /// any further refinement of the estimate.
2720 /// An empty SDValue return means no estimate sequence can be created.
2721 virtual SDValue getRsqrtEstimate(SDValue Operand,
2722 DAGCombinerInfo &DCI,
2723 unsigned &RefinementSteps,
2724 bool &UseOneConstNR) const {
2728 /// Return a reciprocal estimate value for the input operand.
2729 /// The RefinementSteps output is the number of Newton-Raphson refinement
2730 /// iterations required to generate a sufficient (though not necessarily
2731 /// IEEE-754 compliant) estimate for the value type.
2732 /// A target may choose to implement its own refinement within this function.
2733 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2734 /// any further refinement of the estimate.
2735 /// An empty SDValue return means no estimate sequence can be created.
2736 virtual SDValue getRecipEstimate(SDValue Operand,
2737 DAGCombinerInfo &DCI,
2738 unsigned &RefinementSteps) const {
2742 //===--------------------------------------------------------------------===//
2743 // Legalization utility functions
2746 /// Expand a MUL into two nodes. One that computes the high bits of
2747 /// the result and one that computes the low bits.
2748 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2749 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2750 /// if you want to control how low bits are extracted from the LHS.
2751 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2752 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2753 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2754 /// \returns true if the node has been expanded. false if it has not
2755 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2756 SelectionDAG &DAG, SDValue LL = SDValue(),
2757 SDValue LH = SDValue(), SDValue RL = SDValue(),
2758 SDValue RH = SDValue()) const;
2760 /// Expand float(f32) to SINT(i64) conversion
2761 /// \param N Node to expand
2762 /// \param Result output after conversion
2763 /// \returns True, if the expansion was successful, false otherwise
2764 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2766 //===--------------------------------------------------------------------===//
2767 // Instruction Emitting Hooks
2770 /// This method should be implemented by targets that mark instructions with
2771 /// the 'usesCustomInserter' flag. These instructions are special in various
2772 /// ways, which require special support to insert. The specified MachineInstr
2773 /// is created but not inserted into any basic blocks, and this method is
2774 /// called to expand it into a sequence of instructions, potentially also
2775 /// creating new basic blocks and control flow.
2776 virtual MachineBasicBlock *
2777 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2779 /// This method should be implemented by targets that mark instructions with
2780 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2781 /// instruction selection by target hooks. e.g. To fill in optional defs for
2782 /// ARM 's' setting instructions.
2784 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2786 /// If this function returns true, SelectionDAGBuilder emits a
2787 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2788 virtual bool useLoadStackGuardNode() const {
2793 /// Given an LLVM IR type and return type attributes, compute the return value
2794 /// EVTs and flags, and optionally also the offsets, if the return value is
2795 /// being lowered to memory.
2796 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2797 SmallVectorImpl<ISD::OutputArg> &Outs,
2798 const TargetLowering &TLI);
2800 } // end llvm namespace