1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they
130 /// should expand to.
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
164 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
166 virtual bool useSoftFloat() const { return false; }
168 /// Return the pointer type for the given address space, defaults to
169 /// the pointer type from the data layout.
170 /// FIXME: The default needs to be removed once all the code is updated.
171 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
172 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
174 virtual MVT getScalarShiftAmountTy(const DataLayout &) const;
176 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
178 /// Returns the type to be used for the index operand of:
179 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
180 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
181 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
182 return getPointerTy(DL);
185 /// Return true if the select operation is expensive for this target.
186 bool isSelectExpensive() const { return SelectIsExpensive; }
188 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
192 /// Return true if multiple condition registers are available.
193 bool hasMultipleConditionRegisters() const {
194 return HasMultipleConditionRegisters;
197 /// Return true if the target has BitExtract instructions.
198 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
200 /// Return the preferred vector type legalization action.
201 virtual TargetLoweringBase::LegalizeTypeAction
202 getPreferredVectorAction(EVT VT) const {
203 // The default action for one element vectors is to scalarize
204 if (VT.getVectorNumElements() == 1)
205 return TypeScalarizeVector;
206 // The default action for other vectors is to promote
207 return TypePromoteInteger;
210 // There are two general methods for expanding a BUILD_VECTOR node:
211 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
213 // 2. Build the vector on the stack and then load it.
214 // If this function returns true, then method (1) will be used, subject to
215 // the constraint that all of the necessary shuffles are legal (as determined
216 // by isShuffleMaskLegal). If this function returns false, then method (2) is
217 // always used. The vector type, and the number of defined values, are
220 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
221 unsigned DefinedValues) const {
222 return DefinedValues < 3;
225 /// Return true if integer divide is usually cheaper than a sequence of
226 /// several shifts, adds, and multiplies for this target.
227 bool isIntDivCheap() const { return IntDivIsCheap; }
229 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
230 bool isFsqrtCheap() const {
234 /// Returns true if target has indicated at least one type should be bypassed.
235 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
237 /// Returns map of slow types for division or remainder with corresponding
239 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
240 return BypassSlowDivWidths;
243 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
244 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
246 /// Return true if Flow Control is an expensive operation that should be
248 bool isJumpExpensive() const { return JumpIsExpensive; }
250 /// Return true if selects are only cheaper than branches if the branch is
251 /// unlikely to be predicted right.
252 bool isPredictableSelectExpensive() const {
253 return PredictableSelectIsExpensive;
256 /// isLoadBitCastBeneficial() - Return true if the following transform
258 /// fold (conv (load x)) -> (load (conv*)x)
259 /// On architectures that don't natively support some vector loads
260 /// efficiently, casting the load to a smaller vector of larger types and
261 /// loading is more efficient, however, this can be undone by optimizations in
263 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
264 EVT /* Bitcast */) const {
268 /// Return true if it is expected to be cheaper to do a store of a non-zero
269 /// vector constant with the given size and type for the address space than to
270 /// store the individual scalar element constants.
271 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
273 unsigned AddrSpace) const {
277 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
278 virtual bool isCheapToSpeculateCttz() const {
282 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
283 virtual bool isCheapToSpeculateCtlz() const {
287 /// \brief Return if the target supports combining a
290 /// %andResult = and %val1, #imm-with-one-bit-set;
291 /// %icmpResult = icmp %andResult, 0
292 /// br i1 %icmpResult, label %dest1, label %dest2
294 /// into a single machine instruction of a form like:
296 /// brOnBitSet %register, #bitNumber, dest
298 bool isMaskAndBranchFoldingLegal() const {
299 return MaskAndBranchFoldingIsLegal;
302 /// \brief Return true if the target wants to use the optimization that
303 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
304 /// promotedInst1(...(promotedInstN(ext(load)))).
305 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
307 /// Return true if the target can combine store(extractelement VectorTy,
309 /// \p Cost[out] gives the cost of that transformation when this is true.
310 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
311 unsigned &Cost) const {
315 /// Return true if target supports floating point exceptions.
316 bool hasFloatingPointExceptions() const {
317 return HasFloatingPointExceptions;
320 /// Return true if target always beneficiates from combining into FMA for a
321 /// given value type. This must typically return false on targets where FMA
322 /// takes more cycles to execute than FADD.
323 virtual bool enableAggressiveFMAFusion(EVT VT) const {
327 /// Return the ValueType of the result of SETCC operations.
328 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
331 /// Return the ValueType for comparison libcalls. Comparions libcalls include
332 /// floating point comparion calls, and Ordered/Unordered check calls on
333 /// floating point numbers.
335 MVT::SimpleValueType getCmpLibcallReturnType() const;
337 /// For targets without i1 registers, this gives the nature of the high-bits
338 /// of boolean values held in types wider than i1.
340 /// "Boolean values" are special true/false values produced by nodes like
341 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
342 /// Not to be confused with general values promoted from i1. Some cpus
343 /// distinguish between vectors of boolean and scalars; the isVec parameter
344 /// selects between the two kinds. For example on X86 a scalar boolean should
345 /// be zero extended from i1, while the elements of a vector of booleans
346 /// should be sign extended from i1.
348 /// Some cpus also treat floating point types the same way as they treat
349 /// vectors instead of the way they treat scalars.
350 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
352 return BooleanVectorContents;
353 return isFloat ? BooleanFloatContents : BooleanContents;
356 BooleanContent getBooleanContents(EVT Type) const {
357 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
360 /// Return target scheduling preference.
361 Sched::Preference getSchedulingPreference() const {
362 return SchedPreferenceInfo;
365 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
366 /// for different nodes. This function returns the preference (or none) for
368 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
372 /// Return the register class that should be used for the specified value
374 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
375 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
376 assert(RC && "This value type is not natively supported!");
380 /// Return the 'representative' register class for the specified value
383 /// The 'representative' register class is the largest legal super-reg
384 /// register class for the register class of the value type. For example, on
385 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
386 /// register class is GR64 on x86_64.
387 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
388 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
392 /// Return the cost of the 'representative' register class for the specified
394 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
395 return RepRegClassCostForVT[VT.SimpleTy];
398 /// Return true if the target has native support for the specified value type.
399 /// This means that it has a register that directly holds it without
400 /// promotions or expansions.
401 bool isTypeLegal(EVT VT) const {
402 assert(!VT.isSimple() ||
403 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
404 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
407 class ValueTypeActionImpl {
408 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
409 /// that indicates how instruction selection should deal with the type.
410 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
413 ValueTypeActionImpl() {
414 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
417 LegalizeTypeAction getTypeAction(MVT VT) const {
418 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
421 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
422 unsigned I = VT.SimpleTy;
423 ValueTypeActions[I] = Action;
427 const ValueTypeActionImpl &getValueTypeActions() const {
428 return ValueTypeActions;
431 /// Return how we should legalize values of this type, either it is already
432 /// legal (return 'Legal') or we need to promote it to a larger type (return
433 /// 'Promote'), or we need to expand it into multiple registers of smaller
434 /// integer type (return 'Expand'). 'Custom' is not an option.
435 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
436 return getTypeConversion(Context, VT).first;
438 LegalizeTypeAction getTypeAction(MVT VT) const {
439 return ValueTypeActions.getTypeAction(VT);
442 /// For types supported by the target, this is an identity function. For
443 /// types that must be promoted to larger types, this returns the larger type
444 /// to promote to. For integer types that are larger than the largest integer
445 /// register, this contains one step in the expansion to get to the smaller
446 /// register. For illegal floating point types, this returns the integer type
448 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
449 return getTypeConversion(Context, VT).second;
452 /// For types supported by the target, this is an identity function. For
453 /// types that must be expanded (i.e. integer types that are larger than the
454 /// largest integer register or illegal floating point types), this returns
455 /// the largest legal type it will be expanded to.
456 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
457 assert(!VT.isVector());
459 switch (getTypeAction(Context, VT)) {
462 case TypeExpandInteger:
463 VT = getTypeToTransformTo(Context, VT);
466 llvm_unreachable("Type is not legal nor is it to be expanded!");
471 /// Vector types are broken down into some number of legal first class types.
472 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
473 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
474 /// turns into 4 EVT::i32 values with both PPC and X86.
476 /// This method returns the number of registers needed, and the VT for each
477 /// register. It also returns the VT and quantity of the intermediate values
478 /// before they are promoted/expanded.
479 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
481 unsigned &NumIntermediates,
482 MVT &RegisterVT) const;
484 struct IntrinsicInfo {
485 unsigned opc; // target opcode
486 EVT memVT; // memory VT
487 const Value* ptrVal; // value representing memory location
488 int offset; // offset off of ptrVal
489 unsigned size; // the size of the memory location
490 // (taken from memVT if zero)
491 unsigned align; // alignment
492 bool vol; // is volatile?
493 bool readMem; // reads memory?
494 bool writeMem; // writes memory?
496 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
497 vol(false), readMem(false), writeMem(false) {}
500 /// Given an intrinsic, checks if on the target the intrinsic will need to map
501 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
502 /// true and store the intrinsic information into the IntrinsicInfo that was
503 /// passed to the function.
504 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
505 unsigned /*Intrinsic*/) const {
509 /// Returns true if the target can instruction select the specified FP
510 /// immediate natively. If false, the legalizer will materialize the FP
511 /// immediate as a load from a constant pool.
512 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
516 /// Targets can use this to indicate that they only support *some*
517 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
518 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
520 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
525 /// Returns true if the operation can trap for the value type.
527 /// VT must be a legal type. By default, we optimistically assume most
528 /// operations don't trap except for divide and remainder.
529 virtual bool canOpTrap(unsigned Op, EVT VT) const;
531 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
532 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
533 /// a VAND with a constant pool entry.
534 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
539 /// Return how this operation should be treated: either it is legal, needs to
540 /// be promoted to a larger size, needs to be expanded to some other code
541 /// sequence, or the target has a custom expander for it.
542 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
543 if (VT.isExtended()) return Expand;
544 // If a target-specific SDNode requires legalization, require the target
545 // to provide custom legalization for it.
546 if (Op > array_lengthof(OpActions[0])) return Custom;
547 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
548 return (LegalizeAction)OpActions[I][Op];
551 /// Return true if the specified operation is legal on this target or can be
552 /// made legal with custom lowering. This is used to help guide high-level
553 /// lowering decisions.
554 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
555 return (VT == MVT::Other || isTypeLegal(VT)) &&
556 (getOperationAction(Op, VT) == Legal ||
557 getOperationAction(Op, VT) == Custom);
560 /// Return true if the specified operation is legal on this target or can be
561 /// made legal using promotion. This is used to help guide high-level lowering
563 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
564 return (VT == MVT::Other || isTypeLegal(VT)) &&
565 (getOperationAction(Op, VT) == Legal ||
566 getOperationAction(Op, VT) == Promote);
569 /// Return true if the specified operation is illegal on this target or
570 /// unlikely to be made legal with custom lowering. This is used to help guide
571 /// high-level lowering decisions.
572 bool isOperationExpand(unsigned Op, EVT VT) const {
573 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
576 /// Return true if the specified operation is legal on this target.
577 bool isOperationLegal(unsigned Op, EVT VT) const {
578 return (VT == MVT::Other || isTypeLegal(VT)) &&
579 getOperationAction(Op, VT) == Legal;
582 /// Return how this load with extension should be treated: either it is legal,
583 /// needs to be promoted to a larger size, needs to be expanded to some other
584 /// code sequence, or the target has a custom expander for it.
585 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
587 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
588 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
589 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
590 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
591 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
592 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
595 /// Return true if the specified load with extension is legal on this target.
596 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
597 return ValVT.isSimple() && MemVT.isSimple() &&
598 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
601 /// Return true if the specified load with extension is legal or custom
603 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
604 return ValVT.isSimple() && MemVT.isSimple() &&
605 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
606 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
609 /// Return how this store with truncation should be treated: either it is
610 /// legal, needs to be promoted to a larger size, needs to be expanded to some
611 /// other code sequence, or the target has a custom expander for it.
612 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
613 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
614 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
615 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
616 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
617 "Table isn't big enough!");
618 return (LegalizeAction)TruncStoreActions[ValI][MemI];
621 /// Return true if the specified store with truncation is legal on this
623 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
624 return isTypeLegal(ValVT) && MemVT.isSimple() &&
625 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
628 /// Return how the indexed load should be treated: either it is legal, needs
629 /// to be promoted to a larger size, needs to be expanded to some other code
630 /// sequence, or the target has a custom expander for it.
632 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
633 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
634 "Table isn't big enough!");
635 unsigned Ty = (unsigned)VT.SimpleTy;
636 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
639 /// Return true if the specified indexed load is legal on this target.
640 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
641 return VT.isSimple() &&
642 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
643 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
646 /// Return how the indexed store should be treated: either it is legal, needs
647 /// to be promoted to a larger size, needs to be expanded to some other code
648 /// sequence, or the target has a custom expander for it.
650 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
651 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
652 "Table isn't big enough!");
653 unsigned Ty = (unsigned)VT.SimpleTy;
654 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
657 /// Return true if the specified indexed load is legal on this target.
658 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
659 return VT.isSimple() &&
660 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
661 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
664 /// Return how the condition code should be treated: either it is legal, needs
665 /// to be expanded to some other code sequence, or the target has a custom
668 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
669 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
670 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
671 "Table isn't big enough!");
672 // See setCondCodeAction for how this is encoded.
673 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
674 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
675 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
676 assert(Action != Promote && "Can't promote condition code!");
680 /// Return true if the specified condition code is legal on this target.
681 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
683 getCondCodeAction(CC, VT) == Legal ||
684 getCondCodeAction(CC, VT) == Custom;
688 /// If the action for this operation is to promote, this method returns the
689 /// ValueType to promote to.
690 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
691 assert(getOperationAction(Op, VT) == Promote &&
692 "This operation isn't promoted!");
694 // See if this has an explicit type specified.
695 std::map<std::pair<unsigned, MVT::SimpleValueType>,
696 MVT::SimpleValueType>::const_iterator PTTI =
697 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
698 if (PTTI != PromoteToType.end()) return PTTI->second;
700 assert((VT.isInteger() || VT.isFloatingPoint()) &&
701 "Cannot autopromote this type, add it with AddPromotedToType.");
705 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
706 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
707 "Didn't find type to promote to!");
708 } while (!isTypeLegal(NVT) ||
709 getOperationAction(Op, NVT) == Promote);
713 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
714 /// operations except for the pointer size. If AllowUnknown is true, this
715 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
716 /// otherwise it will assert.
717 EVT getValueType(const DataLayout &DL, Type *Ty,
718 bool AllowUnknown = false) const {
719 // Lower scalar pointers to native pointer types.
720 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
721 return getPointerTy(DL, PTy->getAddressSpace());
723 if (Ty->isVectorTy()) {
724 VectorType *VTy = cast<VectorType>(Ty);
725 Type *Elm = VTy->getElementType();
726 // Lower vectors of pointers to native pointer types.
727 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
728 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
729 Elm = PointerTy.getTypeForEVT(Ty->getContext());
732 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
733 VTy->getNumElements());
735 return EVT::getEVT(Ty, AllowUnknown);
738 /// Return the MVT corresponding to this LLVM type. See getValueType.
739 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
740 bool AllowUnknown = false) const {
741 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
744 /// Return the desired alignment for ByVal or InAlloca aggregate function
745 /// arguments in the caller parameter area. This is the actual alignment, not
747 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
749 /// Return the type of registers that this ValueType will eventually require.
750 MVT getRegisterType(MVT VT) const {
751 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
752 return RegisterTypeForVT[VT.SimpleTy];
755 /// Return the type of registers that this ValueType will eventually require.
756 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
758 assert((unsigned)VT.getSimpleVT().SimpleTy <
759 array_lengthof(RegisterTypeForVT));
760 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
765 unsigned NumIntermediates;
766 (void)getVectorTypeBreakdown(Context, VT, VT1,
767 NumIntermediates, RegisterVT);
770 if (VT.isInteger()) {
771 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
773 llvm_unreachable("Unsupported extended type!");
776 /// Return the number of registers that this ValueType will eventually
779 /// This is one for any types promoted to live in larger registers, but may be
780 /// more than one for types (like i64) that are split into pieces. For types
781 /// like i140, which are first promoted then expanded, it is the number of
782 /// registers needed to hold all the bits of the original type. For an i140
783 /// on a 32 bit machine this means 5 registers.
784 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
786 assert((unsigned)VT.getSimpleVT().SimpleTy <
787 array_lengthof(NumRegistersForVT));
788 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
793 unsigned NumIntermediates;
794 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
796 if (VT.isInteger()) {
797 unsigned BitWidth = VT.getSizeInBits();
798 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
799 return (BitWidth + RegWidth - 1) / RegWidth;
801 llvm_unreachable("Unsupported extended type!");
804 /// If true, then instruction selection should seek to shrink the FP constant
805 /// of the specified type to a smaller type in order to save space and / or
807 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
809 // Return true if it is profitable to reduce the given load node to a smaller
812 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
813 virtual bool shouldReduceLoadWidth(SDNode *Load,
814 ISD::LoadExtType ExtTy,
819 /// When splitting a value of the specified type into parts, does the Lo
820 /// or Hi part come first? This usually follows the endianness, except
821 /// for ppcf128, where the Hi part always comes first.
822 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
823 return DL.isBigEndian() || VT == MVT::ppcf128;
826 /// If true, the target has custom DAG combine transformations that it can
827 /// perform for the specified node.
828 bool hasTargetDAGCombine(ISD::NodeType NT) const {
829 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
830 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
833 /// \brief Get maximum # of store operations permitted for llvm.memset
835 /// This function returns the maximum number of store operations permitted
836 /// to replace a call to llvm.memset. The value is set by the target at the
837 /// performance threshold for such a replacement. If OptSize is true,
838 /// return the limit for functions that have OptSize attribute.
839 unsigned getMaxStoresPerMemset(bool OptSize) const {
840 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
843 /// \brief Get maximum # of store operations permitted for llvm.memcpy
845 /// This function returns the maximum number of store operations permitted
846 /// to replace a call to llvm.memcpy. The value is set by the target at the
847 /// performance threshold for such a replacement. If OptSize is true,
848 /// return the limit for functions that have OptSize attribute.
849 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
850 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
853 /// \brief Get maximum # of store operations permitted for llvm.memmove
855 /// This function returns the maximum number of store operations permitted
856 /// to replace a call to llvm.memmove. The value is set by the target at the
857 /// performance threshold for such a replacement. If OptSize is true,
858 /// return the limit for functions that have OptSize attribute.
859 unsigned getMaxStoresPerMemmove(bool OptSize) const {
860 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
863 /// \brief Determine if the target supports unaligned memory accesses.
865 /// This function returns true if the target allows unaligned memory accesses
866 /// of the specified type in the given address space. If true, it also returns
867 /// whether the unaligned memory access is "fast" in the last argument by
868 /// reference. This is used, for example, in situations where an array
869 /// copy/move/set is converted to a sequence of store operations. Its use
870 /// helps to ensure that such replacements don't generate code that causes an
871 /// alignment error (trap) on the target machine.
872 virtual bool allowsMisalignedMemoryAccesses(EVT,
873 unsigned AddrSpace = 0,
875 bool * /*Fast*/ = nullptr) const {
879 /// Returns the target specific optimal type for load and store operations as
880 /// a result of memset, memcpy, and memmove lowering.
882 /// If DstAlign is zero that means it's safe to destination alignment can
883 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
884 /// a need to check it against alignment requirement, probably because the
885 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
886 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
887 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
888 /// does not need to be loaded. It returns EVT::Other if the type should be
889 /// determined using generic target-independent logic.
890 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
891 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
894 bool /*MemcpyStrSrc*/,
895 MachineFunction &/*MF*/) const {
899 /// Returns true if it's safe to use load / store of the specified type to
900 /// expand memcpy / memset inline.
902 /// This is mostly true for all types except for some special cases. For
903 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
904 /// fstpl which also does type conversion. Note the specified type doesn't
905 /// have to be legal as the hook is used before type legalization.
906 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
908 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
909 bool usesUnderscoreSetJmp() const {
910 return UseUnderscoreSetJmp;
913 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
914 bool usesUnderscoreLongJmp() const {
915 return UseUnderscoreLongJmp;
918 /// Return integer threshold on number of blocks to use jump tables rather
919 /// than if sequence.
920 int getMinimumJumpTableEntries() const {
921 return MinimumJumpTableEntries;
924 /// If a physical register, this specifies the register that
925 /// llvm.savestack/llvm.restorestack should save and restore.
926 unsigned getStackPointerRegisterToSaveRestore() const {
927 return StackPointerRegisterToSaveRestore;
930 /// If a physical register, this returns the register that receives the
931 /// exception address on entry to a landing pad.
932 unsigned getExceptionPointerRegister() const {
933 return ExceptionPointerRegister;
936 /// If a physical register, this returns the register that receives the
937 /// exception typeid on entry to a landing pad.
938 unsigned getExceptionSelectorRegister() const {
939 return ExceptionSelectorRegister;
942 /// Returns the target's jmp_buf size in bytes (if never set, the default is
944 unsigned getJumpBufSize() const {
948 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
950 unsigned getJumpBufAlignment() const {
951 return JumpBufAlignment;
954 /// Return the minimum stack alignment of an argument.
955 unsigned getMinStackArgumentAlignment() const {
956 return MinStackArgumentAlignment;
959 /// Return the minimum function alignment.
960 unsigned getMinFunctionAlignment() const {
961 return MinFunctionAlignment;
964 /// Return the preferred function alignment.
965 unsigned getPrefFunctionAlignment() const {
966 return PrefFunctionAlignment;
969 /// Return the preferred loop alignment.
970 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
971 return PrefLoopAlignment;
974 /// Return whether the DAG builder should automatically insert fences and
975 /// reduce ordering for atomics.
976 bool getInsertFencesForAtomic() const {
977 return InsertFencesForAtomic;
980 /// Return true if the target stores stack protector cookies at a fixed offset
981 /// in some non-standard address space, and populates the address space and
982 /// offset as appropriate.
983 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
984 unsigned &/*Offset*/) const {
988 /// Returns true if a cast between SrcAS and DestAS is a noop.
989 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
993 /// Return true if the pointer arguments to CI should be aligned by aligning
994 /// the object whose address is being passed. If so then MinSize is set to the
995 /// minimum size the object must be to be aligned and PrefAlign is set to the
996 /// preferred alignment.
997 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
998 unsigned & /*PrefAlign*/) const {
1002 //===--------------------------------------------------------------------===//
1003 /// \name Helpers for TargetTransformInfo implementations
1006 /// Get the ISD node that corresponds to the Instruction class opcode.
1007 int InstructionOpcodeToISD(unsigned Opcode) const;
1009 /// Estimate the cost of type-legalization and the legalized type.
1010 std::pair<unsigned, MVT> getTypeLegalizationCost(const DataLayout &DL,
1015 //===--------------------------------------------------------------------===//
1016 /// \name Helpers for atomic expansion.
1019 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1020 /// and expand AtomicCmpXchgInst.
1021 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1023 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1024 /// corresponding pointee type. This may entail some non-trivial operations to
1025 /// truncate or reconstruct types that will be illegal in the backend. See
1026 /// ARMISelLowering for an example implementation.
1027 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1028 AtomicOrdering Ord) const {
1029 llvm_unreachable("Load linked unimplemented on this target");
1032 /// Perform a store-conditional operation to Addr. Return the status of the
1033 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1034 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1035 Value *Addr, AtomicOrdering Ord) const {
1036 llvm_unreachable("Store conditional unimplemented on this target");
1039 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1040 /// It is called by AtomicExpandPass before expanding an
1041 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1042 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1043 /// This function should either return a nullptr, or a pointer to an IR-level
1044 /// Instruction*. Even complex fence sequences can be represented by a
1045 /// single Instruction* through an intrinsic to be lowered later.
1046 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1047 /// Backends should override this method to produce target-specific intrinsic
1048 /// for their fences.
1049 /// FIXME: Please note that the default implementation here in terms of
1050 /// IR-level fences exists for historical/compatibility reasons and is
1051 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1052 /// consistency. For example, consider the following example:
1053 /// atomic<int> x = y = 0;
1054 /// int r1, r2, r3, r4;
1065 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1066 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1067 /// IR-level fences can prevent it.
1069 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1070 AtomicOrdering Ord, bool IsStore,
1071 bool IsLoad) const {
1072 if (!getInsertFencesForAtomic())
1075 if (isAtLeastRelease(Ord) && IsStore)
1076 return Builder.CreateFence(Ord);
1081 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1082 AtomicOrdering Ord, bool IsStore,
1083 bool IsLoad) const {
1084 if (!getInsertFencesForAtomic())
1087 if (isAtLeastAcquire(Ord))
1088 return Builder.CreateFence(Ord);
1094 /// Returns true if the given (atomic) store should be expanded by the
1095 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1096 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1100 /// Returns true if arguments should be sign-extended in lib calls.
1101 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1105 /// Returns true if the given (atomic) load should be expanded by the
1106 /// IR-level AtomicExpand pass into a load-linked instruction
1107 /// (through emitLoadLinked()).
1108 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1110 /// Returns how the IR-level AtomicExpand pass should expand the given
1111 /// AtomicRMW, if at all. Default is to never expand.
1112 virtual AtomicRMWExpansionKind
1113 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1114 return AtomicRMWExpansionKind::None;
1117 /// On some platforms, an AtomicRMW that never actually modifies the value
1118 /// (such as fetch_add of 0) can be turned into a fence followed by an
1119 /// atomic load. This may sound useless, but it makes it possible for the
1120 /// processor to keep the cacheline shared, dramatically improving
1121 /// performance. And such idempotent RMWs are useful for implementing some
1122 /// kinds of locks, see for example (justification + benchmarks):
1123 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1124 /// This method tries doing that transformation, returning the atomic load if
1125 /// it succeeds, and nullptr otherwise.
1126 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1127 /// another round of expansion.
1129 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1133 /// Returns true if we should normalize
1134 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1135 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1136 /// that it saves us from materializing N0 and N1 in an integer register.
1137 /// Targets that are able to perform and/or on flags should return false here.
1138 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1140 // If a target has multiple condition registers, then it likely has logical
1141 // operations on those registers.
1142 if (hasMultipleConditionRegisters())
1144 // Only do the transform if the value won't be split into multiple
1146 LegalizeTypeAction Action = getTypeAction(Context, VT);
1147 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1148 Action != TypeSplitVector;
1151 //===--------------------------------------------------------------------===//
1152 // TargetLowering Configuration Methods - These methods should be invoked by
1153 // the derived class constructor to configure this object for the target.
1156 /// Specify how the target extends the result of integer and floating point
1157 /// boolean values from i1 to a wider type. See getBooleanContents.
1158 void setBooleanContents(BooleanContent Ty) {
1159 BooleanContents = Ty;
1160 BooleanFloatContents = Ty;
1163 /// Specify how the target extends the result of integer and floating point
1164 /// boolean values from i1 to a wider type. See getBooleanContents.
1165 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1166 BooleanContents = IntTy;
1167 BooleanFloatContents = FloatTy;
1170 /// Specify how the target extends the result of a vector boolean value from a
1171 /// vector of i1 to a wider type. See getBooleanContents.
1172 void setBooleanVectorContents(BooleanContent Ty) {
1173 BooleanVectorContents = Ty;
1176 /// Specify the target scheduling preference.
1177 void setSchedulingPreference(Sched::Preference Pref) {
1178 SchedPreferenceInfo = Pref;
1181 /// Indicate whether this target prefers to use _setjmp to implement
1182 /// llvm.setjmp or the version without _. Defaults to false.
1183 void setUseUnderscoreSetJmp(bool Val) {
1184 UseUnderscoreSetJmp = Val;
1187 /// Indicate whether this target prefers to use _longjmp to implement
1188 /// llvm.longjmp or the version without _. Defaults to false.
1189 void setUseUnderscoreLongJmp(bool Val) {
1190 UseUnderscoreLongJmp = Val;
1193 /// Indicate the number of blocks to generate jump tables rather than if
1195 void setMinimumJumpTableEntries(int Val) {
1196 MinimumJumpTableEntries = Val;
1199 /// If set to a physical register, this specifies the register that
1200 /// llvm.savestack/llvm.restorestack should save and restore.
1201 void setStackPointerRegisterToSaveRestore(unsigned R) {
1202 StackPointerRegisterToSaveRestore = R;
1205 /// If set to a physical register, this sets the register that receives the
1206 /// exception address on entry to a landing pad.
1207 void setExceptionPointerRegister(unsigned R) {
1208 ExceptionPointerRegister = R;
1211 /// If set to a physical register, this sets the register that receives the
1212 /// exception typeid on entry to a landing pad.
1213 void setExceptionSelectorRegister(unsigned R) {
1214 ExceptionSelectorRegister = R;
1217 /// Tells the code generator not to expand operations into sequences that use
1218 /// the select operations if possible.
1219 void setSelectIsExpensive(bool isExpensive = true) {
1220 SelectIsExpensive = isExpensive;
1223 /// Tells the code generator that the target has multiple (allocatable)
1224 /// condition registers that can be used to store the results of comparisons
1225 /// for use by selects and conditional branches. With multiple condition
1226 /// registers, the code generator will not aggressively sink comparisons into
1227 /// the blocks of their users.
1228 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1229 HasMultipleConditionRegisters = hasManyRegs;
1232 /// Tells the code generator that the target has BitExtract instructions.
1233 /// The code generator will aggressively sink "shift"s into the blocks of
1234 /// their users if the users will generate "and" instructions which can be
1235 /// combined with "shift" to BitExtract instructions.
1236 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1237 HasExtractBitsInsn = hasExtractInsn;
1240 /// Tells the code generator not to expand logic operations on comparison
1241 /// predicates into separate sequences that increase the amount of flow
1243 void setJumpIsExpensive(bool isExpensive = true);
1245 /// Tells the code generator that integer divide is expensive, and if
1246 /// possible, should be replaced by an alternate sequence of instructions not
1247 /// containing an integer divide.
1248 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1250 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1251 /// with an alternative sequence of instructions.
1252 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1254 /// Tells the code generator that this target supports floating point
1255 /// exceptions and cares about preserving floating point exception behavior.
1256 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1257 HasFloatingPointExceptions = FPExceptions;
1260 /// Tells the code generator which bitwidths to bypass.
1261 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1262 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1265 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1266 /// signed divide by power of two; let the target handle it.
1267 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1269 /// Add the specified register class as an available regclass for the
1270 /// specified value type. This indicates the selector can handle values of
1271 /// that class natively.
1272 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1273 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1274 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1275 RegClassForVT[VT.SimpleTy] = RC;
1278 /// Remove all register classes.
1279 void clearRegisterClasses() {
1280 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1282 AvailableRegClasses.clear();
1285 /// \brief Remove all operation actions.
1286 void clearOperationActions() {
1289 /// Return the largest legal super-reg register class of the register class
1290 /// for the specified type and its associated "cost".
1291 virtual std::pair<const TargetRegisterClass *, uint8_t>
1292 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1294 /// Once all of the register classes are added, this allows us to compute
1295 /// derived properties we expose.
1296 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1298 /// Indicate that the specified operation does not work with the specified
1299 /// type and indicate what to do about it.
1300 void setOperationAction(unsigned Op, MVT VT,
1301 LegalizeAction Action) {
1302 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1303 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1306 /// Indicate that the specified load with extension does not work with the
1307 /// specified type and indicate what to do about it.
1308 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1309 LegalizeAction Action) {
1310 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1311 MemVT.isValid() && "Table isn't big enough!");
1312 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1315 /// Indicate that the specified truncating store does not work with the
1316 /// specified type and indicate what to do about it.
1317 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1318 LegalizeAction Action) {
1319 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1320 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1323 /// Indicate that the specified indexed load does or does not work with the
1324 /// specified type and indicate what to do abort it.
1326 /// NOTE: All indexed mode loads are initialized to Expand in
1327 /// TargetLowering.cpp
1328 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1329 LegalizeAction Action) {
1330 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1331 (unsigned)Action < 0xf && "Table isn't big enough!");
1332 // Load action are kept in the upper half.
1333 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1334 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1337 /// Indicate that the specified indexed store does or does not work with the
1338 /// specified type and indicate what to do about it.
1340 /// NOTE: All indexed mode stores are initialized to Expand in
1341 /// TargetLowering.cpp
1342 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1343 LegalizeAction Action) {
1344 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1345 (unsigned)Action < 0xf && "Table isn't big enough!");
1346 // Store action are kept in the lower half.
1347 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1348 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1351 /// Indicate that the specified condition code is or isn't supported on the
1352 /// target and indicate what to do about it.
1353 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1354 LegalizeAction Action) {
1355 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1356 "Table isn't big enough!");
1357 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1358 /// value and the upper 27 bits index into the second dimension of the array
1359 /// to select what 32-bit value to use.
1360 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1361 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1362 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1365 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1366 /// to trying a larger integer/fp until it can find one that works. If that
1367 /// default is insufficient, this method can be used by the target to override
1369 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1370 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1373 /// Targets should invoke this method for each target independent node that
1374 /// they want to provide a custom DAG combiner for by implementing the
1375 /// PerformDAGCombine virtual method.
1376 void setTargetDAGCombine(ISD::NodeType NT) {
1377 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1378 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1381 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1382 void setJumpBufSize(unsigned Size) {
1386 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1388 void setJumpBufAlignment(unsigned Align) {
1389 JumpBufAlignment = Align;
1392 /// Set the target's minimum function alignment (in log2(bytes))
1393 void setMinFunctionAlignment(unsigned Align) {
1394 MinFunctionAlignment = Align;
1397 /// Set the target's preferred function alignment. This should be set if
1398 /// there is a performance benefit to higher-than-minimum alignment (in
1400 void setPrefFunctionAlignment(unsigned Align) {
1401 PrefFunctionAlignment = Align;
1404 /// Set the target's preferred loop alignment. Default alignment is zero, it
1405 /// means the target does not care about loop alignment. The alignment is
1406 /// specified in log2(bytes). The target may also override
1407 /// getPrefLoopAlignment to provide per-loop values.
1408 void setPrefLoopAlignment(unsigned Align) {
1409 PrefLoopAlignment = Align;
1412 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1413 void setMinStackArgumentAlignment(unsigned Align) {
1414 MinStackArgumentAlignment = Align;
1417 /// Set if the DAG builder should automatically insert fences and reduce the
1418 /// order of atomic memory operations to Monotonic.
1419 void setInsertFencesForAtomic(bool fence) {
1420 InsertFencesForAtomic = fence;
1424 //===--------------------------------------------------------------------===//
1425 // Addressing mode description hooks (used by LSR etc).
1428 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1429 /// instructions reading the address. This allows as much computation as
1430 /// possible to be done in the address mode for that operand. This hook lets
1431 /// targets also pass back when this should be done on intrinsics which
1433 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1434 SmallVectorImpl<Value*> &/*Ops*/,
1435 Type *&/*AccessTy*/,
1436 unsigned AddrSpace = 0) const {
1440 /// This represents an addressing mode of:
1441 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1442 /// If BaseGV is null, there is no BaseGV.
1443 /// If BaseOffs is zero, there is no base offset.
1444 /// If HasBaseReg is false, there is no base register.
1445 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1448 GlobalValue *BaseGV;
1452 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1455 /// Return true if the addressing mode represented by AM is legal for this
1456 /// target, for a load/store of the specified type.
1458 /// The type may be VoidTy, in which case only return true if the addressing
1459 /// mode is legal for a load/store of any legal type. TODO: Handle
1460 /// pre/postinc as well.
1462 /// If the address space cannot be determined, it will be -1.
1464 /// TODO: Remove default argument
1465 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
1466 unsigned AddrSpace) const;
1468 /// \brief Return the cost of the scaling factor used in the addressing mode
1469 /// represented by AM for this target, for a load/store of the specified type.
1471 /// If the AM is supported, the return value must be >= 0.
1472 /// If the AM is not supported, it returns a negative value.
1473 /// TODO: Handle pre/postinc as well.
1474 /// TODO: Remove default argument
1475 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty,
1476 unsigned AS = 0) const {
1477 // Default: assume that any scaling factor used in a legal AM is free.
1478 if (isLegalAddressingMode(AM, Ty, AS))
1483 /// Return true if the specified immediate is legal icmp immediate, that is
1484 /// the target has icmp instructions which can compare a register against the
1485 /// immediate without having to materialize the immediate into a register.
1486 virtual bool isLegalICmpImmediate(int64_t) const {
1490 /// Return true if the specified immediate is legal add immediate, that is the
1491 /// target has add instructions which can add a register with the immediate
1492 /// without having to materialize the immediate into a register.
1493 virtual bool isLegalAddImmediate(int64_t) const {
1497 /// Return true if it's significantly cheaper to shift a vector by a uniform
1498 /// scalar than by an amount which will vary across each lane. On x86, for
1499 /// example, there is a "psllw" instruction for the former case, but no simple
1500 /// instruction for a general "a << b" operation on vectors.
1501 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1505 /// Return true if it's free to truncate a value of type Ty1 to type
1506 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1507 /// by referencing its sub-register AX.
1508 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1512 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1513 /// whether a call is in tail position. Typically this means that both results
1514 /// would be assigned to the same register or stack slot, but it could mean
1515 /// the target performs adequate checks of its own before proceeding with the
1517 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1521 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1525 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1527 /// Return true if the extension represented by \p I is free.
1528 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1529 /// this method can use the context provided by \p I to decide
1530 /// whether or not \p I is free.
1531 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1532 /// In other words, if is[Z|FP]Free returns true, then this method
1533 /// returns true as well. The converse is not true.
1534 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1535 /// \pre \p I must be a sign, zero, or fp extension.
1536 bool isExtFree(const Instruction *I) const {
1537 switch (I->getOpcode()) {
1538 case Instruction::FPExt:
1539 if (isFPExtFree(EVT::getEVT(I->getType())))
1542 case Instruction::ZExt:
1543 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1546 case Instruction::SExt:
1549 llvm_unreachable("Instruction is not an extension");
1551 return isExtFreeImpl(I);
1554 /// Return true if any actual instruction that defines a value of type Ty1
1555 /// implicitly zero-extends the value to Ty2 in the result register.
1557 /// This does not necessarily include registers defined in unknown ways, such
1558 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1559 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1560 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1561 /// values implicit zero-extend the result out to 64 bits.
1562 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1566 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1570 /// Return true if the target supplies and combines to a paired load
1571 /// two loaded values of type LoadedType next to each other in memory.
1572 /// RequiredAlignment gives the minimal alignment constraints that must be met
1573 /// to be able to select this paired load.
1575 /// This information is *not* used to generate actual paired loads, but it is
1576 /// used to generate a sequence of loads that is easier to combine into a
1578 /// For instance, something like this:
1579 /// a = load i64* addr
1580 /// b = trunc i64 a to i32
1581 /// c = lshr i64 a, 32
1582 /// d = trunc i64 c to i32
1583 /// will be optimized into:
1584 /// b = load i32* addr1
1585 /// d = load i32* addr2
1586 /// Where addr1 = addr2 +/- sizeof(i32).
1588 /// In other words, unless the target performs a post-isel load combining,
1589 /// this information should not be provided because it will generate more
1591 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1592 unsigned & /*RequiredAligment*/) const {
1596 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1597 unsigned & /*RequiredAligment*/) const {
1601 /// \brief Get the maximum supported factor for interleaved memory accesses.
1602 /// Default to be the minimum interleave factor: 2.
1603 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1605 /// \brief Lower an interleaved load to target specific intrinsics. Return
1606 /// true on success.
1608 /// \p LI is the vector load instruction.
1609 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1610 /// \p Indices is the corresponding indices for each shufflevector.
1611 /// \p Factor is the interleave factor.
1612 virtual bool lowerInterleavedLoad(LoadInst *LI,
1613 ArrayRef<ShuffleVectorInst *> Shuffles,
1614 ArrayRef<unsigned> Indices,
1615 unsigned Factor) const {
1619 /// \brief Lower an interleaved store to target specific intrinsics. Return
1620 /// true on success.
1622 /// \p SI is the vector store instruction.
1623 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1624 /// \p Factor is the interleave factor.
1625 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1626 unsigned Factor) const {
1630 /// Return true if zero-extending the specific node Val to type VT2 is free
1631 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1632 /// because it's folded such as X86 zero-extending loads).
1633 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1634 return isZExtFree(Val.getValueType(), VT2);
1637 /// Return true if an fpext operation is free (for instance, because
1638 /// single-precision floating-point numbers are implicitly extended to
1639 /// double-precision).
1640 virtual bool isFPExtFree(EVT VT) const {
1641 assert(VT.isFloatingPoint());
1645 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1646 /// extend node) is profitable.
1647 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1649 /// Return true if an fneg operation is free to the point where it is never
1650 /// worthwhile to replace it with a bitwise operation.
1651 virtual bool isFNegFree(EVT VT) const {
1652 assert(VT.isFloatingPoint());
1656 /// Return true if an fabs operation is free to the point where it is never
1657 /// worthwhile to replace it with a bitwise operation.
1658 virtual bool isFAbsFree(EVT VT) const {
1659 assert(VT.isFloatingPoint());
1663 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1664 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1665 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1667 /// NOTE: This may be called before legalization on types for which FMAs are
1668 /// not legal, but should return true if those types will eventually legalize
1669 /// to types that support FMAs. After legalization, it will only be called on
1670 /// types that support FMAs (via Legal or Custom actions)
1671 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1675 /// Return true if it's profitable to narrow operations of type VT1 to
1676 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1678 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1682 /// \brief Return true if it is beneficial to convert a load of a constant to
1683 /// just the constant itself.
1684 /// On some targets it might be more efficient to use a combination of
1685 /// arithmetic instructions to materialize the constant instead of loading it
1686 /// from a constant pool.
1687 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1692 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1693 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1694 /// has custom lowering that depends on the index of the first element,
1695 /// and only the target knows which lowering is cheap.
1696 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1700 //===--------------------------------------------------------------------===//
1701 // Runtime Library hooks
1704 /// Rename the default libcall routine name for the specified libcall.
1705 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1706 LibcallRoutineNames[Call] = Name;
1709 /// Get the libcall routine name for the specified libcall.
1710 const char *getLibcallName(RTLIB::Libcall Call) const {
1711 return LibcallRoutineNames[Call];
1714 /// Override the default CondCode to be used to test the result of the
1715 /// comparison libcall against zero.
1716 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1717 CmpLibcallCCs[Call] = CC;
1720 /// Get the CondCode that's to be used to test the result of the comparison
1721 /// libcall against zero.
1722 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1723 return CmpLibcallCCs[Call];
1726 /// Set the CallingConv that should be used for the specified libcall.
1727 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1728 LibcallCallingConvs[Call] = CC;
1731 /// Get the CallingConv that should be used for the specified libcall.
1732 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1733 return LibcallCallingConvs[Call];
1737 const TargetMachine &TM;
1739 /// Tells the code generator not to expand operations into sequences that use
1740 /// the select operations if possible.
1741 bool SelectIsExpensive;
1743 /// Tells the code generator that the target has multiple (allocatable)
1744 /// condition registers that can be used to store the results of comparisons
1745 /// for use by selects and conditional branches. With multiple condition
1746 /// registers, the code generator will not aggressively sink comparisons into
1747 /// the blocks of their users.
1748 bool HasMultipleConditionRegisters;
1750 /// Tells the code generator that the target has BitExtract instructions.
1751 /// The code generator will aggressively sink "shift"s into the blocks of
1752 /// their users if the users will generate "and" instructions which can be
1753 /// combined with "shift" to BitExtract instructions.
1754 bool HasExtractBitsInsn;
1756 /// Tells the code generator not to expand integer divides by constants into a
1757 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1758 /// model is in place. If we ever optimize for size, this will be set to true
1759 /// unconditionally.
1762 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1765 /// Tells the code generator to bypass slow divide or remainder
1766 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1767 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1768 /// div/rem when the operands are positive and less than 256.
1769 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1771 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1772 /// signed divide by power of two; let the target handle it.
1773 bool Pow2SDivIsCheap;
1775 /// Tells the code generator that it shouldn't generate extra flow control
1776 /// instructions and should attempt to combine flow control instructions via
1778 bool JumpIsExpensive;
1780 /// Whether the target supports or cares about preserving floating point
1781 /// exception behavior.
1782 bool HasFloatingPointExceptions;
1784 /// This target prefers to use _setjmp to implement llvm.setjmp.
1786 /// Defaults to false.
1787 bool UseUnderscoreSetJmp;
1789 /// This target prefers to use _longjmp to implement llvm.longjmp.
1791 /// Defaults to false.
1792 bool UseUnderscoreLongJmp;
1794 /// Number of blocks threshold to use jump tables.
1795 int MinimumJumpTableEntries;
1797 /// Information about the contents of the high-bits in boolean values held in
1798 /// a type wider than i1. See getBooleanContents.
1799 BooleanContent BooleanContents;
1801 /// Information about the contents of the high-bits in boolean values held in
1802 /// a type wider than i1. See getBooleanContents.
1803 BooleanContent BooleanFloatContents;
1805 /// Information about the contents of the high-bits in boolean vector values
1806 /// when the element type is wider than i1. See getBooleanContents.
1807 BooleanContent BooleanVectorContents;
1809 /// The target scheduling preference: shortest possible total cycles or lowest
1811 Sched::Preference SchedPreferenceInfo;
1813 /// The size, in bytes, of the target's jmp_buf buffers
1814 unsigned JumpBufSize;
1816 /// The alignment, in bytes, of the target's jmp_buf buffers
1817 unsigned JumpBufAlignment;
1819 /// The minimum alignment that any argument on the stack needs to have.
1820 unsigned MinStackArgumentAlignment;
1822 /// The minimum function alignment (used when optimizing for size, and to
1823 /// prevent explicitly provided alignment from leading to incorrect code).
1824 unsigned MinFunctionAlignment;
1826 /// The preferred function alignment (used when alignment unspecified and
1827 /// optimizing for speed).
1828 unsigned PrefFunctionAlignment;
1830 /// The preferred loop alignment.
1831 unsigned PrefLoopAlignment;
1833 /// Whether the DAG builder should automatically insert fences and reduce
1834 /// ordering for atomics. (This will be set for for most architectures with
1835 /// weak memory ordering.)
1836 bool InsertFencesForAtomic;
1838 /// If set to a physical register, this specifies the register that
1839 /// llvm.savestack/llvm.restorestack should save and restore.
1840 unsigned StackPointerRegisterToSaveRestore;
1842 /// If set to a physical register, this specifies the register that receives
1843 /// the exception address on entry to a landing pad.
1844 unsigned ExceptionPointerRegister;
1846 /// If set to a physical register, this specifies the register that receives
1847 /// the exception typeid on entry to a landing pad.
1848 unsigned ExceptionSelectorRegister;
1850 /// This indicates the default register class to use for each ValueType the
1851 /// target supports natively.
1852 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1853 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1854 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1856 /// This indicates the "representative" register class to use for each
1857 /// ValueType the target supports natively. This information is used by the
1858 /// scheduler to track register pressure. By default, the representative
1859 /// register class is the largest legal super-reg register class of the
1860 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1861 /// representative class would be GR32.
1862 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1864 /// This indicates the "cost" of the "representative" register class for each
1865 /// ValueType. The cost is used by the scheduler to approximate register
1867 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1869 /// For any value types we are promoting or expanding, this contains the value
1870 /// type that we are changing to. For Expanded types, this contains one step
1871 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1872 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1873 /// the same type (e.g. i32 -> i32).
1874 MVT TransformToType[MVT::LAST_VALUETYPE];
1876 /// For each operation and each value type, keep a LegalizeAction that
1877 /// indicates how instruction selection should deal with the operation. Most
1878 /// operations are Legal (aka, supported natively by the target), but
1879 /// operations that are not should be described. Note that operations on
1880 /// non-legal value types are not described here.
1881 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1883 /// For each load extension type and each value type, keep a LegalizeAction
1884 /// that indicates how instruction selection should deal with a load of a
1885 /// specific value type and extension type.
1886 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1887 [ISD::LAST_LOADEXT_TYPE];
1889 /// For each value type pair keep a LegalizeAction that indicates whether a
1890 /// truncating store of a specific value type and truncating type is legal.
1891 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1893 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1894 /// that indicates how instruction selection should deal with the load /
1897 /// The first dimension is the value_type for the reference. The second
1898 /// dimension represents the various modes for load store.
1899 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1901 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1902 /// indicates how instruction selection should deal with the condition code.
1904 /// Because each CC action takes up 2 bits, we need to have the array size be
1905 /// large enough to fit all of the value types. This can be done by rounding
1906 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1907 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1909 ValueTypeActionImpl ValueTypeActions;
1912 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1915 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1917 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1918 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1921 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1923 /// For operations that must be promoted to a specific type, this holds the
1924 /// destination type. This map should be sparse, so don't hold it as an
1927 /// Targets add entries to this map with AddPromotedToType(..), clients access
1928 /// this with getTypeToPromoteTo(..).
1929 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1932 /// Stores the name each libcall.
1933 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1935 /// The ISD::CondCode that should be used to test the result of each of the
1936 /// comparison libcall against zero.
1937 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1939 /// Stores the CallingConv that should be used for each libcall.
1940 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1943 /// Return true if the extension represented by \p I is free.
1944 /// \pre \p I is a sign, zero, or fp extension and
1945 /// is[Z|FP]ExtFree of the related types is not true.
1946 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1948 /// \brief Specify maximum number of store instructions per memset call.
1950 /// When lowering \@llvm.memset this field specifies the maximum number of
1951 /// store operations that may be substituted for the call to memset. Targets
1952 /// must set this value based on the cost threshold for that target. Targets
1953 /// should assume that the memset will be done using as many of the largest
1954 /// store operations first, followed by smaller ones, if necessary, per
1955 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1956 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1957 /// store. This only applies to setting a constant array of a constant size.
1958 unsigned MaxStoresPerMemset;
1960 /// Maximum number of stores operations that may be substituted for the call
1961 /// to memset, used for functions with OptSize attribute.
1962 unsigned MaxStoresPerMemsetOptSize;
1964 /// \brief Specify maximum bytes of store instructions per memcpy call.
1966 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1967 /// store operations that may be substituted for a call to memcpy. Targets
1968 /// must set this value based on the cost threshold for that target. Targets
1969 /// should assume that the memcpy will be done using as many of the largest
1970 /// store operations first, followed by smaller ones, if necessary, per
1971 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1972 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1973 /// and one 1-byte store. This only applies to copying a constant array of
1975 unsigned MaxStoresPerMemcpy;
1977 /// Maximum number of store operations that may be substituted for a call to
1978 /// memcpy, used for functions with OptSize attribute.
1979 unsigned MaxStoresPerMemcpyOptSize;
1981 /// \brief Specify maximum bytes of store instructions per memmove call.
1983 /// When lowering \@llvm.memmove this field specifies the maximum number of
1984 /// store instructions that may be substituted for a call to memmove. Targets
1985 /// must set this value based on the cost threshold for that target. Targets
1986 /// should assume that the memmove will be done using as many of the largest
1987 /// store operations first, followed by smaller ones, if necessary, per
1988 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1989 /// with 8-bit alignment would result in nine 1-byte stores. This only
1990 /// applies to copying a constant array of constant size.
1991 unsigned MaxStoresPerMemmove;
1993 /// Maximum number of store instructions that may be substituted for a call to
1994 /// memmove, used for functions with OpSize attribute.
1995 unsigned MaxStoresPerMemmoveOptSize;
1997 /// Tells the code generator that select is more expensive than a branch if
1998 /// the branch is usually predicted right.
1999 bool PredictableSelectIsExpensive;
2001 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
2002 /// a mask of a single bit, a compare, and a branch into a single instruction.
2003 bool MaskAndBranchFoldingIsLegal;
2005 /// \see enableExtLdPromotion.
2006 bool EnableExtLdPromotion;
2009 /// Return true if the value types that can be represented by the specified
2010 /// register class are all legal.
2011 bool isLegalRC(const TargetRegisterClass *RC) const;
2013 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2014 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2015 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
2016 MachineBasicBlock *MBB) const;
2019 /// This class defines information used to lower LLVM code to legal SelectionDAG
2020 /// operators that the target instruction selector can accept natively.
2022 /// This class also defines callbacks that targets must implement to lower
2023 /// target-specific constructs to SelectionDAG operators.
2024 class TargetLowering : public TargetLoweringBase {
2025 TargetLowering(const TargetLowering&) = delete;
2026 void operator=(const TargetLowering&) = delete;
2029 /// NOTE: The TargetMachine owns TLOF.
2030 explicit TargetLowering(const TargetMachine &TM);
2032 /// Returns true by value, base pointer and offset pointer and addressing mode
2033 /// by reference if the node's address can be legally represented as
2034 /// pre-indexed load / store address.
2035 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2036 SDValue &/*Offset*/,
2037 ISD::MemIndexedMode &/*AM*/,
2038 SelectionDAG &/*DAG*/) const {
2042 /// Returns true by value, base pointer and offset pointer and addressing mode
2043 /// by reference if this node can be combined with a load / store to form a
2044 /// post-indexed load / store.
2045 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2047 SDValue &/*Offset*/,
2048 ISD::MemIndexedMode &/*AM*/,
2049 SelectionDAG &/*DAG*/) const {
2053 /// Return the entry encoding for a jump table in the current function. The
2054 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2055 virtual unsigned getJumpTableEncoding() const;
2057 virtual const MCExpr *
2058 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2059 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2060 MCContext &/*Ctx*/) const {
2061 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2064 /// Returns relocation base for the given PIC jumptable.
2065 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2066 SelectionDAG &DAG) const;
2068 /// This returns the relocation base for the given PIC jumptable, the same as
2069 /// getPICJumpTableRelocBase, but as an MCExpr.
2070 virtual const MCExpr *
2071 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2072 unsigned JTI, MCContext &Ctx) const;
2074 /// Return true if folding a constant offset with the given GlobalAddress is
2075 /// legal. It is frequently not legal in PIC relocation models.
2076 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2078 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2079 SDValue &Chain) const;
2081 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2082 SDValue &NewLHS, SDValue &NewRHS,
2083 ISD::CondCode &CCCode, SDLoc DL) const;
2085 /// Returns a pair of (return value, chain).
2086 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2087 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2088 EVT RetVT, const SDValue *Ops,
2089 unsigned NumOps, bool isSigned,
2090 SDLoc dl, bool doesNotReturn = false,
2091 bool isReturnValueUsed = true) const;
2093 //===--------------------------------------------------------------------===//
2094 // TargetLowering Optimization Methods
2097 /// A convenience struct that encapsulates a DAG, and two SDValues for
2098 /// returning information from TargetLowering to its clients that want to
2100 struct TargetLoweringOpt {
2107 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2109 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2111 bool LegalTypes() const { return LegalTys; }
2112 bool LegalOperations() const { return LegalOps; }
2114 bool CombineTo(SDValue O, SDValue N) {
2120 /// Check to see if the specified operand of the specified instruction is a
2121 /// constant integer. If so, check to see if there are any bits set in the
2122 /// constant that are not demanded. If so, shrink the constant and return
2124 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2126 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2127 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2128 /// generalized for targets with other types of implicit widening casts.
2129 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2133 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2134 /// result of Op are ever used downstream. If we can use this information to
2135 /// simplify Op, create a new simplified DAG node and return true, returning
2136 /// the original and new nodes in Old and New. Otherwise, analyze the
2137 /// expression and return a mask of KnownOne and KnownZero bits for the
2138 /// expression (used to simplify the caller). The KnownZero/One bits may only
2139 /// be accurate for those bits in the DemandedMask.
2140 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2141 APInt &KnownZero, APInt &KnownOne,
2142 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2144 /// Determine which of the bits specified in Mask are known to be either zero
2145 /// or one and return them in the KnownZero/KnownOne bitsets.
2146 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2149 const SelectionDAG &DAG,
2150 unsigned Depth = 0) const;
2152 /// This method can be implemented by targets that want to expose additional
2153 /// information about sign bits to the DAG Combiner.
2154 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2155 const SelectionDAG &DAG,
2156 unsigned Depth = 0) const;
2158 struct DAGCombinerInfo {
2159 void *DC; // The DAG Combiner object.
2161 bool CalledByLegalizer;
2165 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2166 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2168 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2169 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2170 bool isAfterLegalizeVectorOps() const {
2171 return Level == AfterLegalizeDAG;
2173 CombineLevel getDAGCombineLevel() { return Level; }
2174 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2176 void AddToWorklist(SDNode *N);
2177 void RemoveFromWorklist(SDNode *N);
2178 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2179 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2180 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2182 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2185 /// Return if the N is a constant or constant vector equal to the true value
2186 /// from getBooleanContents().
2187 bool isConstTrueVal(const SDNode *N) const;
2189 /// Return if the N is a constant or constant vector equal to the false value
2190 /// from getBooleanContents().
2191 bool isConstFalseVal(const SDNode *N) const;
2193 /// Try to simplify a setcc built with the specified operands and cc. If it is
2194 /// unable to simplify it, return a null SDValue.
2195 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2196 ISD::CondCode Cond, bool foldBooleans,
2197 DAGCombinerInfo &DCI, SDLoc dl) const;
2199 /// Returns true (and the GlobalValue and the offset) if the node is a
2200 /// GlobalAddress + offset.
2202 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2204 /// This method will be invoked for all target nodes and for any
2205 /// target-independent nodes that the target has registered with invoke it
2208 /// The semantics are as follows:
2210 /// SDValue.Val == 0 - No change was made
2211 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2212 /// otherwise - N should be replaced by the returned Operand.
2214 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2215 /// more complex transformations.
2217 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2219 /// Return true if it is profitable to move a following shift through this
2220 // node, adjusting any immediate operands as necessary to preserve semantics.
2221 // This transformation may not be desirable if it disrupts a particularly
2222 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2223 // By default, it returns true.
2224 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2228 /// Return true if the target has native support for the specified value type
2229 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2230 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2231 /// and some i16 instructions are slow.
2232 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2233 // By default, assume all legal types are desirable.
2234 return isTypeLegal(VT);
2237 /// Return true if it is profitable for dag combiner to transform a floating
2238 /// point op of specified opcode to a equivalent op of an integer
2239 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2240 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2245 /// This method query the target whether it is beneficial for dag combiner to
2246 /// promote the specified node. If true, it should return the desired
2247 /// promotion type by reference.
2248 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2252 //===--------------------------------------------------------------------===//
2253 // Lowering methods - These methods must be implemented by targets so that
2254 // the SelectionDAGBuilder code knows how to lower these.
2257 /// This hook must be implemented to lower the incoming (formal) arguments,
2258 /// described by the Ins array, into the specified DAG. The implementation
2259 /// should fill in the InVals array with legal-type argument values, and
2260 /// return the resulting token chain value.
2263 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2265 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2266 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2267 SmallVectorImpl<SDValue> &/*InVals*/) const {
2268 llvm_unreachable("Not Implemented");
2271 struct ArgListEntry {
2280 bool isInAlloca : 1;
2281 bool isReturned : 1;
2284 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2285 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2286 isReturned(false), Alignment(0) { }
2288 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2290 typedef std::vector<ArgListEntry> ArgListTy;
2292 /// This structure contains all information that is necessary for lowering
2293 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2294 /// needs to lower a call, and targets will see this struct in their LowerCall
2296 struct CallLoweringInfo {
2303 bool DoesNotReturn : 1;
2304 bool IsReturnValueUsed : 1;
2306 // IsTailCall should be modified by implementations of
2307 // TargetLowering::LowerCall that perform tail call conversions.
2310 unsigned NumFixedArgs;
2311 CallingConv::ID CallConv;
2316 ImmutableCallSite *CS;
2318 SmallVector<ISD::OutputArg, 32> Outs;
2319 SmallVector<SDValue, 32> OutVals;
2320 SmallVector<ISD::InputArg, 32> Ins;
2322 CallLoweringInfo(SelectionDAG &DAG)
2323 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2324 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2325 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2326 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2328 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2333 CallLoweringInfo &setChain(SDValue InChain) {
2338 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2339 SDValue Target, ArgListTy &&ArgsList,
2340 unsigned FixedArgs = -1) {
2345 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2346 Args = std::move(ArgsList);
2350 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2351 SDValue Target, ArgListTy &&ArgsList,
2352 ImmutableCallSite &Call) {
2355 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2356 DoesNotReturn = Call.doesNotReturn();
2357 IsVarArg = FTy->isVarArg();
2358 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2359 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2360 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2364 CallConv = Call.getCallingConv();
2365 NumFixedArgs = FTy->getNumParams();
2366 Args = std::move(ArgsList);
2373 CallLoweringInfo &setInRegister(bool Value = true) {
2378 CallLoweringInfo &setNoReturn(bool Value = true) {
2379 DoesNotReturn = Value;
2383 CallLoweringInfo &setVarArg(bool Value = true) {
2388 CallLoweringInfo &setTailCall(bool Value = true) {
2393 CallLoweringInfo &setDiscardResult(bool Value = true) {
2394 IsReturnValueUsed = !Value;
2398 CallLoweringInfo &setSExtResult(bool Value = true) {
2403 CallLoweringInfo &setZExtResult(bool Value = true) {
2408 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2409 IsPatchPoint = Value;
2413 ArgListTy &getArgs() {
2419 /// This function lowers an abstract call to a function into an actual call.
2420 /// This returns a pair of operands. The first element is the return value
2421 /// for the function (if RetTy is not VoidTy). The second element is the
2422 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2423 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2425 /// This hook must be implemented to lower calls into the specified
2426 /// DAG. The outgoing arguments to the call are described by the Outs array,
2427 /// and the values to be returned by the call are described by the Ins
2428 /// array. The implementation should fill in the InVals array with legal-type
2429 /// return values from the call, and return the resulting token chain value.
2431 LowerCall(CallLoweringInfo &/*CLI*/,
2432 SmallVectorImpl<SDValue> &/*InVals*/) const {
2433 llvm_unreachable("Not Implemented");
2436 /// Target-specific cleanup for formal ByVal parameters.
2437 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2439 /// This hook should be implemented to check whether the return values
2440 /// described by the Outs array can fit into the return registers. If false
2441 /// is returned, an sret-demotion is performed.
2442 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2443 MachineFunction &/*MF*/, bool /*isVarArg*/,
2444 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2445 LLVMContext &/*Context*/) const
2447 // Return true by default to get preexisting behavior.
2451 /// This hook must be implemented to lower outgoing return values, described
2452 /// by the Outs array, into the specified DAG. The implementation should
2453 /// return the resulting token chain value.
2455 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2457 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2458 const SmallVectorImpl<SDValue> &/*OutVals*/,
2459 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2460 llvm_unreachable("Not Implemented");
2463 /// Return true if result of the specified node is used by a return node
2464 /// only. It also compute and return the input chain for the tail call.
2466 /// This is used to determine whether it is possible to codegen a libcall as
2467 /// tail call at legalization time.
2468 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2472 /// Return true if the target may be able emit the call instruction as a tail
2473 /// call. This is used by optimization passes to determine if it's profitable
2474 /// to duplicate return instructions to enable tailcall optimization.
2475 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2479 /// Return the builtin name for the __builtin___clear_cache intrinsic
2480 /// Default is to invoke the clear cache library call
2481 virtual const char * getClearCacheBuiltinName() const {
2482 return "__clear_cache";
2485 /// Return the register ID of the name passed in. Used by named register
2486 /// global variables extension. There is no target-independent behaviour
2487 /// so the default action is to bail.
2488 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2489 report_fatal_error("Named registers not implemented for this target");
2492 /// Return the type that should be used to zero or sign extend a
2493 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2494 /// convention requires the return type to be promoted, but this is not true
2495 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2496 /// calling conventions. The frontend should handle this and include all of
2497 /// the necessary information.
2498 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2499 ISD::NodeType /*ExtendKind*/) const {
2500 EVT MinVT = getRegisterType(Context, MVT::i32);
2501 return VT.bitsLT(MinVT) ? MinVT : VT;
2504 /// For some targets, an LLVM struct type must be broken down into multiple
2505 /// simple types, but the calling convention specifies that the entire struct
2506 /// must be passed in a block of consecutive registers.
2508 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2509 bool isVarArg) const {
2513 /// Returns a 0 terminated array of registers that can be safely used as
2514 /// scratch registers.
2515 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2519 /// This callback is used to prepare for a volatile or atomic load.
2520 /// It takes a chain node as input and returns the chain for the load itself.
2522 /// Having a callback like this is necessary for targets like SystemZ,
2523 /// which allows a CPU to reuse the result of a previous load indefinitely,
2524 /// even if a cache-coherent store is performed by another CPU. The default
2525 /// implementation does nothing.
2526 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2527 SelectionDAG &DAG) const {
2531 /// This callback is invoked by the type legalizer to legalize nodes with an
2532 /// illegal operand type but legal result types. It replaces the
2533 /// LowerOperation callback in the type Legalizer. The reason we can not do
2534 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2535 /// use this callback.
2537 /// TODO: Consider merging with ReplaceNodeResults.
2539 /// The target places new result values for the node in Results (their number
2540 /// and types must exactly match those of the original return values of
2541 /// the node), or leaves Results empty, which indicates that the node is not
2542 /// to be custom lowered after all.
2543 /// The default implementation calls LowerOperation.
2544 virtual void LowerOperationWrapper(SDNode *N,
2545 SmallVectorImpl<SDValue> &Results,
2546 SelectionDAG &DAG) const;
2548 /// This callback is invoked for operations that are unsupported by the
2549 /// target, which are registered to use 'custom' lowering, and whose defined
2550 /// values are all legal. If the target has no operations that require custom
2551 /// lowering, it need not implement this. The default implementation of this
2553 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2555 /// This callback is invoked when a node result type is illegal for the
2556 /// target, and the operation was registered to use 'custom' lowering for that
2557 /// result type. The target places new result values for the node in Results
2558 /// (their number and types must exactly match those of the original return
2559 /// values of the node), or leaves Results empty, which indicates that the
2560 /// node is not to be custom lowered after all.
2562 /// If the target has no operations that require custom lowering, it need not
2563 /// implement this. The default implementation aborts.
2564 virtual void ReplaceNodeResults(SDNode * /*N*/,
2565 SmallVectorImpl<SDValue> &/*Results*/,
2566 SelectionDAG &/*DAG*/) const {
2567 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2570 /// This method returns the name of a target specific DAG node.
2571 virtual const char *getTargetNodeName(unsigned Opcode) const;
2573 /// This method returns a target specific FastISel object, or null if the
2574 /// target does not support "fast" ISel.
2575 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2576 const TargetLibraryInfo *) const {
2581 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2582 SelectionDAG &DAG) const;
2584 //===--------------------------------------------------------------------===//
2585 // Inline Asm Support hooks
2588 /// This hook allows the target to expand an inline asm call to be explicit
2589 /// llvm code if it wants to. This is useful for turning simple inline asms
2590 /// into LLVM intrinsics, which gives the compiler more information about the
2591 /// behavior of the code.
2592 virtual bool ExpandInlineAsm(CallInst *) const {
2596 enum ConstraintType {
2597 C_Register, // Constraint represents specific register(s).
2598 C_RegisterClass, // Constraint represents any of register(s) in class.
2599 C_Memory, // Memory constraint.
2600 C_Other, // Something else.
2601 C_Unknown // Unsupported constraint.
2604 enum ConstraintWeight {
2606 CW_Invalid = -1, // No match.
2607 CW_Okay = 0, // Acceptable.
2608 CW_Good = 1, // Good weight.
2609 CW_Better = 2, // Better weight.
2610 CW_Best = 3, // Best weight.
2612 // Well-known weights.
2613 CW_SpecificReg = CW_Okay, // Specific register operands.
2614 CW_Register = CW_Good, // Register operands.
2615 CW_Memory = CW_Better, // Memory operands.
2616 CW_Constant = CW_Best, // Constant operand.
2617 CW_Default = CW_Okay // Default or don't know type.
2620 /// This contains information for each constraint that we are lowering.
2621 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2622 /// This contains the actual string for the code, like "m". TargetLowering
2623 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2624 /// matches the operand.
2625 std::string ConstraintCode;
2627 /// Information about the constraint code, e.g. Register, RegisterClass,
2628 /// Memory, Other, Unknown.
2629 TargetLowering::ConstraintType ConstraintType;
2631 /// If this is the result output operand or a clobber, this is null,
2632 /// otherwise it is the incoming operand to the CallInst. This gets
2633 /// modified as the asm is processed.
2634 Value *CallOperandVal;
2636 /// The ValueType for the operand value.
2639 /// Return true of this is an input operand that is a matching constraint
2641 bool isMatchingInputConstraint() const;
2643 /// If this is an input matching constraint, this method returns the output
2644 /// operand it matches.
2645 unsigned getMatchedOperand() const;
2647 /// Copy constructor for copying from a ConstraintInfo.
2648 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2649 : InlineAsm::ConstraintInfo(std::move(Info)),
2650 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2651 ConstraintVT(MVT::Other) {}
2654 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2656 /// Split up the constraint string from the inline assembly value into the
2657 /// specific constraints and their prefixes, and also tie in the associated
2658 /// operand values. If this returns an empty vector, and if the constraint
2659 /// string itself isn't empty, there was an error parsing.
2660 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2661 const TargetRegisterInfo *TRI,
2662 ImmutableCallSite CS) const;
2664 /// Examine constraint type and operand type and determine a weight value.
2665 /// The operand object must already have been set up with the operand type.
2666 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2667 AsmOperandInfo &info, int maIndex) const;
2669 /// Examine constraint string and operand type and determine a weight value.
2670 /// The operand object must already have been set up with the operand type.
2671 virtual ConstraintWeight getSingleConstraintMatchWeight(
2672 AsmOperandInfo &info, const char *constraint) const;
2674 /// Determines the constraint code and constraint type to use for the specific
2675 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2676 /// If the actual operand being passed in is available, it can be passed in as
2677 /// Op, otherwise an empty SDValue can be passed.
2678 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2680 SelectionDAG *DAG = nullptr) const;
2682 /// Given a constraint, return the type of constraint it is for this target.
2683 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2685 /// Given a physical register constraint (e.g. {edx}), return the register
2686 /// number and the register class for the register.
2688 /// Given a register class constraint, like 'r', if this corresponds directly
2689 /// to an LLVM register class, return a register of 0 and the register class
2692 /// This should only be used for C_Register constraints. On error, this
2693 /// returns a register number of 0 and a null register class pointer.
2694 virtual std::pair<unsigned, const TargetRegisterClass *>
2695 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2696 StringRef Constraint, MVT VT) const;
2698 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2699 if (ConstraintCode == "i")
2700 return InlineAsm::Constraint_i;
2701 else if (ConstraintCode == "m")
2702 return InlineAsm::Constraint_m;
2703 return InlineAsm::Constraint_Unknown;
2706 /// Try to replace an X constraint, which matches anything, with another that
2707 /// has more specific requirements based on the type of the corresponding
2708 /// operand. This returns null if there is no replacement to make.
2709 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2711 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2712 /// add anything to Ops.
2713 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2714 std::vector<SDValue> &Ops,
2715 SelectionDAG &DAG) const;
2717 //===--------------------------------------------------------------------===//
2718 // Div utility functions
2720 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2721 bool IsAfterLegalization,
2722 std::vector<SDNode *> *Created) const;
2723 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2724 bool IsAfterLegalization,
2725 std::vector<SDNode *> *Created) const;
2726 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2728 std::vector<SDNode *> *Created) const {
2732 /// Indicate whether this target prefers to combine the given number of FDIVs
2733 /// with the same divisor.
2734 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2738 /// Hooks for building estimates in place of slower divisions and square
2741 /// Return a reciprocal square root estimate value for the input operand.
2742 /// The RefinementSteps output is the number of Newton-Raphson refinement
2743 /// iterations required to generate a sufficient (though not necessarily
2744 /// IEEE-754 compliant) estimate for the value type.
2745 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2746 /// algorithm implementation that uses one constant or two constants.
2747 /// A target may choose to implement its own refinement within this function.
2748 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2749 /// any further refinement of the estimate.
2750 /// An empty SDValue return means no estimate sequence can be created.
2751 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2752 unsigned &RefinementSteps,
2753 bool &UseOneConstNR) const {
2757 /// Return a reciprocal estimate value for the input operand.
2758 /// The RefinementSteps output is the number of Newton-Raphson refinement
2759 /// iterations required to generate a sufficient (though not necessarily
2760 /// IEEE-754 compliant) estimate for the value type.
2761 /// A target may choose to implement its own refinement within this function.
2762 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2763 /// any further refinement of the estimate.
2764 /// An empty SDValue return means no estimate sequence can be created.
2765 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2766 unsigned &RefinementSteps) const {
2770 //===--------------------------------------------------------------------===//
2771 // Legalization utility functions
2774 /// Expand a MUL into two nodes. One that computes the high bits of
2775 /// the result and one that computes the low bits.
2776 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2777 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2778 /// if you want to control how low bits are extracted from the LHS.
2779 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2780 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2781 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2782 /// \returns true if the node has been expanded. false if it has not
2783 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2784 SelectionDAG &DAG, SDValue LL = SDValue(),
2785 SDValue LH = SDValue(), SDValue RL = SDValue(),
2786 SDValue RH = SDValue()) const;
2788 /// Expand float(f32) to SINT(i64) conversion
2789 /// \param N Node to expand
2790 /// \param Result output after conversion
2791 /// \returns True, if the expansion was successful, false otherwise
2792 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2794 //===--------------------------------------------------------------------===//
2795 // Instruction Emitting Hooks
2798 /// This method should be implemented by targets that mark instructions with
2799 /// the 'usesCustomInserter' flag. These instructions are special in various
2800 /// ways, which require special support to insert. The specified MachineInstr
2801 /// is created but not inserted into any basic blocks, and this method is
2802 /// called to expand it into a sequence of instructions, potentially also
2803 /// creating new basic blocks and control flow.
2804 /// As long as the returned basic block is different (i.e., we created a new
2805 /// one), the custom inserter is free to modify the rest of \p MBB.
2806 virtual MachineBasicBlock *
2807 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2809 /// This method should be implemented by targets that mark instructions with
2810 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2811 /// instruction selection by target hooks. e.g. To fill in optional defs for
2812 /// ARM 's' setting instructions.
2814 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2816 /// If this function returns true, SelectionDAGBuilder emits a
2817 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2818 virtual bool useLoadStackGuardNode() const {
2823 /// Given an LLVM IR type and return type attributes, compute the return value
2824 /// EVTs and flags, and optionally also the offsets, if the return value is
2825 /// being lowered to memory.
2826 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
2827 SmallVectorImpl<ISD::OutputArg> &Outs,
2828 const TargetLowering &TLI, const DataLayout &DL);
2830 } // end llvm namespace