1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 class TargetRegisterClass;
39 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData *getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
94 /// isSelectExpensive - Return true if the select operation is expensive for
96 bool isSelectExpensive() const { return SelectIsExpensive; }
98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
99 /// a sequence of several shifts, adds, and multiplies for this target.
100 bool isIntDivCheap() const { return IntDivIsCheap; }
102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
104 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
110 /// getSetCCResultContents - For targets without boolean registers, this flag
111 /// returns information about the contents of the high-bits in the setcc
113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
115 /// getSchedulingPreference - Return target scheduling preference.
116 SchedPreference getSchedulingPreference() const {
117 return SchedPreferenceInfo;
120 /// getRegClassFor - Return the register class that should be used for the
121 /// specified value type. This may only be called on legal types.
122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
123 TargetRegisterClass *RC = RegClassForVT[VT];
124 assert(RC && "This value type is not natively supported!");
128 /// isTypeLegal - Return true if the target has native support for the
129 /// specified value type. This means that it has a register that directly
130 /// holds it without promotions or expansions.
131 bool isTypeLegal(MVT::ValueType VT) const {
132 return RegClassForVT[VT] != 0;
135 class ValueTypeActionImpl {
136 /// ValueTypeActions - This is a bitvector that contains two bits for each
137 /// value type, where the two bits correspond to the LegalizeAction enum.
138 /// This can be queried with "getTypeAction(VT)".
139 uint32_t ValueTypeActions[2];
141 ValueTypeActionImpl() {
142 ValueTypeActions[0] = ValueTypeActions[1] = 0;
144 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
145 ValueTypeActions[0] = RHS.ValueTypeActions[0];
146 ValueTypeActions[1] = RHS.ValueTypeActions[1];
149 LegalizeAction getTypeAction(MVT::ValueType VT) const {
150 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
152 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
153 assert(unsigned(VT >> 4) <
154 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
155 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
159 const ValueTypeActionImpl &getValueTypeActions() const {
160 return ValueTypeActions;
163 /// getTypeAction - Return how we should legalize values of this type, either
164 /// it is already legal (return 'Legal') or we need to promote it to a larger
165 /// type (return 'Promote'), or we need to expand it into multiple registers
166 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
167 LegalizeAction getTypeAction(MVT::ValueType VT) const {
168 return ValueTypeActions.getTypeAction(VT);
171 /// getTypeToTransformTo - For types supported by the target, this is an
172 /// identity function. For types that must be promoted to larger types, this
173 /// returns the larger type to promote to. For integer types that are larger
174 /// than the largest integer register, this contains one step in the expansion
175 /// to get to the smaller register. For illegal floating point types, this
176 /// returns the integer type to transform to.
177 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
178 return TransformToType[VT];
181 /// getTypeToExpandTo - For types supported by the target, this is an
182 /// identity function. For types that must be expanded (i.e. integer types
183 /// that are larger than the largest integer register or illegal floating
184 /// point types), this returns the largest legal type it will be expanded to.
185 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
187 switch (getTypeAction(VT)) {
191 VT = TransformToType[VT];
194 assert(false && "Type is not legal nor is it to be expanded!");
201 /// getVectorTypeBreakdown - Vector types are broken down into some number of
202 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
203 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
204 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
206 /// This method returns the number of registers needed, and the VT for each
207 /// register. It also returns the VT of the VectorType elements before they
208 /// are promoted/expanded.
210 unsigned getVectorTypeBreakdown(const VectorType *PTy,
211 MVT::ValueType &PTyElementVT,
212 MVT::ValueType &PTyLegalElementVT) const;
214 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
215 legal_fpimm_iterator legal_fpimm_begin() const {
216 return LegalFPImmediates.begin();
218 legal_fpimm_iterator legal_fpimm_end() const {
219 return LegalFPImmediates.end();
222 /// isShuffleMaskLegal - Targets can use this to indicate that they only
223 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
224 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
225 /// are assumed to be legal.
226 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
230 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
231 /// used by Targets can use this to indicate if there is a suitable
232 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
234 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
236 SelectionDAG &DAG) const {
240 /// getOperationAction - Return how this operation should be treated: either
241 /// it is legal, needs to be promoted to a larger size, needs to be
242 /// expanded to some other code sequence, or the target has a custom expander
244 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
245 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
248 /// isOperationLegal - Return true if the specified operation is legal on this
250 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
251 return getOperationAction(Op, VT) == Legal ||
252 getOperationAction(Op, VT) == Custom;
255 /// getLoadXAction - Return how this load with extension should be treated:
256 /// either it is legal, needs to be promoted to a larger size, needs to be
257 /// expanded to some other code sequence, or the target has a custom expander
259 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
260 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
263 /// isLoadXLegal - Return true if the specified load with extension is legal
265 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
266 return getLoadXAction(LType, VT) == Legal ||
267 getLoadXAction(LType, VT) == Custom;
270 /// getStoreXAction - Return how this store with truncation should be treated:
271 /// either it is legal, needs to be promoted to a larger size, needs to be
272 /// expanded to some other code sequence, or the target has a custom expander
274 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
275 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
278 /// isStoreXLegal - Return true if the specified store with truncation is
279 /// legal on this target.
280 bool isStoreXLegal(MVT::ValueType VT) const {
281 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
284 /// getIndexedLoadAction - Return how the indexed load should be treated:
285 /// either it is legal, needs to be promoted to a larger size, needs to be
286 /// expanded to some other code sequence, or the target has a custom expander
289 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
290 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
293 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
295 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
296 return getIndexedLoadAction(IdxMode, VT) == Legal ||
297 getIndexedLoadAction(IdxMode, VT) == Custom;
300 /// getIndexedStoreAction - Return how the indexed store should be treated:
301 /// either it is legal, needs to be promoted to a larger size, needs to be
302 /// expanded to some other code sequence, or the target has a custom expander
305 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
306 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
309 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
311 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
312 return getIndexedStoreAction(IdxMode, VT) == Legal ||
313 getIndexedStoreAction(IdxMode, VT) == Custom;
316 /// getTypeToPromoteTo - If the action for this operation is to promote, this
317 /// method returns the ValueType to promote to.
318 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
319 assert(getOperationAction(Op, VT) == Promote &&
320 "This operation isn't promoted!");
322 // See if this has an explicit type specified.
323 std::map<std::pair<unsigned, MVT::ValueType>,
324 MVT::ValueType>::const_iterator PTTI =
325 PromoteToType.find(std::make_pair(Op, VT));
326 if (PTTI != PromoteToType.end()) return PTTI->second;
328 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
329 "Cannot autopromote this type, add it with AddPromotedToType.");
331 MVT::ValueType NVT = VT;
333 NVT = (MVT::ValueType)(NVT+1);
334 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
335 "Didn't find type to promote to!");
336 } while (!isTypeLegal(NVT) ||
337 getOperationAction(Op, NVT) == Promote);
341 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
342 /// This is fixed by the LLVM operations except for the pointer size.
343 MVT::ValueType getValueType(const Type *Ty) const {
344 MVT::ValueType VT = MVT::getValueType(Ty);
345 return VT == MVT::iPTR ? PointerTy : VT;
348 /// getNumElements - Return the number of registers that this ValueType will
349 /// eventually require. This is one for any types promoted to live in larger
350 /// registers, but may be more than one for types (like i64) that are split
352 unsigned getNumElements(MVT::ValueType VT) const {
353 return NumElementsForVT[VT];
356 /// hasTargetDAGCombine - If true, the target has custom DAG combine
357 /// transformations that it can perform for the specified node.
358 bool hasTargetDAGCombine(ISD::NodeType NT) const {
359 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
362 /// This function returns the maximum number of store operations permitted
363 /// to replace a call to llvm.memset. The value is set by the target at the
364 /// performance threshold for such a replacement.
365 /// @brief Get maximum # of store operations permitted for llvm.memset
366 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
368 /// This function returns the maximum number of store operations permitted
369 /// to replace a call to llvm.memcpy. The value is set by the target at the
370 /// performance threshold for such a replacement.
371 /// @brief Get maximum # of store operations permitted for llvm.memcpy
372 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
374 /// This function returns the maximum number of store operations permitted
375 /// to replace a call to llvm.memmove. The value is set by the target at the
376 /// performance threshold for such a replacement.
377 /// @brief Get maximum # of store operations permitted for llvm.memmove
378 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
380 /// This function returns true if the target allows unaligned memory accesses.
381 /// This is used, for example, in situations where an array copy/move/set is
382 /// converted to a sequence of store operations. It's use helps to ensure that
383 /// such replacements don't generate code that causes an alignment error
384 /// (trap) on the target machine.
385 /// @brief Determine if the target supports unaligned memory accesses.
386 bool allowsUnalignedMemoryAccesses() const {
387 return allowUnalignedMemoryAccesses;
390 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
391 /// to implement llvm.setjmp.
392 bool usesUnderscoreSetJmp() const {
393 return UseUnderscoreSetJmp;
396 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
397 /// to implement llvm.longjmp.
398 bool usesUnderscoreLongJmp() const {
399 return UseUnderscoreLongJmp;
402 /// getStackPointerRegisterToSaveRestore - If a physical register, this
403 /// specifies the register that llvm.savestack/llvm.restorestack should save
405 unsigned getStackPointerRegisterToSaveRestore() const {
406 return StackPointerRegisterToSaveRestore;
409 /// getExceptionAddressRegister - If a physical register, this returns
410 /// the register that receives the exception address on entry to a landing
412 unsigned getExceptionAddressRegister() const {
413 return ExceptionPointerRegister;
416 /// getExceptionSelectorRegister - If a physical register, this returns
417 /// the register that receives the exception typeid on entry to a landing
419 unsigned getExceptionSelectorRegister() const {
420 return ExceptionSelectorRegister;
423 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
424 /// set, the default is 200)
425 unsigned getJumpBufSize() const {
429 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
430 /// (if never set, the default is 0)
431 unsigned getJumpBufAlignment() const {
432 return JumpBufAlignment;
435 /// getPreIndexedAddressParts - returns true by value, base pointer and
436 /// offset pointer and addressing mode by reference if the node's address
437 /// can be legally represented as pre-indexed load / store address.
438 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
440 ISD::MemIndexedMode &AM,
445 /// getPostIndexedAddressParts - returns true by value, base pointer and
446 /// offset pointer and addressing mode by reference if this node can be
447 /// combined with a load / store to form a post-indexed load / store.
448 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
449 SDOperand &Base, SDOperand &Offset,
450 ISD::MemIndexedMode &AM,
455 //===--------------------------------------------------------------------===//
456 // TargetLowering Optimization Methods
459 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
460 /// SDOperands for returning information from TargetLowering to its clients
461 /// that want to combine
462 struct TargetLoweringOpt {
467 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
469 bool CombineTo(SDOperand O, SDOperand N) {
475 /// ShrinkDemandedConstant - Check to see if the specified operand of the
476 /// specified instruction is a constant integer. If so, check to see if there
477 /// are any bits set in the constant that are not demanded. If so, shrink the
478 /// constant and return true.
479 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
482 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
483 /// use this predicate to simplify operations downstream. Op and Mask are
484 /// known to be the same type.
485 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
488 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
489 /// known to be either zero or one and return them in the KnownZero/KnownOne
490 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
491 /// processing. Targets can implement the computeMaskedBitsForTargetNode
492 /// method, to allow target nodes to be understood.
493 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
494 uint64_t &KnownOne, unsigned Depth = 0) const;
496 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
497 /// DemandedMask bits of the result of Op are ever used downstream. If we can
498 /// use this information to simplify Op, create a new simplified DAG node and
499 /// return true, returning the original and new nodes in Old and New.
500 /// Otherwise, analyze the expression and return a mask of KnownOne and
501 /// KnownZero bits for the expression (used to simplify the caller).
502 /// The KnownZero/One bits may only be accurate for those bits in the
504 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
505 uint64_t &KnownZero, uint64_t &KnownOne,
506 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
508 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
509 /// Mask are known to be either zero or one and return them in the
510 /// KnownZero/KnownOne bitsets.
511 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
515 unsigned Depth = 0) const;
517 /// ComputeNumSignBits - Return the number of times the sign bit of the
518 /// register is replicated into the other bits. We know that at least 1 bit
519 /// is always equal to the sign bit (itself), but other cases can give us
520 /// information. For example, immediately after an "SRA X, 2", we know that
521 /// the top 3 bits are all equal to each other, so we return 3.
522 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
524 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
525 /// targets that want to expose additional information about sign bits to the
527 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
528 unsigned Depth = 0) const;
530 struct DAGCombinerInfo {
531 void *DC; // The DAG Combiner object.
533 bool CalledByLegalizer;
537 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
538 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
540 bool isBeforeLegalize() const { return BeforeLegalize; }
541 bool isCalledByLegalizer() const { return CalledByLegalizer; }
543 void AddToWorklist(SDNode *N);
544 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
545 SDOperand CombineTo(SDNode *N, SDOperand Res);
546 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
549 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
550 /// and cc. If it is unable to simplify it, return a null SDOperand.
551 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
552 ISD::CondCode Cond, bool foldBooleans,
553 DAGCombinerInfo &DCI) const;
555 /// PerformDAGCombine - This method will be invoked for all target nodes and
556 /// for any target-independent nodes that the target has registered with
559 /// The semantics are as follows:
561 /// SDOperand.Val == 0 - No change was made
562 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
563 /// otherwise - N should be replaced by the returned Operand.
565 /// In addition, methods provided by DAGCombinerInfo may be used to perform
566 /// more complex transformations.
568 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
570 //===--------------------------------------------------------------------===//
571 // TargetLowering Configuration Methods - These methods should be invoked by
572 // the derived class constructor to configure this object for the target.
576 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
577 /// GOT for PC-relative code.
578 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
580 /// setShiftAmountType - Describe the type that should be used for shift
581 /// amounts. This type defaults to the pointer type.
582 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
584 /// setSetCCResultType - Describe the type that shoudl be used as the result
585 /// of a setcc operation. This defaults to the pointer type.
586 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
588 /// setSetCCResultContents - Specify how the target extends the result of a
589 /// setcc operation in a register.
590 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
592 /// setSchedulingPreference - Specify the target scheduling preference.
593 void setSchedulingPreference(SchedPreference Pref) {
594 SchedPreferenceInfo = Pref;
597 /// setShiftAmountFlavor - Describe how the target handles out of range shift
599 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
600 ShiftAmtHandling = OORSA;
603 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
604 /// use _setjmp to implement llvm.setjmp or the non _ version.
605 /// Defaults to false.
606 void setUseUnderscoreSetJmp(bool Val) {
607 UseUnderscoreSetJmp = Val;
610 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
611 /// use _longjmp to implement llvm.longjmp or the non _ version.
612 /// Defaults to false.
613 void setUseUnderscoreLongJmp(bool Val) {
614 UseUnderscoreLongJmp = Val;
617 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
618 /// specifies the register that llvm.savestack/llvm.restorestack should save
620 void setStackPointerRegisterToSaveRestore(unsigned R) {
621 StackPointerRegisterToSaveRestore = R;
624 /// setExceptionPointerRegister - If set to a physical register, this sets
625 /// the register that receives the exception address on entry to a landing
627 void setExceptionPointerRegister(unsigned R) {
628 ExceptionPointerRegister = R;
631 /// setExceptionSelectorRegister - If set to a physical register, this sets
632 /// the register that receives the exception typeid on entry to a landing
634 void setExceptionSelectorRegister(unsigned R) {
635 ExceptionSelectorRegister = R;
638 /// SelectIsExpensive - Tells the code generator not to expand operations
639 /// into sequences that use the select operations if possible.
640 void setSelectIsExpensive() { SelectIsExpensive = true; }
642 /// setIntDivIsCheap - Tells the code generator that integer divide is
643 /// expensive, and if possible, should be replaced by an alternate sequence
644 /// of instructions not containing an integer divide.
645 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
647 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
648 /// srl/add/sra for a signed divide by power of two, and let the target handle
650 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
652 /// addRegisterClass - Add the specified register class as an available
653 /// regclass for the specified value type. This indicates the selector can
654 /// handle values of that class natively.
655 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
656 AvailableRegClasses.push_back(std::make_pair(VT, RC));
657 RegClassForVT[VT] = RC;
660 /// computeRegisterProperties - Once all of the register classes are added,
661 /// this allows us to compute derived properties we expose.
662 void computeRegisterProperties();
664 /// setOperationAction - Indicate that the specified operation does not work
665 /// with the specified type and indicate what to do about it.
666 void setOperationAction(unsigned Op, MVT::ValueType VT,
667 LegalizeAction Action) {
668 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
669 "Table isn't big enough!");
670 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
671 OpActions[Op] |= (uint64_t)Action << VT*2;
674 /// setLoadXAction - Indicate that the specified load with extension does not
675 /// work with the with specified type and indicate what to do about it.
676 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
677 LegalizeAction Action) {
678 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
679 "Table isn't big enough!");
680 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
681 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
684 /// setStoreXAction - Indicate that the specified store with truncation does
685 /// not work with the with specified type and indicate what to do about it.
686 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
687 assert(VT < 32 && "Table isn't big enough!");
688 StoreXActions &= ~(uint64_t(3UL) << VT*2);
689 StoreXActions |= (uint64_t)Action << VT*2;
692 /// setIndexedLoadAction - Indicate that the specified indexed load does or
693 /// does not work with the with specified type and indicate what to do abort
694 /// it. NOTE: All indexed mode loads are initialized to Expand in
695 /// TargetLowering.cpp
696 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
697 LegalizeAction Action) {
698 assert(VT < 32 && IdxMode <
699 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) &&
700 "Table isn't big enough!");
701 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
702 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
705 /// setIndexedStoreAction - Indicate that the specified indexed store does or
706 /// does not work with the with specified type and indicate what to do about
707 /// it. NOTE: All indexed mode stores are initialized to Expand in
708 /// TargetLowering.cpp
709 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
710 LegalizeAction Action) {
711 assert(VT < 32 && IdxMode <
712 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) &&
713 "Table isn't big enough!");
714 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
715 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
718 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
719 /// promotion code defaults to trying a larger integer/fp until it can find
720 /// one that works. If that default is insufficient, this method can be used
721 /// by the target to override the default.
722 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
723 MVT::ValueType DestVT) {
724 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
727 /// addLegalFPImmediate - Indicate that this target can instruction select
728 /// the specified FP immediate natively.
729 void addLegalFPImmediate(double Imm) {
730 LegalFPImmediates.push_back(Imm);
733 /// setTargetDAGCombine - Targets should invoke this method for each target
734 /// independent node that they want to provide a custom DAG combiner for by
735 /// implementing the PerformDAGCombine virtual method.
736 void setTargetDAGCombine(ISD::NodeType NT) {
737 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
740 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
741 /// bytes); default is 200
742 void setJumpBufSize(unsigned Size) {
746 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
747 /// alignment (in bytes); default is 0
748 void setJumpBufAlignment(unsigned Align) {
749 JumpBufAlignment = Align;
754 //===--------------------------------------------------------------------===//
755 // Lowering methods - These methods must be implemented by targets so that
756 // the SelectionDAGLowering code knows how to lower these.
759 /// LowerArguments - This hook must be implemented to indicate how we should
760 /// lower the arguments for the specified function, into the specified DAG.
761 virtual std::vector<SDOperand>
762 LowerArguments(Function &F, SelectionDAG &DAG);
764 /// LowerCallTo - This hook lowers an abstract call to a function into an
765 /// actual call. This returns a pair of operands. The first element is the
766 /// return value for the function (if RetTy is not VoidTy). The second
767 /// element is the outgoing token chain.
768 struct ArgListEntry {
776 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { };
778 typedef std::vector<ArgListEntry> ArgListTy;
779 virtual std::pair<SDOperand, SDOperand>
780 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
781 bool isVarArg, unsigned CallingConv, bool isTailCall,
782 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
784 /// LowerOperation - This callback is invoked for operations that are
785 /// unsupported by the target, which are registered to use 'custom' lowering,
786 /// and whose defined values are all legal.
787 /// If the target has no operations that require custom lowering, it need not
788 /// implement this. The default implementation of this aborts.
789 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
791 /// CustomPromoteOperation - This callback is invoked for operations that are
792 /// unsupported by the target, are registered to use 'custom' lowering, and
793 /// whose type needs to be promoted.
794 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
796 /// getTargetNodeName() - This method returns the name of a target specific
798 virtual const char *getTargetNodeName(unsigned Opcode) const;
800 //===--------------------------------------------------------------------===//
801 // Inline Asm Support hooks
804 enum ConstraintType {
805 C_Register, // Constraint represents a single register.
806 C_RegisterClass, // Constraint represents one or more registers.
807 C_Memory, // Memory constraint.
808 C_Other, // Something else.
809 C_Unknown // Unsupported constraint.
812 /// getConstraintType - Given a constraint, return the type of constraint it
813 /// is for this target.
814 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
817 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
818 /// return a list of registers that can be used to satisfy the constraint.
819 /// This should only be used for C_RegisterClass constraints.
820 virtual std::vector<unsigned>
821 getRegClassForInlineAsmConstraint(const std::string &Constraint,
822 MVT::ValueType VT) const;
824 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
825 /// {edx}), return the register number and the register class for the
828 /// Given a register class constraint, like 'r', if this corresponds directly
829 /// to an LLVM register class, return a register of 0 and the register class
832 /// This should only be used for C_Register constraints. On error,
833 /// this returns a register number of 0 and a null register class pointer..
834 virtual std::pair<unsigned, const TargetRegisterClass*>
835 getRegForInlineAsmConstraint(const std::string &Constraint,
836 MVT::ValueType VT) const;
839 /// isOperandValidForConstraint - Return the specified operand (possibly
840 /// modified) if the specified SDOperand is valid for the specified target
841 /// constraint letter, otherwise return null.
843 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
846 //===--------------------------------------------------------------------===//
850 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
851 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
852 // instructions are special in various ways, which require special support to
853 // insert. The specified MachineInstr is created but not inserted into any
854 // basic blocks, and the scheduler passes ownership of it to this method.
855 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
856 MachineBasicBlock *MBB);
858 //===--------------------------------------------------------------------===//
859 // Addressing mode description hooks (used by LSR etc).
862 /// AddrMode - This represents an addressing mode of:
863 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
864 /// If BaseGV is null, there is no BaseGV.
865 /// If BaseOffs is zero, there is no base offset.
866 /// If HasBaseReg is false, there is no base register.
867 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
875 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
878 /// isLegalAddressingMode - Return true if the addressing mode represented by
879 /// AM is legal for this target, for a load/store of the specified type.
880 /// TODO: Handle pre/postinc as well.
881 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
883 //===--------------------------------------------------------------------===//
884 // Div utility functions
886 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
887 std::vector<SDNode*>* Created) const;
888 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
889 std::vector<SDNode*>* Created) const;
892 //===--------------------------------------------------------------------===//
893 // Runtime Library hooks
896 /// setLibcallName - Rename the default libcall routine name for the specified
898 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
899 LibcallRoutineNames[Call] = Name;
902 /// getLibcallName - Get the libcall routine name for the specified libcall.
904 const char *getLibcallName(RTLIB::Libcall Call) const {
905 return LibcallRoutineNames[Call];
908 /// setCmpLibcallCC - Override the default CondCode to be used to test the
909 /// result of the comparison libcall against zero.
910 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
911 CmpLibcallCCs[Call] = CC;
914 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
915 /// the comparison libcall against zero.
916 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
917 return CmpLibcallCCs[Call];
922 const TargetData *TD;
924 /// IsLittleEndian - True if this is a little endian target.
928 /// PointerTy - The type to use for pointers, usually i32 or i64.
930 MVT::ValueType PointerTy;
932 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
934 bool UsesGlobalOffsetTable;
936 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
938 MVT::ValueType ShiftAmountTy;
940 OutOfRangeShiftAmount ShiftAmtHandling;
942 /// SelectIsExpensive - Tells the code generator not to expand operations
943 /// into sequences that use the select operations if possible.
944 bool SelectIsExpensive;
946 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
947 /// constants into a sequence of muls, adds, and shifts. This is a hack until
948 /// a real cost model is in place. If we ever optimize for size, this will be
949 /// set to true unconditionally.
952 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
953 /// srl/add/sra for a signed divide by power of two, and let the target handle
957 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
959 MVT::ValueType SetCCResultTy;
961 /// SetCCResultContents - Information about the contents of the high-bits in
962 /// the result of a setcc comparison operation.
963 SetCCResultValue SetCCResultContents;
965 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
966 /// total cycles or lowest register usage.
967 SchedPreference SchedPreferenceInfo;
969 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
970 /// llvm.setjmp. Defaults to false.
971 bool UseUnderscoreSetJmp;
973 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
974 /// llvm.longjmp. Defaults to false.
975 bool UseUnderscoreLongJmp;
977 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
978 unsigned JumpBufSize;
980 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
982 unsigned JumpBufAlignment;
984 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
985 /// specifies the register that llvm.savestack/llvm.restorestack should save
987 unsigned StackPointerRegisterToSaveRestore;
989 /// ExceptionPointerRegister - If set to a physical register, this specifies
990 /// the register that receives the exception address on entry to a landing
992 unsigned ExceptionPointerRegister;
994 /// ExceptionSelectorRegister - If set to a physical register, this specifies
995 /// the register that receives the exception typeid on entry to a landing
997 unsigned ExceptionSelectorRegister;
999 /// RegClassForVT - This indicates the default register class to use for
1000 /// each ValueType the target supports natively.
1001 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1002 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
1004 /// TransformToType - For any value types we are promoting or expanding, this
1005 /// contains the value type that we are changing to. For Expanded types, this
1006 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1007 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1008 /// by the system, this holds the same type (e.g. i32 -> i32).
1009 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1011 /// OpActions - For each operation and each value type, keep a LegalizeAction
1012 /// that indicates how instruction selection should deal with the operation.
1013 /// Most operations are Legal (aka, supported natively by the target), but
1014 /// operations that are not should be described. Note that operations on
1015 /// non-legal value types are not described here.
1016 uint64_t OpActions[156];
1018 /// LoadXActions - For each load of load extension type and each value type,
1019 /// keep a LegalizeAction that indicates how instruction selection should deal
1021 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1023 /// StoreXActions - For each store with truncation of each value type, keep a
1024 /// LegalizeAction that indicates how instruction selection should deal with
1026 uint64_t StoreXActions;
1028 /// IndexedModeActions - For each indexed mode and each value type, keep a
1029 /// pair of LegalizeAction that indicates how instruction selection should
1030 /// deal with the load / store.
1031 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1033 ValueTypeActionImpl ValueTypeActions;
1035 std::vector<double> LegalFPImmediates;
1037 std::vector<std::pair<MVT::ValueType,
1038 TargetRegisterClass*> > AvailableRegClasses;
1040 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1041 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1042 /// which sets a bit in this array.
1043 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1045 /// PromoteToType - For operations that must be promoted to a specific type,
1046 /// this holds the destination type. This map should be sparse, so don't hold
1049 /// Targets add entries to this map with AddPromotedToType(..), clients access
1050 /// this with getTypeToPromoteTo(..).
1051 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1053 /// LibcallRoutineNames - Stores the name each libcall.
1055 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1057 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1058 /// of each of the comparison libcall against zero.
1059 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1062 /// When lowering %llvm.memset this field specifies the maximum number of
1063 /// store operations that may be substituted for the call to memset. Targets
1064 /// must set this value based on the cost threshold for that target. Targets
1065 /// should assume that the memset will be done using as many of the largest
1066 /// store operations first, followed by smaller ones, if necessary, per
1067 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1068 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1069 /// store. This only applies to setting a constant array of a constant size.
1070 /// @brief Specify maximum number of store instructions per memset call.
1071 unsigned maxStoresPerMemset;
1073 /// When lowering %llvm.memcpy this field specifies the maximum number of
1074 /// store operations that may be substituted for a call to memcpy. Targets
1075 /// must set this value based on the cost threshold for that target. Targets
1076 /// should assume that the memcpy will be done using as many of the largest
1077 /// store operations first, followed by smaller ones, if necessary, per
1078 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1079 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1080 /// and one 1-byte store. This only applies to copying a constant array of
1082 /// @brief Specify maximum bytes of store instructions per memcpy call.
1083 unsigned maxStoresPerMemcpy;
1085 /// When lowering %llvm.memmove this field specifies the maximum number of
1086 /// store instructions that may be substituted for a call to memmove. Targets
1087 /// must set this value based on the cost threshold for that target. Targets
1088 /// should assume that the memmove will be done using as many of the largest
1089 /// store operations first, followed by smaller ones, if necessary, per
1090 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1091 /// with 8-bit alignment would result in nine 1-byte stores. This only
1092 /// applies to copying a constant array of constant size.
1093 /// @brief Specify maximum bytes of store instructions per memmove call.
1094 unsigned maxStoresPerMemmove;
1096 /// This field specifies whether the target machine permits unaligned memory
1097 /// accesses. This is used, for example, to determine the size of store
1098 /// operations when copying small arrays and other similar tasks.
1099 /// @brief Indicate whether the target permits unaligned memory accesses.
1100 bool allowUnalignedMemoryAccesses;
1102 } // end llvm namespace