1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineModuleInfo;
56 class TargetRegisterClass;
57 class TargetSubtarget;
58 class TargetLoweringObjectFile;
61 // FIXME: should this be here?
70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
73 //===----------------------------------------------------------------------===//
74 /// TargetLowering - This class defines information used to lower LLVM code to
75 /// legal SelectionDAG operators that the target instruction selector can accept
78 /// This class also defines callbacks that targets must implement to lower
79 /// target-specific constructs to SelectionDAG operators.
81 class TargetLowering {
82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
85 /// LegalizeAction - This enum indicates whether operations are valid for a
86 /// target, and if not, what action should be used to make them valid.
88 Legal, // The target natively supports this operation.
89 Promote, // This operation should be executed in a larger type.
90 Expand, // Try to expand this to other ops, otherwise use a libcall.
91 Custom // Use the LowerOperation hook to implement custom lowering.
94 enum BooleanContent { // How the target represents true/false values.
95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
96 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
100 enum SchedPreference {
101 SchedulingForLatency, // Scheduling for shortest total latency.
102 SchedulingForRegPressure // Scheduling for lowest register pressure.
105 /// NOTE: The constructor takes ownership of TLOF.
106 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
107 virtual ~TargetLowering();
109 TargetMachine &getTargetMachine() const { return TM; }
110 const TargetData *getTargetData() const { return TD; }
111 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
113 bool isBigEndian() const { return !IsLittleEndian; }
114 bool isLittleEndian() const { return IsLittleEndian; }
115 MVT getPointerTy() const { return PointerTy; }
116 MVT getShiftAmountTy() const { return ShiftAmountTy; }
118 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
120 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
122 /// isSelectExpensive - Return true if the select operation is expensive for
124 bool isSelectExpensive() const { return SelectIsExpensive; }
126 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
127 /// a sequence of several shifts, adds, and multiplies for this target.
128 bool isIntDivCheap() const { return IntDivIsCheap; }
130 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
132 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
134 /// getSetCCResultType - Return the ValueType of the result of SETCC
135 /// operations. Also used to obtain the target's preferred type for
136 /// the condition operand of SELECT and BRCOND nodes. In the case of
137 /// BRCOND the argument passed is MVT::Other since there are no other
138 /// operands to get a type hint from.
140 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
142 /// getBooleanContents - For targets without i1 registers, this gives the
143 /// nature of the high-bits of boolean values held in types wider than i1.
144 /// "Boolean values" are special true/false values produced by nodes like
145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
146 /// Not to be confused with general values promoted from i1.
147 BooleanContent getBooleanContents() const { return BooleanContents;}
149 /// getSchedulingPreference - Return target scheduling preference.
150 SchedPreference getSchedulingPreference() const {
151 return SchedPreferenceInfo;
154 /// getRegClassFor - Return the register class that should be used for the
155 /// specified value type. This may only be called on legal types.
156 TargetRegisterClass *getRegClassFor(EVT VT) const {
157 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
159 assert(RC && "This value type is not natively supported!");
163 /// isTypeLegal - Return true if the target has native support for the
164 /// specified value type. This means that it has a register that directly
165 /// holds it without promotions or expansions.
166 bool isTypeLegal(EVT VT) const {
167 assert(!VT.isSimple() ||
168 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
172 class ValueTypeActionImpl {
173 /// ValueTypeActions - This is a bitvector that contains two bits for each
174 /// value type, where the two bits correspond to the LegalizeAction enum.
175 /// This can be queried with "getTypeAction(VT)".
176 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
177 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
179 ValueTypeActionImpl() {
180 ValueTypeActions[0] = ValueTypeActions[1] = 0;
181 ValueTypeActions[2] = ValueTypeActions[3] = 0;
183 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
184 ValueTypeActions[0] = RHS.ValueTypeActions[0];
185 ValueTypeActions[1] = RHS.ValueTypeActions[1];
186 ValueTypeActions[2] = RHS.ValueTypeActions[2];
187 ValueTypeActions[3] = RHS.ValueTypeActions[3];
190 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
191 if (VT.isExtended()) {
193 return VT.isPow2VectorType() ? Expand : Promote;
196 // First promote to a power-of-two size, then expand if necessary.
197 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
198 assert(0 && "Unsupported extended type!");
201 unsigned I = VT.getSimpleVT().SimpleTy;
202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
203 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
205 void setTypeAction(EVT VT, LegalizeAction Action) {
206 unsigned I = VT.getSimpleVT().SimpleTy;
207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
208 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
212 const ValueTypeActionImpl &getValueTypeActions() const {
213 return ValueTypeActions;
216 /// getTypeAction - Return how we should legalize values of this type, either
217 /// it is already legal (return 'Legal') or we need to promote it to a larger
218 /// type (return 'Promote'), or we need to expand it into multiple registers
219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
220 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
221 return ValueTypeActions.getTypeAction(Context, VT);
224 /// getTypeToTransformTo - For types supported by the target, this is an
225 /// identity function. For types that must be promoted to larger types, this
226 /// returns the larger type to promote to. For integer types that are larger
227 /// than the largest integer register, this contains one step in the expansion
228 /// to get to the smaller register. For illegal floating point types, this
229 /// returns the integer type to transform to.
230 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
232 assert((unsigned)VT.getSimpleVT().SimpleTy <
233 array_lengthof(TransformToType));
234 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
235 assert(getTypeAction(Context, NVT) != Promote &&
236 "Promote may not follow Expand or Promote");
241 EVT NVT = VT.getPow2VectorType(Context);
243 // Vector length is a power of 2 - split to half the size.
244 unsigned NumElts = VT.getVectorNumElements();
245 EVT EltVT = VT.getVectorElementType();
246 return (NumElts == 1) ?
247 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
249 // Promote to a power of two size, avoiding multi-step promotion.
250 return getTypeAction(Context, NVT) == Promote ?
251 getTypeToTransformTo(Context, NVT) : NVT;
252 } else if (VT.isInteger()) {
253 EVT NVT = VT.getRoundIntegerType(Context);
255 // Size is a power of two - expand to half the size.
256 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
258 // Promote to a power of two size, avoiding multi-step promotion.
259 return getTypeAction(Context, NVT) == Promote ?
260 getTypeToTransformTo(Context, NVT) : NVT;
262 assert(0 && "Unsupported extended type!");
263 return MVT(MVT::Other); // Not reached
266 /// getTypeToExpandTo - For types supported by the target, this is an
267 /// identity function. For types that must be expanded (i.e. integer types
268 /// that are larger than the largest integer register or illegal floating
269 /// point types), this returns the largest legal type it will be expanded to.
270 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
271 assert(!VT.isVector());
273 switch (getTypeAction(Context, VT)) {
277 VT = getTypeToTransformTo(Context, VT);
280 assert(false && "Type is not legal nor is it to be expanded!");
287 /// getVectorTypeBreakdown - Vector types are broken down into some number of
288 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
289 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
290 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
292 /// This method returns the number of registers needed, and the VT for each
293 /// register. It also returns the VT and quantity of the intermediate values
294 /// before they are promoted/expanded.
296 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
298 unsigned &NumIntermediates,
299 EVT &RegisterVT) const;
301 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
302 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
303 /// this is the case, it returns true and store the intrinsic
304 /// information into the IntrinsicInfo that was passed to the function.
305 typedef struct IntrinsicInfo {
306 unsigned opc; // target opcode
307 EVT memVT; // memory VT
308 const Value* ptrVal; // value representing memory location
309 int offset; // offset off of ptrVal
310 unsigned align; // alignment
311 bool vol; // is volatile?
312 bool readMem; // reads memory?
313 bool writeMem; // writes memory?
316 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
317 CallInst &I, unsigned Intrinsic) {
321 /// getWidenVectorType: given a vector type, returns the type to widen to
322 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
323 /// If there is no vector type that we want to widen to, returns MVT::Other
324 /// When and were to widen is target dependent based on the cost of
325 /// scalarizing vs using the wider vector type.
326 virtual EVT getWidenVectorType(EVT VT) const;
328 /// isFPImmLegal - Returns true if the target can instruction select the
329 /// specified FP immediate natively. If false, the legalizer will materialize
330 /// the FP immediate as a load from a constant pool.
331 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
335 /// isShuffleMaskLegal - Targets can use this to indicate that they only
336 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
337 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
338 /// are assumed to be legal.
339 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
344 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
345 /// used by Targets can use this to indicate if there is a suitable
346 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
348 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
353 /// getOperationAction - Return how this operation should be treated: either
354 /// it is legal, needs to be promoted to a larger size, needs to be
355 /// expanded to some other code sequence, or the target has a custom expander
357 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
358 if (VT.isExtended()) return Expand;
359 assert(Op < array_lengthof(OpActions[0]) &&
360 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
361 "Table isn't big enough!");
362 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
365 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
368 /// isOperationLegalOrCustom - Return true if the specified operation is
369 /// legal on this target or can be made legal with custom lowering. This
370 /// is used to help guide high-level lowering decisions.
371 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
372 return (VT == MVT::Other || isTypeLegal(VT)) &&
373 (getOperationAction(Op, VT) == Legal ||
374 getOperationAction(Op, VT) == Custom);
377 /// isOperationLegal - Return true if the specified operation is legal on this
379 bool isOperationLegal(unsigned Op, EVT VT) const {
380 return (VT == MVT::Other || isTypeLegal(VT)) &&
381 getOperationAction(Op, VT) == Legal;
384 /// getLoadExtAction - Return how this load with extension should be treated:
385 /// either it is legal, needs to be promoted to a larger size, needs to be
386 /// expanded to some other code sequence, or the target has a custom expander
388 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
389 assert(LType < array_lengthof(LoadExtActions) &&
390 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
391 "Table isn't big enough!");
392 return (LegalizeAction)((LoadExtActions[LType] >>
393 (2*VT.getSimpleVT().SimpleTy)) & 3);
396 /// isLoadExtLegal - Return true if the specified load with extension is legal
398 bool isLoadExtLegal(unsigned LType, EVT VT) const {
399 return VT.isSimple() &&
400 (getLoadExtAction(LType, VT) == Legal ||
401 getLoadExtAction(LType, VT) == Custom);
404 /// getTruncStoreAction - Return how this store with truncation should be
405 /// treated: either it is legal, needs to be promoted to a larger size, needs
406 /// to be expanded to some other code sequence, or the target has a custom
408 LegalizeAction getTruncStoreAction(EVT ValVT,
410 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
411 array_lengthof(TruncStoreActions) &&
412 (unsigned)MemVT.getSimpleVT().SimpleTy <
413 sizeof(TruncStoreActions[0])*4 &&
414 "Table isn't big enough!");
415 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
416 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
419 /// isTruncStoreLegal - Return true if the specified store with truncation is
420 /// legal on this target.
421 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
422 return isTypeLegal(ValVT) && MemVT.isSimple() &&
423 (getTruncStoreAction(ValVT, MemVT) == Legal ||
424 getTruncStoreAction(ValVT, MemVT) == Custom);
427 /// getIndexedLoadAction - Return how the indexed load should be treated:
428 /// either it is legal, needs to be promoted to a larger size, needs to be
429 /// expanded to some other code sequence, or the target has a custom expander
432 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
433 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
434 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
435 "Table isn't big enough!");
436 return (LegalizeAction)((IndexedModeActions[
437 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
440 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
442 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
443 return VT.isSimple() &&
444 (getIndexedLoadAction(IdxMode, VT) == Legal ||
445 getIndexedLoadAction(IdxMode, VT) == Custom);
448 /// getIndexedStoreAction - Return how the indexed store should be treated:
449 /// either it is legal, needs to be promoted to a larger size, needs to be
450 /// expanded to some other code sequence, or the target has a custom expander
453 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
454 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
455 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
456 "Table isn't big enough!");
457 return (LegalizeAction)((IndexedModeActions[
458 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
461 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
463 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
464 return VT.isSimple() &&
465 (getIndexedStoreAction(IdxMode, VT) == Legal ||
466 getIndexedStoreAction(IdxMode, VT) == Custom);
469 /// getConvertAction - Return how the conversion should be treated:
470 /// either it is legal, needs to be promoted to a larger size, needs to be
471 /// expanded to some other code sequence, or the target has a custom expander
474 getConvertAction(EVT FromVT, EVT ToVT) const {
475 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
476 array_lengthof(ConvertActions) &&
477 (unsigned)ToVT.getSimpleVT().SimpleTy <
478 sizeof(ConvertActions[0])*4 &&
479 "Table isn't big enough!");
480 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
481 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
484 /// isConvertLegal - Return true if the specified conversion is legal
486 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
487 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
488 (getConvertAction(FromVT, ToVT) == Legal ||
489 getConvertAction(FromVT, ToVT) == Custom);
492 /// getCondCodeAction - Return how the condition code should be treated:
493 /// either it is legal, needs to be expanded to some other code sequence,
494 /// or the target has a custom expander for it.
496 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
497 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
498 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
499 "Table isn't big enough!");
500 LegalizeAction Action = (LegalizeAction)
501 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
502 assert(Action != Promote && "Can't promote condition code!");
506 /// isCondCodeLegal - Return true if the specified condition code is legal
508 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
509 return getCondCodeAction(CC, VT) == Legal ||
510 getCondCodeAction(CC, VT) == Custom;
514 /// getTypeToPromoteTo - If the action for this operation is to promote, this
515 /// method returns the ValueType to promote to.
516 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
517 assert(getOperationAction(Op, VT) == Promote &&
518 "This operation isn't promoted!");
520 // See if this has an explicit type specified.
521 std::map<std::pair<unsigned, MVT::SimpleValueType>,
522 MVT::SimpleValueType>::const_iterator PTTI =
523 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
524 if (PTTI != PromoteToType.end()) return PTTI->second;
526 assert((VT.isInteger() || VT.isFloatingPoint()) &&
527 "Cannot autopromote this type, add it with AddPromotedToType.");
531 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
532 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
533 "Didn't find type to promote to!");
534 } while (!isTypeLegal(NVT) ||
535 getOperationAction(Op, NVT) == Promote);
539 /// getValueType - Return the EVT corresponding to this LLVM type.
540 /// This is fixed by the LLVM operations except for the pointer size. If
541 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
542 /// counterpart (e.g. structs), otherwise it will assert.
543 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
544 EVT VT = EVT::getEVT(Ty, AllowUnknown);
545 return VT == MVT:: iPTR ? PointerTy : VT;
548 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
549 /// function arguments in the caller parameter area. This is the actual
550 /// alignment, not its logarithm.
551 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
553 /// getRegisterType - Return the type of registers that this ValueType will
554 /// eventually require.
555 EVT getRegisterType(MVT VT) const {
556 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
557 return RegisterTypeForVT[VT.SimpleTy];
560 /// getRegisterType - Return the type of registers that this ValueType will
561 /// eventually require.
562 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
564 assert((unsigned)VT.getSimpleVT().SimpleTy <
565 array_lengthof(RegisterTypeForVT));
566 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
570 unsigned NumIntermediates;
571 (void)getVectorTypeBreakdown(Context, VT, VT1,
572 NumIntermediates, RegisterVT);
575 if (VT.isInteger()) {
576 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
578 assert(0 && "Unsupported extended type!");
579 return EVT(MVT::Other); // Not reached
582 /// getNumRegisters - Return the number of registers that this ValueType will
583 /// eventually require. This is one for any types promoted to live in larger
584 /// registers, but may be more than one for types (like i64) that are split
585 /// into pieces. For types like i140, which are first promoted then expanded,
586 /// it is the number of registers needed to hold all the bits of the original
587 /// type. For an i140 on a 32 bit machine this means 5 registers.
588 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
590 assert((unsigned)VT.getSimpleVT().SimpleTy <
591 array_lengthof(NumRegistersForVT));
592 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
596 unsigned NumIntermediates;
597 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
599 if (VT.isInteger()) {
600 unsigned BitWidth = VT.getSizeInBits();
601 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
602 return (BitWidth + RegWidth - 1) / RegWidth;
604 assert(0 && "Unsupported extended type!");
605 return 0; // Not reached
608 /// ShouldShrinkFPConstant - If true, then instruction selection should
609 /// seek to shrink the FP constant of the specified type to a smaller type
610 /// in order to save space and / or reduce runtime.
611 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
613 /// hasTargetDAGCombine - If true, the target has custom DAG combine
614 /// transformations that it can perform for the specified node.
615 bool hasTargetDAGCombine(ISD::NodeType NT) const {
616 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
617 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
620 /// This function returns the maximum number of store operations permitted
621 /// to replace a call to llvm.memset. The value is set by the target at the
622 /// performance threshold for such a replacement.
623 /// @brief Get maximum # of store operations permitted for llvm.memset
624 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
626 /// This function returns the maximum number of store operations permitted
627 /// to replace a call to llvm.memcpy. The value is set by the target at the
628 /// performance threshold for such a replacement.
629 /// @brief Get maximum # of store operations permitted for llvm.memcpy
630 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
632 /// This function returns the maximum number of store operations permitted
633 /// to replace a call to llvm.memmove. The value is set by the target at the
634 /// performance threshold for such a replacement.
635 /// @brief Get maximum # of store operations permitted for llvm.memmove
636 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
638 /// This function returns true if the target allows unaligned memory accesses.
639 /// of the specified type. This is used, for example, in situations where an
640 /// array copy/move/set is converted to a sequence of store operations. It's
641 /// use helps to ensure that such replacements don't generate code that causes
642 /// an alignment error (trap) on the target machine.
643 /// @brief Determine if the target supports unaligned memory accesses.
644 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
648 /// This function returns true if the target would benefit from code placement
650 /// @brief Determine if the target should perform code placement optimization.
651 bool shouldOptimizeCodePlacement() const {
652 return benefitFromCodePlacementOpt;
655 /// getOptimalMemOpType - Returns the target specific optimal type for load
656 /// and store operations as a result of memset, memcpy, and memmove lowering.
657 /// It returns EVT::iAny if SelectionDAG should be responsible for
659 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
660 bool isSrcConst, bool isSrcStr,
661 SelectionDAG &DAG) const {
665 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
666 /// to implement llvm.setjmp.
667 bool usesUnderscoreSetJmp() const {
668 return UseUnderscoreSetJmp;
671 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
672 /// to implement llvm.longjmp.
673 bool usesUnderscoreLongJmp() const {
674 return UseUnderscoreLongJmp;
677 /// getStackPointerRegisterToSaveRestore - If a physical register, this
678 /// specifies the register that llvm.savestack/llvm.restorestack should save
680 unsigned getStackPointerRegisterToSaveRestore() const {
681 return StackPointerRegisterToSaveRestore;
684 /// getExceptionAddressRegister - If a physical register, this returns
685 /// the register that receives the exception address on entry to a landing
687 unsigned getExceptionAddressRegister() const {
688 return ExceptionPointerRegister;
691 /// getExceptionSelectorRegister - If a physical register, this returns
692 /// the register that receives the exception typeid on entry to a landing
694 unsigned getExceptionSelectorRegister() const {
695 return ExceptionSelectorRegister;
698 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
699 /// set, the default is 200)
700 unsigned getJumpBufSize() const {
704 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
705 /// (if never set, the default is 0)
706 unsigned getJumpBufAlignment() const {
707 return JumpBufAlignment;
710 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
711 /// limit. Any block whose size is greater should not be predicated.
712 unsigned getIfCvtBlockSizeLimit() const {
713 return IfCvtBlockSizeLimit;
716 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
717 /// block to be considered for duplication. Any block whose size is greater
718 /// should not be duplicated to facilitate its predication.
719 unsigned getIfCvtDupBlockSizeLimit() const {
720 return IfCvtDupBlockSizeLimit;
723 /// getPrefLoopAlignment - return the preferred loop alignment.
725 unsigned getPrefLoopAlignment() const {
726 return PrefLoopAlignment;
729 /// getPreIndexedAddressParts - returns true by value, base pointer and
730 /// offset pointer and addressing mode by reference if the node's address
731 /// can be legally represented as pre-indexed load / store address.
732 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
734 ISD::MemIndexedMode &AM,
735 SelectionDAG &DAG) const {
739 /// getPostIndexedAddressParts - returns true by value, base pointer and
740 /// offset pointer and addressing mode by reference if this node can be
741 /// combined with a load / store to form a post-indexed load / store.
742 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
743 SDValue &Base, SDValue &Offset,
744 ISD::MemIndexedMode &AM,
745 SelectionDAG &DAG) const {
749 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
751 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
752 SelectionDAG &DAG) const;
754 /// isOffsetFoldingLegal - Return true if folding a constant offset
755 /// with the given GlobalAddress is legal. It is frequently not legal in
756 /// PIC relocation models.
757 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
759 /// getFunctionAlignment - Return the Log2 alignment of this function.
760 virtual unsigned getFunctionAlignment(const Function *) const = 0;
762 //===--------------------------------------------------------------------===//
763 // TargetLowering Optimization Methods
766 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
767 /// SDValues for returning information from TargetLowering to its clients
768 /// that want to combine
769 struct TargetLoweringOpt {
774 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
776 bool CombineTo(SDValue O, SDValue N) {
782 /// ShrinkDemandedConstant - Check to see if the specified operand of the
783 /// specified instruction is a constant integer. If so, check to see if
784 /// there are any bits set in the constant that are not demanded. If so,
785 /// shrink the constant and return true.
786 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
788 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
789 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
790 /// cast, but it could be generalized for targets with other types of
791 /// implicit widening casts.
792 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
796 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
797 /// DemandedMask bits of the result of Op are ever used downstream. If we can
798 /// use this information to simplify Op, create a new simplified DAG node and
799 /// return true, returning the original and new nodes in Old and New.
800 /// Otherwise, analyze the expression and return a mask of KnownOne and
801 /// KnownZero bits for the expression (used to simplify the caller).
802 /// The KnownZero/One bits may only be accurate for those bits in the
804 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
805 APInt &KnownZero, APInt &KnownOne,
806 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
808 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
809 /// Mask are known to be either zero or one and return them in the
810 /// KnownZero/KnownOne bitsets.
811 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
815 const SelectionDAG &DAG,
816 unsigned Depth = 0) const;
818 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
819 /// targets that want to expose additional information about sign bits to the
821 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
822 unsigned Depth = 0) const;
824 struct DAGCombinerInfo {
825 void *DC; // The DAG Combiner object.
827 bool BeforeLegalizeOps;
828 bool CalledByLegalizer;
832 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
833 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
834 CalledByLegalizer(cl), DAG(dag) {}
836 bool isBeforeLegalize() const { return BeforeLegalize; }
837 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
838 bool isCalledByLegalizer() const { return CalledByLegalizer; }
840 void AddToWorklist(SDNode *N);
841 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
843 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
844 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
846 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
849 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
850 /// and cc. If it is unable to simplify it, return a null SDValue.
851 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
852 ISD::CondCode Cond, bool foldBooleans,
853 DAGCombinerInfo &DCI, DebugLoc dl) const;
855 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
856 /// node is a GlobalAddress + offset.
858 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
860 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
861 /// location that is 'Dist' units away from the location that the 'Base' load
863 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes,
864 int Dist, const MachineFrameInfo *MFI) const;
866 /// PerformDAGCombine - This method will be invoked for all target nodes and
867 /// for any target-independent nodes that the target has registered with
870 /// The semantics are as follows:
872 /// SDValue.Val == 0 - No change was made
873 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
874 /// otherwise - N should be replaced by the returned Operand.
876 /// In addition, methods provided by DAGCombinerInfo may be used to perform
877 /// more complex transformations.
879 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
881 //===--------------------------------------------------------------------===//
882 // TargetLowering Configuration Methods - These methods should be invoked by
883 // the derived class constructor to configure this object for the target.
887 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
888 /// GOT for PC-relative code.
889 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
891 /// setShiftAmountType - Describe the type that should be used for shift
892 /// amounts. This type defaults to the pointer type.
893 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
895 /// setBooleanContents - Specify how the target extends the result of a
896 /// boolean value from i1 to a wider type. See getBooleanContents.
897 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
899 /// setSchedulingPreference - Specify the target scheduling preference.
900 void setSchedulingPreference(SchedPreference Pref) {
901 SchedPreferenceInfo = Pref;
904 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
905 /// use _setjmp to implement llvm.setjmp or the non _ version.
906 /// Defaults to false.
907 void setUseUnderscoreSetJmp(bool Val) {
908 UseUnderscoreSetJmp = Val;
911 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
912 /// use _longjmp to implement llvm.longjmp or the non _ version.
913 /// Defaults to false.
914 void setUseUnderscoreLongJmp(bool Val) {
915 UseUnderscoreLongJmp = Val;
918 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
919 /// specifies the register that llvm.savestack/llvm.restorestack should save
921 void setStackPointerRegisterToSaveRestore(unsigned R) {
922 StackPointerRegisterToSaveRestore = R;
925 /// setExceptionPointerRegister - If set to a physical register, this sets
926 /// the register that receives the exception address on entry to a landing
928 void setExceptionPointerRegister(unsigned R) {
929 ExceptionPointerRegister = R;
932 /// setExceptionSelectorRegister - If set to a physical register, this sets
933 /// the register that receives the exception typeid on entry to a landing
935 void setExceptionSelectorRegister(unsigned R) {
936 ExceptionSelectorRegister = R;
939 /// SelectIsExpensive - Tells the code generator not to expand operations
940 /// into sequences that use the select operations if possible.
941 void setSelectIsExpensive() { SelectIsExpensive = true; }
943 /// setIntDivIsCheap - Tells the code generator that integer divide is
944 /// expensive, and if possible, should be replaced by an alternate sequence
945 /// of instructions not containing an integer divide.
946 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
948 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
949 /// srl/add/sra for a signed divide by power of two, and let the target handle
951 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
953 /// addRegisterClass - Add the specified register class as an available
954 /// regclass for the specified value type. This indicates the selector can
955 /// handle values of that class natively.
956 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
957 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
958 AvailableRegClasses.push_back(std::make_pair(VT, RC));
959 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
962 /// computeRegisterProperties - Once all of the register classes are added,
963 /// this allows us to compute derived properties we expose.
964 void computeRegisterProperties();
966 /// setOperationAction - Indicate that the specified operation does not work
967 /// with the specified type and indicate what to do about it.
968 void setOperationAction(unsigned Op, MVT VT,
969 LegalizeAction Action) {
970 unsigned I = (unsigned)VT.SimpleTy;
973 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
974 OpActions[I][Op] |= (uint64_t)Action << (J*2);
977 /// setLoadExtAction - Indicate that the specified load with extension does
978 /// not work with the with specified type and indicate what to do about it.
979 void setLoadExtAction(unsigned ExtType, MVT VT,
980 LegalizeAction Action) {
981 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
982 ExtType < array_lengthof(LoadExtActions) &&
983 "Table isn't big enough!");
984 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
985 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
988 /// setTruncStoreAction - Indicate that the specified truncating store does
989 /// not work with the with specified type and indicate what to do about it.
990 void setTruncStoreAction(MVT ValVT, MVT MemVT,
991 LegalizeAction Action) {
992 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
993 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
994 "Table isn't big enough!");
995 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
996 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
999 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1000 /// does not work with the with specified type and indicate what to do abort
1001 /// it. NOTE: All indexed mode loads are initialized to Expand in
1002 /// TargetLowering.cpp
1003 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1004 LegalizeAction Action) {
1005 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1006 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1007 "Table isn't big enough!");
1008 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1011 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1012 /// does not work with the with specified type and indicate what to do about
1013 /// it. NOTE: All indexed mode stores are initialized to Expand in
1014 /// TargetLowering.cpp
1015 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1016 LegalizeAction Action) {
1017 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1018 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1019 "Table isn't big enough!");
1020 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1023 /// setConvertAction - Indicate that the specified conversion does or does
1024 /// not work with the with specified type and indicate what to do about it.
1025 void setConvertAction(MVT FromVT, MVT ToVT,
1026 LegalizeAction Action) {
1027 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1028 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
1029 "Table isn't big enough!");
1030 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1031 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
1034 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1035 /// supported on the target and indicate what to do about it.
1036 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1037 LegalizeAction Action) {
1038 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1039 (unsigned)CC < array_lengthof(CondCodeActions) &&
1040 "Table isn't big enough!");
1041 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1042 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1045 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1046 /// promotion code defaults to trying a larger integer/fp until it can find
1047 /// one that works. If that default is insufficient, this method can be used
1048 /// by the target to override the default.
1049 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1050 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1053 /// setTargetDAGCombine - Targets should invoke this method for each target
1054 /// independent node that they want to provide a custom DAG combiner for by
1055 /// implementing the PerformDAGCombine virtual method.
1056 void setTargetDAGCombine(ISD::NodeType NT) {
1057 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1058 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1061 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1062 /// bytes); default is 200
1063 void setJumpBufSize(unsigned Size) {
1067 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1068 /// alignment (in bytes); default is 0
1069 void setJumpBufAlignment(unsigned Align) {
1070 JumpBufAlignment = Align;
1073 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1074 /// limit (in number of instructions); default is 2.
1075 void setIfCvtBlockSizeLimit(unsigned Limit) {
1076 IfCvtBlockSizeLimit = Limit;
1079 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1080 /// of instructions) to be considered for code duplication during
1081 /// if-conversion; default is 2.
1082 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1083 IfCvtDupBlockSizeLimit = Limit;
1086 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1087 /// alignment is zero, it means the target does not care about loop alignment.
1088 void setPrefLoopAlignment(unsigned Align) {
1089 PrefLoopAlignment = Align;
1094 virtual const TargetSubtarget *getSubtarget() {
1095 assert(0 && "Not Implemented");
1096 return NULL; // this is here to silence compiler errors
1099 //===--------------------------------------------------------------------===//
1100 // Lowering methods - These methods must be implemented by targets so that
1101 // the SelectionDAGLowering code knows how to lower these.
1104 /// LowerFormalArguments - This hook must be implemented to lower the
1105 /// incoming (formal) arguments, described by the Ins array, into the
1106 /// specified DAG. The implementation should fill in the InVals array
1107 /// with legal-type argument values, and return the resulting token
1111 LowerFormalArguments(SDValue Chain,
1112 CallingConv::ID CallConv, bool isVarArg,
1113 const SmallVectorImpl<ISD::InputArg> &Ins,
1114 DebugLoc dl, SelectionDAG &DAG,
1115 SmallVectorImpl<SDValue> &InVals) {
1116 assert(0 && "Not Implemented");
1117 return SDValue(); // this is here to silence compiler errors
1120 /// LowerCallTo - This function lowers an abstract call to a function into an
1121 /// actual call. This returns a pair of operands. The first element is the
1122 /// return value for the function (if RetTy is not VoidTy). The second
1123 /// element is the outgoing token chain. It calls LowerCall to do the actual
1125 struct ArgListEntry {
1136 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1137 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1139 typedef std::vector<ArgListEntry> ArgListTy;
1140 std::pair<SDValue, SDValue>
1141 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1142 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1143 CallingConv::ID CallConv, bool isTailCall,
1144 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1145 SelectionDAG &DAG, DebugLoc dl);
1147 /// LowerCall - This hook must be implemented to lower calls into the
1148 /// the specified DAG. The outgoing arguments to the call are described
1149 /// by the Outs array, and the values to be returned by the call are
1150 /// described by the Ins array. The implementation should fill in the
1151 /// InVals array with legal-type return values from the call, and return
1152 /// the resulting token chain value.
1154 /// The isTailCall flag here is normative. If it is true, the
1155 /// implementation must emit a tail call. The
1156 /// IsEligibleForTailCallOptimization hook should be used to catch
1157 /// cases that cannot be handled.
1160 LowerCall(SDValue Chain, SDValue Callee,
1161 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
1162 const SmallVectorImpl<ISD::OutputArg> &Outs,
1163 const SmallVectorImpl<ISD::InputArg> &Ins,
1164 DebugLoc dl, SelectionDAG &DAG,
1165 SmallVectorImpl<SDValue> &InVals) {
1166 assert(0 && "Not Implemented");
1167 return SDValue(); // this is here to silence compiler errors
1170 /// CanLowerReturn - This hook should be implemented to check whether the
1171 /// return values described by the Outs array can fit into the return
1172 /// registers. If false is returned, an sret-demotion is performed.
1174 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1175 const SmallVectorImpl<EVT> &OutTys,
1176 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1179 // Return true by default to get preexisting behavior.
1182 /// LowerReturn - This hook must be implemented to lower outgoing
1183 /// return values, described by the Outs array, into the specified
1184 /// DAG. The implementation should return the resulting token chain
1188 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1189 const SmallVectorImpl<ISD::OutputArg> &Outs,
1190 DebugLoc dl, SelectionDAG &DAG) {
1191 assert(0 && "Not Implemented");
1192 return SDValue(); // this is here to silence compiler errors
1195 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1196 /// memcpy. This can be used by targets to provide code sequences for cases
1197 /// that don't fit the target's parameters for simple loads/stores and can be
1198 /// more efficient than using a library call. This function can return a null
1199 /// SDValue if the target declines to use custom code and a different
1200 /// lowering strategy should be used.
1202 /// If AlwaysInline is true, the size is constant and the target should not
1203 /// emit any calls and is strongly encouraged to attempt to emit inline code
1204 /// even if it is beyond the usual threshold because this intrinsic is being
1205 /// expanded in a place where calls are not feasible (e.g. within the prologue
1206 /// for another call). If the target chooses to decline an AlwaysInline
1207 /// request here, legalize will resort to using simple loads and stores.
1209 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1211 SDValue Op1, SDValue Op2,
1212 SDValue Op3, unsigned Align,
1214 const Value *DstSV, uint64_t DstOff,
1215 const Value *SrcSV, uint64_t SrcOff) {
1219 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1220 /// memmove. This can be used by targets to provide code sequences for cases
1221 /// that don't fit the target's parameters for simple loads/stores and can be
1222 /// more efficient than using a library call. This function can return a null
1223 /// SDValue if the target declines to use custom code and a different
1224 /// lowering strategy should be used.
1226 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1228 SDValue Op1, SDValue Op2,
1229 SDValue Op3, unsigned Align,
1230 const Value *DstSV, uint64_t DstOff,
1231 const Value *SrcSV, uint64_t SrcOff) {
1235 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1236 /// memset. This can be used by targets to provide code sequences for cases
1237 /// that don't fit the target's parameters for simple stores and can be more
1238 /// efficient than using a library call. This function can return a null
1239 /// SDValue if the target declines to use custom code and a different
1240 /// lowering strategy should be used.
1242 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1244 SDValue Op1, SDValue Op2,
1245 SDValue Op3, unsigned Align,
1246 const Value *DstSV, uint64_t DstOff) {
1250 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1251 /// to legalize nodes with an illegal operand type but legal result types.
1252 /// It replaces the LowerOperation callback in the type Legalizer.
1253 /// The reason we can not do away with LowerOperation entirely is that
1254 /// LegalizeDAG isn't yet ready to use this callback.
1255 /// TODO: Consider merging with ReplaceNodeResults.
1257 /// The target places new result values for the node in Results (their number
1258 /// and types must exactly match those of the original return values of
1259 /// the node), or leaves Results empty, which indicates that the node is not
1260 /// to be custom lowered after all.
1261 /// The default implementation calls LowerOperation.
1262 virtual void LowerOperationWrapper(SDNode *N,
1263 SmallVectorImpl<SDValue> &Results,
1266 /// LowerOperation - This callback is invoked for operations that are
1267 /// unsupported by the target, which are registered to use 'custom' lowering,
1268 /// and whose defined values are all legal.
1269 /// If the target has no operations that require custom lowering, it need not
1270 /// implement this. The default implementation of this aborts.
1271 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1273 /// ReplaceNodeResults - This callback is invoked when a node result type is
1274 /// illegal for the target, and the operation was registered to use 'custom'
1275 /// lowering for that result type. The target places new result values for
1276 /// the node in Results (their number and types must exactly match those of
1277 /// the original return values of the node), or leaves Results empty, which
1278 /// indicates that the node is not to be custom lowered after all.
1280 /// If the target has no operations that require custom lowering, it need not
1281 /// implement this. The default implementation aborts.
1282 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1283 SelectionDAG &DAG) {
1284 assert(0 && "ReplaceNodeResults not implemented for this target!");
1287 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1288 /// tail call optimization. Targets which want to do tail call optimization
1289 /// should override this function.
1291 IsEligibleForTailCallOptimization(SDValue Callee,
1292 CallingConv::ID CalleeCC,
1294 const SmallVectorImpl<ISD::InputArg> &Ins,
1295 SelectionDAG& DAG) const {
1296 // Conservative default: no calls are eligible.
1300 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1301 /// it exists. Skip a possible ISD::TokenFactor.
1302 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1303 unsigned TailCallNodeOpCode) {
1304 if (Chain.getOpcode() == TailCallNodeOpCode) {
1306 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1307 if (Chain.getNumOperands() &&
1308 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1309 return Chain.getOperand(0);
1314 /// getTargetNodeName() - This method returns the name of a target specific
1316 virtual const char *getTargetNodeName(unsigned Opcode) const;
1318 /// createFastISel - This method returns a target specific FastISel object,
1319 /// or null if the target does not support "fast" ISel.
1321 createFastISel(MachineFunction &,
1322 MachineModuleInfo *, DwarfWriter *,
1323 DenseMap<const Value *, unsigned> &,
1324 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1325 DenseMap<const AllocaInst *, int> &
1327 , SmallSet<Instruction*, 8> &CatchInfoLost
1333 //===--------------------------------------------------------------------===//
1334 // Inline Asm Support hooks
1337 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1338 /// call to be explicit llvm code if it wants to. This is useful for
1339 /// turning simple inline asms into LLVM intrinsics, which gives the
1340 /// compiler more information about the behavior of the code.
1341 virtual bool ExpandInlineAsm(CallInst *CI) const {
1345 enum ConstraintType {
1346 C_Register, // Constraint represents specific register(s).
1347 C_RegisterClass, // Constraint represents any of register(s) in class.
1348 C_Memory, // Memory constraint.
1349 C_Other, // Something else.
1350 C_Unknown // Unsupported constraint.
1353 /// AsmOperandInfo - This contains information for each constraint that we are
1355 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1356 /// ConstraintCode - This contains the actual string for the code, like "m".
1357 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1358 /// most closely matches the operand.
1359 std::string ConstraintCode;
1361 /// ConstraintType - Information about the constraint code, e.g. Register,
1362 /// RegisterClass, Memory, Other, Unknown.
1363 TargetLowering::ConstraintType ConstraintType;
1365 /// CallOperandval - If this is the result output operand or a
1366 /// clobber, this is null, otherwise it is the incoming operand to the
1367 /// CallInst. This gets modified as the asm is processed.
1368 Value *CallOperandVal;
1370 /// ConstraintVT - The ValueType for the operand value.
1373 /// isMatchingInputConstraint - Return true of this is an input operand that
1374 /// is a matching constraint like "4".
1375 bool isMatchingInputConstraint() const;
1377 /// getMatchedOperand - If this is an input matching constraint, this method
1378 /// returns the output operand it matches.
1379 unsigned getMatchedOperand() const;
1381 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1382 : InlineAsm::ConstraintInfo(info),
1383 ConstraintType(TargetLowering::C_Unknown),
1384 CallOperandVal(0), ConstraintVT(MVT::Other) {
1388 /// ComputeConstraintToUse - Determines the constraint code and constraint
1389 /// type to use for the specific AsmOperandInfo, setting
1390 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1391 /// being passed in is available, it can be passed in as Op, otherwise an
1392 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1393 /// constraint of the inline asm instruction being processed is 'm'.
1394 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1397 SelectionDAG *DAG = 0) const;
1399 /// getConstraintType - Given a constraint, return the type of constraint it
1400 /// is for this target.
1401 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1403 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1404 /// return a list of registers that can be used to satisfy the constraint.
1405 /// This should only be used for C_RegisterClass constraints.
1406 virtual std::vector<unsigned>
1407 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1410 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1411 /// {edx}), return the register number and the register class for the
1414 /// Given a register class constraint, like 'r', if this corresponds directly
1415 /// to an LLVM register class, return a register of 0 and the register class
1418 /// This should only be used for C_Register constraints. On error,
1419 /// this returns a register number of 0 and a null register class pointer..
1420 virtual std::pair<unsigned, const TargetRegisterClass*>
1421 getRegForInlineAsmConstraint(const std::string &Constraint,
1424 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1425 /// with another that has more specific requirements based on the type of the
1426 /// corresponding operand. This returns null if there is no replacement to
1428 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1430 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1431 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1432 /// it means one of the asm constraint of the inline asm instruction being
1433 /// processed is 'm'.
1434 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1436 std::vector<SDValue> &Ops,
1437 SelectionDAG &DAG) const;
1439 //===--------------------------------------------------------------------===//
1440 // Instruction Emitting Hooks
1443 // EmitInstrWithCustomInserter - This method should be implemented by targets
1444 // that mark instructions with the 'usesCustomInserter' flag. These
1445 // instructions are special in various ways, which require special support to
1446 // insert. The specified MachineInstr is created but not inserted into any
1447 // basic blocks, and this method is called to expand it into a sequence of
1448 // instructions, potentially also creating new basic blocks and control flow.
1449 // When new basic blocks are inserted and the edges from MBB to its successors
1450 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1452 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1453 MachineBasicBlock *MBB,
1454 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1456 //===--------------------------------------------------------------------===//
1457 // Addressing mode description hooks (used by LSR etc).
1460 /// AddrMode - This represents an addressing mode of:
1461 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1462 /// If BaseGV is null, there is no BaseGV.
1463 /// If BaseOffs is zero, there is no base offset.
1464 /// If HasBaseReg is false, there is no base register.
1465 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1469 GlobalValue *BaseGV;
1473 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1476 /// isLegalAddressingMode - Return true if the addressing mode represented by
1477 /// AM is legal for this target, for a load/store of the specified type.
1478 /// The type may be VoidTy, in which case only return true if the addressing
1479 /// mode is legal for a load/store of any legal type.
1480 /// TODO: Handle pre/postinc as well.
1481 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1483 /// isTruncateFree - Return true if it's free to truncate a value of
1484 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1485 /// register EAX to i16 by referencing its sub-register AX.
1486 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1490 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1494 /// isZExtFree - Return true if any actual instruction that defines a
1495 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1496 /// register. This does not necessarily include registers defined in
1497 /// unknown ways, such as incoming arguments, or copies from unknown
1498 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1499 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1500 /// all instructions that define 32-bit values implicit zero-extend the
1501 /// result out to 64 bits.
1502 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1506 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1510 /// isNarrowingProfitable - Return true if it's profitable to narrow
1511 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1512 /// from i32 to i8 but not from i32 to i16.
1513 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1517 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1518 /// icmp immediate, that is the target has icmp instructions which can compare
1519 /// a register against the immediate without having to materialize the
1520 /// immediate into a register.
1521 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1525 //===--------------------------------------------------------------------===//
1526 // Div utility functions
1528 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1529 std::vector<SDNode*>* Created) const;
1530 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1531 std::vector<SDNode*>* Created) const;
1534 //===--------------------------------------------------------------------===//
1535 // Runtime Library hooks
1538 /// setLibcallName - Rename the default libcall routine name for the specified
1540 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1541 LibcallRoutineNames[Call] = Name;
1544 /// getLibcallName - Get the libcall routine name for the specified libcall.
1546 const char *getLibcallName(RTLIB::Libcall Call) const {
1547 return LibcallRoutineNames[Call];
1550 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1551 /// result of the comparison libcall against zero.
1552 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1553 CmpLibcallCCs[Call] = CC;
1556 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1557 /// the comparison libcall against zero.
1558 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1559 return CmpLibcallCCs[Call];
1562 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1563 /// specified libcall.
1564 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1565 LibcallCallingConvs[Call] = CC;
1568 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1569 /// specified libcall.
1570 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1571 return LibcallCallingConvs[Call];
1576 const TargetData *TD;
1577 TargetLoweringObjectFile &TLOF;
1579 /// PointerTy - The type to use for pointers, usually i32 or i64.
1583 /// IsLittleEndian - True if this is a little endian target.
1585 bool IsLittleEndian;
1587 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1589 bool UsesGlobalOffsetTable;
1591 /// SelectIsExpensive - Tells the code generator not to expand operations
1592 /// into sequences that use the select operations if possible.
1593 bool SelectIsExpensive;
1595 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1596 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1597 /// a real cost model is in place. If we ever optimize for size, this will be
1598 /// set to true unconditionally.
1601 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1602 /// srl/add/sra for a signed divide by power of two, and let the target handle
1604 bool Pow2DivIsCheap;
1606 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1607 /// llvm.setjmp. Defaults to false.
1608 bool UseUnderscoreSetJmp;
1610 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1611 /// llvm.longjmp. Defaults to false.
1612 bool UseUnderscoreLongJmp;
1614 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1618 /// BooleanContents - Information about the contents of the high-bits in
1619 /// boolean values held in a type wider than i1. See getBooleanContents.
1620 BooleanContent BooleanContents;
1622 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1623 /// total cycles or lowest register usage.
1624 SchedPreference SchedPreferenceInfo;
1626 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1627 unsigned JumpBufSize;
1629 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1631 unsigned JumpBufAlignment;
1633 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1635 unsigned IfCvtBlockSizeLimit;
1637 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1638 /// duplicated during if-conversion.
1639 unsigned IfCvtDupBlockSizeLimit;
1641 /// PrefLoopAlignment - The perferred loop alignment.
1643 unsigned PrefLoopAlignment;
1645 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1646 /// specifies the register that llvm.savestack/llvm.restorestack should save
1648 unsigned StackPointerRegisterToSaveRestore;
1650 /// ExceptionPointerRegister - If set to a physical register, this specifies
1651 /// the register that receives the exception address on entry to a landing
1653 unsigned ExceptionPointerRegister;
1655 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1656 /// the register that receives the exception typeid on entry to a landing
1658 unsigned ExceptionSelectorRegister;
1660 /// RegClassForVT - This indicates the default register class to use for
1661 /// each ValueType the target supports natively.
1662 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1663 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1664 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1666 /// TransformToType - For any value types we are promoting or expanding, this
1667 /// contains the value type that we are changing to. For Expanded types, this
1668 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1669 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1670 /// by the system, this holds the same type (e.g. i32 -> i32).
1671 EVT TransformToType[MVT::LAST_VALUETYPE];
1673 /// OpActions - For each operation and each value type, keep a LegalizeAction
1674 /// that indicates how instruction selection should deal with the operation.
1675 /// Most operations are Legal (aka, supported natively by the target), but
1676 /// operations that are not should be described. Note that operations on
1677 /// non-legal value types are not described here.
1678 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1679 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1680 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1682 /// LoadExtActions - For each load of load extension type and each value type,
1683 /// keep a LegalizeAction that indicates how instruction selection should deal
1685 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1687 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1688 /// indicates how instruction selection should deal with the store.
1689 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1691 /// IndexedModeActions - For each indexed mode and each value type,
1692 /// keep a pair of LegalizeAction that indicates how instruction
1693 /// selection should deal with the load / store. The first
1694 /// dimension is now the value_type for the reference. The second
1695 /// dimension is the load [0] vs. store[1]. The third dimension
1696 /// represents the various modes for load store.
1697 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1699 /// ConvertActions - For each conversion from source type to destination type,
1700 /// keep a LegalizeAction that indicates how instruction selection should
1701 /// deal with the conversion.
1702 /// Currently, this is used only for floating->floating conversions
1703 /// (FP_EXTEND and FP_ROUND).
1704 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1706 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1707 /// LegalizeAction that indicates how instruction selection should
1708 /// deal with the condition code.
1709 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1711 ValueTypeActionImpl ValueTypeActions;
1713 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1715 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1716 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1717 /// which sets a bit in this array.
1719 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1721 /// PromoteToType - For operations that must be promoted to a specific type,
1722 /// this holds the destination type. This map should be sparse, so don't hold
1725 /// Targets add entries to this map with AddPromotedToType(..), clients access
1726 /// this with getTypeToPromoteTo(..).
1727 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1730 /// LibcallRoutineNames - Stores the name each libcall.
1732 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1734 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1735 /// of each of the comparison libcall against zero.
1736 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1738 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1740 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1743 /// When lowering \@llvm.memset this field specifies the maximum number of
1744 /// store operations that may be substituted for the call to memset. Targets
1745 /// must set this value based on the cost threshold for that target. Targets
1746 /// should assume that the memset will be done using as many of the largest
1747 /// store operations first, followed by smaller ones, if necessary, per
1748 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1749 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1750 /// store. This only applies to setting a constant array of a constant size.
1751 /// @brief Specify maximum number of store instructions per memset call.
1752 unsigned maxStoresPerMemset;
1754 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1755 /// store operations that may be substituted for a call to memcpy. Targets
1756 /// must set this value based on the cost threshold for that target. Targets
1757 /// should assume that the memcpy will be done using as many of the largest
1758 /// store operations first, followed by smaller ones, if necessary, per
1759 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1760 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1761 /// and one 1-byte store. This only applies to copying a constant array of
1763 /// @brief Specify maximum bytes of store instructions per memcpy call.
1764 unsigned maxStoresPerMemcpy;
1766 /// When lowering \@llvm.memmove this field specifies the maximum number of
1767 /// store instructions that may be substituted for a call to memmove. Targets
1768 /// must set this value based on the cost threshold for that target. Targets
1769 /// should assume that the memmove will be done using as many of the largest
1770 /// store operations first, followed by smaller ones, if necessary, per
1771 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1772 /// with 8-bit alignment would result in nine 1-byte stores. This only
1773 /// applies to copying a constant array of constant size.
1774 /// @brief Specify maximum bytes of store instructions per memmove call.
1775 unsigned maxStoresPerMemmove;
1777 /// This field specifies whether the target can benefit from code placement
1779 bool benefitFromCodePlacementOpt;
1781 } // end llvm namespace