1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 class TargetRegisterClass;
38 class MachineBasicBlock;
41 //===----------------------------------------------------------------------===//
42 /// TargetLowering - This class defines information used to lower LLVM code to
43 /// legal SelectionDAG operators that the target instruction selector can accept
46 /// This class also defines callbacks that targets must implement to lower
47 /// target-specific constructs to SelectionDAG operators.
49 class TargetLowering {
51 /// LegalizeAction - This enum indicates whether operations are valid for a
52 /// target, and if not, what action should be used to make them valid.
54 Legal, // The target natively supports this operation.
55 Promote, // This operation should be executed in a larger type.
56 Expand, // Try to expand this to other ops, otherwise use a libcall.
57 Custom // Use the LowerOperation hook to implement custom lowering.
60 enum OutOfRangeShiftAmount {
61 Undefined, // Oversized shift amounts are undefined (default).
62 Mask, // Shift amounts are auto masked (anded) to value size.
63 Extend // Oversized shift pulls in zeros or sign bits.
66 enum SetCCResultValue {
67 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
68 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
69 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
72 enum SchedPreference {
73 SchedulingForLatency, // Scheduling for shortest total latency.
74 SchedulingForRegPressure // Scheduling for lowest register pressure.
77 TargetLowering(TargetMachine &TM);
78 virtual ~TargetLowering();
80 TargetMachine &getTargetMachine() const { return TM; }
81 const TargetData *getTargetData() const { return TD; }
83 bool isLittleEndian() const { return IsLittleEndian; }
84 MVT::ValueType getPointerTy() const { return PointerTy; }
85 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
86 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
88 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
90 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
92 /// isSetCCExpensive - Return true if the setcc operation is expensive for
94 bool isSetCCExpensive() const { return SetCCIsExpensive; }
96 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
97 /// a sequence of several shifts, adds, and multiplies for this target.
98 bool isIntDivCheap() const { return IntDivIsCheap; }
100 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
102 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
104 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
106 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
108 /// getSetCCResultContents - For targets without boolean registers, this flag
109 /// returns information about the contents of the high-bits in the setcc
111 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
113 /// getSchedulingPreference - Return target scheduling preference.
114 SchedPreference getSchedulingPreference() const {
115 return SchedPreferenceInfo;
118 /// getRegClassFor - Return the register class that should be used for the
119 /// specified value type. This may only be called on legal types.
120 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
121 TargetRegisterClass *RC = RegClassForVT[VT];
122 assert(RC && "This value type is not natively supported!");
126 /// isTypeLegal - Return true if the target has native support for the
127 /// specified value type. This means that it has a register that directly
128 /// holds it without promotions or expansions.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return RegClassForVT[VT] != 0;
133 class ValueTypeActionImpl {
134 /// ValueTypeActions - This is a bitvector that contains two bits for each
135 /// value type, where the two bits correspond to the LegalizeAction enum.
136 /// This can be queried with "getTypeAction(VT)".
137 uint32_t ValueTypeActions[2];
139 ValueTypeActionImpl() {
140 ValueTypeActions[0] = ValueTypeActions[1] = 0;
142 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
143 ValueTypeActions[0] = RHS.ValueTypeActions[0];
144 ValueTypeActions[1] = RHS.ValueTypeActions[1];
147 LegalizeAction getTypeAction(MVT::ValueType VT) const {
148 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
150 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
151 assert(unsigned(VT >> 4) <
152 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
153 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
157 const ValueTypeActionImpl &getValueTypeActions() const {
158 return ValueTypeActions;
161 /// getTypeAction - Return how we should legalize values of this type, either
162 /// it is already legal (return 'Legal') or we need to promote it to a larger
163 /// type (return 'Promote'), or we need to expand it into multiple registers
164 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
165 LegalizeAction getTypeAction(MVT::ValueType VT) const {
166 return ValueTypeActions.getTypeAction(VT);
169 /// getTypeToTransformTo - For types supported by the target, this is an
170 /// identity function. For types that must be promoted to larger types, this
171 /// returns the larger type to promote to. For types that are larger than the
172 /// largest integer register, this contains one step in the expansion to get
173 /// to the smaller register.
174 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
175 return TransformToType[VT];
178 /// getPackedTypeBreakdown - Packed types are broken down into some number of
179 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
180 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
181 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
183 /// This method returns the number of registers needed, and the VT for each
184 /// register. It also returns the VT of the PackedType elements before they
185 /// are promoted/expanded.
187 unsigned getPackedTypeBreakdown(const PackedType *PTy,
188 MVT::ValueType &PTyElementVT,
189 MVT::ValueType &PTyLegalElementVT) const;
191 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
192 legal_fpimm_iterator legal_fpimm_begin() const {
193 return LegalFPImmediates.begin();
195 legal_fpimm_iterator legal_fpimm_end() const {
196 return LegalFPImmediates.end();
199 /// isShuffleMaskLegal - Targets can use this to indicate that they only
200 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
201 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
202 /// are assumed to be legal.
203 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
207 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
208 /// used by Targets can use this to indicate if there is a suitable
209 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
211 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
213 SelectionDAG &DAG) const {
217 /// getOperationAction - Return how this operation should be treated: either
218 /// it is legal, needs to be promoted to a larger size, needs to be
219 /// expanded to some other code sequence, or the target has a custom expander
221 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
222 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
225 /// isOperationLegal - Return true if the specified operation is legal on this
227 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
228 return getOperationAction(Op, VT) == Legal ||
229 getOperationAction(Op, VT) == Custom;
232 /// getLoadXAction - Return how this load with extension should be treated:
233 /// either it is legal, needs to be promoted to a larger size, needs to be
234 /// expanded to some other code sequence, or the target has a custom expander
236 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
237 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
240 /// isLoadXLegal - Return true if the specified load with extension is legal
242 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
243 return getLoadXAction(LType, VT) == Legal ||
244 getLoadXAction(LType, VT) == Custom;
247 /// getStoreXAction - Return how this store with truncation should be treated:
248 /// either it is legal, needs to be promoted to a larger size, needs to be
249 /// expanded to some other code sequence, or the target has a custom expander
251 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
252 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
255 /// isStoreXLegal - Return true if the specified store with truncation is
256 /// legal on this target.
257 bool isStoreXLegal(MVT::ValueType VT) const {
258 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
261 /// getIndexedLoadAction - Return how the indexed load should be treated:
262 /// either it is legal, needs to be promoted to a larger size, needs to be
263 /// expanded to some other code sequence, or the target has a custom expander
266 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
267 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
270 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
272 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
273 return getIndexedLoadAction(IdxMode, VT) == Legal ||
274 getIndexedLoadAction(IdxMode, VT) == Custom;
277 /// getIndexedStoreAction - Return how the indexed store should be treated:
278 /// either it is legal, needs to be promoted to a larger size, needs to be
279 /// expanded to some other code sequence, or the target has a custom expander
282 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
283 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
286 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
288 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
289 return getIndexedStoreAction(IdxMode, VT) == Legal ||
290 getIndexedStoreAction(IdxMode, VT) == Custom;
293 /// getTypeToPromoteTo - If the action for this operation is to promote, this
294 /// method returns the ValueType to promote to.
295 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
296 assert(getOperationAction(Op, VT) == Promote &&
297 "This operation isn't promoted!");
299 // See if this has an explicit type specified.
300 std::map<std::pair<unsigned, MVT::ValueType>,
301 MVT::ValueType>::const_iterator PTTI =
302 PromoteToType.find(std::make_pair(Op, VT));
303 if (PTTI != PromoteToType.end()) return PTTI->second;
305 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
306 "Cannot autopromote this type, add it with AddPromotedToType.");
308 MVT::ValueType NVT = VT;
310 NVT = (MVT::ValueType)(NVT+1);
311 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
312 "Didn't find type to promote to!");
313 } while (!isTypeLegal(NVT) ||
314 getOperationAction(Op, NVT) == Promote);
318 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
319 /// This is fixed by the LLVM operations except for the pointer size.
320 MVT::ValueType getValueType(const Type *Ty) const {
321 switch (Ty->getTypeID()) {
322 default: assert(0 && "Unknown type!");
323 case Type::VoidTyID: return MVT::isVoid;
324 case Type::BoolTyID: return MVT::i1;
325 case Type::UByteTyID:
326 case Type::SByteTyID: return MVT::i8;
327 case Type::ShortTyID:
328 case Type::UShortTyID: return MVT::i16;
330 case Type::UIntTyID: return MVT::i32;
332 case Type::ULongTyID: return MVT::i64;
333 case Type::FloatTyID: return MVT::f32;
334 case Type::DoubleTyID: return MVT::f64;
335 case Type::PointerTyID: return PointerTy;
336 case Type::PackedTyID: return MVT::Vector;
340 /// getNumElements - Return the number of registers that this ValueType will
341 /// eventually require. This is always one for all non-integer types, is
342 /// one for any types promoted to live in larger registers, but may be more
343 /// than one for types (like i64) that are split into pieces.
344 unsigned getNumElements(MVT::ValueType VT) const {
345 return NumElementsForVT[VT];
348 /// hasTargetDAGCombine - If true, the target has custom DAG combine
349 /// transformations that it can perform for the specified node.
350 bool hasTargetDAGCombine(ISD::NodeType NT) const {
351 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
354 /// This function returns the maximum number of store operations permitted
355 /// to replace a call to llvm.memset. The value is set by the target at the
356 /// performance threshold for such a replacement.
357 /// @brief Get maximum # of store operations permitted for llvm.memset
358 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
360 /// This function returns the maximum number of store operations permitted
361 /// to replace a call to llvm.memcpy. The value is set by the target at the
362 /// performance threshold for such a replacement.
363 /// @brief Get maximum # of store operations permitted for llvm.memcpy
364 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
366 /// This function returns the maximum number of store operations permitted
367 /// to replace a call to llvm.memmove. The value is set by the target at the
368 /// performance threshold for such a replacement.
369 /// @brief Get maximum # of store operations permitted for llvm.memmove
370 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
372 /// This function returns true if the target allows unaligned memory accesses.
373 /// This is used, for example, in situations where an array copy/move/set is
374 /// converted to a sequence of store operations. It's use helps to ensure that
375 /// such replacements don't generate code that causes an alignment error
376 /// (trap) on the target machine.
377 /// @brief Determine if the target supports unaligned memory accesses.
378 bool allowsUnalignedMemoryAccesses() const {
379 return allowUnalignedMemoryAccesses;
382 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
383 /// to implement llvm.setjmp.
384 bool usesUnderscoreSetJmp() const {
385 return UseUnderscoreSetJmp;
388 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
389 /// to implement llvm.longjmp.
390 bool usesUnderscoreLongJmp() const {
391 return UseUnderscoreLongJmp;
394 /// getStackPointerRegisterToSaveRestore - If a physical register, this
395 /// specifies the register that llvm.savestack/llvm.restorestack should save
397 unsigned getStackPointerRegisterToSaveRestore() const {
398 return StackPointerRegisterToSaveRestore;
401 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
402 /// set, the default is 200)
403 unsigned getJumpBufSize() const {
407 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
408 /// (if never set, the default is 0)
409 unsigned getJumpBufAlignment() const {
410 return JumpBufAlignment;
413 /// getPreIndexedAddressParts - returns true by value, base pointer and
414 /// offset pointer and addressing mode by reference if the node's address
415 /// can be legally represented as pre-indexed load / store address.
416 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
418 ISD::MemIndexedMode &AM,
423 /// getPostIndexedAddressParts - returns true by value, base pointer and
424 /// offset pointer and addressing mode by reference if this node can be
425 /// combined with a load / store to form a post-indexed load / store.
426 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
427 SDOperand &Base, SDOperand &Offset,
428 ISD::MemIndexedMode &AM,
433 //===--------------------------------------------------------------------===//
434 // TargetLowering Optimization Methods
437 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
438 /// SDOperands for returning information from TargetLowering to its clients
439 /// that want to combine
440 struct TargetLoweringOpt {
445 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
447 bool CombineTo(SDOperand O, SDOperand N) {
453 /// ShrinkDemandedConstant - Check to see if the specified operand of the
454 /// specified instruction is a constant integer. If so, check to see if there
455 /// are any bits set in the constant that are not demanded. If so, shrink the
456 /// constant and return true.
457 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
460 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
461 /// use this predicate to simplify operations downstream. Op and Mask are
462 /// known to be the same type.
463 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
466 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
467 /// known to be either zero or one and return them in the KnownZero/KnownOne
468 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
469 /// processing. Targets can implement the computeMaskedBitsForTargetNode
470 /// method, to allow target nodes to be understood.
471 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
472 uint64_t &KnownOne, unsigned Depth = 0) const;
474 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
475 /// DemandedMask bits of the result of Op are ever used downstream. If we can
476 /// use this information to simplify Op, create a new simplified DAG node and
477 /// return true, returning the original and new nodes in Old and New.
478 /// Otherwise, analyze the expression and return a mask of KnownOne and
479 /// KnownZero bits for the expression (used to simplify the caller).
480 /// The KnownZero/One bits may only be accurate for those bits in the
482 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
483 uint64_t &KnownZero, uint64_t &KnownOne,
484 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
486 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
487 /// Mask are known to be either zero or one and return them in the
488 /// KnownZero/KnownOne bitsets.
489 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
493 unsigned Depth = 0) const;
495 /// ComputeNumSignBits - Return the number of times the sign bit of the
496 /// register is replicated into the other bits. We know that at least 1 bit
497 /// is always equal to the sign bit (itself), but other cases can give us
498 /// information. For example, immediately after an "SRA X, 2", we know that
499 /// the top 3 bits are all equal to each other, so we return 3.
500 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
502 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
503 /// targets that want to expose additional information about sign bits to the
505 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
506 unsigned Depth = 0) const;
508 struct DAGCombinerInfo {
509 void *DC; // The DAG Combiner object.
514 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
515 : DC(dc), BeforeLegalize(bl), DAG(dag) {}
517 bool isBeforeLegalize() const { return BeforeLegalize; }
519 void AddToWorklist(SDNode *N);
520 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
521 SDOperand CombineTo(SDNode *N, SDOperand Res);
522 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
525 /// PerformDAGCombine - This method will be invoked for all target nodes and
526 /// for any target-independent nodes that the target has registered with
529 /// The semantics are as follows:
531 /// SDOperand.Val == 0 - No change was made
532 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
533 /// otherwise - N should be replaced by the returned Operand.
535 /// In addition, methods provided by DAGCombinerInfo may be used to perform
536 /// more complex transformations.
538 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
540 //===--------------------------------------------------------------------===//
541 // TargetLowering Configuration Methods - These methods should be invoked by
542 // the derived class constructor to configure this object for the target.
546 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
547 /// GOT for PC-relative code.
548 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
550 /// setShiftAmountType - Describe the type that should be used for shift
551 /// amounts. This type defaults to the pointer type.
552 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
554 /// setSetCCResultType - Describe the type that shoudl be used as the result
555 /// of a setcc operation. This defaults to the pointer type.
556 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
558 /// setSetCCResultContents - Specify how the target extends the result of a
559 /// setcc operation in a register.
560 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
562 /// setSchedulingPreference - Specify the target scheduling preference.
563 void setSchedulingPreference(SchedPreference Pref) {
564 SchedPreferenceInfo = Pref;
567 /// setShiftAmountFlavor - Describe how the target handles out of range shift
569 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
570 ShiftAmtHandling = OORSA;
573 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
574 /// use _setjmp to implement llvm.setjmp or the non _ version.
575 /// Defaults to false.
576 void setUseUnderscoreSetJmp(bool Val) {
577 UseUnderscoreSetJmp = Val;
580 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
581 /// use _longjmp to implement llvm.longjmp or the non _ version.
582 /// Defaults to false.
583 void setUseUnderscoreLongJmp(bool Val) {
584 UseUnderscoreLongJmp = Val;
587 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
588 /// specifies the register that llvm.savestack/llvm.restorestack should save
590 void setStackPointerRegisterToSaveRestore(unsigned R) {
591 StackPointerRegisterToSaveRestore = R;
594 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
595 /// setcc as a conditional branch. This encourages the code generator to fold
596 /// setcc operations into other operations if possible.
597 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
599 /// setIntDivIsCheap - Tells the code generator that integer divide is
600 /// expensive, and if possible, should be replaced by an alternate sequence
601 /// of instructions not containing an integer divide.
602 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
604 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
605 /// srl/add/sra for a signed divide by power of two, and let the target handle
607 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
609 /// addRegisterClass - Add the specified register class as an available
610 /// regclass for the specified value type. This indicates the selector can
611 /// handle values of that class natively.
612 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
613 AvailableRegClasses.push_back(std::make_pair(VT, RC));
614 RegClassForVT[VT] = RC;
617 /// computeRegisterProperties - Once all of the register classes are added,
618 /// this allows us to compute derived properties we expose.
619 void computeRegisterProperties();
621 /// setOperationAction - Indicate that the specified operation does not work
622 /// with the specified type and indicate what to do about it.
623 void setOperationAction(unsigned Op, MVT::ValueType VT,
624 LegalizeAction Action) {
625 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
626 "Table isn't big enough!");
627 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
628 OpActions[Op] |= (uint64_t)Action << VT*2;
631 /// setLoadXAction - Indicate that the specified load with extension does not
632 /// work with the with specified type and indicate what to do about it.
633 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
634 LegalizeAction Action) {
635 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
636 "Table isn't big enough!");
637 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
638 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
641 /// setStoreXAction - Indicate that the specified store with truncation does
642 /// not work with the with specified type and indicate what to do about it.
643 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
644 assert(VT < 32 && "Table isn't big enough!");
645 StoreXActions &= ~(uint64_t(3UL) << VT*2);
646 StoreXActions |= (uint64_t)Action << VT*2;
649 /// setIndexedLoadAction - Indicate that the specified indexed load does or
650 /// does not work with the with specified type and indicate what to do abort
651 /// it. NOTE: All indexed mode loads are initialized to Expand in
652 /// TargetLowering.cpp
653 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
654 LegalizeAction Action) {
655 assert(VT < 32 && IdxMode <
656 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) &&
657 "Table isn't big enough!");
658 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
659 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
662 /// setIndexedStoreAction - Indicate that the specified indexed store does or
663 /// does not work with the with specified type and indicate what to do about
664 /// it. NOTE: All indexed mode stores are initialized to Expand in
665 /// TargetLowering.cpp
666 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
667 LegalizeAction Action) {
668 assert(VT < 32 && IdxMode <
669 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) &&
670 "Table isn't big enough!");
671 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
672 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
675 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
676 /// promotion code defaults to trying a larger integer/fp until it can find
677 /// one that works. If that default is insufficient, this method can be used
678 /// by the target to override the default.
679 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
680 MVT::ValueType DestVT) {
681 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
684 /// addLegalFPImmediate - Indicate that this target can instruction select
685 /// the specified FP immediate natively.
686 void addLegalFPImmediate(double Imm) {
687 LegalFPImmediates.push_back(Imm);
690 /// setTargetDAGCombine - Targets should invoke this method for each target
691 /// independent node that they want to provide a custom DAG combiner for by
692 /// implementing the PerformDAGCombine virtual method.
693 void setTargetDAGCombine(ISD::NodeType NT) {
694 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
697 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
698 /// bytes); default is 200
699 void setJumpBufSize(unsigned Size) {
703 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
704 /// alignment (in bytes); default is 0
705 void setJumpBufAlignment(unsigned Align) {
706 JumpBufAlignment = Align;
711 //===--------------------------------------------------------------------===//
712 // Lowering methods - These methods must be implemented by targets so that
713 // the SelectionDAGLowering code knows how to lower these.
716 /// LowerArguments - This hook must be implemented to indicate how we should
717 /// lower the arguments for the specified function, into the specified DAG.
718 virtual std::vector<SDOperand>
719 LowerArguments(Function &F, SelectionDAG &DAG);
721 /// LowerCallTo - This hook lowers an abstract call to a function into an
722 /// actual call. This returns a pair of operands. The first element is the
723 /// return value for the function (if RetTy is not VoidTy). The second
724 /// element is the outgoing token chain.
725 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
726 virtual std::pair<SDOperand, SDOperand>
727 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
728 unsigned CallingConv, bool isTailCall, SDOperand Callee,
729 ArgListTy &Args, SelectionDAG &DAG);
731 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
732 /// llvm.frameaddress (depending on the value of the first argument). The
733 /// return values are the result pointer and the resultant token chain. If
734 /// not implemented, both of these intrinsics will return null.
735 virtual std::pair<SDOperand, SDOperand>
736 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
739 /// LowerOperation - This callback is invoked for operations that are
740 /// unsupported by the target, which are registered to use 'custom' lowering,
741 /// and whose defined values are all legal.
742 /// If the target has no operations that require custom lowering, it need not
743 /// implement this. The default implementation of this aborts.
744 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
746 /// CustomPromoteOperation - This callback is invoked for operations that are
747 /// unsupported by the target, are registered to use 'custom' lowering, and
748 /// whose type needs to be promoted.
749 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
751 /// getTargetNodeName() - This method returns the name of a target specific
753 virtual const char *getTargetNodeName(unsigned Opcode) const;
755 //===--------------------------------------------------------------------===//
756 // Inline Asm Support hooks
759 enum ConstraintType {
760 C_Register, // Constraint represents a single register.
761 C_RegisterClass, // Constraint represents one or more registers.
762 C_Memory, // Memory constraint.
763 C_Other, // Something else.
764 C_Unknown // Unsupported constraint.
767 /// getConstraintType - Given a constraint letter, return the type of
768 /// constraint it is for this target.
769 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
772 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
773 /// return a list of registers that can be used to satisfy the constraint.
774 /// This should only be used for C_RegisterClass constraints.
775 virtual std::vector<unsigned>
776 getRegClassForInlineAsmConstraint(const std::string &Constraint,
777 MVT::ValueType VT) const;
779 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
780 /// {edx}), return the register number and the register class for the
783 /// Given a register class constraint, like 'r', if this corresponds directly
784 /// to an LLVM register class, return a register of 0 and the register class
787 /// This should only be used for C_Register constraints. On error,
788 /// this returns a register number of 0 and a null register class pointer..
789 virtual std::pair<unsigned, const TargetRegisterClass*>
790 getRegForInlineAsmConstraint(const std::string &Constraint,
791 MVT::ValueType VT) const;
794 /// isOperandValidForConstraint - Return the specified operand (possibly
795 /// modified) if the specified SDOperand is valid for the specified target
796 /// constraint letter, otherwise return null.
798 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
801 //===--------------------------------------------------------------------===//
805 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
806 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
807 // instructions are special in various ways, which require special support to
808 // insert. The specified MachineInstr is created but not inserted into any
809 // basic blocks, and the scheduler passes ownership of it to this method.
810 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
811 MachineBasicBlock *MBB);
813 //===--------------------------------------------------------------------===//
814 // Loop Strength Reduction hooks
817 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
818 /// can be used as the offset of the target addressing mode.
819 virtual bool isLegalAddressImmediate(int64_t V) const;
820 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
822 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator;
823 legal_am_scale_iterator legal_am_scale_begin() const {
824 return LegalAddressScales.begin();
826 legal_am_scale_iterator legal_am_scale_end() const {
827 return LegalAddressScales.end();
830 //===--------------------------------------------------------------------===//
831 // Div utility functions
833 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
834 std::vector<SDNode*>* Created) const;
835 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
836 std::vector<SDNode*>* Created) const;
840 /// addLegalAddressScale - Add a integer (> 1) value which can be used as
841 /// scale in the target addressing mode. Note: the ordering matters so the
842 /// least efficient ones should be entered first.
843 void addLegalAddressScale(unsigned Scale) {
844 LegalAddressScales.push_back(Scale);
848 std::vector<unsigned> LegalAddressScales;
851 const TargetData *TD;
853 /// IsLittleEndian - True if this is a little endian target.
857 /// PointerTy - The type to use for pointers, usually i32 or i64.
859 MVT::ValueType PointerTy;
861 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
863 bool UsesGlobalOffsetTable;
865 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
867 MVT::ValueType ShiftAmountTy;
869 OutOfRangeShiftAmount ShiftAmtHandling;
871 /// SetCCIsExpensive - This is a short term hack for targets that codegen
872 /// setcc as a conditional branch. This encourages the code generator to fold
873 /// setcc operations into other operations if possible.
874 bool SetCCIsExpensive;
876 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
877 /// constants into a sequence of muls, adds, and shifts. This is a hack until
878 /// a real cost model is in place. If we ever optimize for size, this will be
879 /// set to true unconditionally.
882 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
883 /// srl/add/sra for a signed divide by power of two, and let the target handle
887 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
889 MVT::ValueType SetCCResultTy;
891 /// SetCCResultContents - Information about the contents of the high-bits in
892 /// the result of a setcc comparison operation.
893 SetCCResultValue SetCCResultContents;
895 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
896 /// total cycles or lowest register usage.
897 SchedPreference SchedPreferenceInfo;
899 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
900 /// llvm.setjmp. Defaults to false.
901 bool UseUnderscoreSetJmp;
903 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
904 /// llvm.longjmp. Defaults to false.
905 bool UseUnderscoreLongJmp;
907 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
908 unsigned JumpBufSize;
910 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
912 unsigned JumpBufAlignment;
914 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
915 /// specifies the register that llvm.savestack/llvm.restorestack should save
917 unsigned StackPointerRegisterToSaveRestore;
919 /// RegClassForVT - This indicates the default register class to use for
920 /// each ValueType the target supports natively.
921 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
922 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
924 /// TransformToType - For any value types we are promoting or expanding, this
925 /// contains the value type that we are changing to. For Expanded types, this
926 /// contains one step of the expand (e.g. i64 -> i32), even if there are
927 /// multiple steps required (e.g. i64 -> i16). For types natively supported
928 /// by the system, this holds the same type (e.g. i32 -> i32).
929 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
931 /// OpActions - For each operation and each value type, keep a LegalizeAction
932 /// that indicates how instruction selection should deal with the operation.
933 /// Most operations are Legal (aka, supported natively by the target), but
934 /// operations that are not should be described. Note that operations on
935 /// non-legal value types are not described here.
936 uint64_t OpActions[156];
938 /// LoadXActions - For each load of load extension type and each value type,
939 /// keep a LegalizeAction that indicates how instruction selection should deal
941 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
943 /// StoreXActions - For each store with truncation of each value type, keep a
944 /// LegalizeAction that indicates how instruction selection should deal with
946 uint64_t StoreXActions;
948 /// IndexedModeActions - For each indexed mode and each value type, keep a
949 /// pair of LegalizeAction that indicates how instruction selection should
950 /// deal with the load / store.
951 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
953 ValueTypeActionImpl ValueTypeActions;
955 std::vector<double> LegalFPImmediates;
957 std::vector<std::pair<MVT::ValueType,
958 TargetRegisterClass*> > AvailableRegClasses;
960 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
961 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
962 /// which sets a bit in this array.
963 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
965 /// PromoteToType - For operations that must be promoted to a specific type,
966 /// this holds the destination type. This map should be sparse, so don't hold
969 /// Targets add entries to this map with AddPromotedToType(..), clients access
970 /// this with getTypeToPromoteTo(..).
971 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
974 /// When lowering %llvm.memset this field specifies the maximum number of
975 /// store operations that may be substituted for the call to memset. Targets
976 /// must set this value based on the cost threshold for that target. Targets
977 /// should assume that the memset will be done using as many of the largest
978 /// store operations first, followed by smaller ones, if necessary, per
979 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
980 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
981 /// store. This only applies to setting a constant array of a constant size.
982 /// @brief Specify maximum number of store instructions per memset call.
983 unsigned maxStoresPerMemset;
985 /// When lowering %llvm.memcpy this field specifies the maximum number of
986 /// store operations that may be substituted for a call to memcpy. Targets
987 /// must set this value based on the cost threshold for that target. Targets
988 /// should assume that the memcpy will be done using as many of the largest
989 /// store operations first, followed by smaller ones, if necessary, per
990 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
991 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
992 /// and one 1-byte store. This only applies to copying a constant array of
994 /// @brief Specify maximum bytes of store instructions per memcpy call.
995 unsigned maxStoresPerMemcpy;
997 /// When lowering %llvm.memmove this field specifies the maximum number of
998 /// store instructions that may be substituted for a call to memmove. Targets
999 /// must set this value based on the cost threshold for that target. Targets
1000 /// should assume that the memmove will be done using as many of the largest
1001 /// store operations first, followed by smaller ones, if necessary, per
1002 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1003 /// with 8-bit alignment would result in nine 1-byte stores. This only
1004 /// applies to copying a constant array of constant size.
1005 /// @brief Specify maximum bytes of store instructions per memmove call.
1006 unsigned maxStoresPerMemmove;
1008 /// This field specifies whether the target machine permits unaligned memory
1009 /// accesses. This is used, for example, to determine the size of store
1010 /// operations when copying small arrays and other similar tasks.
1011 /// @brief Indicate whether the target permits unaligned memory accesses.
1012 bool allowUnalignedMemoryAccesses;
1014 } // end llvm namespace