1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/IRBuilder.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
46 class FunctionLoweringInfo;
47 class ImmutableCallSite;
49 class MachineBasicBlock;
50 class MachineFunction;
52 class MachineJumpTableInfo;
57 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLibraryInfo;
61 class TargetLoweringObjectFile;
66 None, // No preference
67 Source, // Follow source order.
68 RegPressure, // Scheduling for lowest register pressure.
69 Hybrid, // Scheduling for both latency and register pressure.
70 ILP, // Scheduling for ILP in low register pressure mode.
71 VLIW // Scheduling for VLIW targets.
75 /// This base class for TargetLowering contains the SelectionDAG-independent
76 /// parts that can be used from the rest of CodeGen.
77 class TargetLoweringBase {
78 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
79 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
82 /// This enum indicates whether operations are valid for a target, and if not,
83 /// what action should be used to make them valid.
85 Legal, // The target natively supports this operation.
86 Promote, // This operation should be executed in a larger type.
87 Expand, // Try to expand this to other ops, otherwise use a libcall.
88 Custom // Use the LowerOperation hook to implement custom lowering.
91 /// This enum indicates whether a types are legal for a target, and if not,
92 /// what action should be used to make them valid.
93 enum LegalizeTypeAction {
94 TypeLegal, // The target natively supports this type.
95 TypePromoteInteger, // Replace this integer with a larger one.
96 TypeExpandInteger, // Split this integer into two of half the size.
97 TypeSoftenFloat, // Convert this float to a same size integer type.
98 TypeExpandFloat, // Split this float into two of half the size.
99 TypeScalarizeVector, // Replace this one-element vector with its element.
100 TypeSplitVector, // Split this vector into two of half the size.
101 TypeWidenVector // This vector should be widened into a larger vector.
104 /// LegalizeKind holds the legalization kind that needs to happen to EVT
105 /// in order to type-legalize it.
106 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
108 /// Enum that describes how the target represents true/false values.
109 enum BooleanContent {
110 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
111 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
112 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
115 /// Enum that describes what type of support for selects the target has.
116 enum SelectSupportKind {
117 ScalarValSelect, // The target supports scalar selects (ex: cmov).
118 ScalarCondVectorVal, // The target supports selects with a scalar condition
119 // and vector values (ex: cmov).
120 VectorMaskSelect // The target supports vector selects with a vector
121 // mask (ex: x86 blends).
124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
126 case UndefinedBooleanContent:
127 // Extend by adding rubbish bits.
128 return ISD::ANY_EXTEND;
129 case ZeroOrOneBooleanContent:
130 // Extend by adding zero bits.
131 return ISD::ZERO_EXTEND;
132 case ZeroOrNegativeOneBooleanContent:
133 // Extend by copying the sign bit.
134 return ISD::SIGN_EXTEND;
136 llvm_unreachable("Invalid content kind");
139 /// NOTE: The constructor takes ownership of TLOF.
140 explicit TargetLoweringBase(const TargetMachine &TM,
141 const TargetLoweringObjectFile *TLOF);
142 virtual ~TargetLoweringBase();
145 /// \brief Initialize all of the actions to default values.
149 const TargetMachine &getTargetMachine() const { return TM; }
150 const DataLayout *getDataLayout() const { return DL; }
151 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
153 bool isBigEndian() const { return !IsLittleEndian; }
154 bool isLittleEndian() const { return IsLittleEndian; }
156 /// Return the pointer type for the given address space, defaults to
157 /// the pointer type from the data layout.
158 /// FIXME: The default needs to be removed once all the code is updated.
159 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
160 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
161 unsigned getPointerTypeSizeInBits(Type *Ty) const;
162 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
164 EVT getShiftAmountTy(EVT LHSTy) const;
166 /// Returns the type to be used for the index operand of:
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
169 virtual MVT getVectorIdxTy() const {
170 return getPointerTy();
173 /// Return true if the select operation is expensive for this target.
174 bool isSelectExpensive() const { return SelectIsExpensive; }
176 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
180 /// Return true if multiple condition registers are available.
181 bool hasMultipleConditionRegisters() const {
182 return HasMultipleConditionRegisters;
185 /// Return true if the target has BitExtract instructions.
186 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
188 /// Return true if a vector of the given type should be split
189 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
191 virtual bool shouldSplitVectorType(EVT /*VT*/) const { return false; }
193 // There are two general methods for expanding a BUILD_VECTOR node:
194 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
196 // 2. Build the vector on the stack and then load it.
197 // If this function returns true, then method (1) will be used, subject to
198 // the constraint that all of the necessary shuffles are legal (as determined
199 // by isShuffleMaskLegal). If this function returns false, then method (2) is
200 // always used. The vector type, and the number of defined values, are
203 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
204 unsigned DefinedValues) const {
205 return DefinedValues < 3;
208 /// Return true if integer divide is usually cheaper than a sequence of
209 /// several shifts, adds, and multiplies for this target.
210 bool isIntDivCheap() const { return IntDivIsCheap; }
212 /// Returns true if target has indicated at least one type should be bypassed.
213 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
215 /// Returns map of slow types for division or remainder with corresponding
217 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
218 return BypassSlowDivWidths;
221 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
222 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
224 /// Return true if Flow Control is an expensive operation that should be
226 bool isJumpExpensive() const { return JumpIsExpensive; }
228 /// Return true if selects are only cheaper than branches if the branch is
229 /// unlikely to be predicted right.
230 bool isPredictableSelectExpensive() const {
231 return PredictableSelectIsExpensive;
234 /// isLoadBitCastBeneficial() - Return true if the following transform
236 /// fold (conv (load x)) -> (load (conv*)x)
237 /// On architectures that don't natively support some vector loads efficiently,
238 /// casting the load to a smaller vector of larger types and loading
239 /// is more efficient, however, this can be undone by optimizations in
241 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
245 /// \brief Return if the target supports combining a
248 /// %andResult = and %val1, #imm-with-one-bit-set;
249 /// %icmpResult = icmp %andResult, 0
250 /// br i1 %icmpResult, label %dest1, label %dest2
252 /// into a single machine instruction of a form like:
254 /// brOnBitSet %register, #bitNumber, dest
256 bool isMaskAndBranchFoldingLegal() const {
257 return MaskAndBranchFoldingIsLegal;
260 /// Return the ValueType of the result of SETCC operations. Also used to
261 /// obtain the target's preferred type for the condition operand of SELECT and
262 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
263 /// since there are no other operands to get a type hint from.
264 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
266 /// Return the ValueType for comparison libcalls. Comparions libcalls include
267 /// floating point comparion calls, and Ordered/Unordered check calls on
268 /// floating point numbers.
270 MVT::SimpleValueType getCmpLibcallReturnType() const;
272 /// For targets without i1 registers, this gives the nature of the high-bits
273 /// of boolean values held in types wider than i1.
275 /// "Boolean values" are special true/false values produced by nodes like
276 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
277 /// Not to be confused with general values promoted from i1. Some cpus
278 /// distinguish between vectors of boolean and scalars; the isVec parameter
279 /// selects between the two kinds. For example on X86 a scalar boolean should
280 /// be zero extended from i1, while the elements of a vector of booleans
281 /// should be sign extended from i1.
282 BooleanContent getBooleanContents(bool isVec) const {
283 return isVec ? BooleanVectorContents : BooleanContents;
286 /// Return target scheduling preference.
287 Sched::Preference getSchedulingPreference() const {
288 return SchedPreferenceInfo;
291 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
292 /// for different nodes. This function returns the preference (or none) for
294 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
298 /// Return the register class that should be used for the specified value
300 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
301 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
302 assert(RC && "This value type is not natively supported!");
306 /// Return the 'representative' register class for the specified value
309 /// The 'representative' register class is the largest legal super-reg
310 /// register class for the register class of the value type. For example, on
311 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
312 /// register class is GR64 on x86_64.
313 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
314 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
318 /// Return the cost of the 'representative' register class for the specified
320 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
321 return RepRegClassCostForVT[VT.SimpleTy];
324 /// Return true if the target has native support for the specified value type.
325 /// This means that it has a register that directly holds it without
326 /// promotions or expansions.
327 bool isTypeLegal(EVT VT) const {
328 assert(!VT.isSimple() ||
329 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
330 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
333 class ValueTypeActionImpl {
334 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
335 /// that indicates how instruction selection should deal with the type.
336 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
339 ValueTypeActionImpl() {
340 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
343 LegalizeTypeAction getTypeAction(MVT VT) const {
344 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
347 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
348 unsigned I = VT.SimpleTy;
349 ValueTypeActions[I] = Action;
353 const ValueTypeActionImpl &getValueTypeActions() const {
354 return ValueTypeActions;
357 /// Return how we should legalize values of this type, either it is already
358 /// legal (return 'Legal') or we need to promote it to a larger type (return
359 /// 'Promote'), or we need to expand it into multiple registers of smaller
360 /// integer type (return 'Expand'). 'Custom' is not an option.
361 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
362 return getTypeConversion(Context, VT).first;
364 LegalizeTypeAction getTypeAction(MVT VT) const {
365 return ValueTypeActions.getTypeAction(VT);
368 /// For types supported by the target, this is an identity function. For
369 /// types that must be promoted to larger types, this returns the larger type
370 /// to promote to. For integer types that are larger than the largest integer
371 /// register, this contains one step in the expansion to get to the smaller
372 /// register. For illegal floating point types, this returns the integer type
374 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
375 return getTypeConversion(Context, VT).second;
378 /// For types supported by the target, this is an identity function. For
379 /// types that must be expanded (i.e. integer types that are larger than the
380 /// largest integer register or illegal floating point types), this returns
381 /// the largest legal type it will be expanded to.
382 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
383 assert(!VT.isVector());
385 switch (getTypeAction(Context, VT)) {
388 case TypeExpandInteger:
389 VT = getTypeToTransformTo(Context, VT);
392 llvm_unreachable("Type is not legal nor is it to be expanded!");
397 /// Vector types are broken down into some number of legal first class types.
398 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
399 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
400 /// turns into 4 EVT::i32 values with both PPC and X86.
402 /// This method returns the number of registers needed, and the VT for each
403 /// register. It also returns the VT and quantity of the intermediate values
404 /// before they are promoted/expanded.
405 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
407 unsigned &NumIntermediates,
408 MVT &RegisterVT) const;
410 struct IntrinsicInfo {
411 unsigned opc; // target opcode
412 EVT memVT; // memory VT
413 const Value* ptrVal; // value representing memory location
414 int offset; // offset off of ptrVal
415 unsigned align; // alignment
416 bool vol; // is volatile?
417 bool readMem; // reads memory?
418 bool writeMem; // writes memory?
421 /// Given an intrinsic, checks if on the target the intrinsic will need to map
422 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
423 /// true and store the intrinsic information into the IntrinsicInfo that was
424 /// passed to the function.
425 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
426 unsigned /*Intrinsic*/) const {
430 /// Returns true if the target can instruction select the specified FP
431 /// immediate natively. If false, the legalizer will materialize the FP
432 /// immediate as a load from a constant pool.
433 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
437 /// Targets can use this to indicate that they only support *some*
438 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
439 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
441 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
446 /// Returns true if the operation can trap for the value type.
448 /// VT must be a legal type. By default, we optimistically assume most
449 /// operations don't trap except for divide and remainder.
450 virtual bool canOpTrap(unsigned Op, EVT VT) const;
452 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
453 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
454 /// a VAND with a constant pool entry.
455 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
460 /// Return how this operation should be treated: either it is legal, needs to
461 /// be promoted to a larger size, needs to be expanded to some other code
462 /// sequence, or the target has a custom expander for it.
463 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
464 if (VT.isExtended()) return Expand;
465 // If a target-specific SDNode requires legalization, require the target
466 // to provide custom legalization for it.
467 if (Op > array_lengthof(OpActions[0])) return Custom;
468 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
469 return (LegalizeAction)OpActions[I][Op];
472 /// Return true if the specified operation is legal on this target or can be
473 /// made legal with custom lowering. This is used to help guide high-level
474 /// lowering decisions.
475 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
476 return (VT == MVT::Other || isTypeLegal(VT)) &&
477 (getOperationAction(Op, VT) == Legal ||
478 getOperationAction(Op, VT) == Custom);
481 /// Return true if the specified operation is legal on this target or can be
482 /// made legal using promotion. This is used to help guide high-level lowering
484 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
485 return (VT == MVT::Other || isTypeLegal(VT)) &&
486 (getOperationAction(Op, VT) == Legal ||
487 getOperationAction(Op, VT) == Promote);
490 /// Return true if the specified operation is illegal on this target or
491 /// unlikely to be made legal with custom lowering. This is used to help guide
492 /// high-level lowering decisions.
493 bool isOperationExpand(unsigned Op, EVT VT) const {
494 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
497 /// Return true if the specified operation is legal on this target.
498 bool isOperationLegal(unsigned Op, EVT VT) const {
499 return (VT == MVT::Other || isTypeLegal(VT)) &&
500 getOperationAction(Op, VT) == Legal;
503 /// Return how this load with extension should be treated: either it is legal,
504 /// needs to be promoted to a larger size, needs to be expanded to some other
505 /// code sequence, or the target has a custom expander for it.
506 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
507 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
508 "Table isn't big enough!");
509 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
512 /// Return true if the specified load with extension is legal on this target.
513 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
514 return VT.isSimple() &&
515 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
518 /// Return how this store with truncation should be treated: either it is
519 /// legal, needs to be promoted to a larger size, needs to be expanded to some
520 /// other code sequence, or the target has a custom expander for it.
521 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
522 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
523 "Table isn't big enough!");
524 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
528 /// Return true if the specified store with truncation is legal on this
530 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
531 return isTypeLegal(ValVT) && MemVT.isSimple() &&
532 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
535 /// Return how the indexed load should be treated: either it is legal, needs
536 /// to be promoted to a larger size, needs to be expanded to some other code
537 /// sequence, or the target has a custom expander for it.
539 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
540 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
541 "Table isn't big enough!");
542 unsigned Ty = (unsigned)VT.SimpleTy;
543 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
546 /// Return true if the specified indexed load is legal on this target.
547 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
548 return VT.isSimple() &&
549 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
550 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
553 /// Return how the indexed store should be treated: either it is legal, needs
554 /// to be promoted to a larger size, needs to be expanded to some other code
555 /// sequence, or the target has a custom expander for it.
557 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
558 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
559 "Table isn't big enough!");
560 unsigned Ty = (unsigned)VT.SimpleTy;
561 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
564 /// Return true if the specified indexed load is legal on this target.
565 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
566 return VT.isSimple() &&
567 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
568 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
571 /// Return how the condition code should be treated: either it is legal, needs
572 /// to be expanded to some other code sequence, or the target has a custom
575 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
576 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
577 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
578 "Table isn't big enough!");
579 // See setCondCodeAction for how this is encoded.
580 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
581 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
582 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
583 assert(Action != Promote && "Can't promote condition code!");
587 /// Return true if the specified condition code is legal on this target.
588 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
590 getCondCodeAction(CC, VT) == Legal ||
591 getCondCodeAction(CC, VT) == Custom;
595 /// If the action for this operation is to promote, this method returns the
596 /// ValueType to promote to.
597 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
598 assert(getOperationAction(Op, VT) == Promote &&
599 "This operation isn't promoted!");
601 // See if this has an explicit type specified.
602 std::map<std::pair<unsigned, MVT::SimpleValueType>,
603 MVT::SimpleValueType>::const_iterator PTTI =
604 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
605 if (PTTI != PromoteToType.end()) return PTTI->second;
607 assert((VT.isInteger() || VT.isFloatingPoint()) &&
608 "Cannot autopromote this type, add it with AddPromotedToType.");
612 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
613 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
614 "Didn't find type to promote to!");
615 } while (!isTypeLegal(NVT) ||
616 getOperationAction(Op, NVT) == Promote);
620 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
621 /// operations except for the pointer size. If AllowUnknown is true, this
622 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
623 /// otherwise it will assert.
624 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
625 // Lower scalar pointers to native pointer types.
626 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
627 return getPointerTy(PTy->getAddressSpace());
629 if (Ty->isVectorTy()) {
630 VectorType *VTy = cast<VectorType>(Ty);
631 Type *Elm = VTy->getElementType();
632 // Lower vectors of pointers to native pointer types.
633 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
634 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
635 Elm = PointerTy.getTypeForEVT(Ty->getContext());
638 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
639 VTy->getNumElements());
641 return EVT::getEVT(Ty, AllowUnknown);
644 /// Return the MVT corresponding to this LLVM type. See getValueType.
645 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
646 return getValueType(Ty, AllowUnknown).getSimpleVT();
649 /// Return the desired alignment for ByVal or InAlloca aggregate function
650 /// arguments in the caller parameter area. This is the actual alignment, not
652 virtual unsigned getByValTypeAlignment(Type *Ty) const;
654 /// Return the type of registers that this ValueType will eventually require.
655 MVT getRegisterType(MVT VT) const {
656 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
657 return RegisterTypeForVT[VT.SimpleTy];
660 /// Return the type of registers that this ValueType will eventually require.
661 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
663 assert((unsigned)VT.getSimpleVT().SimpleTy <
664 array_lengthof(RegisterTypeForVT));
665 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
670 unsigned NumIntermediates;
671 (void)getVectorTypeBreakdown(Context, VT, VT1,
672 NumIntermediates, RegisterVT);
675 if (VT.isInteger()) {
676 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
678 llvm_unreachable("Unsupported extended type!");
681 /// Return the number of registers that this ValueType will eventually
684 /// This is one for any types promoted to live in larger registers, but may be
685 /// more than one for types (like i64) that are split into pieces. For types
686 /// like i140, which are first promoted then expanded, it is the number of
687 /// registers needed to hold all the bits of the original type. For an i140
688 /// on a 32 bit machine this means 5 registers.
689 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
691 assert((unsigned)VT.getSimpleVT().SimpleTy <
692 array_lengthof(NumRegistersForVT));
693 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
698 unsigned NumIntermediates;
699 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
701 if (VT.isInteger()) {
702 unsigned BitWidth = VT.getSizeInBits();
703 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
704 return (BitWidth + RegWidth - 1) / RegWidth;
706 llvm_unreachable("Unsupported extended type!");
709 /// If true, then instruction selection should seek to shrink the FP constant
710 /// of the specified type to a smaller type in order to save space and / or
712 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
714 /// If true, the target has custom DAG combine transformations that it can
715 /// perform for the specified node.
716 bool hasTargetDAGCombine(ISD::NodeType NT) const {
717 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
718 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
721 /// \brief Get maximum # of store operations permitted for llvm.memset
723 /// This function returns the maximum number of store operations permitted
724 /// to replace a call to llvm.memset. The value is set by the target at the
725 /// performance threshold for such a replacement. If OptSize is true,
726 /// return the limit for functions that have OptSize attribute.
727 unsigned getMaxStoresPerMemset(bool OptSize) const {
728 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
731 /// \brief Get maximum # of store operations permitted for llvm.memcpy
733 /// This function returns the maximum number of store operations permitted
734 /// to replace a call to llvm.memcpy. The value is set by the target at the
735 /// performance threshold for such a replacement. If OptSize is true,
736 /// return the limit for functions that have OptSize attribute.
737 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
738 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
741 /// \brief Get maximum # of store operations permitted for llvm.memmove
743 /// This function returns the maximum number of store operations permitted
744 /// to replace a call to llvm.memmove. The value is set by the target at the
745 /// performance threshold for such a replacement. If OptSize is true,
746 /// return the limit for functions that have OptSize attribute.
747 unsigned getMaxStoresPerMemmove(bool OptSize) const {
748 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
751 /// \brief Determine if the target supports unaligned memory accesses.
753 /// This function returns true if the target allows unaligned memory accesses
754 /// of the specified type in the given address space. If true, it also returns
755 /// whether the unaligned memory access is "fast" in the third argument by
756 /// reference. This is used, for example, in situations where an array
757 /// copy/move/set is converted to a sequence of store operations. Its use
758 /// helps to ensure that such replacements don't generate code that causes an
759 /// alignment error (trap) on the target machine.
760 virtual bool allowsUnalignedMemoryAccesses(EVT,
761 unsigned AddrSpace = 0,
762 bool * /*Fast*/ = nullptr) const {
766 /// Returns the target specific optimal type for load and store operations as
767 /// a result of memset, memcpy, and memmove lowering.
769 /// If DstAlign is zero that means it's safe to destination alignment can
770 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
771 /// a need to check it against alignment requirement, probably because the
772 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
773 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
774 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
775 /// does not need to be loaded. It returns EVT::Other if the type should be
776 /// determined using generic target-independent logic.
777 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
778 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
781 bool /*MemcpyStrSrc*/,
782 MachineFunction &/*MF*/) const {
786 /// Returns true if it's safe to use load / store of the specified type to
787 /// expand memcpy / memset inline.
789 /// This is mostly true for all types except for some special cases. For
790 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
791 /// fstpl which also does type conversion. Note the specified type doesn't
792 /// have to be legal as the hook is used before type legalization.
793 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
795 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
796 bool usesUnderscoreSetJmp() const {
797 return UseUnderscoreSetJmp;
800 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
801 bool usesUnderscoreLongJmp() const {
802 return UseUnderscoreLongJmp;
805 /// Return whether the target can generate code for jump tables.
806 bool supportJumpTables() const {
807 return SupportJumpTables;
810 /// Return integer threshold on number of blocks to use jump tables rather
811 /// than if sequence.
812 int getMinimumJumpTableEntries() const {
813 return MinimumJumpTableEntries;
816 /// If a physical register, this specifies the register that
817 /// llvm.savestack/llvm.restorestack should save and restore.
818 unsigned getStackPointerRegisterToSaveRestore() const {
819 return StackPointerRegisterToSaveRestore;
822 /// If a physical register, this returns the register that receives the
823 /// exception address on entry to a landing pad.
824 unsigned getExceptionPointerRegister() const {
825 return ExceptionPointerRegister;
828 /// If a physical register, this returns the register that receives the
829 /// exception typeid on entry to a landing pad.
830 unsigned getExceptionSelectorRegister() const {
831 return ExceptionSelectorRegister;
834 /// Returns the target's jmp_buf size in bytes (if never set, the default is
836 unsigned getJumpBufSize() const {
840 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
842 unsigned getJumpBufAlignment() const {
843 return JumpBufAlignment;
846 /// Return the minimum stack alignment of an argument.
847 unsigned getMinStackArgumentAlignment() const {
848 return MinStackArgumentAlignment;
851 /// Return the minimum function alignment.
852 unsigned getMinFunctionAlignment() const {
853 return MinFunctionAlignment;
856 /// Return the preferred function alignment.
857 unsigned getPrefFunctionAlignment() const {
858 return PrefFunctionAlignment;
861 /// Return the preferred loop alignment.
862 unsigned getPrefLoopAlignment() const {
863 return PrefLoopAlignment;
866 /// Return whether the DAG builder should automatically insert fences and
867 /// reduce ordering for atomics.
868 bool getInsertFencesForAtomic() const {
869 return InsertFencesForAtomic;
872 /// Return true if the target stores stack protector cookies at a fixed offset
873 /// in some non-standard address space, and populates the address space and
874 /// offset as appropriate.
875 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
876 unsigned &/*Offset*/) const {
880 /// Returns the maximal possible offset which can be used for loads / stores
882 virtual unsigned getMaximalGlobalOffset() const {
886 /// Returns true if a cast between SrcAS and DestAS is a noop.
887 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
891 //===--------------------------------------------------------------------===//
892 /// \name Helpers for TargetTransformInfo implementations
895 /// Get the ISD node that corresponds to the Instruction class opcode.
896 int InstructionOpcodeToISD(unsigned Opcode) const;
898 /// Estimate the cost of type-legalization and the legalized type.
899 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
903 //===--------------------------------------------------------------------===//
904 /// \name Helpers for load-linked/store-conditional atomic expansion.
907 /// Perform a load-linked operation on Addr, returning a "Value *" with the
908 /// corresponding pointee type. This may entail some non-trivial operations to
909 /// truncate or reconstruct types that will be illegal in the backend. See
910 /// ARMISelLowering for an example implementation.
911 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
912 AtomicOrdering Ord) const {
913 llvm_unreachable("Load linked unimplemented on this target");
916 /// Perform a store-conditional operation to Addr. Return the status of the
917 /// store. This should be 0 if the store succeeded, non-zero otherwise.
918 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
919 Value *Addr, AtomicOrdering Ord) const {
920 llvm_unreachable("Store conditional unimplemented on this target");
923 /// Return true if the given (atomic) instruction should be expanded by the
924 /// IR-level AtomicExpandLoadLinked pass into a loop involving
925 /// load-linked/store-conditional pairs. Atomic stores will be expanded in the
926 /// same way as "atomic xchg" operations which ignore their output if needed.
927 virtual bool shouldExpandAtomicInIR(Instruction *Inst) const {
932 //===--------------------------------------------------------------------===//
933 // TargetLowering Configuration Methods - These methods should be invoked by
934 // the derived class constructor to configure this object for the target.
937 /// \brief Reset the operation actions based on target options.
938 virtual void resetOperationActions() {}
941 /// Specify how the target extends the result of a boolean value from i1 to a
942 /// wider type. See getBooleanContents.
943 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
945 /// Specify how the target extends the result of a vector boolean value from a
946 /// vector of i1 to a wider type. See getBooleanContents.
947 void setBooleanVectorContents(BooleanContent Ty) {
948 BooleanVectorContents = Ty;
951 /// Specify the target scheduling preference.
952 void setSchedulingPreference(Sched::Preference Pref) {
953 SchedPreferenceInfo = Pref;
956 /// Indicate whether this target prefers to use _setjmp to implement
957 /// llvm.setjmp or the version without _. Defaults to false.
958 void setUseUnderscoreSetJmp(bool Val) {
959 UseUnderscoreSetJmp = Val;
962 /// Indicate whether this target prefers to use _longjmp to implement
963 /// llvm.longjmp or the version without _. Defaults to false.
964 void setUseUnderscoreLongJmp(bool Val) {
965 UseUnderscoreLongJmp = Val;
968 /// Indicate whether the target can generate code for jump tables.
969 void setSupportJumpTables(bool Val) {
970 SupportJumpTables = Val;
973 /// Indicate the number of blocks to generate jump tables rather than if
975 void setMinimumJumpTableEntries(int Val) {
976 MinimumJumpTableEntries = Val;
979 /// If set to a physical register, this specifies the register that
980 /// llvm.savestack/llvm.restorestack should save and restore.
981 void setStackPointerRegisterToSaveRestore(unsigned R) {
982 StackPointerRegisterToSaveRestore = R;
985 /// If set to a physical register, this sets the register that receives the
986 /// exception address on entry to a landing pad.
987 void setExceptionPointerRegister(unsigned R) {
988 ExceptionPointerRegister = R;
991 /// If set to a physical register, this sets the register that receives the
992 /// exception typeid on entry to a landing pad.
993 void setExceptionSelectorRegister(unsigned R) {
994 ExceptionSelectorRegister = R;
997 /// Tells the code generator not to expand operations into sequences that use
998 /// the select operations if possible.
999 void setSelectIsExpensive(bool isExpensive = true) {
1000 SelectIsExpensive = isExpensive;
1003 /// Tells the code generator that the target has multiple (allocatable)
1004 /// condition registers that can be used to store the results of comparisons
1005 /// for use by selects and conditional branches. With multiple condition
1006 /// registers, the code generator will not aggressively sink comparisons into
1007 /// the blocks of their users.
1008 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1009 HasMultipleConditionRegisters = hasManyRegs;
1012 /// Tells the code generator that the target has BitExtract instructions.
1013 /// The code generator will aggressively sink "shift"s into the blocks of
1014 /// their users if the users will generate "and" instructions which can be
1015 /// combined with "shift" to BitExtract instructions.
1016 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1017 HasExtractBitsInsn = hasExtractInsn;
1020 /// Tells the code generator not to expand sequence of operations into a
1021 /// separate sequences that increases the amount of flow control.
1022 void setJumpIsExpensive(bool isExpensive = true) {
1023 JumpIsExpensive = isExpensive;
1026 /// Tells the code generator that integer divide is expensive, and if
1027 /// possible, should be replaced by an alternate sequence of instructions not
1028 /// containing an integer divide.
1029 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1031 /// Tells the code generator which bitwidths to bypass.
1032 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1033 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1036 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1037 /// signed divide by power of two, and let the target handle it.
1038 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1040 /// Add the specified register class as an available regclass for the
1041 /// specified value type. This indicates the selector can handle values of
1042 /// that class natively.
1043 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1044 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1045 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1046 RegClassForVT[VT.SimpleTy] = RC;
1049 /// Remove all register classes.
1050 void clearRegisterClasses() {
1051 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1053 AvailableRegClasses.clear();
1056 /// \brief Remove all operation actions.
1057 void clearOperationActions() {
1060 /// Return the largest legal super-reg register class of the register class
1061 /// for the specified type and its associated "cost".
1062 virtual std::pair<const TargetRegisterClass*, uint8_t>
1063 findRepresentativeClass(MVT VT) const;
1065 /// Once all of the register classes are added, this allows us to compute
1066 /// derived properties we expose.
1067 void computeRegisterProperties();
1069 /// Indicate that the specified operation does not work with the specified
1070 /// type and indicate what to do about it.
1071 void setOperationAction(unsigned Op, MVT VT,
1072 LegalizeAction Action) {
1073 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1074 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1077 /// Indicate that the specified load with extension does not work with the
1078 /// specified type and indicate what to do about it.
1079 void setLoadExtAction(unsigned ExtType, MVT VT,
1080 LegalizeAction Action) {
1081 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1082 "Table isn't big enough!");
1083 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1086 /// Indicate that the specified truncating store does not work with the
1087 /// specified type and indicate what to do about it.
1088 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1089 LegalizeAction Action) {
1090 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1091 "Table isn't big enough!");
1092 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1095 /// Indicate that the specified indexed load does or does not work with the
1096 /// specified type and indicate what to do abort it.
1098 /// NOTE: All indexed mode loads are initialized to Expand in
1099 /// TargetLowering.cpp
1100 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1101 LegalizeAction Action) {
1102 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1103 (unsigned)Action < 0xf && "Table isn't big enough!");
1104 // Load action are kept in the upper half.
1105 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1106 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1109 /// Indicate that the specified indexed store does or does not work with the
1110 /// specified type and indicate what to do about it.
1112 /// NOTE: All indexed mode stores are initialized to Expand in
1113 /// TargetLowering.cpp
1114 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1115 LegalizeAction Action) {
1116 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1117 (unsigned)Action < 0xf && "Table isn't big enough!");
1118 // Store action are kept in the lower half.
1119 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1120 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1123 /// Indicate that the specified condition code is or isn't supported on the
1124 /// target and indicate what to do about it.
1125 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1126 LegalizeAction Action) {
1127 assert(VT < MVT::LAST_VALUETYPE &&
1128 (unsigned)CC < array_lengthof(CondCodeActions) &&
1129 "Table isn't big enough!");
1130 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1131 /// value and the upper 27 bits index into the second dimension of the array
1132 /// to select what 32-bit value to use.
1133 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1134 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1135 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1138 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1139 /// to trying a larger integer/fp until it can find one that works. If that
1140 /// default is insufficient, this method can be used by the target to override
1142 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1143 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1146 /// Targets should invoke this method for each target independent node that
1147 /// they want to provide a custom DAG combiner for by implementing the
1148 /// PerformDAGCombine virtual method.
1149 void setTargetDAGCombine(ISD::NodeType NT) {
1150 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1151 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1154 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1155 void setJumpBufSize(unsigned Size) {
1159 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1161 void setJumpBufAlignment(unsigned Align) {
1162 JumpBufAlignment = Align;
1165 /// Set the target's minimum function alignment (in log2(bytes))
1166 void setMinFunctionAlignment(unsigned Align) {
1167 MinFunctionAlignment = Align;
1170 /// Set the target's preferred function alignment. This should be set if
1171 /// there is a performance benefit to higher-than-minimum alignment (in
1173 void setPrefFunctionAlignment(unsigned Align) {
1174 PrefFunctionAlignment = Align;
1177 /// Set the target's preferred loop alignment. Default alignment is zero, it
1178 /// means the target does not care about loop alignment. The alignment is
1179 /// specified in log2(bytes).
1180 void setPrefLoopAlignment(unsigned Align) {
1181 PrefLoopAlignment = Align;
1184 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1185 void setMinStackArgumentAlignment(unsigned Align) {
1186 MinStackArgumentAlignment = Align;
1189 /// Set if the DAG builder should automatically insert fences and reduce the
1190 /// order of atomic memory operations to Monotonic.
1191 void setInsertFencesForAtomic(bool fence) {
1192 InsertFencesForAtomic = fence;
1196 //===--------------------------------------------------------------------===//
1197 // Addressing mode description hooks (used by LSR etc).
1200 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1201 /// instructions reading the address. This allows as much computation as
1202 /// possible to be done in the address mode for that operand. This hook lets
1203 /// targets also pass back when this should be done on intrinsics which
1205 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1206 SmallVectorImpl<Value*> &/*Ops*/,
1207 Type *&/*AccessTy*/) const {
1211 /// This represents an addressing mode of:
1212 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1213 /// If BaseGV is null, there is no BaseGV.
1214 /// If BaseOffs is zero, there is no base offset.
1215 /// If HasBaseReg is false, there is no base register.
1216 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1219 GlobalValue *BaseGV;
1223 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1226 /// Return true if the addressing mode represented by AM is legal for this
1227 /// target, for a load/store of the specified type.
1229 /// The type may be VoidTy, in which case only return true if the addressing
1230 /// mode is legal for a load/store of any legal type. TODO: Handle
1231 /// pre/postinc as well.
1232 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1234 /// \brief Return the cost of the scaling factor used in the addressing mode
1235 /// represented by AM for this target, for a load/store of the specified type.
1237 /// If the AM is supported, the return value must be >= 0.
1238 /// If the AM is not supported, it returns a negative value.
1239 /// TODO: Handle pre/postinc as well.
1240 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1241 // Default: assume that any scaling factor used in a legal AM is free.
1242 if (isLegalAddressingMode(AM, Ty)) return 0;
1246 /// Return true if the specified immediate is legal icmp immediate, that is
1247 /// the target has icmp instructions which can compare a register against the
1248 /// immediate without having to materialize the immediate into a register.
1249 virtual bool isLegalICmpImmediate(int64_t) const {
1253 /// Return true if the specified immediate is legal add immediate, that is the
1254 /// target has add instructions which can add a register with the immediate
1255 /// without having to materialize the immediate into a register.
1256 virtual bool isLegalAddImmediate(int64_t) const {
1260 /// Return true if it's significantly cheaper to shift a vector by a uniform
1261 /// scalar than by an amount which will vary across each lane. On x86, for
1262 /// example, there is a "psllw" instruction for the former case, but no simple
1263 /// instruction for a general "a << b" operation on vectors.
1264 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1268 /// Return true if it's free to truncate a value of type Ty1 to type
1269 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1270 /// by referencing its sub-register AX.
1271 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1275 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1276 /// whether a call is in tail position. Typically this means that both results
1277 /// would be assigned to the same register or stack slot, but it could mean
1278 /// the target performs adequate checks of its own before proceeding with the
1280 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1284 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1288 /// Return true if any actual instruction that defines a value of type Ty1
1289 /// implicitly zero-extends the value to Ty2 in the result register.
1291 /// This does not necessarily include registers defined in unknown ways, such
1292 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1293 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1294 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1295 /// values implicit zero-extend the result out to 64 bits.
1296 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1300 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1304 /// Return true if the target supplies and combines to a paired load
1305 /// two loaded values of type LoadedType next to each other in memory.
1306 /// RequiredAlignment gives the minimal alignment constraints that must be met
1307 /// to be able to select this paired load.
1309 /// This information is *not* used to generate actual paired loads, but it is
1310 /// used to generate a sequence of loads that is easier to combine into a
1312 /// For instance, something like this:
1313 /// a = load i64* addr
1314 /// b = trunc i64 a to i32
1315 /// c = lshr i64 a, 32
1316 /// d = trunc i64 c to i32
1317 /// will be optimized into:
1318 /// b = load i32* addr1
1319 /// d = load i32* addr2
1320 /// Where addr1 = addr2 +/- sizeof(i32).
1322 /// In other words, unless the target performs a post-isel load combining,
1323 /// this information should not be provided because it will generate more
1325 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1326 unsigned & /*RequiredAligment*/) const {
1330 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1331 unsigned & /*RequiredAligment*/) const {
1335 /// Return true if zero-extending the specific node Val to type VT2 is free
1336 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1337 /// because it's folded such as X86 zero-extending loads).
1338 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1339 return isZExtFree(Val.getValueType(), VT2);
1342 /// Return true if an fneg operation is free to the point where it is never
1343 /// worthwhile to replace it with a bitwise operation.
1344 virtual bool isFNegFree(EVT VT) const {
1345 assert(VT.isFloatingPoint());
1349 /// Return true if an fabs operation is free to the point where it is never
1350 /// worthwhile to replace it with a bitwise operation.
1351 virtual bool isFAbsFree(EVT VT) const {
1352 assert(VT.isFloatingPoint());
1356 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1357 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1358 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1360 /// NOTE: This may be called before legalization on types for which FMAs are
1361 /// not legal, but should return true if those types will eventually legalize
1362 /// to types that support FMAs. After legalization, it will only be called on
1363 /// types that support FMAs (via Legal or Custom actions)
1364 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1368 /// Return true if it's profitable to narrow operations of type VT1 to
1369 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1371 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1375 /// \brief Return true if it is beneficial to convert a load of a constant to
1376 /// just the constant itself.
1377 /// On some targets it might be more efficient to use a combination of
1378 /// arithmetic instructions to materialize the constant instead of loading it
1379 /// from a constant pool.
1380 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1384 //===--------------------------------------------------------------------===//
1385 // Runtime Library hooks
1388 /// Rename the default libcall routine name for the specified libcall.
1389 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1390 LibcallRoutineNames[Call] = Name;
1393 /// Get the libcall routine name for the specified libcall.
1394 const char *getLibcallName(RTLIB::Libcall Call) const {
1395 return LibcallRoutineNames[Call];
1398 /// Override the default CondCode to be used to test the result of the
1399 /// comparison libcall against zero.
1400 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1401 CmpLibcallCCs[Call] = CC;
1404 /// Get the CondCode that's to be used to test the result of the comparison
1405 /// libcall against zero.
1406 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1407 return CmpLibcallCCs[Call];
1410 /// Set the CallingConv that should be used for the specified libcall.
1411 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1412 LibcallCallingConvs[Call] = CC;
1415 /// Get the CallingConv that should be used for the specified libcall.
1416 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1417 return LibcallCallingConvs[Call];
1421 const TargetMachine &TM;
1422 const DataLayout *DL;
1423 const TargetLoweringObjectFile &TLOF;
1425 /// True if this is a little endian target.
1426 bool IsLittleEndian;
1428 /// Tells the code generator not to expand operations into sequences that use
1429 /// the select operations if possible.
1430 bool SelectIsExpensive;
1432 /// Tells the code generator that the target has multiple (allocatable)
1433 /// condition registers that can be used to store the results of comparisons
1434 /// for use by selects and conditional branches. With multiple condition
1435 /// registers, the code generator will not aggressively sink comparisons into
1436 /// the blocks of their users.
1437 bool HasMultipleConditionRegisters;
1439 /// Tells the code generator that the target has BitExtract instructions.
1440 /// The code generator will aggressively sink "shift"s into the blocks of
1441 /// their users if the users will generate "and" instructions which can be
1442 /// combined with "shift" to BitExtract instructions.
1443 bool HasExtractBitsInsn;
1445 /// Tells the code generator not to expand integer divides by constants into a
1446 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1447 /// model is in place. If we ever optimize for size, this will be set to true
1448 /// unconditionally.
1451 /// Tells the code generator to bypass slow divide or remainder
1452 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1453 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1454 /// div/rem when the operands are positive and less than 256.
1455 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1457 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1458 /// signed divide by power of two, and let the target handle it.
1459 bool Pow2DivIsCheap;
1461 /// Tells the code generator that it shouldn't generate extra flow control
1462 /// instructions and should attempt to combine flow control instructions via
1464 bool JumpIsExpensive;
1466 /// This target prefers to use _setjmp to implement llvm.setjmp.
1468 /// Defaults to false.
1469 bool UseUnderscoreSetJmp;
1471 /// This target prefers to use _longjmp to implement llvm.longjmp.
1473 /// Defaults to false.
1474 bool UseUnderscoreLongJmp;
1476 /// Whether the target can generate code for jumptables. If it's not true,
1477 /// then each jumptable must be lowered into if-then-else's.
1478 bool SupportJumpTables;
1480 /// Number of blocks threshold to use jump tables.
1481 int MinimumJumpTableEntries;
1483 /// Information about the contents of the high-bits in boolean values held in
1484 /// a type wider than i1. See getBooleanContents.
1485 BooleanContent BooleanContents;
1487 /// Information about the contents of the high-bits in boolean vector values
1488 /// when the element type is wider than i1. See getBooleanContents.
1489 BooleanContent BooleanVectorContents;
1491 /// The target scheduling preference: shortest possible total cycles or lowest
1493 Sched::Preference SchedPreferenceInfo;
1495 /// The size, in bytes, of the target's jmp_buf buffers
1496 unsigned JumpBufSize;
1498 /// The alignment, in bytes, of the target's jmp_buf buffers
1499 unsigned JumpBufAlignment;
1501 /// The minimum alignment that any argument on the stack needs to have.
1502 unsigned MinStackArgumentAlignment;
1504 /// The minimum function alignment (used when optimizing for size, and to
1505 /// prevent explicitly provided alignment from leading to incorrect code).
1506 unsigned MinFunctionAlignment;
1508 /// The preferred function alignment (used when alignment unspecified and
1509 /// optimizing for speed).
1510 unsigned PrefFunctionAlignment;
1512 /// The preferred loop alignment.
1513 unsigned PrefLoopAlignment;
1515 /// Whether the DAG builder should automatically insert fences and reduce
1516 /// ordering for atomics. (This will be set for for most architectures with
1517 /// weak memory ordering.)
1518 bool InsertFencesForAtomic;
1520 /// If set to a physical register, this specifies the register that
1521 /// llvm.savestack/llvm.restorestack should save and restore.
1522 unsigned StackPointerRegisterToSaveRestore;
1524 /// If set to a physical register, this specifies the register that receives
1525 /// the exception address on entry to a landing pad.
1526 unsigned ExceptionPointerRegister;
1528 /// If set to a physical register, this specifies the register that receives
1529 /// the exception typeid on entry to a landing pad.
1530 unsigned ExceptionSelectorRegister;
1532 /// This indicates the default register class to use for each ValueType the
1533 /// target supports natively.
1534 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1535 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1536 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1538 /// This indicates the "representative" register class to use for each
1539 /// ValueType the target supports natively. This information is used by the
1540 /// scheduler to track register pressure. By default, the representative
1541 /// register class is the largest legal super-reg register class of the
1542 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1543 /// representative class would be GR32.
1544 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1546 /// This indicates the "cost" of the "representative" register class for each
1547 /// ValueType. The cost is used by the scheduler to approximate register
1549 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1551 /// For any value types we are promoting or expanding, this contains the value
1552 /// type that we are changing to. For Expanded types, this contains one step
1553 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1554 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1555 /// the same type (e.g. i32 -> i32).
1556 MVT TransformToType[MVT::LAST_VALUETYPE];
1558 /// For each operation and each value type, keep a LegalizeAction that
1559 /// indicates how instruction selection should deal with the operation. Most
1560 /// operations are Legal (aka, supported natively by the target), but
1561 /// operations that are not should be described. Note that operations on
1562 /// non-legal value types are not described here.
1563 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1565 /// For each load extension type and each value type, keep a LegalizeAction
1566 /// that indicates how instruction selection should deal with a load of a
1567 /// specific value type and extension type.
1568 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1570 /// For each value type pair keep a LegalizeAction that indicates whether a
1571 /// truncating store of a specific value type and truncating type is legal.
1572 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1574 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1575 /// that indicates how instruction selection should deal with the load /
1578 /// The first dimension is the value_type for the reference. The second
1579 /// dimension represents the various modes for load store.
1580 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1582 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1583 /// indicates how instruction selection should deal with the condition code.
1585 /// Because each CC action takes up 2 bits, we need to have the array size be
1586 /// large enough to fit all of the value types. This can be done by rounding
1587 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1588 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1590 ValueTypeActionImpl ValueTypeActions;
1594 getTypeConversion(LLVMContext &Context, EVT VT) const {
1595 // If this is a simple type, use the ComputeRegisterProp mechanism.
1596 if (VT.isSimple()) {
1597 MVT SVT = VT.getSimpleVT();
1598 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1599 MVT NVT = TransformToType[SVT.SimpleTy];
1600 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1604 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1605 && "Promote may not follow Expand or Promote");
1607 if (LA == TypeSplitVector)
1608 return LegalizeKind(LA, EVT::getVectorVT(Context,
1609 SVT.getVectorElementType(),
1610 SVT.getVectorNumElements()/2));
1611 if (LA == TypeScalarizeVector)
1612 return LegalizeKind(LA, SVT.getVectorElementType());
1613 return LegalizeKind(LA, NVT);
1616 // Handle Extended Scalar Types.
1617 if (!VT.isVector()) {
1618 assert(VT.isInteger() && "Float types must be simple");
1619 unsigned BitSize = VT.getSizeInBits();
1620 // First promote to a power-of-two size, then expand if necessary.
1621 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1622 EVT NVT = VT.getRoundIntegerType(Context);
1623 assert(NVT != VT && "Unable to round integer VT");
1624 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1625 // Avoid multi-step promotion.
1626 if (NextStep.first == TypePromoteInteger) return NextStep;
1627 // Return rounded integer type.
1628 return LegalizeKind(TypePromoteInteger, NVT);
1631 return LegalizeKind(TypeExpandInteger,
1632 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1635 // Handle vector types.
1636 unsigned NumElts = VT.getVectorNumElements();
1637 EVT EltVT = VT.getVectorElementType();
1639 // Vectors with only one element are always scalarized.
1641 return LegalizeKind(TypeScalarizeVector, EltVT);
1643 // Try to widen vector elements until the element type is a power of two and
1644 // promote it to a legal type later on, for example:
1645 // <3 x i8> -> <4 x i8> -> <4 x i32>
1646 if (EltVT.isInteger()) {
1647 // Vectors with a number of elements that is not a power of two are always
1648 // widened, for example <3 x i8> -> <4 x i8>.
1649 if (!VT.isPow2VectorType()) {
1650 NumElts = (unsigned)NextPowerOf2(NumElts);
1651 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1652 return LegalizeKind(TypeWidenVector, NVT);
1655 // Examine the element type.
1656 LegalizeKind LK = getTypeConversion(Context, EltVT);
1658 // If type is to be expanded, split the vector.
1659 // <4 x i140> -> <2 x i140>
1660 if (LK.first == TypeExpandInteger)
1661 return LegalizeKind(TypeSplitVector,
1662 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1664 // Promote the integer element types until a legal vector type is found
1665 // or until the element integer type is too big. If a legal type was not
1666 // found, fallback to the usual mechanism of widening/splitting the
1668 EVT OldEltVT = EltVT;
1670 // Increase the bitwidth of the element to the next pow-of-two
1671 // (which is greater than 8 bits).
1672 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1673 ).getRoundIntegerType(Context);
1675 // Stop trying when getting a non-simple element type.
1676 // Note that vector elements may be greater than legal vector element
1677 // types. Example: X86 XMM registers hold 64bit element on 32bit
1679 if (!EltVT.isSimple()) break;
1681 // Build a new vector type and check if it is legal.
1682 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1683 // Found a legal promoted vector type.
1684 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1685 return LegalizeKind(TypePromoteInteger,
1686 EVT::getVectorVT(Context, EltVT, NumElts));
1689 // Reset the type to the unexpanded type if we did not find a legal vector
1690 // type with a promoted vector element type.
1694 // Try to widen the vector until a legal type is found.
1695 // If there is no wider legal type, split the vector.
1697 // Round up to the next power of 2.
1698 NumElts = (unsigned)NextPowerOf2(NumElts);
1700 // If there is no simple vector type with this many elements then there
1701 // cannot be a larger legal vector type. Note that this assumes that
1702 // there are no skipped intermediate vector types in the simple types.
1703 if (!EltVT.isSimple()) break;
1704 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1705 if (LargerVector == MVT()) break;
1707 // If this type is legal then widen the vector.
1708 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1709 return LegalizeKind(TypeWidenVector, LargerVector);
1712 // Widen odd vectors to next power of two.
1713 if (!VT.isPow2VectorType()) {
1714 EVT NVT = VT.getPow2VectorType(Context);
1715 return LegalizeKind(TypeWidenVector, NVT);
1718 // Vectors with illegal element types are expanded.
1719 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1720 return LegalizeKind(TypeSplitVector, NVT);
1724 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1726 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1727 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1730 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1732 /// For operations that must be promoted to a specific type, this holds the
1733 /// destination type. This map should be sparse, so don't hold it as an
1736 /// Targets add entries to this map with AddPromotedToType(..), clients access
1737 /// this with getTypeToPromoteTo(..).
1738 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1741 /// Stores the name each libcall.
1742 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1744 /// The ISD::CondCode that should be used to test the result of each of the
1745 /// comparison libcall against zero.
1746 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1748 /// Stores the CallingConv that should be used for each libcall.
1749 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1752 /// \brief Specify maximum number of store instructions per memset call.
1754 /// When lowering \@llvm.memset this field specifies the maximum number of
1755 /// store operations that may be substituted for the call to memset. Targets
1756 /// must set this value based on the cost threshold for that target. Targets
1757 /// should assume that the memset will be done using as many of the largest
1758 /// store operations first, followed by smaller ones, if necessary, per
1759 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1760 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1761 /// store. This only applies to setting a constant array of a constant size.
1762 unsigned MaxStoresPerMemset;
1764 /// Maximum number of stores operations that may be substituted for the call
1765 /// to memset, used for functions with OptSize attribute.
1766 unsigned MaxStoresPerMemsetOptSize;
1768 /// \brief Specify maximum bytes of store instructions per memcpy call.
1770 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1771 /// store operations that may be substituted for a call to memcpy. Targets
1772 /// must set this value based on the cost threshold for that target. Targets
1773 /// should assume that the memcpy will be done using as many of the largest
1774 /// store operations first, followed by smaller ones, if necessary, per
1775 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1776 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1777 /// and one 1-byte store. This only applies to copying a constant array of
1779 unsigned MaxStoresPerMemcpy;
1781 /// Maximum number of store operations that may be substituted for a call to
1782 /// memcpy, used for functions with OptSize attribute.
1783 unsigned MaxStoresPerMemcpyOptSize;
1785 /// \brief Specify maximum bytes of store instructions per memmove call.
1787 /// When lowering \@llvm.memmove this field specifies the maximum number of
1788 /// store instructions that may be substituted for a call to memmove. Targets
1789 /// must set this value based on the cost threshold for that target. Targets
1790 /// should assume that the memmove will be done using as many of the largest
1791 /// store operations first, followed by smaller ones, if necessary, per
1792 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1793 /// with 8-bit alignment would result in nine 1-byte stores. This only
1794 /// applies to copying a constant array of constant size.
1795 unsigned MaxStoresPerMemmove;
1797 /// Maximum number of store instructions that may be substituted for a call to
1798 /// memmove, used for functions with OpSize attribute.
1799 unsigned MaxStoresPerMemmoveOptSize;
1801 /// Tells the code generator that select is more expensive than a branch if
1802 /// the branch is usually predicted right.
1803 bool PredictableSelectIsExpensive;
1805 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1806 /// a mask of a single bit, a compare, and a branch into a single instruction.
1807 bool MaskAndBranchFoldingIsLegal;
1810 /// Return true if the value types that can be represented by the specified
1811 /// register class are all legal.
1812 bool isLegalRC(const TargetRegisterClass *RC) const;
1814 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1815 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1816 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1819 /// This class defines information used to lower LLVM code to legal SelectionDAG
1820 /// operators that the target instruction selector can accept natively.
1822 /// This class also defines callbacks that targets must implement to lower
1823 /// target-specific constructs to SelectionDAG operators.
1824 class TargetLowering : public TargetLoweringBase {
1825 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1826 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1829 /// NOTE: The constructor takes ownership of TLOF.
1830 explicit TargetLowering(const TargetMachine &TM,
1831 const TargetLoweringObjectFile *TLOF);
1833 /// Returns true by value, base pointer and offset pointer and addressing mode
1834 /// by reference if the node's address can be legally represented as
1835 /// pre-indexed load / store address.
1836 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1837 SDValue &/*Offset*/,
1838 ISD::MemIndexedMode &/*AM*/,
1839 SelectionDAG &/*DAG*/) const {
1843 /// Returns true by value, base pointer and offset pointer and addressing mode
1844 /// by reference if this node can be combined with a load / store to form a
1845 /// post-indexed load / store.
1846 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1848 SDValue &/*Offset*/,
1849 ISD::MemIndexedMode &/*AM*/,
1850 SelectionDAG &/*DAG*/) const {
1854 /// Return the entry encoding for a jump table in the current function. The
1855 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1856 virtual unsigned getJumpTableEncoding() const;
1858 virtual const MCExpr *
1859 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1860 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1861 MCContext &/*Ctx*/) const {
1862 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1865 /// Returns relocation base for the given PIC jumptable.
1866 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1867 SelectionDAG &DAG) const;
1869 /// This returns the relocation base for the given PIC jumptable, the same as
1870 /// getPICJumpTableRelocBase, but as an MCExpr.
1871 virtual const MCExpr *
1872 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1873 unsigned JTI, MCContext &Ctx) const;
1875 /// Return true if folding a constant offset with the given GlobalAddress is
1876 /// legal. It is frequently not legal in PIC relocation models.
1877 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1879 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1880 SDValue &Chain) const;
1882 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1883 SDValue &NewLHS, SDValue &NewRHS,
1884 ISD::CondCode &CCCode, SDLoc DL) const;
1886 /// Returns a pair of (return value, chain).
1887 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1888 EVT RetVT, const SDValue *Ops,
1889 unsigned NumOps, bool isSigned,
1890 SDLoc dl, bool doesNotReturn = false,
1891 bool isReturnValueUsed = true) const;
1893 //===--------------------------------------------------------------------===//
1894 // TargetLowering Optimization Methods
1897 /// A convenience struct that encapsulates a DAG, and two SDValues for
1898 /// returning information from TargetLowering to its clients that want to
1900 struct TargetLoweringOpt {
1907 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1909 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1911 bool LegalTypes() const { return LegalTys; }
1912 bool LegalOperations() const { return LegalOps; }
1914 bool CombineTo(SDValue O, SDValue N) {
1920 /// Check to see if the specified operand of the specified instruction is a
1921 /// constant integer. If so, check to see if there are any bits set in the
1922 /// constant that are not demanded. If so, shrink the constant and return
1924 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1926 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1927 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1928 /// generalized for targets with other types of implicit widening casts.
1929 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1933 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1934 /// result of Op are ever used downstream. If we can use this information to
1935 /// simplify Op, create a new simplified DAG node and return true, returning
1936 /// the original and new nodes in Old and New. Otherwise, analyze the
1937 /// expression and return a mask of KnownOne and KnownZero bits for the
1938 /// expression (used to simplify the caller). The KnownZero/One bits may only
1939 /// be accurate for those bits in the DemandedMask.
1940 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1941 APInt &KnownZero, APInt &KnownOne,
1942 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1944 /// Determine which of the bits specified in Mask are known to be either zero
1945 /// or one and return them in the KnownZero/KnownOne bitsets.
1946 virtual void computeKnownBitsForTargetNode(const SDValue Op,
1949 const SelectionDAG &DAG,
1950 unsigned Depth = 0) const;
1952 /// This method can be implemented by targets that want to expose additional
1953 /// information about sign bits to the DAG Combiner.
1954 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1955 const SelectionDAG &DAG,
1956 unsigned Depth = 0) const;
1958 struct DAGCombinerInfo {
1959 void *DC; // The DAG Combiner object.
1961 bool CalledByLegalizer;
1965 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1966 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1968 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1969 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1970 bool isAfterLegalizeVectorOps() const {
1971 return Level == AfterLegalizeDAG;
1973 CombineLevel getDAGCombineLevel() { return Level; }
1974 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1976 void AddToWorklist(SDNode *N);
1977 void RemoveFromWorklist(SDNode *N);
1978 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1980 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1981 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1983 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1986 /// Return if the N is a constant or constant vector equal to the true value
1987 /// from getBooleanContents().
1988 bool isConstTrueVal(const SDNode *N) const;
1990 /// Return if the N is a constant or constant vector equal to the false value
1991 /// from getBooleanContents().
1992 bool isConstFalseVal(const SDNode *N) const;
1994 /// Try to simplify a setcc built with the specified operands and cc. If it is
1995 /// unable to simplify it, return a null SDValue.
1996 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1997 ISD::CondCode Cond, bool foldBooleans,
1998 DAGCombinerInfo &DCI, SDLoc dl) const;
2000 /// Returns true (and the GlobalValue and the offset) if the node is a
2001 /// GlobalAddress + offset.
2003 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2005 /// This method will be invoked for all target nodes and for any
2006 /// target-independent nodes that the target has registered with invoke it
2009 /// The semantics are as follows:
2011 /// SDValue.Val == 0 - No change was made
2012 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2013 /// otherwise - N should be replaced by the returned Operand.
2015 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2016 /// more complex transformations.
2018 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2020 /// Return true if it is profitable to move a following shift through this
2021 // node, adjusting any immediate operands as necessary to preserve semantics.
2022 // This transformation may not be desirable if it disrupts a particularly
2023 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2024 // By default, it returns true.
2025 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2029 /// Return true if the target has native support for the specified value type
2030 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2031 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2032 /// and some i16 instructions are slow.
2033 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2034 // By default, assume all legal types are desirable.
2035 return isTypeLegal(VT);
2038 /// Return true if it is profitable for dag combiner to transform a floating
2039 /// point op of specified opcode to a equivalent op of an integer
2040 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2041 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2046 /// This method query the target whether it is beneficial for dag combiner to
2047 /// promote the specified node. If true, it should return the desired
2048 /// promotion type by reference.
2049 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2053 //===--------------------------------------------------------------------===//
2054 // Lowering methods - These methods must be implemented by targets so that
2055 // the SelectionDAGBuilder code knows how to lower these.
2058 /// This hook must be implemented to lower the incoming (formal) arguments,
2059 /// described by the Ins array, into the specified DAG. The implementation
2060 /// should fill in the InVals array with legal-type argument values, and
2061 /// return the resulting token chain value.
2064 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2066 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2067 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2068 SmallVectorImpl<SDValue> &/*InVals*/) const {
2069 llvm_unreachable("Not Implemented");
2072 struct ArgListEntry {
2081 bool isInAlloca : 1;
2082 bool isReturned : 1;
2085 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2086 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2087 isReturned(false), Alignment(0) { }
2089 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2091 typedef std::vector<ArgListEntry> ArgListTy;
2093 /// This structure contains all information that is necessary for lowering
2094 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2095 /// needs to lower a call, and targets will see this struct in their LowerCall
2097 struct CallLoweringInfo {
2104 bool DoesNotReturn : 1;
2105 bool IsReturnValueUsed : 1;
2107 // IsTailCall should be modified by implementations of
2108 // TargetLowering::LowerCall that perform tail call conversions.
2111 unsigned NumFixedArgs;
2112 CallingConv::ID CallConv;
2117 ImmutableCallSite *CS;
2118 SmallVector<ISD::OutputArg, 32> Outs;
2119 SmallVector<SDValue, 32> OutVals;
2120 SmallVector<ISD::InputArg, 32> Ins;
2123 /// Constructs a call lowering context based on the ImmutableCallSite \p cs.
2124 CallLoweringInfo(SDValue chain, Type *retTy,
2125 FunctionType *FTy, bool isTailCall, SDValue callee,
2126 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
2127 ImmutableCallSite &cs)
2128 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
2129 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
2130 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
2131 DoesNotReturn(cs.doesNotReturn()),
2132 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
2133 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
2134 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
2137 /// Constructs a call lowering context based on the provided call
2139 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
2140 bool isVarArg, bool isInReg, unsigned numFixedArgs,
2141 CallingConv::ID callConv, bool isTailCall,
2142 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
2143 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
2144 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
2145 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
2146 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
2147 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
2148 Args(args), DAG(dag), DL(dl), CS(nullptr) {}
2151 /// This function lowers an abstract call to a function into an actual call.
2152 /// This returns a pair of operands. The first element is the return value
2153 /// for the function (if RetTy is not VoidTy). The second element is the
2154 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2155 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2157 /// This hook must be implemented to lower calls into the the specified
2158 /// DAG. The outgoing arguments to the call are described by the Outs array,
2159 /// and the values to be returned by the call are described by the Ins
2160 /// array. The implementation should fill in the InVals array with legal-type
2161 /// return values from the call, and return the resulting token chain value.
2163 LowerCall(CallLoweringInfo &/*CLI*/,
2164 SmallVectorImpl<SDValue> &/*InVals*/) const {
2165 llvm_unreachable("Not Implemented");
2168 /// Target-specific cleanup for formal ByVal parameters.
2169 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2171 /// This hook should be implemented to check whether the return values
2172 /// described by the Outs array can fit into the return registers. If false
2173 /// is returned, an sret-demotion is performed.
2174 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2175 MachineFunction &/*MF*/, bool /*isVarArg*/,
2176 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2177 LLVMContext &/*Context*/) const
2179 // Return true by default to get preexisting behavior.
2183 /// This hook must be implemented to lower outgoing return values, described
2184 /// by the Outs array, into the specified DAG. The implementation should
2185 /// return the resulting token chain value.
2187 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2189 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2190 const SmallVectorImpl<SDValue> &/*OutVals*/,
2191 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2192 llvm_unreachable("Not Implemented");
2195 /// Return true if result of the specified node is used by a return node
2196 /// only. It also compute and return the input chain for the tail call.
2198 /// This is used to determine whether it is possible to codegen a libcall as
2199 /// tail call at legalization time.
2200 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2204 /// Return true if the target may be able emit the call instruction as a tail
2205 /// call. This is used by optimization passes to determine if it's profitable
2206 /// to duplicate return instructions to enable tailcall optimization.
2207 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2211 /// Return the builtin name for the __builtin___clear_cache intrinsic
2212 /// Default is to invoke the clear cache library call
2213 virtual const char * getClearCacheBuiltinName() const {
2214 return "__clear_cache";
2217 /// Return the register ID of the name passed in. Used by named register
2218 /// global variables extension. There is no target-independent behaviour
2219 /// so the default action is to bail.
2220 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2221 report_fatal_error("Named registers not implemented for this target");
2224 /// Return the type that should be used to zero or sign extend a
2225 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2226 /// convention requires the return type to be promoted, but this is not true
2227 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2228 /// calling conventions. The frontend should handle this and include all of
2229 /// the necessary information.
2230 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2231 ISD::NodeType /*ExtendKind*/) const {
2232 MVT MinVT = getRegisterType(MVT::i32);
2233 return VT.bitsLT(MinVT) ? MinVT : VT;
2236 /// For some targets, an LLVM struct type must be broken down into multiple
2237 /// simple types, but the calling convention specifies that the entire struct
2238 /// must be passed in a block of consecutive registers.
2240 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2241 bool isVarArg) const {
2245 /// Returns a 0 terminated array of registers that can be safely used as
2246 /// scratch registers.
2247 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2251 /// This callback is used to prepare for a volatile or atomic load.
2252 /// It takes a chain node as input and returns the chain for the load itself.
2254 /// Having a callback like this is necessary for targets like SystemZ,
2255 /// which allows a CPU to reuse the result of a previous load indefinitely,
2256 /// even if a cache-coherent store is performed by another CPU. The default
2257 /// implementation does nothing.
2258 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2259 SelectionDAG &DAG) const {
2263 /// This callback is invoked by the type legalizer to legalize nodes with an
2264 /// illegal operand type but legal result types. It replaces the
2265 /// LowerOperation callback in the type Legalizer. The reason we can not do
2266 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2267 /// use this callback.
2269 /// TODO: Consider merging with ReplaceNodeResults.
2271 /// The target places new result values for the node in Results (their number
2272 /// and types must exactly match those of the original return values of
2273 /// the node), or leaves Results empty, which indicates that the node is not
2274 /// to be custom lowered after all.
2275 /// The default implementation calls LowerOperation.
2276 virtual void LowerOperationWrapper(SDNode *N,
2277 SmallVectorImpl<SDValue> &Results,
2278 SelectionDAG &DAG) const;
2280 /// This callback is invoked for operations that are unsupported by the
2281 /// target, which are registered to use 'custom' lowering, and whose defined
2282 /// values are all legal. If the target has no operations that require custom
2283 /// lowering, it need not implement this. The default implementation of this
2285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2287 /// This callback is invoked when a node result type is illegal for the
2288 /// target, and the operation was registered to use 'custom' lowering for that
2289 /// result type. The target places new result values for the node in Results
2290 /// (their number and types must exactly match those of the original return
2291 /// values of the node), or leaves Results empty, which indicates that the
2292 /// node is not to be custom lowered after all.
2294 /// If the target has no operations that require custom lowering, it need not
2295 /// implement this. The default implementation aborts.
2296 virtual void ReplaceNodeResults(SDNode * /*N*/,
2297 SmallVectorImpl<SDValue> &/*Results*/,
2298 SelectionDAG &/*DAG*/) const {
2299 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2302 /// This method returns the name of a target specific DAG node.
2303 virtual const char *getTargetNodeName(unsigned Opcode) const;
2305 /// This method returns a target specific FastISel object, or null if the
2306 /// target does not support "fast" ISel.
2307 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2308 const TargetLibraryInfo *) const {
2313 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2314 SelectionDAG &DAG) const;
2316 //===--------------------------------------------------------------------===//
2317 // Inline Asm Support hooks
2320 /// This hook allows the target to expand an inline asm call to be explicit
2321 /// llvm code if it wants to. This is useful for turning simple inline asms
2322 /// into LLVM intrinsics, which gives the compiler more information about the
2323 /// behavior of the code.
2324 virtual bool ExpandInlineAsm(CallInst *) const {
2328 enum ConstraintType {
2329 C_Register, // Constraint represents specific register(s).
2330 C_RegisterClass, // Constraint represents any of register(s) in class.
2331 C_Memory, // Memory constraint.
2332 C_Other, // Something else.
2333 C_Unknown // Unsupported constraint.
2336 enum ConstraintWeight {
2338 CW_Invalid = -1, // No match.
2339 CW_Okay = 0, // Acceptable.
2340 CW_Good = 1, // Good weight.
2341 CW_Better = 2, // Better weight.
2342 CW_Best = 3, // Best weight.
2344 // Well-known weights.
2345 CW_SpecificReg = CW_Okay, // Specific register operands.
2346 CW_Register = CW_Good, // Register operands.
2347 CW_Memory = CW_Better, // Memory operands.
2348 CW_Constant = CW_Best, // Constant operand.
2349 CW_Default = CW_Okay // Default or don't know type.
2352 /// This contains information for each constraint that we are lowering.
2353 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2354 /// This contains the actual string for the code, like "m". TargetLowering
2355 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2356 /// matches the operand.
2357 std::string ConstraintCode;
2359 /// Information about the constraint code, e.g. Register, RegisterClass,
2360 /// Memory, Other, Unknown.
2361 TargetLowering::ConstraintType ConstraintType;
2363 /// If this is the result output operand or a clobber, this is null,
2364 /// otherwise it is the incoming operand to the CallInst. This gets
2365 /// modified as the asm is processed.
2366 Value *CallOperandVal;
2368 /// The ValueType for the operand value.
2371 /// Return true of this is an input operand that is a matching constraint
2373 bool isMatchingInputConstraint() const;
2375 /// If this is an input matching constraint, this method returns the output
2376 /// operand it matches.
2377 unsigned getMatchedOperand() const;
2379 /// Copy constructor for copying from a ConstraintInfo.
2380 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2381 : InlineAsm::ConstraintInfo(info),
2382 ConstraintType(TargetLowering::C_Unknown),
2383 CallOperandVal(nullptr), ConstraintVT(MVT::Other) {
2387 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2389 /// Split up the constraint string from the inline assembly value into the
2390 /// specific constraints and their prefixes, and also tie in the associated
2391 /// operand values. If this returns an empty vector, and if the constraint
2392 /// string itself isn't empty, there was an error parsing.
2393 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2395 /// Examine constraint type and operand type and determine a weight value.
2396 /// The operand object must already have been set up with the operand type.
2397 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2398 AsmOperandInfo &info, int maIndex) const;
2400 /// Examine constraint string and operand type and determine a weight value.
2401 /// The operand object must already have been set up with the operand type.
2402 virtual ConstraintWeight getSingleConstraintMatchWeight(
2403 AsmOperandInfo &info, const char *constraint) const;
2405 /// Determines the constraint code and constraint type to use for the specific
2406 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2407 /// If the actual operand being passed in is available, it can be passed in as
2408 /// Op, otherwise an empty SDValue can be passed.
2409 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2411 SelectionDAG *DAG = nullptr) const;
2413 /// Given a constraint, return the type of constraint it is for this target.
2414 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2416 /// Given a physical register constraint (e.g. {edx}), return the register
2417 /// number and the register class for the register.
2419 /// Given a register class constraint, like 'r', if this corresponds directly
2420 /// to an LLVM register class, return a register of 0 and the register class
2423 /// This should only be used for C_Register constraints. On error, this
2424 /// returns a register number of 0 and a null register class pointer..
2425 virtual std::pair<unsigned, const TargetRegisterClass*>
2426 getRegForInlineAsmConstraint(const std::string &Constraint,
2429 /// Try to replace an X constraint, which matches anything, with another that
2430 /// has more specific requirements based on the type of the corresponding
2431 /// operand. This returns null if there is no replacement to make.
2432 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2434 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2435 /// add anything to Ops.
2436 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2437 std::vector<SDValue> &Ops,
2438 SelectionDAG &DAG) const;
2440 //===--------------------------------------------------------------------===//
2441 // Div utility functions
2443 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2444 SelectionDAG &DAG) const;
2445 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2446 bool IsAfterLegalization,
2447 std::vector<SDNode *> *Created) const;
2448 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2449 bool IsAfterLegalization,
2450 std::vector<SDNode *> *Created) const;
2452 //===--------------------------------------------------------------------===//
2453 // Legalization utility functions
2456 /// Expand a MUL into two nodes. One that computes the high bits of
2457 /// the result and one that computes the low bits.
2458 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2459 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2460 /// if you want to control how low bits are extracted from the LHS.
2461 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2462 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2463 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2464 /// \returns true if the node has been expanded. false if it has not
2465 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2466 SelectionDAG &DAG, SDValue LL = SDValue(),
2467 SDValue LH = SDValue(), SDValue RL = SDValue(),
2468 SDValue RH = SDValue()) const;
2470 //===--------------------------------------------------------------------===//
2471 // Instruction Emitting Hooks
2474 /// This method should be implemented by targets that mark instructions with
2475 /// the 'usesCustomInserter' flag. These instructions are special in various
2476 /// ways, which require special support to insert. The specified MachineInstr
2477 /// is created but not inserted into any basic blocks, and this method is
2478 /// called to expand it into a sequence of instructions, potentially also
2479 /// creating new basic blocks and control flow.
2480 virtual MachineBasicBlock *
2481 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2483 /// This method should be implemented by targets that mark instructions with
2484 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2485 /// instruction selection by target hooks. e.g. To fill in optional defs for
2486 /// ARM 's' setting instructions.
2488 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2491 /// Given an LLVM IR type and return type attributes, compute the return value
2492 /// EVTs and flags, and optionally also the offsets, if the return value is
2493 /// being lowered to memory.
2494 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2495 SmallVectorImpl<ISD::OutputArg> &Outs,
2496 const TargetLowering &TLI);
2498 } // end llvm namespace