1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Constants.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/STLExtras.h"
41 class MachineBasicBlock;
42 class MachineFunction;
43 class MachineFrameInfo;
45 class MachineModuleInfo;
51 class TargetRegisterClass;
52 class TargetSubtarget;
56 //===----------------------------------------------------------------------===//
57 /// TargetLowering - This class defines information used to lower LLVM code to
58 /// legal SelectionDAG operators that the target instruction selector can accept
61 /// This class also defines callbacks that targets must implement to lower
62 /// target-specific constructs to SelectionDAG operators.
64 class TargetLowering {
66 /// LegalizeAction - This enum indicates whether operations are valid for a
67 /// target, and if not, what action should be used to make them valid.
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand, // Try to expand this to other ops, otherwise use a libcall.
72 Custom // Use the LowerOperation hook to implement custom lowering.
75 enum OutOfRangeShiftAmount {
76 Undefined, // Oversized shift amounts are undefined (default).
77 Mask, // Shift amounts are auto masked (anded) to value size.
78 Extend // Oversized shift pulls in zeros or sign bits.
81 enum BooleanContent { // How the target represents true/false values.
82 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
83 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
84 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
87 enum SchedPreference {
88 SchedulingForLatency, // Scheduling for shortest total latency.
89 SchedulingForRegPressure // Scheduling for lowest register pressure.
92 explicit TargetLowering(TargetMachine &TM);
93 virtual ~TargetLowering();
95 TargetMachine &getTargetMachine() const { return TM; }
96 const TargetData *getTargetData() const { return TD; }
98 bool isBigEndian() const { return !IsLittleEndian; }
99 bool isLittleEndian() const { return IsLittleEndian; }
100 MVT getPointerTy() const { return PointerTy; }
101 MVT getShiftAmountTy() const { return ShiftAmountTy; }
102 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
104 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
106 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
108 /// isSelectExpensive - Return true if the select operation is expensive for
110 bool isSelectExpensive() const { return SelectIsExpensive; }
112 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
113 /// a sequence of several shifts, adds, and multiplies for this target.
114 bool isIntDivCheap() const { return IntDivIsCheap; }
116 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
118 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
120 /// getSetCCResultType - Return the ValueType of the result of setcc
122 virtual MVT getSetCCResultType(const SDValue &) const;
124 /// getBooleanContents - For targets without i1 registers, this gives the
125 /// nature of the high-bits of boolean values held in types wider than i1.
126 /// "Boolean values" are special true/false values produced by nodes like
127 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
128 /// Not to be confused with general values promoted from i1.
129 BooleanContent getBooleanContents() const { return BooleanContents;}
131 /// getSchedulingPreference - Return target scheduling preference.
132 SchedPreference getSchedulingPreference() const {
133 return SchedPreferenceInfo;
136 /// getRegClassFor - Return the register class that should be used for the
137 /// specified value type. This may only be called on legal types.
138 TargetRegisterClass *getRegClassFor(MVT VT) const {
139 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
140 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
141 assert(RC && "This value type is not natively supported!");
145 /// isTypeLegal - Return true if the target has native support for the
146 /// specified value type. This means that it has a register that directly
147 /// holds it without promotions or expansions.
148 bool isTypeLegal(MVT VT) const {
149 assert(!VT.isSimple() ||
150 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
151 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
154 class ValueTypeActionImpl {
155 /// ValueTypeActions - This is a bitvector that contains two bits for each
156 /// value type, where the two bits correspond to the LegalizeAction enum.
157 /// This can be queried with "getTypeAction(VT)".
158 uint32_t ValueTypeActions[2];
160 ValueTypeActionImpl() {
161 ValueTypeActions[0] = ValueTypeActions[1] = 0;
163 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
164 ValueTypeActions[0] = RHS.ValueTypeActions[0];
165 ValueTypeActions[1] = RHS.ValueTypeActions[1];
168 LegalizeAction getTypeAction(MVT VT) const {
169 if (VT.isExtended()) {
171 // First try vector widening
175 // First promote to a power-of-two size, then expand if necessary.
176 return VT == VT.getRoundIntegerType() ? Expand : Promote;
177 assert(0 && "Unsupported extended type!");
180 unsigned I = VT.getSimpleVT();
181 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
182 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
184 void setTypeAction(MVT VT, LegalizeAction Action) {
185 unsigned I = VT.getSimpleVT();
186 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
187 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
191 const ValueTypeActionImpl &getValueTypeActions() const {
192 return ValueTypeActions;
195 /// getTypeAction - Return how we should legalize values of this type, either
196 /// it is already legal (return 'Legal') or we need to promote it to a larger
197 /// type (return 'Promote'), or we need to expand it into multiple registers
198 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
199 LegalizeAction getTypeAction(MVT VT) const {
200 return ValueTypeActions.getTypeAction(VT);
203 /// getTypeToTransformTo - For types supported by the target, this is an
204 /// identity function. For types that must be promoted to larger types, this
205 /// returns the larger type to promote to. For integer types that are larger
206 /// than the largest integer register, this contains one step in the expansion
207 /// to get to the smaller register. For illegal floating point types, this
208 /// returns the integer type to transform to.
209 MVT getTypeToTransformTo(MVT VT) const {
211 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
212 MVT NVT = TransformToType[VT.getSimpleVT()];
213 assert(getTypeAction(NVT) != Promote &&
214 "Promote may not follow Expand or Promote");
219 unsigned NumElts = VT.getVectorNumElements();
220 MVT EltVT = VT.getVectorElementType();
221 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
222 } else if (VT.isInteger()) {
223 MVT NVT = VT.getRoundIntegerType();
225 // Size is a power of two - expand to half the size.
226 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
228 // Promote to a power of two size, avoiding multi-step promotion.
229 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
231 assert(0 && "Unsupported extended type!");
232 return MVT(); // Not reached
235 /// getTypeToExpandTo - For types supported by the target, this is an
236 /// identity function. For types that must be expanded (i.e. integer types
237 /// that are larger than the largest integer register or illegal floating
238 /// point types), this returns the largest legal type it will be expanded to.
239 MVT getTypeToExpandTo(MVT VT) const {
240 assert(!VT.isVector());
242 switch (getTypeAction(VT)) {
246 VT = getTypeToTransformTo(VT);
249 assert(false && "Type is not legal nor is it to be expanded!");
256 /// getVectorTypeBreakdown - Vector types are broken down into some number of
257 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
258 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
259 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
261 /// This method returns the number of registers needed, and the VT for each
262 /// register. It also returns the VT and quantity of the intermediate values
263 /// before they are promoted/expanded.
265 unsigned getVectorTypeBreakdown(MVT VT,
267 unsigned &NumIntermediates,
268 MVT &RegisterVT) const;
270 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
271 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
272 /// this is the case, it returns true and store the intrinsic
273 /// information into the IntrinsicInfo that was passed to the function.
274 typedef struct IntrinsicInfo {
275 unsigned opc; // target opcode
276 MVT memVT; // memory VT
277 const Value* ptrVal; // value representing memory location
278 int offset; // offset off of ptrVal
279 unsigned align; // alignment
280 bool vol; // is volatile?
281 bool readMem; // reads memory?
282 bool writeMem; // writes memory?
285 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
286 CallInst &I, unsigned Intrinsic) {
290 /// getWidenVectorType: given a vector type, returns the type to widen to
291 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
292 /// If there is no vector type that we want to widen to, returns MVT::Other
293 /// When and were to widen is target dependent based on the cost of
294 /// scalarizing vs using the wider vector type.
295 virtual MVT getWidenVectorType(MVT VT);
297 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
298 legal_fpimm_iterator legal_fpimm_begin() const {
299 return LegalFPImmediates.begin();
301 legal_fpimm_iterator legal_fpimm_end() const {
302 return LegalFPImmediates.end();
305 /// isShuffleMaskLegal - Targets can use this to indicate that they only
306 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
307 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
308 /// are assumed to be legal.
309 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
313 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
314 /// used by Targets can use this to indicate if there is a suitable
315 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
317 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
319 SelectionDAG &DAG) const {
323 /// getOperationAction - Return how this operation should be treated: either
324 /// it is legal, needs to be promoted to a larger size, needs to be
325 /// expanded to some other code sequence, or the target has a custom expander
327 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
328 if (VT.isExtended()) return Expand;
329 assert(Op < array_lengthof(OpActions) &&
330 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
331 "Table isn't big enough!");
332 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
335 /// isOperationLegal - Return true if the specified operation is legal on this
337 bool isOperationLegal(unsigned Op, MVT VT) const {
338 return (VT == MVT::Other || isTypeLegal(VT)) &&
339 (getOperationAction(Op, VT) == Legal ||
340 getOperationAction(Op, VT) == Custom);
343 /// getLoadExtAction - Return how this load with extension should be treated:
344 /// either it is legal, needs to be promoted to a larger size, needs to be
345 /// expanded to some other code sequence, or the target has a custom expander
347 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
348 assert(LType < array_lengthof(LoadExtActions) &&
349 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
350 "Table isn't big enough!");
351 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
354 /// isLoadExtLegal - Return true if the specified load with extension is legal
356 bool isLoadExtLegal(unsigned LType, MVT VT) const {
357 return VT.isSimple() &&
358 (getLoadExtAction(LType, VT) == Legal ||
359 getLoadExtAction(LType, VT) == Custom);
362 /// getTruncStoreAction - Return how this store with truncation should be
363 /// treated: either it is legal, needs to be promoted to a larger size, needs
364 /// to be expanded to some other code sequence, or the target has a custom
366 LegalizeAction getTruncStoreAction(MVT ValVT,
368 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
369 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
370 "Table isn't big enough!");
371 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
372 (2*MemVT.getSimpleVT())) & 3);
375 /// isTruncStoreLegal - Return true if the specified store with truncation is
376 /// legal on this target.
377 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
378 return isTypeLegal(ValVT) && MemVT.isSimple() &&
379 (getTruncStoreAction(ValVT, MemVT) == Legal ||
380 getTruncStoreAction(ValVT, MemVT) == Custom);
383 /// getIndexedLoadAction - Return how the indexed load should be treated:
384 /// either it is legal, needs to be promoted to a larger size, needs to be
385 /// expanded to some other code sequence, or the target has a custom expander
388 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
389 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
390 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
391 "Table isn't big enough!");
392 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
393 (2*VT.getSimpleVT())) & 3);
396 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
398 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
399 return VT.isSimple() &&
400 (getIndexedLoadAction(IdxMode, VT) == Legal ||
401 getIndexedLoadAction(IdxMode, VT) == Custom);
404 /// getIndexedStoreAction - Return how the indexed store should be treated:
405 /// either it is legal, needs to be promoted to a larger size, needs to be
406 /// expanded to some other code sequence, or the target has a custom expander
409 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
410 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
411 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
412 "Table isn't big enough!");
413 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
414 (2*VT.getSimpleVT())) & 3);
417 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
419 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
420 return VT.isSimple() &&
421 (getIndexedStoreAction(IdxMode, VT) == Legal ||
422 getIndexedStoreAction(IdxMode, VT) == Custom);
425 /// getConvertAction - Return how the conversion should be treated:
426 /// either it is legal, needs to be promoted to a larger size, needs to be
427 /// expanded to some other code sequence, or the target has a custom expander
430 getConvertAction(MVT FromVT, MVT ToVT) const {
431 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
432 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
433 "Table isn't big enough!");
434 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
435 (2*ToVT.getSimpleVT())) & 3);
438 /// isConvertLegal - Return true if the specified conversion is legal
440 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
441 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
442 (getConvertAction(FromVT, ToVT) == Legal ||
443 getConvertAction(FromVT, ToVT) == Custom);
446 /// getCondCodeAction - Return how the condition code should be treated:
447 /// either it is legal, needs to be expanded to some other code sequence,
448 /// or the target has a custom expander for it.
450 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
451 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
452 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
453 "Table isn't big enough!");
454 LegalizeAction Action = (LegalizeAction)
455 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
456 assert(Action != Promote && "Can't promote condition code!");
460 /// isCondCodeLegal - Return true if the specified condition code is legal
462 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
463 return getCondCodeAction(CC, VT) == Legal ||
464 getCondCodeAction(CC, VT) == Custom;
468 /// getTypeToPromoteTo - If the action for this operation is to promote, this
469 /// method returns the ValueType to promote to.
470 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
471 assert(getOperationAction(Op, VT) == Promote &&
472 "This operation isn't promoted!");
474 // See if this has an explicit type specified.
475 std::map<std::pair<unsigned, MVT::SimpleValueType>,
476 MVT::SimpleValueType>::const_iterator PTTI =
477 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
478 if (PTTI != PromoteToType.end()) return PTTI->second;
480 assert((VT.isInteger() || VT.isFloatingPoint()) &&
481 "Cannot autopromote this type, add it with AddPromotedToType.");
485 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
486 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
487 "Didn't find type to promote to!");
488 } while (!isTypeLegal(NVT) ||
489 getOperationAction(Op, NVT) == Promote);
493 /// getValueType - Return the MVT corresponding to this LLVM type.
494 /// This is fixed by the LLVM operations except for the pointer size. If
495 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
496 /// counterpart (e.g. structs), otherwise it will assert.
497 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
498 MVT VT = MVT::getMVT(Ty, AllowUnknown);
499 return VT == MVT::iPTR ? PointerTy : VT;
502 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
503 /// function arguments in the caller parameter area. This is the actual
504 /// alignment, not its logarithm.
505 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
507 /// getRegisterType - Return the type of registers that this ValueType will
508 /// eventually require.
509 MVT getRegisterType(MVT VT) const {
511 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
512 return RegisterTypeForVT[VT.getSimpleVT()];
516 unsigned NumIntermediates;
517 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
520 if (VT.isInteger()) {
521 return getRegisterType(getTypeToTransformTo(VT));
523 assert(0 && "Unsupported extended type!");
524 return MVT(); // Not reached
527 /// getNumRegisters - Return the number of registers that this ValueType will
528 /// eventually require. This is one for any types promoted to live in larger
529 /// registers, but may be more than one for types (like i64) that are split
530 /// into pieces. For types like i140, which are first promoted then expanded,
531 /// it is the number of registers needed to hold all the bits of the original
532 /// type. For an i140 on a 32 bit machine this means 5 registers.
533 unsigned getNumRegisters(MVT VT) const {
535 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
536 return NumRegistersForVT[VT.getSimpleVT()];
540 unsigned NumIntermediates;
541 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
543 if (VT.isInteger()) {
544 unsigned BitWidth = VT.getSizeInBits();
545 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
546 return (BitWidth + RegWidth - 1) / RegWidth;
548 assert(0 && "Unsupported extended type!");
549 return 0; // Not reached
552 /// ShouldShrinkFPConstant - If true, then instruction selection should
553 /// seek to shrink the FP constant of the specified type to a smaller type
554 /// in order to save space and / or reduce runtime.
555 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
557 /// hasTargetDAGCombine - If true, the target has custom DAG combine
558 /// transformations that it can perform for the specified node.
559 bool hasTargetDAGCombine(ISD::NodeType NT) const {
560 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
561 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
564 /// This function returns the maximum number of store operations permitted
565 /// to replace a call to llvm.memset. The value is set by the target at the
566 /// performance threshold for such a replacement.
567 /// @brief Get maximum # of store operations permitted for llvm.memset
568 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
570 /// This function returns the maximum number of store operations permitted
571 /// to replace a call to llvm.memcpy. The value is set by the target at the
572 /// performance threshold for such a replacement.
573 /// @brief Get maximum # of store operations permitted for llvm.memcpy
574 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
576 /// This function returns the maximum number of store operations permitted
577 /// to replace a call to llvm.memmove. The value is set by the target at the
578 /// performance threshold for such a replacement.
579 /// @brief Get maximum # of store operations permitted for llvm.memmove
580 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
582 /// This function returns true if the target allows unaligned memory accesses.
583 /// This is used, for example, in situations where an array copy/move/set is
584 /// converted to a sequence of store operations. It's use helps to ensure that
585 /// such replacements don't generate code that causes an alignment error
586 /// (trap) on the target machine.
587 /// @brief Determine if the target supports unaligned memory accesses.
588 bool allowsUnalignedMemoryAccesses() const {
589 return allowUnalignedMemoryAccesses;
592 /// getOptimalMemOpType - Returns the target specific optimal type for load
593 /// and store operations as a result of memset, memcpy, and memmove lowering.
594 /// It returns MVT::iAny if SelectionDAG should be responsible for
596 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
597 bool isSrcConst, bool isSrcStr) const {
601 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
602 /// to implement llvm.setjmp.
603 bool usesUnderscoreSetJmp() const {
604 return UseUnderscoreSetJmp;
607 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
608 /// to implement llvm.longjmp.
609 bool usesUnderscoreLongJmp() const {
610 return UseUnderscoreLongJmp;
613 /// getStackPointerRegisterToSaveRestore - If a physical register, this
614 /// specifies the register that llvm.savestack/llvm.restorestack should save
616 unsigned getStackPointerRegisterToSaveRestore() const {
617 return StackPointerRegisterToSaveRestore;
620 /// getExceptionAddressRegister - If a physical register, this returns
621 /// the register that receives the exception address on entry to a landing
623 unsigned getExceptionAddressRegister() const {
624 return ExceptionPointerRegister;
627 /// getExceptionSelectorRegister - If a physical register, this returns
628 /// the register that receives the exception typeid on entry to a landing
630 unsigned getExceptionSelectorRegister() const {
631 return ExceptionSelectorRegister;
634 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
635 /// set, the default is 200)
636 unsigned getJumpBufSize() const {
640 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
641 /// (if never set, the default is 0)
642 unsigned getJumpBufAlignment() const {
643 return JumpBufAlignment;
646 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
647 /// limit. Any block whose size is greater should not be predicated.
648 unsigned getIfCvtBlockSizeLimit() const {
649 return IfCvtBlockSizeLimit;
652 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
653 /// block to be considered for duplication. Any block whose size is greater
654 /// should not be duplicated to facilitate its predication.
655 unsigned getIfCvtDupBlockSizeLimit() const {
656 return IfCvtDupBlockSizeLimit;
659 /// getPrefLoopAlignment - return the preferred loop alignment.
661 unsigned getPrefLoopAlignment() const {
662 return PrefLoopAlignment;
665 /// getPreIndexedAddressParts - returns true by value, base pointer and
666 /// offset pointer and addressing mode by reference if the node's address
667 /// can be legally represented as pre-indexed load / store address.
668 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
670 ISD::MemIndexedMode &AM,
675 /// getPostIndexedAddressParts - returns true by value, base pointer and
676 /// offset pointer and addressing mode by reference if this node can be
677 /// combined with a load / store to form a post-indexed load / store.
678 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
679 SDValue &Base, SDValue &Offset,
680 ISD::MemIndexedMode &AM,
685 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
687 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
688 SelectionDAG &DAG) const;
690 /// isOffsetFoldingLegal - Return true if folding a constant offset
691 /// with the given GlobalAddress is legal. It is frequently not legal in
692 /// PIC relocation models.
693 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
695 //===--------------------------------------------------------------------===//
696 // TargetLowering Optimization Methods
699 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
700 /// SDValues for returning information from TargetLowering to its clients
701 /// that want to combine
702 struct TargetLoweringOpt {
708 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
709 : DAG(InDAG), AfterLegalize(afterLegalize) {}
711 bool CombineTo(SDValue O, SDValue N) {
717 /// ShrinkDemandedConstant - Check to see if the specified operand of the
718 /// specified instruction is a constant integer. If so, check to see if
719 /// there are any bits set in the constant that are not demanded. If so,
720 /// shrink the constant and return true.
721 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
724 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
725 /// DemandedMask bits of the result of Op are ever used downstream. If we can
726 /// use this information to simplify Op, create a new simplified DAG node and
727 /// return true, returning the original and new nodes in Old and New.
728 /// Otherwise, analyze the expression and return a mask of KnownOne and
729 /// KnownZero bits for the expression (used to simplify the caller).
730 /// The KnownZero/One bits may only be accurate for those bits in the
732 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
733 APInt &KnownZero, APInt &KnownOne,
734 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
736 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
737 /// Mask are known to be either zero or one and return them in the
738 /// KnownZero/KnownOne bitsets.
739 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
743 const SelectionDAG &DAG,
744 unsigned Depth = 0) const;
746 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
747 /// targets that want to expose additional information about sign bits to the
749 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
750 unsigned Depth = 0) const;
752 struct DAGCombinerInfo {
753 void *DC; // The DAG Combiner object.
755 bool CalledByLegalizer;
759 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
760 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
762 bool isBeforeLegalize() const { return BeforeLegalize; }
763 bool isCalledByLegalizer() const { return CalledByLegalizer; }
765 void AddToWorklist(SDNode *N);
766 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
767 SDValue CombineTo(SDNode *N, SDValue Res);
768 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
771 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
772 /// and cc. If it is unable to simplify it, return a null SDValue.
773 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
774 ISD::CondCode Cond, bool foldBooleans,
775 DAGCombinerInfo &DCI) const;
777 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
778 /// node is a GlobalAddress + offset.
780 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
782 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
783 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
784 /// location that the 'Base' load is loading from.
785 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
786 const MachineFrameInfo *MFI) const;
788 /// PerformDAGCombine - This method will be invoked for all target nodes and
789 /// for any target-independent nodes that the target has registered with
792 /// The semantics are as follows:
794 /// SDValue.Val == 0 - No change was made
795 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
796 /// otherwise - N should be replaced by the returned Operand.
798 /// In addition, methods provided by DAGCombinerInfo may be used to perform
799 /// more complex transformations.
801 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
803 //===--------------------------------------------------------------------===//
804 // TargetLowering Configuration Methods - These methods should be invoked by
805 // the derived class constructor to configure this object for the target.
809 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
810 /// GOT for PC-relative code.
811 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
813 /// setShiftAmountType - Describe the type that should be used for shift
814 /// amounts. This type defaults to the pointer type.
815 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
817 /// setBooleanContents - Specify how the target extends the result of a
818 /// boolean value from i1 to a wider type. See getBooleanContents.
819 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
821 /// setSchedulingPreference - Specify the target scheduling preference.
822 void setSchedulingPreference(SchedPreference Pref) {
823 SchedPreferenceInfo = Pref;
826 /// setShiftAmountFlavor - Describe how the target handles out of range shift
828 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
829 ShiftAmtHandling = OORSA;
832 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
833 /// use _setjmp to implement llvm.setjmp or the non _ version.
834 /// Defaults to false.
835 void setUseUnderscoreSetJmp(bool Val) {
836 UseUnderscoreSetJmp = Val;
839 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
840 /// use _longjmp to implement llvm.longjmp or the non _ version.
841 /// Defaults to false.
842 void setUseUnderscoreLongJmp(bool Val) {
843 UseUnderscoreLongJmp = Val;
846 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
847 /// specifies the register that llvm.savestack/llvm.restorestack should save
849 void setStackPointerRegisterToSaveRestore(unsigned R) {
850 StackPointerRegisterToSaveRestore = R;
853 /// setExceptionPointerRegister - If set to a physical register, this sets
854 /// the register that receives the exception address on entry to a landing
856 void setExceptionPointerRegister(unsigned R) {
857 ExceptionPointerRegister = R;
860 /// setExceptionSelectorRegister - If set to a physical register, this sets
861 /// the register that receives the exception typeid on entry to a landing
863 void setExceptionSelectorRegister(unsigned R) {
864 ExceptionSelectorRegister = R;
867 /// SelectIsExpensive - Tells the code generator not to expand operations
868 /// into sequences that use the select operations if possible.
869 void setSelectIsExpensive() { SelectIsExpensive = true; }
871 /// setIntDivIsCheap - Tells the code generator that integer divide is
872 /// expensive, and if possible, should be replaced by an alternate sequence
873 /// of instructions not containing an integer divide.
874 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
876 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
877 /// srl/add/sra for a signed divide by power of two, and let the target handle
879 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
881 /// addRegisterClass - Add the specified register class as an available
882 /// regclass for the specified value type. This indicates the selector can
883 /// handle values of that class natively.
884 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
885 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
886 AvailableRegClasses.push_back(std::make_pair(VT, RC));
887 RegClassForVT[VT.getSimpleVT()] = RC;
890 /// computeRegisterProperties - Once all of the register classes are added,
891 /// this allows us to compute derived properties we expose.
892 void computeRegisterProperties();
894 /// setOperationAction - Indicate that the specified operation does not work
895 /// with the specified type and indicate what to do about it.
896 void setOperationAction(unsigned Op, MVT VT,
897 LegalizeAction Action) {
898 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
899 Op < array_lengthof(OpActions) && "Table isn't big enough!");
900 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
901 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
904 /// setLoadExtAction - Indicate that the specified load with extension does
905 /// not work with the with specified type and indicate what to do about it.
906 void setLoadExtAction(unsigned ExtType, MVT VT,
907 LegalizeAction Action) {
908 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
909 ExtType < array_lengthof(LoadExtActions) &&
910 "Table isn't big enough!");
911 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
912 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
915 /// setTruncStoreAction - Indicate that the specified truncating store does
916 /// not work with the with specified type and indicate what to do about it.
917 void setTruncStoreAction(MVT ValVT, MVT MemVT,
918 LegalizeAction Action) {
919 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
920 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
921 "Table isn't big enough!");
922 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
923 MemVT.getSimpleVT()*2);
924 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
925 MemVT.getSimpleVT()*2;
928 /// setIndexedLoadAction - Indicate that the specified indexed load does or
929 /// does not work with the with specified type and indicate what to do abort
930 /// it. NOTE: All indexed mode loads are initialized to Expand in
931 /// TargetLowering.cpp
932 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
933 LegalizeAction Action) {
934 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
935 IdxMode < array_lengthof(IndexedModeActions[0]) &&
936 "Table isn't big enough!");
937 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
938 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
941 /// setIndexedStoreAction - Indicate that the specified indexed store does or
942 /// does not work with the with specified type and indicate what to do about
943 /// it. NOTE: All indexed mode stores are initialized to Expand in
944 /// TargetLowering.cpp
945 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
946 LegalizeAction Action) {
947 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
948 IdxMode < array_lengthof(IndexedModeActions[1]) &&
949 "Table isn't big enough!");
950 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
951 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
954 /// setConvertAction - Indicate that the specified conversion does or does
955 /// not work with the with specified type and indicate what to do about it.
956 void setConvertAction(MVT FromVT, MVT ToVT,
957 LegalizeAction Action) {
958 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
959 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
960 "Table isn't big enough!");
961 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
962 ToVT.getSimpleVT()*2);
963 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
964 ToVT.getSimpleVT()*2;
967 /// setCondCodeAction - Indicate that the specified condition code is or isn't
968 /// supported on the target and indicate what to do about it.
969 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
970 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
971 (unsigned)CC < array_lengthof(CondCodeActions) &&
972 "Table isn't big enough!");
973 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
974 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
977 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
978 /// promotion code defaults to trying a larger integer/fp until it can find
979 /// one that works. If that default is insufficient, this method can be used
980 /// by the target to override the default.
981 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
982 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
983 DestVT.getSimpleVT();
986 /// addLegalFPImmediate - Indicate that this target can instruction select
987 /// the specified FP immediate natively.
988 void addLegalFPImmediate(const APFloat& Imm) {
989 LegalFPImmediates.push_back(Imm);
992 /// setTargetDAGCombine - Targets should invoke this method for each target
993 /// independent node that they want to provide a custom DAG combiner for by
994 /// implementing the PerformDAGCombine virtual method.
995 void setTargetDAGCombine(ISD::NodeType NT) {
996 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
997 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1000 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1001 /// bytes); default is 200
1002 void setJumpBufSize(unsigned Size) {
1006 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1007 /// alignment (in bytes); default is 0
1008 void setJumpBufAlignment(unsigned Align) {
1009 JumpBufAlignment = Align;
1012 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1013 /// limit (in number of instructions); default is 2.
1014 void setIfCvtBlockSizeLimit(unsigned Limit) {
1015 IfCvtBlockSizeLimit = Limit;
1018 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1019 /// of instructions) to be considered for code duplication during
1020 /// if-conversion; default is 2.
1021 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1022 IfCvtDupBlockSizeLimit = Limit;
1025 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1026 /// alignment is zero, it means the target does not care about loop alignment.
1027 void setPrefLoopAlignment(unsigned Align) {
1028 PrefLoopAlignment = Align;
1033 virtual const TargetSubtarget *getSubtarget() {
1034 assert(0 && "Not Implemented");
1035 return NULL; // this is here to silence compiler errors
1037 //===--------------------------------------------------------------------===//
1038 // Lowering methods - These methods must be implemented by targets so that
1039 // the SelectionDAGLowering code knows how to lower these.
1042 /// LowerArguments - This hook must be implemented to indicate how we should
1043 /// lower the arguments for the specified function, into the specified DAG.
1045 LowerArguments(Function &F, SelectionDAG &DAG,
1046 SmallVectorImpl<SDValue>& ArgValues);
1048 /// LowerCallTo - This hook lowers an abstract call to a function into an
1049 /// actual call. This returns a pair of operands. The first element is the
1050 /// return value for the function (if RetTy is not VoidTy). The second
1051 /// element is the outgoing token chain.
1052 struct ArgListEntry {
1063 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1064 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1066 typedef std::vector<ArgListEntry> ArgListTy;
1067 virtual std::pair<SDValue, SDValue>
1068 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1069 bool isVarArg, bool isInreg, unsigned CallingConv,
1070 bool isTailCall, SDValue Callee, ArgListTy &Args,
1073 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1074 /// memcpy. This can be used by targets to provide code sequences for cases
1075 /// that don't fit the target's parameters for simple loads/stores and can be
1076 /// more efficient than using a library call. This function can return a null
1077 /// SDValue if the target declines to use custom code and a different
1078 /// lowering strategy should be used.
1080 /// If AlwaysInline is true, the size is constant and the target should not
1081 /// emit any calls and is strongly encouraged to attempt to emit inline code
1082 /// even if it is beyond the usual threshold because this intrinsic is being
1083 /// expanded in a place where calls are not feasible (e.g. within the prologue
1084 /// for another call). If the target chooses to decline an AlwaysInline
1085 /// request here, legalize will resort to using simple loads and stores.
1087 EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1089 SDValue Op1, SDValue Op2,
1090 SDValue Op3, unsigned Align,
1092 const Value *DstSV, uint64_t DstOff,
1093 const Value *SrcSV, uint64_t SrcOff) {
1097 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1098 /// memmove. This can be used by targets to provide code sequences for cases
1099 /// that don't fit the target's parameters for simple loads/stores and can be
1100 /// more efficient than using a library call. This function can return a null
1101 /// SDValue if the target declines to use custom code and a different
1102 /// lowering strategy should be used.
1104 EmitTargetCodeForMemmove(SelectionDAG &DAG,
1106 SDValue Op1, SDValue Op2,
1107 SDValue Op3, unsigned Align,
1108 const Value *DstSV, uint64_t DstOff,
1109 const Value *SrcSV, uint64_t SrcOff) {
1113 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1114 /// memset. This can be used by targets to provide code sequences for cases
1115 /// that don't fit the target's parameters for simple stores and can be more
1116 /// efficient than using a library call. This function can return a null
1117 /// SDValue if the target declines to use custom code and a different
1118 /// lowering strategy should be used.
1120 EmitTargetCodeForMemset(SelectionDAG &DAG,
1122 SDValue Op1, SDValue Op2,
1123 SDValue Op3, unsigned Align,
1124 const Value *DstSV, uint64_t DstOff) {
1128 /// LowerOperation - This callback is invoked for operations that are
1129 /// unsupported by the target, which are registered to use 'custom' lowering,
1130 /// and whose defined values are all legal.
1131 /// If the target has no operations that require custom lowering, it need not
1132 /// implement this. The default implementation of this aborts.
1133 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1135 /// ReplaceNodeResults - This callback is invoked for operations that are
1136 /// unsupported by the target, which are registered to use 'custom' lowering,
1137 /// and whose result type is illegal. This must return a node whose results
1138 /// precisely match the results of the input node. This typically involves a
1139 /// MERGE_VALUES node and/or BUILD_PAIR.
1141 /// If the target has no operations that require custom lowering, it need not
1142 /// implement this. The default implementation aborts.
1143 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
1144 assert(0 && "ReplaceNodeResults not implemented for this target!");
1148 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1149 /// tail call optimization. Targets which want to do tail call optimization
1150 /// should override this function.
1151 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1153 SelectionDAG &DAG) const {
1157 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1158 /// preceeds the RET node and whether the return uses the result of the node
1159 /// or is a void return. This function can be used by the target to determine
1160 /// eligiblity of tail call optimization.
1161 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) {
1162 unsigned NumOps = Ret.getNumOperands();
1164 (Ret.getOperand(0) == SDValue(TheCall,1) ||
1165 Ret.getOperand(0) == SDValue(TheCall,0))) ||
1167 Ret.getOperand(0) == SDValue(TheCall,
1168 TheCall->getNumValues()-1) &&
1169 Ret.getOperand(1) == SDValue(TheCall,0)))
1174 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1175 /// it exists skip possible ISD:TokenFactor.
1176 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1177 unsigned TailCallNodeOpCode) {
1178 if (Chain.getOpcode() == TailCallNodeOpCode) {
1180 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1181 if (Chain.getNumOperands() &&
1182 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1183 return Chain.getOperand(0);
1188 /// getTargetNodeName() - This method returns the name of a target specific
1190 virtual const char *getTargetNodeName(unsigned Opcode) const;
1192 /// createFastISel - This method returns a target specific FastISel object,
1193 /// or null if the target does not support "fast" ISel.
1195 createFastISel(MachineFunction &,
1196 MachineModuleInfo *,
1197 DenseMap<const Value *, unsigned> &,
1198 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1199 DenseMap<const AllocaInst *, int> &
1201 , SmallSet<Instruction*, 8> &CatchInfoLost
1207 //===--------------------------------------------------------------------===//
1208 // Inline Asm Support hooks
1211 enum ConstraintType {
1212 C_Register, // Constraint represents specific register(s).
1213 C_RegisterClass, // Constraint represents any of register(s) in class.
1214 C_Memory, // Memory constraint.
1215 C_Other, // Something else.
1216 C_Unknown // Unsupported constraint.
1219 /// AsmOperandInfo - This contains information for each constraint that we are
1221 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1222 /// ConstraintCode - This contains the actual string for the code, like "m".
1223 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1224 /// most closely matches the operand.
1225 std::string ConstraintCode;
1227 /// ConstraintType - Information about the constraint code, e.g. Register,
1228 /// RegisterClass, Memory, Other, Unknown.
1229 TargetLowering::ConstraintType ConstraintType;
1231 /// CallOperandval - If this is the result output operand or a
1232 /// clobber, this is null, otherwise it is the incoming operand to the
1233 /// CallInst. This gets modified as the asm is processed.
1234 Value *CallOperandVal;
1236 /// ConstraintVT - The ValueType for the operand value.
1239 /// isMatchingInputConstraint - Return true of this is an input operand that
1240 /// is a matching constraint like "4".
1241 bool isMatchingInputConstraint() const;
1243 /// getMatchedOperand - If this is an input matching constraint, this method
1244 /// returns the output operand it matches.
1245 unsigned getMatchedOperand() const;
1247 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1248 : InlineAsm::ConstraintInfo(info),
1249 ConstraintType(TargetLowering::C_Unknown),
1250 CallOperandVal(0), ConstraintVT(MVT::Other) {
1254 /// ComputeConstraintToUse - Determines the constraint code and constraint
1255 /// type to use for the specific AsmOperandInfo, setting
1256 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1257 /// being passed in is available, it can be passed in as Op, otherwise an
1258 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1259 /// constraint of the inline asm instruction being processed is 'm'.
1260 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1263 SelectionDAG *DAG = 0) const;
1265 /// getConstraintType - Given a constraint, return the type of constraint it
1266 /// is for this target.
1267 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1269 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1270 /// return a list of registers that can be used to satisfy the constraint.
1271 /// This should only be used for C_RegisterClass constraints.
1272 virtual std::vector<unsigned>
1273 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1276 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1277 /// {edx}), return the register number and the register class for the
1280 /// Given a register class constraint, like 'r', if this corresponds directly
1281 /// to an LLVM register class, return a register of 0 and the register class
1284 /// This should only be used for C_Register constraints. On error,
1285 /// this returns a register number of 0 and a null register class pointer..
1286 virtual std::pair<unsigned, const TargetRegisterClass*>
1287 getRegForInlineAsmConstraint(const std::string &Constraint,
1290 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1291 /// with another that has more specific requirements based on the type of the
1292 /// corresponding operand. This returns null if there is no replacement to
1294 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1296 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1297 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1298 /// it means one of the asm constraint of the inline asm instruction being
1299 /// processed is 'm'.
1300 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1302 std::vector<SDValue> &Ops,
1303 SelectionDAG &DAG) const;
1305 //===--------------------------------------------------------------------===//
1309 // EmitInstrWithCustomInserter - This method should be implemented by targets
1310 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1311 // instructions are special in various ways, which require special support to
1312 // insert. The specified MachineInstr is created but not inserted into any
1313 // basic blocks, and the scheduler passes ownership of it to this method.
1314 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1315 MachineBasicBlock *MBB);
1317 //===--------------------------------------------------------------------===//
1318 // Addressing mode description hooks (used by LSR etc).
1321 /// AddrMode - This represents an addressing mode of:
1322 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1323 /// If BaseGV is null, there is no BaseGV.
1324 /// If BaseOffs is zero, there is no base offset.
1325 /// If HasBaseReg is false, there is no base register.
1326 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1330 GlobalValue *BaseGV;
1334 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1337 /// isLegalAddressingMode - Return true if the addressing mode represented by
1338 /// AM is legal for this target, for a load/store of the specified type.
1339 /// TODO: Handle pre/postinc as well.
1340 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1342 /// isTruncateFree - Return true if it's free to truncate a value of
1343 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1344 /// register EAX to i16 by referencing its sub-register AX.
1345 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1349 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1353 //===--------------------------------------------------------------------===//
1354 // Div utility functions
1356 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1357 std::vector<SDNode*>* Created) const;
1358 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1359 std::vector<SDNode*>* Created) const;
1362 //===--------------------------------------------------------------------===//
1363 // Runtime Library hooks
1366 /// setLibcallName - Rename the default libcall routine name for the specified
1368 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1369 LibcallRoutineNames[Call] = Name;
1372 /// getLibcallName - Get the libcall routine name for the specified libcall.
1374 const char *getLibcallName(RTLIB::Libcall Call) const {
1375 return LibcallRoutineNames[Call];
1378 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1379 /// result of the comparison libcall against zero.
1380 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1381 CmpLibcallCCs[Call] = CC;
1384 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1385 /// the comparison libcall against zero.
1386 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1387 return CmpLibcallCCs[Call];
1392 const TargetData *TD;
1394 /// PointerTy - The type to use for pointers, usually i32 or i64.
1398 /// IsLittleEndian - True if this is a little endian target.
1400 bool IsLittleEndian;
1402 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1404 bool UsesGlobalOffsetTable;
1406 /// SelectIsExpensive - Tells the code generator not to expand operations
1407 /// into sequences that use the select operations if possible.
1408 bool SelectIsExpensive;
1410 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1411 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1412 /// a real cost model is in place. If we ever optimize for size, this will be
1413 /// set to true unconditionally.
1416 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1417 /// srl/add/sra for a signed divide by power of two, and let the target handle
1419 bool Pow2DivIsCheap;
1421 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1422 /// llvm.setjmp. Defaults to false.
1423 bool UseUnderscoreSetJmp;
1425 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1426 /// llvm.longjmp. Defaults to false.
1427 bool UseUnderscoreLongJmp;
1429 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1433 OutOfRangeShiftAmount ShiftAmtHandling;
1435 /// BooleanContents - Information about the contents of the high-bits in
1436 /// boolean values held in a type wider than i1. See getBooleanContents.
1437 BooleanContent BooleanContents;
1439 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1440 /// total cycles or lowest register usage.
1441 SchedPreference SchedPreferenceInfo;
1443 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1444 unsigned JumpBufSize;
1446 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1448 unsigned JumpBufAlignment;
1450 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1452 unsigned IfCvtBlockSizeLimit;
1454 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1455 /// duplicated during if-conversion.
1456 unsigned IfCvtDupBlockSizeLimit;
1458 /// PrefLoopAlignment - The perferred loop alignment.
1460 unsigned PrefLoopAlignment;
1462 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1463 /// specifies the register that llvm.savestack/llvm.restorestack should save
1465 unsigned StackPointerRegisterToSaveRestore;
1467 /// ExceptionPointerRegister - If set to a physical register, this specifies
1468 /// the register that receives the exception address on entry to a landing
1470 unsigned ExceptionPointerRegister;
1472 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1473 /// the register that receives the exception typeid on entry to a landing
1475 unsigned ExceptionSelectorRegister;
1477 /// RegClassForVT - This indicates the default register class to use for
1478 /// each ValueType the target supports natively.
1479 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1480 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1481 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1483 /// TransformToType - For any value types we are promoting or expanding, this
1484 /// contains the value type that we are changing to. For Expanded types, this
1485 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1486 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1487 /// by the system, this holds the same type (e.g. i32 -> i32).
1488 MVT TransformToType[MVT::LAST_VALUETYPE];
1490 // Defines the capacity of the TargetLowering::OpActions table
1491 static const int OpActionsCapacity = 218;
1493 /// OpActions - For each operation and each value type, keep a LegalizeAction
1494 /// that indicates how instruction selection should deal with the operation.
1495 /// Most operations are Legal (aka, supported natively by the target), but
1496 /// operations that are not should be described. Note that operations on
1497 /// non-legal value types are not described here.
1498 uint64_t OpActions[OpActionsCapacity];
1500 /// LoadExtActions - For each load of load extension type and each value type,
1501 /// keep a LegalizeAction that indicates how instruction selection should deal
1503 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1505 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1506 /// indicates how instruction selection should deal with the store.
1507 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1509 /// IndexedModeActions - For each indexed mode and each value type, keep a
1510 /// pair of LegalizeAction that indicates how instruction selection should
1511 /// deal with the load / store.
1512 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1514 /// ConvertActions - For each conversion from source type to destination type,
1515 /// keep a LegalizeAction that indicates how instruction selection should
1516 /// deal with the conversion.
1517 /// Currently, this is used only for floating->floating conversions
1518 /// (FP_EXTEND and FP_ROUND).
1519 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1521 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1522 /// LegalizeAction that indicates how instruction selection should
1523 /// deal with the condition code.
1524 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1526 ValueTypeActionImpl ValueTypeActions;
1528 std::vector<APFloat> LegalFPImmediates;
1530 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1532 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1533 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1534 /// which sets a bit in this array.
1536 TargetDAGCombineArray[OpActionsCapacity/(sizeof(unsigned char)*8)];
1538 /// PromoteToType - For operations that must be promoted to a specific type,
1539 /// this holds the destination type. This map should be sparse, so don't hold
1542 /// Targets add entries to this map with AddPromotedToType(..), clients access
1543 /// this with getTypeToPromoteTo(..).
1544 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1547 /// LibcallRoutineNames - Stores the name each libcall.
1549 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1551 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1552 /// of each of the comparison libcall against zero.
1553 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1556 /// When lowering @llvm.memset this field specifies the maximum number of
1557 /// store operations that may be substituted for the call to memset. Targets
1558 /// must set this value based on the cost threshold for that target. Targets
1559 /// should assume that the memset will be done using as many of the largest
1560 /// store operations first, followed by smaller ones, if necessary, per
1561 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1562 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1563 /// store. This only applies to setting a constant array of a constant size.
1564 /// @brief Specify maximum number of store instructions per memset call.
1565 unsigned maxStoresPerMemset;
1567 /// When lowering @llvm.memcpy this field specifies the maximum number of
1568 /// store operations that may be substituted for a call to memcpy. Targets
1569 /// must set this value based on the cost threshold for that target. Targets
1570 /// should assume that the memcpy will be done using as many of the largest
1571 /// store operations first, followed by smaller ones, if necessary, per
1572 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1573 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1574 /// and one 1-byte store. This only applies to copying a constant array of
1576 /// @brief Specify maximum bytes of store instructions per memcpy call.
1577 unsigned maxStoresPerMemcpy;
1579 /// When lowering @llvm.memmove this field specifies the maximum number of
1580 /// store instructions that may be substituted for a call to memmove. Targets
1581 /// must set this value based on the cost threshold for that target. Targets
1582 /// should assume that the memmove will be done using as many of the largest
1583 /// store operations first, followed by smaller ones, if necessary, per
1584 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1585 /// with 8-bit alignment would result in nine 1-byte stores. This only
1586 /// applies to copying a constant array of constant size.
1587 /// @brief Specify maximum bytes of store instructions per memmove call.
1588 unsigned maxStoresPerMemmove;
1590 /// This field specifies whether the target machine permits unaligned memory
1591 /// accesses. This is used, for example, to determine the size of store
1592 /// operations when copying small arrays and other similar tasks.
1593 /// @brief Indicate whether the target permits unaligned memory accesses.
1594 bool allowUnalignedMemoryAccesses;
1596 } // end llvm namespace