1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/CodeGen/DebugLoc.h"
33 #include "llvm/Target/TargetMachine.h"
43 class MachineBasicBlock;
44 class MachineFunction;
45 class MachineFrameInfo;
47 class MachineModuleInfo;
54 class TargetRegisterClass;
55 class TargetSubtarget;
58 // FIXME: should this be here?
67 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
70 //===----------------------------------------------------------------------===//
71 /// TargetLowering - This class defines information used to lower LLVM code to
72 /// legal SelectionDAG operators that the target instruction selector can accept
75 /// This class also defines callbacks that targets must implement to lower
76 /// target-specific constructs to SelectionDAG operators.
78 class TargetLowering {
80 /// LegalizeAction - This enum indicates whether operations are valid for a
81 /// target, and if not, what action should be used to make them valid.
83 Legal, // The target natively supports this operation.
84 Promote, // This operation should be executed in a larger type.
85 Expand, // Try to expand this to other ops, otherwise use a libcall.
86 Custom // Use the LowerOperation hook to implement custom lowering.
89 enum OutOfRangeShiftAmount {
90 Undefined, // Oversized shift amounts are undefined (default).
91 Mask, // Shift amounts are auto masked (anded) to value size.
92 Extend // Oversized shift pulls in zeros or sign bits.
95 enum BooleanContent { // How the target represents true/false values.
96 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
97 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
98 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
101 enum SchedPreference {
102 SchedulingForLatency, // Scheduling for shortest total latency.
103 SchedulingForRegPressure // Scheduling for lowest register pressure.
106 explicit TargetLowering(TargetMachine &TM);
107 virtual ~TargetLowering();
109 TargetMachine &getTargetMachine() const { return TM; }
110 const TargetData *getTargetData() const { return TD; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT getPointerTy() const { return PointerTy; }
115 MVT getShiftAmountTy() const { return ShiftAmountTy; }
116 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
118 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
120 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
122 /// isSelectExpensive - Return true if the select operation is expensive for
124 bool isSelectExpensive() const { return SelectIsExpensive; }
126 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
127 /// a sequence of several shifts, adds, and multiplies for this target.
128 bool isIntDivCheap() const { return IntDivIsCheap; }
130 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
132 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
134 /// getSetCCResultType - Return the ValueType of the result of SETCC
135 /// operations. Also used to obtain the target's preferred type for
136 /// the condition operand of SELECT and BRCOND nodes. In the case of
137 /// BRCOND the argument passed is MVT::Other since there are no other
138 /// operands to get a type hint from.
139 virtual MVT getSetCCResultType(MVT VT) const;
141 /// getBooleanContents - For targets without i1 registers, this gives the
142 /// nature of the high-bits of boolean values held in types wider than i1.
143 /// "Boolean values" are special true/false values produced by nodes like
144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
145 /// Not to be confused with general values promoted from i1.
146 BooleanContent getBooleanContents() const { return BooleanContents;}
148 /// getSchedulingPreference - Return target scheduling preference.
149 SchedPreference getSchedulingPreference() const {
150 return SchedPreferenceInfo;
153 /// getRegClassFor - Return the register class that should be used for the
154 /// specified value type. This may only be called on legal types.
155 TargetRegisterClass *getRegClassFor(MVT VT) const {
156 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
157 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
158 assert(RC && "This value type is not natively supported!");
162 /// isTypeLegal - Return true if the target has native support for the
163 /// specified value type. This means that it has a register that directly
164 /// holds it without promotions or expansions.
165 bool isTypeLegal(MVT VT) const {
166 assert(!VT.isSimple() ||
167 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
168 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
171 class ValueTypeActionImpl {
172 /// ValueTypeActions - This is a bitvector that contains two bits for each
173 /// value type, where the two bits correspond to the LegalizeAction enum.
174 /// This can be queried with "getTypeAction(VT)".
175 uint32_t ValueTypeActions[2];
177 ValueTypeActionImpl() {
178 ValueTypeActions[0] = ValueTypeActions[1] = 0;
180 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
181 ValueTypeActions[0] = RHS.ValueTypeActions[0];
182 ValueTypeActions[1] = RHS.ValueTypeActions[1];
185 LegalizeAction getTypeAction(MVT VT) const {
186 if (VT.isExtended()) {
188 return VT.isPow2VectorType() ? Expand : Promote;
191 // First promote to a power-of-two size, then expand if necessary.
192 return VT == VT.getRoundIntegerType() ? Expand : Promote;
193 assert(0 && "Unsupported extended type!");
196 unsigned I = VT.getSimpleVT();
197 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
198 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
200 void setTypeAction(MVT VT, LegalizeAction Action) {
201 unsigned I = VT.getSimpleVT();
202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
203 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
207 const ValueTypeActionImpl &getValueTypeActions() const {
208 return ValueTypeActions;
211 /// getTypeAction - Return how we should legalize values of this type, either
212 /// it is already legal (return 'Legal') or we need to promote it to a larger
213 /// type (return 'Promote'), or we need to expand it into multiple registers
214 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
215 LegalizeAction getTypeAction(MVT VT) const {
216 return ValueTypeActions.getTypeAction(VT);
219 /// getTypeToTransformTo - For types supported by the target, this is an
220 /// identity function. For types that must be promoted to larger types, this
221 /// returns the larger type to promote to. For integer types that are larger
222 /// than the largest integer register, this contains one step in the expansion
223 /// to get to the smaller register. For illegal floating point types, this
224 /// returns the integer type to transform to.
225 MVT getTypeToTransformTo(MVT VT) const {
227 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
228 MVT NVT = TransformToType[VT.getSimpleVT()];
229 assert(getTypeAction(NVT) != Promote &&
230 "Promote may not follow Expand or Promote");
235 MVT NVT = VT.getPow2VectorType();
237 // Vector length is a power of 2 - split to half the size.
238 unsigned NumElts = VT.getVectorNumElements();
239 MVT EltVT = VT.getVectorElementType();
240 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
242 // Promote to a power of two size, avoiding multi-step promotion.
243 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
244 } else if (VT.isInteger()) {
245 MVT NVT = VT.getRoundIntegerType();
247 // Size is a power of two - expand to half the size.
248 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
250 // Promote to a power of two size, avoiding multi-step promotion.
251 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
253 assert(0 && "Unsupported extended type!");
254 return MVT(); // Not reached
257 /// getTypeToExpandTo - For types supported by the target, this is an
258 /// identity function. For types that must be expanded (i.e. integer types
259 /// that are larger than the largest integer register or illegal floating
260 /// point types), this returns the largest legal type it will be expanded to.
261 MVT getTypeToExpandTo(MVT VT) const {
262 assert(!VT.isVector());
264 switch (getTypeAction(VT)) {
268 VT = getTypeToTransformTo(VT);
271 assert(false && "Type is not legal nor is it to be expanded!");
278 /// getVectorTypeBreakdown - Vector types are broken down into some number of
279 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
280 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
281 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
283 /// This method returns the number of registers needed, and the VT for each
284 /// register. It also returns the VT and quantity of the intermediate values
285 /// before they are promoted/expanded.
287 unsigned getVectorTypeBreakdown(MVT VT,
289 unsigned &NumIntermediates,
290 MVT &RegisterVT) const;
292 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
293 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
294 /// this is the case, it returns true and store the intrinsic
295 /// information into the IntrinsicInfo that was passed to the function.
296 typedef struct IntrinsicInfo {
297 unsigned opc; // target opcode
298 MVT memVT; // memory VT
299 const Value* ptrVal; // value representing memory location
300 int offset; // offset off of ptrVal
301 unsigned align; // alignment
302 bool vol; // is volatile?
303 bool readMem; // reads memory?
304 bool writeMem; // writes memory?
307 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
308 CallInst &I, unsigned Intrinsic) {
312 /// getWidenVectorType: given a vector type, returns the type to widen to
313 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
314 /// If there is no vector type that we want to widen to, returns MVT::Other
315 /// When and were to widen is target dependent based on the cost of
316 /// scalarizing vs using the wider vector type.
317 virtual MVT getWidenVectorType(MVT VT) const;
319 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
320 legal_fpimm_iterator legal_fpimm_begin() const {
321 return LegalFPImmediates.begin();
323 legal_fpimm_iterator legal_fpimm_end() const {
324 return LegalFPImmediates.end();
327 /// isShuffleMaskLegal - Targets can use this to indicate that they only
328 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
329 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
330 /// are assumed to be legal.
331 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
335 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
336 /// used by Targets can use this to indicate if there is a suitable
337 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
339 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
341 SelectionDAG &DAG) const {
345 /// getOperationAction - Return how this operation should be treated: either
346 /// it is legal, needs to be promoted to a larger size, needs to be
347 /// expanded to some other code sequence, or the target has a custom expander
349 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
350 if (VT.isExtended()) return Expand;
351 assert(Op < array_lengthof(OpActions) &&
352 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
353 "Table isn't big enough!");
354 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
357 /// isOperationLegalOrCustom - Return true if the specified operation is
358 /// legal on this target or can be made legal with custom lowering. This
359 /// is used to help guide high-level lowering decisions.
360 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
361 return (VT == MVT::Other || isTypeLegal(VT)) &&
362 (getOperationAction(Op, VT) == Legal ||
363 getOperationAction(Op, VT) == Custom);
366 /// isOperationLegal - Return true if the specified operation is legal on this
368 bool isOperationLegal(unsigned Op, MVT VT) const {
369 return (VT == MVT::Other || isTypeLegal(VT)) &&
370 getOperationAction(Op, VT) == Legal;
373 /// getLoadExtAction - Return how this load with extension should be treated:
374 /// either it is legal, needs to be promoted to a larger size, needs to be
375 /// expanded to some other code sequence, or the target has a custom expander
377 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
378 assert(LType < array_lengthof(LoadExtActions) &&
379 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
380 "Table isn't big enough!");
381 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
384 /// isLoadExtLegal - Return true if the specified load with extension is legal
386 bool isLoadExtLegal(unsigned LType, MVT VT) const {
387 return VT.isSimple() &&
388 (getLoadExtAction(LType, VT) == Legal ||
389 getLoadExtAction(LType, VT) == Custom);
392 /// getTruncStoreAction - Return how this store with truncation should be
393 /// treated: either it is legal, needs to be promoted to a larger size, needs
394 /// to be expanded to some other code sequence, or the target has a custom
396 LegalizeAction getTruncStoreAction(MVT ValVT,
398 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
399 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
400 "Table isn't big enough!");
401 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
402 (2*MemVT.getSimpleVT())) & 3);
405 /// isTruncStoreLegal - Return true if the specified store with truncation is
406 /// legal on this target.
407 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
408 return isTypeLegal(ValVT) && MemVT.isSimple() &&
409 (getTruncStoreAction(ValVT, MemVT) == Legal ||
410 getTruncStoreAction(ValVT, MemVT) == Custom);
413 /// getIndexedLoadAction - Return how the indexed load should be treated:
414 /// either it is legal, needs to be promoted to a larger size, needs to be
415 /// expanded to some other code sequence, or the target has a custom expander
418 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
419 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
420 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
421 "Table isn't big enough!");
422 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
423 (2*VT.getSimpleVT())) & 3);
426 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
428 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
429 return VT.isSimple() &&
430 (getIndexedLoadAction(IdxMode, VT) == Legal ||
431 getIndexedLoadAction(IdxMode, VT) == Custom);
434 /// getIndexedStoreAction - Return how the indexed store should be treated:
435 /// either it is legal, needs to be promoted to a larger size, needs to be
436 /// expanded to some other code sequence, or the target has a custom expander
439 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
440 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
441 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
442 "Table isn't big enough!");
443 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
444 (2*VT.getSimpleVT())) & 3);
447 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
449 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
450 return VT.isSimple() &&
451 (getIndexedStoreAction(IdxMode, VT) == Legal ||
452 getIndexedStoreAction(IdxMode, VT) == Custom);
455 /// getConvertAction - Return how the conversion should be treated:
456 /// either it is legal, needs to be promoted to a larger size, needs to be
457 /// expanded to some other code sequence, or the target has a custom expander
460 getConvertAction(MVT FromVT, MVT ToVT) const {
461 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
462 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
463 "Table isn't big enough!");
464 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
465 (2*ToVT.getSimpleVT())) & 3);
468 /// isConvertLegal - Return true if the specified conversion is legal
470 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
471 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
472 (getConvertAction(FromVT, ToVT) == Legal ||
473 getConvertAction(FromVT, ToVT) == Custom);
476 /// getCondCodeAction - Return how the condition code should be treated:
477 /// either it is legal, needs to be expanded to some other code sequence,
478 /// or the target has a custom expander for it.
480 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
481 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
482 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
483 "Table isn't big enough!");
484 LegalizeAction Action = (LegalizeAction)
485 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
486 assert(Action != Promote && "Can't promote condition code!");
490 /// isCondCodeLegal - Return true if the specified condition code is legal
492 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
493 return getCondCodeAction(CC, VT) == Legal ||
494 getCondCodeAction(CC, VT) == Custom;
498 /// getTypeToPromoteTo - If the action for this operation is to promote, this
499 /// method returns the ValueType to promote to.
500 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
501 assert(getOperationAction(Op, VT) == Promote &&
502 "This operation isn't promoted!");
504 // See if this has an explicit type specified.
505 std::map<std::pair<unsigned, MVT::SimpleValueType>,
506 MVT::SimpleValueType>::const_iterator PTTI =
507 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
508 if (PTTI != PromoteToType.end()) return PTTI->second;
510 assert((VT.isInteger() || VT.isFloatingPoint()) &&
511 "Cannot autopromote this type, add it with AddPromotedToType.");
515 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
516 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
517 "Didn't find type to promote to!");
518 } while (!isTypeLegal(NVT) ||
519 getOperationAction(Op, NVT) == Promote);
523 /// getValueType - Return the MVT corresponding to this LLVM type.
524 /// This is fixed by the LLVM operations except for the pointer size. If
525 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
526 /// counterpart (e.g. structs), otherwise it will assert.
527 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
528 MVT VT = MVT::getMVT(Ty, AllowUnknown);
529 return VT == MVT::iPTR ? PointerTy : VT;
532 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
533 /// function arguments in the caller parameter area. This is the actual
534 /// alignment, not its logarithm.
535 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
537 /// getRegisterType - Return the type of registers that this ValueType will
538 /// eventually require.
539 MVT getRegisterType(MVT VT) const {
541 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
542 return RegisterTypeForVT[VT.getSimpleVT()];
546 unsigned NumIntermediates;
547 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
550 if (VT.isInteger()) {
551 return getRegisterType(getTypeToTransformTo(VT));
553 assert(0 && "Unsupported extended type!");
554 return MVT(); // Not reached
557 /// getNumRegisters - Return the number of registers that this ValueType will
558 /// eventually require. This is one for any types promoted to live in larger
559 /// registers, but may be more than one for types (like i64) that are split
560 /// into pieces. For types like i140, which are first promoted then expanded,
561 /// it is the number of registers needed to hold all the bits of the original
562 /// type. For an i140 on a 32 bit machine this means 5 registers.
563 unsigned getNumRegisters(MVT VT) const {
565 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
566 return NumRegistersForVT[VT.getSimpleVT()];
570 unsigned NumIntermediates;
571 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
573 if (VT.isInteger()) {
574 unsigned BitWidth = VT.getSizeInBits();
575 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
576 return (BitWidth + RegWidth - 1) / RegWidth;
578 assert(0 && "Unsupported extended type!");
579 return 0; // Not reached
582 /// ShouldShrinkFPConstant - If true, then instruction selection should
583 /// seek to shrink the FP constant of the specified type to a smaller type
584 /// in order to save space and / or reduce runtime.
585 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
587 /// hasTargetDAGCombine - If true, the target has custom DAG combine
588 /// transformations that it can perform for the specified node.
589 bool hasTargetDAGCombine(ISD::NodeType NT) const {
590 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
591 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
594 /// This function returns the maximum number of store operations permitted
595 /// to replace a call to llvm.memset. The value is set by the target at the
596 /// performance threshold for such a replacement.
597 /// @brief Get maximum # of store operations permitted for llvm.memset
598 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
600 /// This function returns the maximum number of store operations permitted
601 /// to replace a call to llvm.memcpy. The value is set by the target at the
602 /// performance threshold for such a replacement.
603 /// @brief Get maximum # of store operations permitted for llvm.memcpy
604 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
606 /// This function returns the maximum number of store operations permitted
607 /// to replace a call to llvm.memmove. The value is set by the target at the
608 /// performance threshold for such a replacement.
609 /// @brief Get maximum # of store operations permitted for llvm.memmove
610 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
612 /// This function returns true if the target allows unaligned memory accesses.
613 /// This is used, for example, in situations where an array copy/move/set is
614 /// converted to a sequence of store operations. It's use helps to ensure that
615 /// such replacements don't generate code that causes an alignment error
616 /// (trap) on the target machine.
617 /// @brief Determine if the target supports unaligned memory accesses.
618 bool allowsUnalignedMemoryAccesses() const {
619 return allowUnalignedMemoryAccesses;
622 /// getOptimalMemOpType - Returns the target specific optimal type for load
623 /// and store operations as a result of memset, memcpy, and memmove lowering.
624 /// It returns MVT::iAny if SelectionDAG should be responsible for
626 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
627 bool isSrcConst, bool isSrcStr) const {
631 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
632 /// to implement llvm.setjmp.
633 bool usesUnderscoreSetJmp() const {
634 return UseUnderscoreSetJmp;
637 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
638 /// to implement llvm.longjmp.
639 bool usesUnderscoreLongJmp() const {
640 return UseUnderscoreLongJmp;
643 /// getStackPointerRegisterToSaveRestore - If a physical register, this
644 /// specifies the register that llvm.savestack/llvm.restorestack should save
646 unsigned getStackPointerRegisterToSaveRestore() const {
647 return StackPointerRegisterToSaveRestore;
650 /// getExceptionAddressRegister - If a physical register, this returns
651 /// the register that receives the exception address on entry to a landing
653 unsigned getExceptionAddressRegister() const {
654 return ExceptionPointerRegister;
657 /// getExceptionSelectorRegister - If a physical register, this returns
658 /// the register that receives the exception typeid on entry to a landing
660 unsigned getExceptionSelectorRegister() const {
661 return ExceptionSelectorRegister;
664 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
665 /// set, the default is 200)
666 unsigned getJumpBufSize() const {
670 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
671 /// (if never set, the default is 0)
672 unsigned getJumpBufAlignment() const {
673 return JumpBufAlignment;
676 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
677 /// limit. Any block whose size is greater should not be predicated.
678 unsigned getIfCvtBlockSizeLimit() const {
679 return IfCvtBlockSizeLimit;
682 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
683 /// block to be considered for duplication. Any block whose size is greater
684 /// should not be duplicated to facilitate its predication.
685 unsigned getIfCvtDupBlockSizeLimit() const {
686 return IfCvtDupBlockSizeLimit;
689 /// getPrefLoopAlignment - return the preferred loop alignment.
691 unsigned getPrefLoopAlignment() const {
692 return PrefLoopAlignment;
695 /// getPreIndexedAddressParts - returns true by value, base pointer and
696 /// offset pointer and addressing mode by reference if the node's address
697 /// can be legally represented as pre-indexed load / store address.
698 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
700 ISD::MemIndexedMode &AM,
701 SelectionDAG &DAG) const {
705 /// getPostIndexedAddressParts - returns true by value, base pointer and
706 /// offset pointer and addressing mode by reference if this node can be
707 /// combined with a load / store to form a post-indexed load / store.
708 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
709 SDValue &Base, SDValue &Offset,
710 ISD::MemIndexedMode &AM,
711 SelectionDAG &DAG) const {
715 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
717 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
718 SelectionDAG &DAG) const;
720 /// isOffsetFoldingLegal - Return true if folding a constant offset
721 /// with the given GlobalAddress is legal. It is frequently not legal in
722 /// PIC relocation models.
723 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
725 //===--------------------------------------------------------------------===//
726 // TargetLowering Optimization Methods
729 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
730 /// SDValues for returning information from TargetLowering to its clients
731 /// that want to combine
732 struct TargetLoweringOpt {
737 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
739 bool CombineTo(SDValue O, SDValue N) {
745 /// ShrinkDemandedConstant - Check to see if the specified operand of the
746 /// specified instruction is a constant integer. If so, check to see if
747 /// there are any bits set in the constant that are not demanded. If so,
748 /// shrink the constant and return true.
749 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
752 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
753 /// DemandedMask bits of the result of Op are ever used downstream. If we can
754 /// use this information to simplify Op, create a new simplified DAG node and
755 /// return true, returning the original and new nodes in Old and New.
756 /// Otherwise, analyze the expression and return a mask of KnownOne and
757 /// KnownZero bits for the expression (used to simplify the caller).
758 /// The KnownZero/One bits may only be accurate for those bits in the
760 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
761 APInt &KnownZero, APInt &KnownOne,
762 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
764 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
765 /// Mask are known to be either zero or one and return them in the
766 /// KnownZero/KnownOne bitsets.
767 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
771 const SelectionDAG &DAG,
772 unsigned Depth = 0) const;
774 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
775 /// targets that want to expose additional information about sign bits to the
777 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
778 unsigned Depth = 0) const;
780 struct DAGCombinerInfo {
781 void *DC; // The DAG Combiner object.
783 bool CalledByLegalizer;
787 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
788 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
790 bool isBeforeLegalize() const { return BeforeLegalize; }
791 bool isCalledByLegalizer() const { return CalledByLegalizer; }
793 void AddToWorklist(SDNode *N);
794 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
796 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
797 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
799 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
802 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
803 /// and cc. If it is unable to simplify it, return a null SDValue.
804 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
805 ISD::CondCode Cond, bool foldBooleans,
806 DAGCombinerInfo &DCI, DebugLoc dl) const;
808 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
809 /// node is a GlobalAddress + offset.
811 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
813 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
814 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
815 /// location that the 'Base' load is loading from.
816 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
817 const MachineFrameInfo *MFI) const;
819 /// PerformDAGCombine - This method will be invoked for all target nodes and
820 /// for any target-independent nodes that the target has registered with
823 /// The semantics are as follows:
825 /// SDValue.Val == 0 - No change was made
826 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
827 /// otherwise - N should be replaced by the returned Operand.
829 /// In addition, methods provided by DAGCombinerInfo may be used to perform
830 /// more complex transformations.
832 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
834 //===--------------------------------------------------------------------===//
835 // TargetLowering Configuration Methods - These methods should be invoked by
836 // the derived class constructor to configure this object for the target.
840 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
841 /// GOT for PC-relative code.
842 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
844 /// setShiftAmountType - Describe the type that should be used for shift
845 /// amounts. This type defaults to the pointer type.
846 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
848 /// setBooleanContents - Specify how the target extends the result of a
849 /// boolean value from i1 to a wider type. See getBooleanContents.
850 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
852 /// setSchedulingPreference - Specify the target scheduling preference.
853 void setSchedulingPreference(SchedPreference Pref) {
854 SchedPreferenceInfo = Pref;
857 /// setShiftAmountFlavor - Describe how the target handles out of range shift
859 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
860 ShiftAmtHandling = OORSA;
863 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
864 /// use _setjmp to implement llvm.setjmp or the non _ version.
865 /// Defaults to false.
866 void setUseUnderscoreSetJmp(bool Val) {
867 UseUnderscoreSetJmp = Val;
870 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
871 /// use _longjmp to implement llvm.longjmp or the non _ version.
872 /// Defaults to false.
873 void setUseUnderscoreLongJmp(bool Val) {
874 UseUnderscoreLongJmp = Val;
877 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
878 /// specifies the register that llvm.savestack/llvm.restorestack should save
880 void setStackPointerRegisterToSaveRestore(unsigned R) {
881 StackPointerRegisterToSaveRestore = R;
884 /// setExceptionPointerRegister - If set to a physical register, this sets
885 /// the register that receives the exception address on entry to a landing
887 void setExceptionPointerRegister(unsigned R) {
888 ExceptionPointerRegister = R;
891 /// setExceptionSelectorRegister - If set to a physical register, this sets
892 /// the register that receives the exception typeid on entry to a landing
894 void setExceptionSelectorRegister(unsigned R) {
895 ExceptionSelectorRegister = R;
898 /// SelectIsExpensive - Tells the code generator not to expand operations
899 /// into sequences that use the select operations if possible.
900 void setSelectIsExpensive() { SelectIsExpensive = true; }
902 /// setIntDivIsCheap - Tells the code generator that integer divide is
903 /// expensive, and if possible, should be replaced by an alternate sequence
904 /// of instructions not containing an integer divide.
905 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
907 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
908 /// srl/add/sra for a signed divide by power of two, and let the target handle
910 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
912 /// addRegisterClass - Add the specified register class as an available
913 /// regclass for the specified value type. This indicates the selector can
914 /// handle values of that class natively.
915 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
916 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
917 AvailableRegClasses.push_back(std::make_pair(VT, RC));
918 RegClassForVT[VT.getSimpleVT()] = RC;
921 /// computeRegisterProperties - Once all of the register classes are added,
922 /// this allows us to compute derived properties we expose.
923 void computeRegisterProperties();
925 /// setOperationAction - Indicate that the specified operation does not work
926 /// with the specified type and indicate what to do about it.
927 void setOperationAction(unsigned Op, MVT VT,
928 LegalizeAction Action) {
929 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
930 Op < array_lengthof(OpActions) && "Table isn't big enough!");
931 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
932 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
935 /// setLoadExtAction - Indicate that the specified load with extension does
936 /// not work with the with specified type and indicate what to do about it.
937 void setLoadExtAction(unsigned ExtType, MVT VT,
938 LegalizeAction Action) {
939 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
940 ExtType < array_lengthof(LoadExtActions) &&
941 "Table isn't big enough!");
942 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
943 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
946 /// setTruncStoreAction - Indicate that the specified truncating store does
947 /// not work with the with specified type and indicate what to do about it.
948 void setTruncStoreAction(MVT ValVT, MVT MemVT,
949 LegalizeAction Action) {
950 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
951 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
952 "Table isn't big enough!");
953 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
954 MemVT.getSimpleVT()*2);
955 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
956 MemVT.getSimpleVT()*2;
959 /// setIndexedLoadAction - Indicate that the specified indexed load does or
960 /// does not work with the with specified type and indicate what to do abort
961 /// it. NOTE: All indexed mode loads are initialized to Expand in
962 /// TargetLowering.cpp
963 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
964 LegalizeAction Action) {
965 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
966 IdxMode < array_lengthof(IndexedModeActions[0]) &&
967 "Table isn't big enough!");
968 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
969 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
972 /// setIndexedStoreAction - Indicate that the specified indexed store does or
973 /// does not work with the with specified type and indicate what to do about
974 /// it. NOTE: All indexed mode stores are initialized to Expand in
975 /// TargetLowering.cpp
976 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
977 LegalizeAction Action) {
978 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
979 IdxMode < array_lengthof(IndexedModeActions[1]) &&
980 "Table isn't big enough!");
981 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
982 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
985 /// setConvertAction - Indicate that the specified conversion does or does
986 /// not work with the with specified type and indicate what to do about it.
987 void setConvertAction(MVT FromVT, MVT ToVT,
988 LegalizeAction Action) {
989 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
990 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
991 "Table isn't big enough!");
992 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
993 ToVT.getSimpleVT()*2);
994 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
995 ToVT.getSimpleVT()*2;
998 /// setCondCodeAction - Indicate that the specified condition code is or isn't
999 /// supported on the target and indicate what to do about it.
1000 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
1001 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
1002 (unsigned)CC < array_lengthof(CondCodeActions) &&
1003 "Table isn't big enough!");
1004 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
1005 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
1008 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1009 /// promotion code defaults to trying a larger integer/fp until it can find
1010 /// one that works. If that default is insufficient, this method can be used
1011 /// by the target to override the default.
1012 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1013 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
1014 DestVT.getSimpleVT();
1017 /// addLegalFPImmediate - Indicate that this target can instruction select
1018 /// the specified FP immediate natively.
1019 void addLegalFPImmediate(const APFloat& Imm) {
1020 LegalFPImmediates.push_back(Imm);
1023 /// setTargetDAGCombine - Targets should invoke this method for each target
1024 /// independent node that they want to provide a custom DAG combiner for by
1025 /// implementing the PerformDAGCombine virtual method.
1026 void setTargetDAGCombine(ISD::NodeType NT) {
1027 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1028 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1031 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1032 /// bytes); default is 200
1033 void setJumpBufSize(unsigned Size) {
1037 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1038 /// alignment (in bytes); default is 0
1039 void setJumpBufAlignment(unsigned Align) {
1040 JumpBufAlignment = Align;
1043 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1044 /// limit (in number of instructions); default is 2.
1045 void setIfCvtBlockSizeLimit(unsigned Limit) {
1046 IfCvtBlockSizeLimit = Limit;
1049 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1050 /// of instructions) to be considered for code duplication during
1051 /// if-conversion; default is 2.
1052 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1053 IfCvtDupBlockSizeLimit = Limit;
1056 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1057 /// alignment is zero, it means the target does not care about loop alignment.
1058 void setPrefLoopAlignment(unsigned Align) {
1059 PrefLoopAlignment = Align;
1064 virtual const TargetSubtarget *getSubtarget() {
1065 assert(0 && "Not Implemented");
1066 return NULL; // this is here to silence compiler errors
1068 //===--------------------------------------------------------------------===//
1069 // Lowering methods - These methods must be implemented by targets so that
1070 // the SelectionDAGLowering code knows how to lower these.
1073 /// LowerArguments - This hook must be implemented to indicate how we should
1074 /// lower the arguments for the specified function, into the specified DAG.
1076 LowerArguments(Function &F, SelectionDAG &DAG,
1077 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl);
1079 /// LowerCallTo - This hook lowers an abstract call to a function into an
1080 /// actual call. This returns a pair of operands. The first element is the
1081 /// return value for the function (if RetTy is not VoidTy). The second
1082 /// element is the outgoing token chain.
1083 struct ArgListEntry {
1094 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1095 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1097 typedef std::vector<ArgListEntry> ArgListTy;
1098 virtual std::pair<SDValue, SDValue>
1099 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1100 bool isVarArg, bool isInreg, unsigned CallingConv,
1101 bool isTailCall, SDValue Callee, ArgListTy &Args,
1102 SelectionDAG &DAG, DebugLoc dl);
1104 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1105 /// memcpy. This can be used by targets to provide code sequences for cases
1106 /// that don't fit the target's parameters for simple loads/stores and can be
1107 /// more efficient than using a library call. This function can return a null
1108 /// SDValue if the target declines to use custom code and a different
1109 /// lowering strategy should be used.
1111 /// If AlwaysInline is true, the size is constant and the target should not
1112 /// emit any calls and is strongly encouraged to attempt to emit inline code
1113 /// even if it is beyond the usual threshold because this intrinsic is being
1114 /// expanded in a place where calls are not feasible (e.g. within the prologue
1115 /// for another call). If the target chooses to decline an AlwaysInline
1116 /// request here, legalize will resort to using simple loads and stores.
1118 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1120 SDValue Op1, SDValue Op2,
1121 SDValue Op3, unsigned Align,
1123 const Value *DstSV, uint64_t DstOff,
1124 const Value *SrcSV, uint64_t SrcOff) {
1128 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1129 /// memmove. This can be used by targets to provide code sequences for cases
1130 /// that don't fit the target's parameters for simple loads/stores and can be
1131 /// more efficient than using a library call. This function can return a null
1132 /// SDValue if the target declines to use custom code and a different
1133 /// lowering strategy should be used.
1135 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1137 SDValue Op1, SDValue Op2,
1138 SDValue Op3, unsigned Align,
1139 const Value *DstSV, uint64_t DstOff,
1140 const Value *SrcSV, uint64_t SrcOff) {
1144 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1145 /// memset. This can be used by targets to provide code sequences for cases
1146 /// that don't fit the target's parameters for simple stores and can be more
1147 /// efficient than using a library call. This function can return a null
1148 /// SDValue if the target declines to use custom code and a different
1149 /// lowering strategy should be used.
1151 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1153 SDValue Op1, SDValue Op2,
1154 SDValue Op3, unsigned Align,
1155 const Value *DstSV, uint64_t DstOff) {
1159 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1160 /// to legalize nodes with an illegal operand type but legal result types.
1161 /// It replaces the LowerOperation callback in the type Legalizer.
1162 /// The reason we can not do away with LowerOperation entirely is that
1163 /// LegalizeDAG isn't yet ready to use this callback.
1164 /// TODO: Consider merging with ReplaceNodeResults.
1166 /// The target places new result values for the node in Results (their number
1167 /// and types must exactly match those of the original return values of
1168 /// the node), or leaves Results empty, which indicates that the node is not
1169 /// to be custom lowered after all.
1170 /// The default implementation calls LowerOperation.
1171 virtual void LowerOperationWrapper(SDNode *N,
1172 SmallVectorImpl<SDValue> &Results,
1175 /// LowerOperation - This callback is invoked for operations that are
1176 /// unsupported by the target, which are registered to use 'custom' lowering,
1177 /// and whose defined values are all legal.
1178 /// If the target has no operations that require custom lowering, it need not
1179 /// implement this. The default implementation of this aborts.
1180 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1182 /// ReplaceNodeResults - This callback is invoked when a node result type is
1183 /// illegal for the target, and the operation was registered to use 'custom'
1184 /// lowering for that result type. The target places new result values for
1185 /// the node in Results (their number and types must exactly match those of
1186 /// the original return values of the node), or leaves Results empty, which
1187 /// indicates that the node is not to be custom lowered after all.
1189 /// If the target has no operations that require custom lowering, it need not
1190 /// implement this. The default implementation aborts.
1191 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1192 SelectionDAG &DAG) {
1193 assert(0 && "ReplaceNodeResults not implemented for this target!");
1196 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1197 /// tail call optimization. Targets which want to do tail call optimization
1198 /// should override this function.
1199 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1201 SelectionDAG &DAG) const {
1205 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1206 /// preceeds the RET node and whether the return uses the result of the node
1207 /// or is a void return. This function can be used by the target to determine
1208 /// eligiblity of tail call optimization.
1209 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) {
1210 unsigned NumOps = Ret.getNumOperands();
1212 (Ret.getOperand(0) == SDValue(TheCall,1) ||
1213 Ret.getOperand(0) == SDValue(TheCall,0))) ||
1215 Ret.getOperand(0) == SDValue(TheCall,
1216 TheCall->getNumValues()-1) &&
1217 Ret.getOperand(1) == SDValue(TheCall,0)))
1222 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1223 /// it exists. Skip a possible ISD::TokenFactor.
1224 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1225 unsigned TailCallNodeOpCode) {
1226 if (Chain.getOpcode() == TailCallNodeOpCode) {
1228 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1229 if (Chain.getNumOperands() &&
1230 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1231 return Chain.getOperand(0);
1236 /// getTargetNodeName() - This method returns the name of a target specific
1238 virtual const char *getTargetNodeName(unsigned Opcode) const;
1240 /// createFastISel - This method returns a target specific FastISel object,
1241 /// or null if the target does not support "fast" ISel.
1243 createFastISel(MachineFunction &,
1244 MachineModuleInfo *, DwarfWriter *,
1245 DenseMap<const Value *, unsigned> &,
1246 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1247 DenseMap<const AllocaInst *, int> &
1249 , SmallSet<Instruction*, 8> &CatchInfoLost
1255 //===--------------------------------------------------------------------===//
1256 // Inline Asm Support hooks
1259 enum ConstraintType {
1260 C_Register, // Constraint represents specific register(s).
1261 C_RegisterClass, // Constraint represents any of register(s) in class.
1262 C_Memory, // Memory constraint.
1263 C_Other, // Something else.
1264 C_Unknown // Unsupported constraint.
1267 /// AsmOperandInfo - This contains information for each constraint that we are
1269 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1270 /// ConstraintCode - This contains the actual string for the code, like "m".
1271 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1272 /// most closely matches the operand.
1273 std::string ConstraintCode;
1275 /// ConstraintType - Information about the constraint code, e.g. Register,
1276 /// RegisterClass, Memory, Other, Unknown.
1277 TargetLowering::ConstraintType ConstraintType;
1279 /// CallOperandval - If this is the result output operand or a
1280 /// clobber, this is null, otherwise it is the incoming operand to the
1281 /// CallInst. This gets modified as the asm is processed.
1282 Value *CallOperandVal;
1284 /// ConstraintVT - The ValueType for the operand value.
1287 /// isMatchingInputConstraint - Return true of this is an input operand that
1288 /// is a matching constraint like "4".
1289 bool isMatchingInputConstraint() const;
1291 /// getMatchedOperand - If this is an input matching constraint, this method
1292 /// returns the output operand it matches.
1293 unsigned getMatchedOperand() const;
1295 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1296 : InlineAsm::ConstraintInfo(info),
1297 ConstraintType(TargetLowering::C_Unknown),
1298 CallOperandVal(0), ConstraintVT(MVT::Other) {
1302 /// ComputeConstraintToUse - Determines the constraint code and constraint
1303 /// type to use for the specific AsmOperandInfo, setting
1304 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1305 /// being passed in is available, it can be passed in as Op, otherwise an
1306 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1307 /// constraint of the inline asm instruction being processed is 'm'.
1308 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1311 SelectionDAG *DAG = 0) const;
1313 /// getConstraintType - Given a constraint, return the type of constraint it
1314 /// is for this target.
1315 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1317 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1318 /// return a list of registers that can be used to satisfy the constraint.
1319 /// This should only be used for C_RegisterClass constraints.
1320 virtual std::vector<unsigned>
1321 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1324 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1325 /// {edx}), return the register number and the register class for the
1328 /// Given a register class constraint, like 'r', if this corresponds directly
1329 /// to an LLVM register class, return a register of 0 and the register class
1332 /// This should only be used for C_Register constraints. On error,
1333 /// this returns a register number of 0 and a null register class pointer..
1334 virtual std::pair<unsigned, const TargetRegisterClass*>
1335 getRegForInlineAsmConstraint(const std::string &Constraint,
1338 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1339 /// with another that has more specific requirements based on the type of the
1340 /// corresponding operand. This returns null if there is no replacement to
1342 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1344 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1345 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1346 /// it means one of the asm constraint of the inline asm instruction being
1347 /// processed is 'm'.
1348 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1350 std::vector<SDValue> &Ops,
1351 SelectionDAG &DAG) const;
1353 //===--------------------------------------------------------------------===//
1357 // EmitInstrWithCustomInserter - This method should be implemented by targets
1358 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1359 // instructions are special in various ways, which require special support to
1360 // insert. The specified MachineInstr is created but not inserted into any
1361 // basic blocks, and the scheduler passes ownership of it to this method.
1362 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1363 MachineBasicBlock *MBB) const;
1365 //===--------------------------------------------------------------------===//
1366 // Addressing mode description hooks (used by LSR etc).
1369 /// AddrMode - This represents an addressing mode of:
1370 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1371 /// If BaseGV is null, there is no BaseGV.
1372 /// If BaseOffs is zero, there is no base offset.
1373 /// If HasBaseReg is false, there is no base register.
1374 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1378 GlobalValue *BaseGV;
1382 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1385 /// isLegalAddressingMode - Return true if the addressing mode represented by
1386 /// AM is legal for this target, for a load/store of the specified type.
1387 /// TODO: Handle pre/postinc as well.
1388 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1390 /// isTruncateFree - Return true if it's free to truncate a value of
1391 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1392 /// register EAX to i16 by referencing its sub-register AX.
1393 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1397 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1401 //===--------------------------------------------------------------------===//
1402 // Div utility functions
1404 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1405 std::vector<SDNode*>* Created) const;
1406 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1407 std::vector<SDNode*>* Created) const;
1410 //===--------------------------------------------------------------------===//
1411 // Runtime Library hooks
1414 /// setLibcallName - Rename the default libcall routine name for the specified
1416 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1417 LibcallRoutineNames[Call] = Name;
1420 /// getLibcallName - Get the libcall routine name for the specified libcall.
1422 const char *getLibcallName(RTLIB::Libcall Call) const {
1423 return LibcallRoutineNames[Call];
1426 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1427 /// result of the comparison libcall against zero.
1428 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1429 CmpLibcallCCs[Call] = CC;
1432 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1433 /// the comparison libcall against zero.
1434 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1435 return CmpLibcallCCs[Call];
1440 const TargetData *TD;
1442 /// PointerTy - The type to use for pointers, usually i32 or i64.
1446 /// IsLittleEndian - True if this is a little endian target.
1448 bool IsLittleEndian;
1450 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1452 bool UsesGlobalOffsetTable;
1454 /// SelectIsExpensive - Tells the code generator not to expand operations
1455 /// into sequences that use the select operations if possible.
1456 bool SelectIsExpensive;
1458 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1459 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1460 /// a real cost model is in place. If we ever optimize for size, this will be
1461 /// set to true unconditionally.
1464 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1465 /// srl/add/sra for a signed divide by power of two, and let the target handle
1467 bool Pow2DivIsCheap;
1469 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1470 /// llvm.setjmp. Defaults to false.
1471 bool UseUnderscoreSetJmp;
1473 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1474 /// llvm.longjmp. Defaults to false.
1475 bool UseUnderscoreLongJmp;
1477 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1481 OutOfRangeShiftAmount ShiftAmtHandling;
1483 /// BooleanContents - Information about the contents of the high-bits in
1484 /// boolean values held in a type wider than i1. See getBooleanContents.
1485 BooleanContent BooleanContents;
1487 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1488 /// total cycles or lowest register usage.
1489 SchedPreference SchedPreferenceInfo;
1491 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1492 unsigned JumpBufSize;
1494 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1496 unsigned JumpBufAlignment;
1498 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1500 unsigned IfCvtBlockSizeLimit;
1502 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1503 /// duplicated during if-conversion.
1504 unsigned IfCvtDupBlockSizeLimit;
1506 /// PrefLoopAlignment - The perferred loop alignment.
1508 unsigned PrefLoopAlignment;
1510 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1511 /// specifies the register that llvm.savestack/llvm.restorestack should save
1513 unsigned StackPointerRegisterToSaveRestore;
1515 /// ExceptionPointerRegister - If set to a physical register, this specifies
1516 /// the register that receives the exception address on entry to a landing
1518 unsigned ExceptionPointerRegister;
1520 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1521 /// the register that receives the exception typeid on entry to a landing
1523 unsigned ExceptionSelectorRegister;
1525 /// RegClassForVT - This indicates the default register class to use for
1526 /// each ValueType the target supports natively.
1527 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1528 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1529 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1531 /// TransformToType - For any value types we are promoting or expanding, this
1532 /// contains the value type that we are changing to. For Expanded types, this
1533 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1534 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1535 /// by the system, this holds the same type (e.g. i32 -> i32).
1536 MVT TransformToType[MVT::LAST_VALUETYPE];
1538 /// OpActions - For each operation and each value type, keep a LegalizeAction
1539 /// that indicates how instruction selection should deal with the operation.
1540 /// Most operations are Legal (aka, supported natively by the target), but
1541 /// operations that are not should be described. Note that operations on
1542 /// non-legal value types are not described here.
1543 uint64_t OpActions[ISD::BUILTIN_OP_END];
1545 /// LoadExtActions - For each load of load extension type and each value type,
1546 /// keep a LegalizeAction that indicates how instruction selection should deal
1548 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1550 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1551 /// indicates how instruction selection should deal with the store.
1552 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1554 /// IndexedModeActions - For each indexed mode and each value type, keep a
1555 /// pair of LegalizeAction that indicates how instruction selection should
1556 /// deal with the load / store.
1557 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1559 /// ConvertActions - For each conversion from source type to destination type,
1560 /// keep a LegalizeAction that indicates how instruction selection should
1561 /// deal with the conversion.
1562 /// Currently, this is used only for floating->floating conversions
1563 /// (FP_EXTEND and FP_ROUND).
1564 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1566 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1567 /// LegalizeAction that indicates how instruction selection should
1568 /// deal with the condition code.
1569 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1571 ValueTypeActionImpl ValueTypeActions;
1573 std::vector<APFloat> LegalFPImmediates;
1575 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1577 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1578 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1579 /// which sets a bit in this array.
1581 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1583 /// PromoteToType - For operations that must be promoted to a specific type,
1584 /// this holds the destination type. This map should be sparse, so don't hold
1587 /// Targets add entries to this map with AddPromotedToType(..), clients access
1588 /// this with getTypeToPromoteTo(..).
1589 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1592 /// LibcallRoutineNames - Stores the name each libcall.
1594 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1596 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1597 /// of each of the comparison libcall against zero.
1598 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1601 /// When lowering \@llvm.memset this field specifies the maximum number of
1602 /// store operations that may be substituted for the call to memset. Targets
1603 /// must set this value based on the cost threshold for that target. Targets
1604 /// should assume that the memset will be done using as many of the largest
1605 /// store operations first, followed by smaller ones, if necessary, per
1606 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1607 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1608 /// store. This only applies to setting a constant array of a constant size.
1609 /// @brief Specify maximum number of store instructions per memset call.
1610 unsigned maxStoresPerMemset;
1612 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1613 /// store operations that may be substituted for a call to memcpy. Targets
1614 /// must set this value based on the cost threshold for that target. Targets
1615 /// should assume that the memcpy will be done using as many of the largest
1616 /// store operations first, followed by smaller ones, if necessary, per
1617 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1618 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1619 /// and one 1-byte store. This only applies to copying a constant array of
1621 /// @brief Specify maximum bytes of store instructions per memcpy call.
1622 unsigned maxStoresPerMemcpy;
1624 /// When lowering \@llvm.memmove this field specifies the maximum number of
1625 /// store instructions that may be substituted for a call to memmove. Targets
1626 /// must set this value based on the cost threshold for that target. Targets
1627 /// should assume that the memmove will be done using as many of the largest
1628 /// store operations first, followed by smaller ones, if necessary, per
1629 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1630 /// with 8-bit alignment would result in nine 1-byte stores. This only
1631 /// applies to copying a constant array of constant size.
1632 /// @brief Specify maximum bytes of store instructions per memmove call.
1633 unsigned maxStoresPerMemmove;
1635 /// This field specifies whether the target machine permits unaligned memory
1636 /// accesses. This is used, for example, to determine the size of store
1637 /// operations when copying small arrays and other similar tasks.
1638 /// @brief Indicate whether the target permits unaligned memory accesses.
1639 bool allowUnalignedMemoryAccesses;
1641 } // end llvm namespace