1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/Support/DataTypes.h"
36 class TargetRegisterClass;
40 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData &getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// isSetCCExpensive - Return true if the setcc operation is expensive for
92 bool isSetCCExpensive() const { return SetCCIsExpensive; }
94 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
95 /// a sequence of several shifts, adds, and multiplies for this target.
96 bool isIntDivCheap() const { return IntDivIsCheap; }
98 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
100 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
102 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
104 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
106 /// getSetCCResultContents - For targets without boolean registers, this flag
107 /// returns information about the contents of the high-bits in the setcc
109 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
111 /// getSchedulingPreference - Return target scheduling preference.
112 SchedPreference getSchedulingPreference() const {
113 return SchedPreferenceInfo;
116 /// getRegClassFor - Return the register class that should be used for the
117 /// specified value type. This may only be called on legal types.
118 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
119 TargetRegisterClass *RC = RegClassForVT[VT];
120 assert(RC && "This value type is not natively supported!");
124 /// isTypeLegal - Return true if the target has native support for the
125 /// specified value type. This means that it has a register that directly
126 /// holds it without promotions or expansions.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return RegClassForVT[VT] != 0;
131 class ValueTypeActionImpl {
132 /// ValueTypeActions - This is a bitvector that contains two bits for each
133 /// value type, where the two bits correspond to the LegalizeAction enum.
134 /// This can be queried with "getTypeAction(VT)".
135 uint32_t ValueTypeActions[2];
137 ValueTypeActionImpl() {
138 ValueTypeActions[0] = ValueTypeActions[1] = 0;
140 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
141 ValueTypeActions[0] = RHS.ValueTypeActions[0];
142 ValueTypeActions[1] = RHS.ValueTypeActions[1];
145 LegalizeAction getTypeAction(MVT::ValueType VT) const {
146 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
148 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
149 assert(unsigned(VT >> 4) <
150 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
151 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
155 const ValueTypeActionImpl &getValueTypeActions() const {
156 return ValueTypeActions;
159 /// getTypeAction - Return how we should legalize values of this type, either
160 /// it is already legal (return 'Legal') or we need to promote it to a larger
161 /// type (return 'Promote'), or we need to expand it into multiple registers
162 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
163 LegalizeAction getTypeAction(MVT::ValueType VT) const {
164 return ValueTypeActions.getTypeAction(VT);
167 /// getTypeToTransformTo - For types supported by the target, this is an
168 /// identity function. For types that must be promoted to larger types, this
169 /// returns the larger type to promote to. For types that are larger than the
170 /// largest integer register, this contains one step in the expansion to get
171 /// to the smaller register.
172 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
173 return TransformToType[VT];
176 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
177 legal_fpimm_iterator legal_fpimm_begin() const {
178 return LegalFPImmediates.begin();
180 legal_fpimm_iterator legal_fpimm_end() const {
181 return LegalFPImmediates.end();
184 /// getOperationAction - Return how this operation should be treated: either
185 /// it is legal, needs to be promoted to a larger size, needs to be
186 /// expanded to some other code sequence, or the target has a custom expander
188 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
189 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
192 /// isOperationLegal - Return true if the specified operation is legal on this
194 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
195 return getOperationAction(Op, VT) == Legal ||
196 getOperationAction(Op, VT) == Custom;
199 /// getTypeToPromoteTo - If the action for this operation is to promote, this
200 /// method returns the ValueType to promote to.
201 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
202 assert(getOperationAction(Op, VT) == Promote &&
203 "This operation isn't promoted!");
204 MVT::ValueType NVT = VT;
206 NVT = (MVT::ValueType)(NVT+1);
207 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
208 "Didn't find type to promote to!");
209 } while (!isTypeLegal(NVT) ||
210 getOperationAction(Op, NVT) == Promote);
214 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
215 /// This is fixed by the LLVM operations except for the pointer size.
216 MVT::ValueType getValueType(const Type *Ty) const {
217 switch (Ty->getTypeID()) {
218 default: assert(0 && "Unknown type!");
219 case Type::VoidTyID: return MVT::isVoid;
220 case Type::BoolTyID: return MVT::i1;
221 case Type::UByteTyID:
222 case Type::SByteTyID: return MVT::i8;
223 case Type::ShortTyID:
224 case Type::UShortTyID: return MVT::i16;
226 case Type::UIntTyID: return MVT::i32;
228 case Type::ULongTyID: return MVT::i64;
229 case Type::FloatTyID: return MVT::f32;
230 case Type::DoubleTyID: return MVT::f64;
231 case Type::PointerTyID: return PointerTy;
232 case Type::PackedTyID: return MVT::Vector;
236 /// getNumElements - Return the number of registers that this ValueType will
237 /// eventually require. This is always one for all non-integer types, is
238 /// one for any types promoted to live in larger registers, but may be more
239 /// than one for types (like i64) that are split into pieces.
240 unsigned getNumElements(MVT::ValueType VT) const {
241 return NumElementsForVT[VT];
244 /// hasTargetDAGCombine - If true, the target has custom DAG combine
245 /// transformations that it can perform for the specified node.
246 bool hasTargetDAGCombine(ISD::NodeType NT) const {
247 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
250 /// This function returns the maximum number of store operations permitted
251 /// to replace a call to llvm.memset. The value is set by the target at the
252 /// performance threshold for such a replacement.
253 /// @brief Get maximum # of store operations permitted for llvm.memset
254 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
256 /// This function returns the maximum number of store operations permitted
257 /// to replace a call to llvm.memcpy. The value is set by the target at the
258 /// performance threshold for such a replacement.
259 /// @brief Get maximum # of store operations permitted for llvm.memcpy
260 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
262 /// This function returns the maximum number of store operations permitted
263 /// to replace a call to llvm.memmove. The value is set by the target at the
264 /// performance threshold for such a replacement.
265 /// @brief Get maximum # of store operations permitted for llvm.memmove
266 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
268 /// This function returns true if the target allows unaligned memory accesses.
269 /// This is used, for example, in situations where an array copy/move/set is
270 /// converted to a sequence of store operations. It's use helps to ensure that
271 /// such replacements don't generate code that causes an alignment error
272 /// (trap) on the target machine.
273 /// @brief Determine if the target supports unaligned memory accesses.
274 bool allowsUnalignedMemoryAccesses() const {
275 return allowUnalignedMemoryAccesses;
278 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
279 /// to implement llvm.setjmp.
280 bool usesUnderscoreSetJmpLongJmp() const {
281 return UseUnderscoreSetJmpLongJmp;
284 /// getStackPointerRegisterToSaveRestore - If a physical register, this
285 /// specifies the register that llvm.savestack/llvm.restorestack should save
287 unsigned getStackPointerRegisterToSaveRestore() const {
288 return StackPointerRegisterToSaveRestore;
291 //===--------------------------------------------------------------------===//
292 // TargetLowering Optimization Methods
295 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
296 /// SDOperands for returning information from TargetLowering to its clients
297 /// that want to combine
298 struct TargetLoweringOpt {
303 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
305 bool CombineTo(SDOperand O, SDOperand N) {
311 /// ShrinkDemandedConstant - Check to see if the specified operand of the
312 /// specified instruction is a constant integer. If so, check to see if there
313 /// are any bits set in the constant that are not demanded. If so, shrink the
314 /// constant and return true.
315 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
318 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
319 /// use this predicate to simplify operations downstream. Op and Mask are
320 /// known to be the same type.
321 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
324 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
325 /// known to be either zero or one and return them in the KnownZero/KnownOne
326 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
327 /// processing. Targets can implement the computeMaskedBitsForTargetNode
328 /// method, to allow target nodes to be understood.
329 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
330 uint64_t &KnownOne, unsigned Depth = 0) const;
332 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
333 /// DemandedMask bits of the result of Op are ever used downstream. If we can
334 /// use this information to simplify Op, create a new simplified DAG node and
335 /// return true, returning the original and new nodes in Old and New.
336 /// Otherwise, analyze the expression and return a mask of KnownOne and
337 /// KnownZero bits for the expression (used to simplify the caller).
338 /// The KnownZero/One bits may only be accurate for those bits in the
340 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
341 uint64_t &KnownZero, uint64_t &KnownOne,
342 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
344 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
345 /// Mask are known to be either zero or one and return them in the
346 /// KnownZero/KnownOne bitsets.
347 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
351 unsigned Depth = 0) const;
353 struct DAGCombinerInfo {
354 void *DC; // The DAG Combiner object.
359 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
360 : DC(dc), BeforeLegalize(bl), DAG(dag) {}
362 bool isBeforeLegalize() const { return BeforeLegalize; }
364 void AddToWorklist(SDNode *N);
365 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
366 SDOperand CombineTo(SDNode *N, SDOperand Res);
367 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
370 /// PerformDAGCombine - This method will be invoked for all target nodes and
371 /// for any target-independent nodes that the target has registered with
374 /// The semantics are as follows:
376 /// SDOperand.Val == 0 - No change was made
377 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
378 /// otherwise - N should be replaced by the returned Operand.
380 /// In addition, methods provided by DAGCombinerInfo may be used to perform
381 /// more complex transformations.
383 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
385 //===--------------------------------------------------------------------===//
386 // TargetLowering Configuration Methods - These methods should be invoked by
387 // the derived class constructor to configure this object for the target.
392 /// setShiftAmountType - Describe the type that should be used for shift
393 /// amounts. This type defaults to the pointer type.
394 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
396 /// setSetCCResultType - Describe the type that shoudl be used as the result
397 /// of a setcc operation. This defaults to the pointer type.
398 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
400 /// setSetCCResultContents - Specify how the target extends the result of a
401 /// setcc operation in a register.
402 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
404 /// setSchedulingPreference - Specify the target scheduling preference.
405 void setSchedulingPreference(SchedPreference Pref) {
406 SchedPreferenceInfo = Pref;
409 /// setShiftAmountFlavor - Describe how the target handles out of range shift
411 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
412 ShiftAmtHandling = OORSA;
415 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
416 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
417 /// the non _ versions. Defaults to false.
418 void setUseUnderscoreSetJmpLongJmp(bool Val) {
419 UseUnderscoreSetJmpLongJmp = Val;
422 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
423 /// specifies the register that llvm.savestack/llvm.restorestack should save
425 void setStackPointerRegisterToSaveRestore(unsigned R) {
426 StackPointerRegisterToSaveRestore = R;
429 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
430 /// setcc as a conditional branch. This encourages the code generator to fold
431 /// setcc operations into other operations if possible.
432 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
434 /// setIntDivIsCheap - Tells the code generator that integer divide is
435 /// expensive, and if possible, should be replaced by an alternate sequence
436 /// of instructions not containing an integer divide.
437 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
439 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
440 /// srl/add/sra for a signed divide by power of two, and let the target handle
442 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
444 /// addRegisterClass - Add the specified register class as an available
445 /// regclass for the specified value type. This indicates the selector can
446 /// handle values of that class natively.
447 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
448 AvailableRegClasses.push_back(std::make_pair(VT, RC));
449 RegClassForVT[VT] = RC;
452 /// computeRegisterProperties - Once all of the register classes are added,
453 /// this allows us to compute derived properties we expose.
454 void computeRegisterProperties();
456 /// setOperationAction - Indicate that the specified operation does not work
457 /// with the specified type and indicate what to do about it.
458 void setOperationAction(unsigned Op, MVT::ValueType VT,
459 LegalizeAction Action) {
460 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
461 "Table isn't big enough!");
462 OpActions[Op] &= ~(3ULL << VT*2);
463 OpActions[Op] |= (uint64_t)Action << VT*2;
466 /// addLegalFPImmediate - Indicate that this target can instruction select
467 /// the specified FP immediate natively.
468 void addLegalFPImmediate(double Imm) {
469 LegalFPImmediates.push_back(Imm);
472 /// setTargetDAGCombine - Targets should invoke this method for each target
473 /// independent node that they want to provide a custom DAG combiner for by
474 /// implementing the PerformDAGCombine virtual method.
475 void setTargetDAGCombine(ISD::NodeType NT) {
476 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
481 //===--------------------------------------------------------------------===//
482 // Lowering methods - These methods must be implemented by targets so that
483 // the SelectionDAGLowering code knows how to lower these.
486 /// LowerArguments - This hook must be implemented to indicate how we should
487 /// lower the arguments for the specified function, into the specified DAG.
488 virtual std::vector<SDOperand>
489 LowerArguments(Function &F, SelectionDAG &DAG) = 0;
491 /// LowerCallTo - This hook lowers an abstract call to a function into an
492 /// actual call. This returns a pair of operands. The first element is the
493 /// return value for the function (if RetTy is not VoidTy). The second
494 /// element is the outgoing token chain.
495 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
496 virtual std::pair<SDOperand, SDOperand>
497 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
498 unsigned CallingConv, bool isTailCall, SDOperand Callee,
499 ArgListTy &Args, SelectionDAG &DAG) = 0;
501 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
502 /// llvm.frameaddress (depending on the value of the first argument). The
503 /// return values are the result pointer and the resultant token chain. If
504 /// not implemented, both of these intrinsics will return null.
505 virtual std::pair<SDOperand, SDOperand>
506 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
509 /// LowerOperation - This callback is invoked for operations that are
510 /// unsupported by the target, which are registered to use 'custom' lowering,
511 /// and whose defined values are all legal.
512 /// If the target has no operations that require custom lowering, it need not
513 /// implement this. The default implementation of this aborts.
514 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
516 /// CustomPromoteOperation - This callback is invoked for operations that are
517 /// unsupported by the target, are registered to use 'custom' lowering, and
518 /// whose type needs to be promoted.
519 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
521 /// getTargetNodeName() - This method returns the name of a target specific
523 virtual const char *getTargetNodeName(unsigned Opcode) const;
525 //===--------------------------------------------------------------------===//
526 // Inline Asm Support hooks
529 enum ConstraintType {
530 C_Register, // Constraint represents a single register.
531 C_RegisterClass, // Constraint represents one or more registers.
532 C_Memory, // Memory constraint.
533 C_Other, // Something else.
534 C_Unknown // Unsupported constraint.
537 /// getConstraintType - Given a constraint letter, return the type of
538 /// constraint it is for this target.
539 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
542 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
543 /// return a list of registers that can be used to satisfy the constraint.
544 /// This should only be used for C_RegisterClass constraints.
545 virtual std::vector<unsigned>
546 getRegClassForInlineAsmConstraint(const std::string &Constraint,
547 MVT::ValueType VT) const;
549 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
550 /// {edx}), return the register number and the register class for the
551 /// register. This should only be used for C_Register constraints. On error,
552 /// this returns a register number of 0.
553 virtual std::pair<unsigned, const TargetRegisterClass*>
554 getRegForInlineAsmConstraint(const std::string &Constraint,
555 MVT::ValueType VT) const;
558 /// isOperandValidForConstraint - Return true if the specified SDOperand is
559 /// valid for the specified target constraint letter.
560 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
562 //===--------------------------------------------------------------------===//
566 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
567 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
568 // instructions are special in various ways, which require special support to
569 // insert. The specified MachineInstr is created but not inserted into any
570 // basic blocks, and the scheduler passes ownership of it to this method.
571 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
572 MachineBasicBlock *MBB);
576 const TargetData &TD;
578 /// IsLittleEndian - True if this is a little endian target.
582 /// PointerTy - The type to use for pointers, usually i32 or i64.
584 MVT::ValueType PointerTy;
586 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
588 MVT::ValueType ShiftAmountTy;
590 OutOfRangeShiftAmount ShiftAmtHandling;
592 /// SetCCIsExpensive - This is a short term hack for targets that codegen
593 /// setcc as a conditional branch. This encourages the code generator to fold
594 /// setcc operations into other operations if possible.
595 bool SetCCIsExpensive;
597 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
598 /// constants into a sequence of muls, adds, and shifts. This is a hack until
599 /// a real cost model is in place. If we ever optimize for size, this will be
600 /// set to true unconditionally.
603 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
604 /// srl/add/sra for a signed divide by power of two, and let the target handle
608 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
610 MVT::ValueType SetCCResultTy;
612 /// SetCCResultContents - Information about the contents of the high-bits in
613 /// the result of a setcc comparison operation.
614 SetCCResultValue SetCCResultContents;
616 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
617 /// total cycles or lowest register usage.
618 SchedPreference SchedPreferenceInfo;
620 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
621 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
622 bool UseUnderscoreSetJmpLongJmp;
624 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
625 /// specifies the register that llvm.savestack/llvm.restorestack should save
627 unsigned StackPointerRegisterToSaveRestore;
629 /// RegClassForVT - This indicates the default register class to use for
630 /// each ValueType the target supports natively.
631 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
632 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
634 /// TransformToType - For any value types we are promoting or expanding, this
635 /// contains the value type that we are changing to. For Expanded types, this
636 /// contains one step of the expand (e.g. i64 -> i32), even if there are
637 /// multiple steps required (e.g. i64 -> i16). For types natively supported
638 /// by the system, this holds the same type (e.g. i32 -> i32).
639 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
641 /// OpActions - For each operation and each value type, keep a LegalizeAction
642 /// that indicates how instruction selection should deal with the operation.
643 /// Most operations are Legal (aka, supported natively by the target), but
644 /// operations that are not should be described. Note that operations on
645 /// non-legal value types are not described here.
646 uint64_t OpActions[156];
648 ValueTypeActionImpl ValueTypeActions;
650 std::vector<double> LegalFPImmediates;
652 std::vector<std::pair<MVT::ValueType,
653 TargetRegisterClass*> > AvailableRegClasses;
655 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
656 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
657 /// which sets a bit in this array.
658 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
661 /// When lowering %llvm.memset this field specifies the maximum number of
662 /// store operations that may be substituted for the call to memset. Targets
663 /// must set this value based on the cost threshold for that target. Targets
664 /// should assume that the memset will be done using as many of the largest
665 /// store operations first, followed by smaller ones, if necessary, per
666 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
667 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
668 /// store. This only applies to setting a constant array of a constant size.
669 /// @brief Specify maximum number of store instructions per memset call.
670 unsigned maxStoresPerMemset;
672 /// When lowering %llvm.memcpy this field specifies the maximum number of
673 /// store operations that may be substituted for a call to memcpy. Targets
674 /// must set this value based on the cost threshold for that target. Targets
675 /// should assume that the memcpy will be done using as many of the largest
676 /// store operations first, followed by smaller ones, if necessary, per
677 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
678 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
679 /// and one 1-byte store. This only applies to copying a constant array of
681 /// @brief Specify maximum bytes of store instructions per memcpy call.
682 unsigned maxStoresPerMemcpy;
684 /// When lowering %llvm.memmove this field specifies the maximum number of
685 /// store instructions that may be substituted for a call to memmove. Targets
686 /// must set this value based on the cost threshold for that target. Targets
687 /// should assume that the memmove will be done using as many of the largest
688 /// store operations first, followed by smaller ones, if necessary, per
689 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
690 /// with 8-bit alignment would result in nine 1-byte stores. This only
691 /// applies to copying a constant array of constant size.
692 /// @brief Specify maximum bytes of store instructions per memmove call.
693 unsigned maxStoresPerMemmove;
695 /// This field specifies whether the target machine permits unaligned memory
696 /// accesses. This is used, for example, to determine the size of store
697 /// operations when copying small arrays and other similar tasks.
698 /// @brief Indicate whether the target permits unaligned memory accesses.
699 bool allowUnalignedMemoryAccesses;
701 } // end llvm namespace