1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
57 class TargetRegisterClass;
58 class TargetLoweringObjectFile;
61 // FIXME: should this be here?
70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
73 //===----------------------------------------------------------------------===//
74 /// TargetLowering - This class defines information used to lower LLVM code to
75 /// legal SelectionDAG operators that the target instruction selector can accept
78 /// This class also defines callbacks that targets must implement to lower
79 /// target-specific constructs to SelectionDAG operators.
81 class TargetLowering {
82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
85 /// LegalizeAction - This enum indicates whether operations are valid for a
86 /// target, and if not, what action should be used to make them valid.
88 Legal, // The target natively supports this operation.
89 Promote, // This operation should be executed in a larger type.
90 Expand, // Try to expand this to other ops, otherwise use a libcall.
91 Custom // Use the LowerOperation hook to implement custom lowering.
94 enum BooleanContent { // How the target represents true/false values.
95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
96 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
100 enum SchedPreference {
101 SchedulingForLatency, // Scheduling for shortest total latency.
102 SchedulingForRegPressure // Scheduling for lowest register pressure.
105 /// NOTE: The constructor takes ownership of TLOF.
106 explicit TargetLowering(const TargetMachine &TM,
107 const TargetLoweringObjectFile *TLOF);
108 virtual ~TargetLowering();
110 const TargetMachine &getTargetMachine() const { return TM; }
111 const TargetData *getTargetData() const { return TD; }
112 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
114 bool isBigEndian() const { return !IsLittleEndian; }
115 bool isLittleEndian() const { return IsLittleEndian; }
116 MVT getPointerTy() const { return PointerTy; }
117 MVT getShiftAmountTy() const { return ShiftAmountTy; }
119 /// isSelectExpensive - Return true if the select operation is expensive for
121 bool isSelectExpensive() const { return SelectIsExpensive; }
123 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
124 /// a sequence of several shifts, adds, and multiplies for this target.
125 bool isIntDivCheap() const { return IntDivIsCheap; }
127 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
129 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
131 /// getSetCCResultType - Return the ValueType of the result of SETCC
132 /// operations. Also used to obtain the target's preferred type for
133 /// the condition operand of SELECT and BRCOND nodes. In the case of
134 /// BRCOND the argument passed is MVT::Other since there are no other
135 /// operands to get a type hint from.
137 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
139 /// getCmpLibcallReturnType - Return the ValueType for comparison
140 /// libcalls. Comparions libcalls include floating point comparion calls,
141 /// and Ordered/Unordered check calls on floating point numbers.
143 MVT::SimpleValueType getCmpLibcallReturnType() const;
145 /// getBooleanContents - For targets without i1 registers, this gives the
146 /// nature of the high-bits of boolean values held in types wider than i1.
147 /// "Boolean values" are special true/false values produced by nodes like
148 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
149 /// Not to be confused with general values promoted from i1.
150 BooleanContent getBooleanContents() const { return BooleanContents;}
152 /// getSchedulingPreference - Return target scheduling preference.
153 SchedPreference getSchedulingPreference() const {
154 return SchedPreferenceInfo;
157 /// getRegClassFor - Return the register class that should be used for the
158 /// specified value type. This may only be called on legal types.
159 TargetRegisterClass *getRegClassFor(EVT VT) const {
160 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
161 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
162 assert(RC && "This value type is not natively supported!");
166 /// isTypeLegal - Return true if the target has native support for the
167 /// specified value type. This means that it has a register that directly
168 /// holds it without promotions or expansions.
169 bool isTypeLegal(EVT VT) const {
170 assert(!VT.isSimple() ||
171 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
172 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
175 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
176 /// new operations of this type. All Legal types are synthesizable except
177 /// MMX vector types on X86. Non-Legal types are not synthesizable.
178 bool isTypeSynthesizable(EVT VT) const {
179 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
182 class ValueTypeActionImpl {
183 /// ValueTypeActions - This is a bitvector that contains two bits for each
184 /// value type, where the two bits correspond to the LegalizeAction enum.
185 /// This can be queried with "getTypeAction(VT)".
186 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
187 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
189 ValueTypeActionImpl() {
190 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
192 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
193 if (VT.isExtended()) {
195 return VT.isPow2VectorType() ? Expand : Promote;
198 // First promote to a power-of-two size, then expand if necessary.
199 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
200 assert(0 && "Unsupported extended type!");
203 unsigned I = VT.getSimpleVT().SimpleTy;
204 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
205 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
207 void setTypeAction(EVT VT, LegalizeAction Action) {
208 unsigned I = VT.getSimpleVT().SimpleTy;
209 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
210 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
214 const ValueTypeActionImpl &getValueTypeActions() const {
215 return ValueTypeActions;
218 /// getTypeAction - Return how we should legalize values of this type, either
219 /// it is already legal (return 'Legal') or we need to promote it to a larger
220 /// type (return 'Promote'), or we need to expand it into multiple registers
221 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
222 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
223 return ValueTypeActions.getTypeAction(Context, VT);
226 /// getTypeToTransformTo - For types supported by the target, this is an
227 /// identity function. For types that must be promoted to larger types, this
228 /// returns the larger type to promote to. For integer types that are larger
229 /// than the largest integer register, this contains one step in the expansion
230 /// to get to the smaller register. For illegal floating point types, this
231 /// returns the integer type to transform to.
232 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
234 assert((unsigned)VT.getSimpleVT().SimpleTy <
235 array_lengthof(TransformToType));
236 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
237 assert(getTypeAction(Context, NVT) != Promote &&
238 "Promote may not follow Expand or Promote");
243 EVT NVT = VT.getPow2VectorType(Context);
245 // Vector length is a power of 2 - split to half the size.
246 unsigned NumElts = VT.getVectorNumElements();
247 EVT EltVT = VT.getVectorElementType();
248 return (NumElts == 1) ?
249 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
251 // Promote to a power of two size, avoiding multi-step promotion.
252 return getTypeAction(Context, NVT) == Promote ?
253 getTypeToTransformTo(Context, NVT) : NVT;
254 } else if (VT.isInteger()) {
255 EVT NVT = VT.getRoundIntegerType(Context);
257 // Size is a power of two - expand to half the size.
258 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
260 // Promote to a power of two size, avoiding multi-step promotion.
261 return getTypeAction(Context, NVT) == Promote ?
262 getTypeToTransformTo(Context, NVT) : NVT;
264 assert(0 && "Unsupported extended type!");
265 return MVT(MVT::Other); // Not reached
268 /// getTypeToExpandTo - For types supported by the target, this is an
269 /// identity function. For types that must be expanded (i.e. integer types
270 /// that are larger than the largest integer register or illegal floating
271 /// point types), this returns the largest legal type it will be expanded to.
272 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
273 assert(!VT.isVector());
275 switch (getTypeAction(Context, VT)) {
279 VT = getTypeToTransformTo(Context, VT);
282 assert(false && "Type is not legal nor is it to be expanded!");
289 /// getVectorTypeBreakdown - Vector types are broken down into some number of
290 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
291 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
292 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
294 /// This method returns the number of registers needed, and the VT for each
295 /// register. It also returns the VT and quantity of the intermediate values
296 /// before they are promoted/expanded.
298 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
300 unsigned &NumIntermediates,
301 EVT &RegisterVT) const;
303 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
304 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
305 /// this is the case, it returns true and store the intrinsic
306 /// information into the IntrinsicInfo that was passed to the function.
307 struct IntrinsicInfo {
308 unsigned opc; // target opcode
309 EVT memVT; // memory VT
310 const Value* ptrVal; // value representing memory location
311 int offset; // offset off of ptrVal
312 unsigned align; // alignment
313 bool vol; // is volatile?
314 bool readMem; // reads memory?
315 bool writeMem; // writes memory?
318 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
319 const CallInst &I, unsigned Intrinsic) const {
323 /// isFPImmLegal - Returns true if the target can instruction select the
324 /// specified FP immediate natively. If false, the legalizer will materialize
325 /// the FP immediate as a load from a constant pool.
326 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
330 /// isShuffleMaskLegal - Targets can use this to indicate that they only
331 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
332 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
333 /// are assumed to be legal.
334 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
339 /// canOpTrap - Returns true if the operation can trap for the value type.
340 /// VT must be a legal type. By default, we optimistically assume most
341 /// operations don't trap except for divide and remainder.
342 virtual bool canOpTrap(unsigned Op, EVT VT) const;
344 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
345 /// used by Targets can use this to indicate if there is a suitable
346 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
348 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
353 /// getOperationAction - Return how this operation should be treated: either
354 /// it is legal, needs to be promoted to a larger size, needs to be
355 /// expanded to some other code sequence, or the target has a custom expander
357 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
358 if (VT.isExtended()) return Expand;
359 assert(Op < array_lengthof(OpActions[0]) &&
360 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
361 "Table isn't big enough!");
362 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
365 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
368 /// isOperationLegalOrCustom - Return true if the specified operation is
369 /// legal on this target or can be made legal with custom lowering. This
370 /// is used to help guide high-level lowering decisions.
371 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
372 return (VT == MVT::Other || isTypeLegal(VT)) &&
373 (getOperationAction(Op, VT) == Legal ||
374 getOperationAction(Op, VT) == Custom);
377 /// isOperationLegal - Return true if the specified operation is legal on this
379 bool isOperationLegal(unsigned Op, EVT VT) const {
380 return (VT == MVT::Other || isTypeLegal(VT)) &&
381 getOperationAction(Op, VT) == Legal;
384 /// getLoadExtAction - Return how this load with extension should be treated:
385 /// either it is legal, needs to be promoted to a larger size, needs to be
386 /// expanded to some other code sequence, or the target has a custom expander
388 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
389 assert(LType < array_lengthof(LoadExtActions) &&
390 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
391 "Table isn't big enough!");
392 return (LegalizeAction)((LoadExtActions[LType] >>
393 (2*VT.getSimpleVT().SimpleTy)) & 3);
396 /// isLoadExtLegal - Return true if the specified load with extension is legal
398 bool isLoadExtLegal(unsigned LType, EVT VT) const {
399 return VT.isSimple() &&
400 (getLoadExtAction(LType, VT) == Legal ||
401 getLoadExtAction(LType, VT) == Custom);
404 /// getTruncStoreAction - Return how this store with truncation should be
405 /// treated: either it is legal, needs to be promoted to a larger size, needs
406 /// to be expanded to some other code sequence, or the target has a custom
408 LegalizeAction getTruncStoreAction(EVT ValVT,
410 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
411 array_lengthof(TruncStoreActions) &&
412 (unsigned)MemVT.getSimpleVT().SimpleTy <
413 sizeof(TruncStoreActions[0])*4 &&
414 "Table isn't big enough!");
415 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
416 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
419 /// isTruncStoreLegal - Return true if the specified store with truncation is
420 /// legal on this target.
421 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
422 return isTypeLegal(ValVT) && MemVT.isSimple() &&
423 (getTruncStoreAction(ValVT, MemVT) == Legal ||
424 getTruncStoreAction(ValVT, MemVT) == Custom);
427 /// getIndexedLoadAction - Return how the indexed load should be treated:
428 /// either it is legal, needs to be promoted to a larger size, needs to be
429 /// expanded to some other code sequence, or the target has a custom expander
432 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
433 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
434 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
435 "Table isn't big enough!");
436 return (LegalizeAction)((IndexedModeActions[
437 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
440 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
442 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
443 return VT.isSimple() &&
444 (getIndexedLoadAction(IdxMode, VT) == Legal ||
445 getIndexedLoadAction(IdxMode, VT) == Custom);
448 /// getIndexedStoreAction - Return how the indexed store should be treated:
449 /// either it is legal, needs to be promoted to a larger size, needs to be
450 /// expanded to some other code sequence, or the target has a custom expander
453 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
454 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
455 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
456 "Table isn't big enough!");
457 return (LegalizeAction)((IndexedModeActions[
458 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
461 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
463 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
464 return VT.isSimple() &&
465 (getIndexedStoreAction(IdxMode, VT) == Legal ||
466 getIndexedStoreAction(IdxMode, VT) == Custom);
469 /// getCondCodeAction - Return how the condition code should be treated:
470 /// either it is legal, needs to be expanded to some other code sequence,
471 /// or the target has a custom expander for it.
473 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
474 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
475 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
476 "Table isn't big enough!");
477 LegalizeAction Action = (LegalizeAction)
478 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
479 assert(Action != Promote && "Can't promote condition code!");
483 /// isCondCodeLegal - Return true if the specified condition code is legal
485 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
486 return getCondCodeAction(CC, VT) == Legal ||
487 getCondCodeAction(CC, VT) == Custom;
491 /// getTypeToPromoteTo - If the action for this operation is to promote, this
492 /// method returns the ValueType to promote to.
493 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
494 assert(getOperationAction(Op, VT) == Promote &&
495 "This operation isn't promoted!");
497 // See if this has an explicit type specified.
498 std::map<std::pair<unsigned, MVT::SimpleValueType>,
499 MVT::SimpleValueType>::const_iterator PTTI =
500 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
501 if (PTTI != PromoteToType.end()) return PTTI->second;
503 assert((VT.isInteger() || VT.isFloatingPoint()) &&
504 "Cannot autopromote this type, add it with AddPromotedToType.");
508 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
509 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
510 "Didn't find type to promote to!");
511 } while (!isTypeLegal(NVT) ||
512 getOperationAction(Op, NVT) == Promote);
516 /// getValueType - Return the EVT corresponding to this LLVM type.
517 /// This is fixed by the LLVM operations except for the pointer size. If
518 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
519 /// counterpart (e.g. structs), otherwise it will assert.
520 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
521 EVT VT = EVT::getEVT(Ty, AllowUnknown);
522 return VT == MVT::iPTR ? PointerTy : VT;
525 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
526 /// function arguments in the caller parameter area. This is the actual
527 /// alignment, not its logarithm.
528 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
530 /// getRegisterType - Return the type of registers that this ValueType will
531 /// eventually require.
532 EVT getRegisterType(MVT VT) const {
533 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
534 return RegisterTypeForVT[VT.SimpleTy];
537 /// getRegisterType - Return the type of registers that this ValueType will
538 /// eventually require.
539 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
541 assert((unsigned)VT.getSimpleVT().SimpleTy <
542 array_lengthof(RegisterTypeForVT));
543 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
547 unsigned NumIntermediates;
548 (void)getVectorTypeBreakdown(Context, VT, VT1,
549 NumIntermediates, RegisterVT);
552 if (VT.isInteger()) {
553 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
555 assert(0 && "Unsupported extended type!");
556 return EVT(MVT::Other); // Not reached
559 /// getNumRegisters - Return the number of registers that this ValueType will
560 /// eventually require. This is one for any types promoted to live in larger
561 /// registers, but may be more than one for types (like i64) that are split
562 /// into pieces. For types like i140, which are first promoted then expanded,
563 /// it is the number of registers needed to hold all the bits of the original
564 /// type. For an i140 on a 32 bit machine this means 5 registers.
565 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
567 assert((unsigned)VT.getSimpleVT().SimpleTy <
568 array_lengthof(NumRegistersForVT));
569 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
573 unsigned NumIntermediates;
574 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
576 if (VT.isInteger()) {
577 unsigned BitWidth = VT.getSizeInBits();
578 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
579 return (BitWidth + RegWidth - 1) / RegWidth;
581 assert(0 && "Unsupported extended type!");
582 return 0; // Not reached
585 /// ShouldShrinkFPConstant - If true, then instruction selection should
586 /// seek to shrink the FP constant of the specified type to a smaller type
587 /// in order to save space and / or reduce runtime.
588 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
590 /// hasTargetDAGCombine - If true, the target has custom DAG combine
591 /// transformations that it can perform for the specified node.
592 bool hasTargetDAGCombine(ISD::NodeType NT) const {
593 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
594 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
597 /// This function returns the maximum number of store operations permitted
598 /// to replace a call to llvm.memset. The value is set by the target at the
599 /// performance threshold for such a replacement.
600 /// @brief Get maximum # of store operations permitted for llvm.memset
601 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
603 /// This function returns the maximum number of store operations permitted
604 /// to replace a call to llvm.memcpy. The value is set by the target at the
605 /// performance threshold for such a replacement.
606 /// @brief Get maximum # of store operations permitted for llvm.memcpy
607 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
609 /// This function returns the maximum number of store operations permitted
610 /// to replace a call to llvm.memmove. The value is set by the target at the
611 /// performance threshold for such a replacement.
612 /// @brief Get maximum # of store operations permitted for llvm.memmove
613 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
615 /// This function returns true if the target allows unaligned memory accesses.
616 /// of the specified type. This is used, for example, in situations where an
617 /// array copy/move/set is converted to a sequence of store operations. It's
618 /// use helps to ensure that such replacements don't generate code that causes
619 /// an alignment error (trap) on the target machine.
620 /// @brief Determine if the target supports unaligned memory accesses.
621 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
625 /// This function returns true if the target would benefit from code placement
627 /// @brief Determine if the target should perform code placement optimization.
628 bool shouldOptimizeCodePlacement() const {
629 return benefitFromCodePlacementOpt;
632 /// getOptimalMemOpType - Returns the target specific optimal type for load
633 /// and store operations as a result of memset, memcpy, and memmove
634 /// lowering. If DstAlign is zero that means it's safe to destination
635 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
636 /// means there isn't a need to check it against alignment requirement,
637 /// probably because the source does not need to be loaded. If
638 /// 'NonScalarIntSafe' is true, that means it's safe to return a
639 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
640 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
641 /// constant so it does not need to be loaded.
642 /// It returns EVT::Other if the type should be determined using generic
643 /// target-independent logic.
644 virtual EVT getOptimalMemOpType(uint64_t Size,
645 unsigned DstAlign, unsigned SrcAlign,
646 bool NonScalarIntSafe, bool MemcpyStrSrc,
647 MachineFunction &MF) const {
651 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
652 /// to implement llvm.setjmp.
653 bool usesUnderscoreSetJmp() const {
654 return UseUnderscoreSetJmp;
657 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
658 /// to implement llvm.longjmp.
659 bool usesUnderscoreLongJmp() const {
660 return UseUnderscoreLongJmp;
663 /// getStackPointerRegisterToSaveRestore - If a physical register, this
664 /// specifies the register that llvm.savestack/llvm.restorestack should save
666 unsigned getStackPointerRegisterToSaveRestore() const {
667 return StackPointerRegisterToSaveRestore;
670 /// getExceptionAddressRegister - If a physical register, this returns
671 /// the register that receives the exception address on entry to a landing
673 unsigned getExceptionAddressRegister() const {
674 return ExceptionPointerRegister;
677 /// getExceptionSelectorRegister - If a physical register, this returns
678 /// the register that receives the exception typeid on entry to a landing
680 unsigned getExceptionSelectorRegister() const {
681 return ExceptionSelectorRegister;
684 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
685 /// set, the default is 200)
686 unsigned getJumpBufSize() const {
690 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
691 /// (if never set, the default is 0)
692 unsigned getJumpBufAlignment() const {
693 return JumpBufAlignment;
696 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
697 /// limit. Any block whose size is greater should not be predicated.
698 unsigned getIfCvtBlockSizeLimit() const {
699 return IfCvtBlockSizeLimit;
702 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
703 /// block to be considered for duplication. Any block whose size is greater
704 /// should not be duplicated to facilitate its predication.
705 unsigned getIfCvtDupBlockSizeLimit() const {
706 return IfCvtDupBlockSizeLimit;
709 /// getPrefLoopAlignment - return the preferred loop alignment.
711 unsigned getPrefLoopAlignment() const {
712 return PrefLoopAlignment;
715 /// getPreIndexedAddressParts - returns true by value, base pointer and
716 /// offset pointer and addressing mode by reference if the node's address
717 /// can be legally represented as pre-indexed load / store address.
718 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
720 ISD::MemIndexedMode &AM,
721 SelectionDAG &DAG) const {
725 /// getPostIndexedAddressParts - returns true by value, base pointer and
726 /// offset pointer and addressing mode by reference if this node can be
727 /// combined with a load / store to form a post-indexed load / store.
728 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
729 SDValue &Base, SDValue &Offset,
730 ISD::MemIndexedMode &AM,
731 SelectionDAG &DAG) const {
735 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
736 /// current function. The returned value is a member of the
737 /// MachineJumpTableInfo::JTEntryKind enum.
738 virtual unsigned getJumpTableEncoding() const;
740 virtual const MCExpr *
741 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
742 const MachineBasicBlock *MBB, unsigned uid,
743 MCContext &Ctx) const {
744 assert(0 && "Need to implement this hook if target has custom JTIs");
748 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
750 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
751 SelectionDAG &DAG) const;
753 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
754 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
756 virtual const MCExpr *
757 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
758 unsigned JTI, MCContext &Ctx) const;
760 /// isOffsetFoldingLegal - Return true if folding a constant offset
761 /// with the given GlobalAddress is legal. It is frequently not legal in
762 /// PIC relocation models.
763 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
765 /// getFunctionAlignment - Return the Log2 alignment of this function.
766 virtual unsigned getFunctionAlignment(const Function *) const = 0;
768 //===--------------------------------------------------------------------===//
769 // TargetLowering Optimization Methods
772 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
773 /// SDValues for returning information from TargetLowering to its clients
774 /// that want to combine
775 struct TargetLoweringOpt {
783 explicit TargetLoweringOpt(SelectionDAG &InDAG,
785 bool Shrink = false) :
786 DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {}
788 bool LegalTypes() const { return LegalTys; }
789 bool LegalOperations() const { return LegalOps; }
791 bool CombineTo(SDValue O, SDValue N) {
797 /// ShrinkDemandedConstant - Check to see if the specified operand of the
798 /// specified instruction is a constant integer. If so, check to see if
799 /// there are any bits set in the constant that are not demanded. If so,
800 /// shrink the constant and return true.
801 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
803 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
804 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
805 /// cast, but it could be generalized for targets with other types of
806 /// implicit widening casts.
807 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
811 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
812 /// DemandedMask bits of the result of Op are ever used downstream. If we can
813 /// use this information to simplify Op, create a new simplified DAG node and
814 /// return true, returning the original and new nodes in Old and New.
815 /// Otherwise, analyze the expression and return a mask of KnownOne and
816 /// KnownZero bits for the expression (used to simplify the caller).
817 /// The KnownZero/One bits may only be accurate for those bits in the
819 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
820 APInt &KnownZero, APInt &KnownOne,
821 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
823 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
824 /// Mask are known to be either zero or one and return them in the
825 /// KnownZero/KnownOne bitsets.
826 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
830 const SelectionDAG &DAG,
831 unsigned Depth = 0) const;
833 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
834 /// targets that want to expose additional information about sign bits to the
836 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
837 unsigned Depth = 0) const;
839 struct DAGCombinerInfo {
840 void *DC; // The DAG Combiner object.
842 bool BeforeLegalizeOps;
843 bool CalledByLegalizer;
847 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
848 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
849 CalledByLegalizer(cl), DAG(dag) {}
851 bool isBeforeLegalize() const { return BeforeLegalize; }
852 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
853 bool isCalledByLegalizer() const { return CalledByLegalizer; }
855 void AddToWorklist(SDNode *N);
856 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
858 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
859 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
861 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
864 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
865 /// and cc. If it is unable to simplify it, return a null SDValue.
866 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
867 ISD::CondCode Cond, bool foldBooleans,
868 DAGCombinerInfo &DCI, DebugLoc dl) const;
870 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
871 /// node is a GlobalAddress + offset.
873 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
875 /// PerformDAGCombine - This method will be invoked for all target nodes and
876 /// for any target-independent nodes that the target has registered with
879 /// The semantics are as follows:
881 /// SDValue.Val == 0 - No change was made
882 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
883 /// otherwise - N should be replaced by the returned Operand.
885 /// In addition, methods provided by DAGCombinerInfo may be used to perform
886 /// more complex transformations.
888 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
890 /// isTypeDesirableForOp - Return true if the target has native support for
891 /// the specified value type and it is 'desirable' to use the type for the
892 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
893 /// instruction encodings are longer and some i16 instructions are slow.
894 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
895 // By default, assume all legal types are desirable.
896 return isTypeLegal(VT);
899 /// IsDesirableToPromoteOp - This method query the target whether it is
900 /// beneficial for dag combiner to promote the specified node. If true, it
901 /// should return the desired promotion type by reference.
902 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
906 //===--------------------------------------------------------------------===//
907 // TargetLowering Configuration Methods - These methods should be invoked by
908 // the derived class constructor to configure this object for the target.
912 /// setShiftAmountType - Describe the type that should be used for shift
913 /// amounts. This type defaults to the pointer type.
914 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
916 /// setBooleanContents - Specify how the target extends the result of a
917 /// boolean value from i1 to a wider type. See getBooleanContents.
918 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
920 /// setSchedulingPreference - Specify the target scheduling preference.
921 void setSchedulingPreference(SchedPreference Pref) {
922 SchedPreferenceInfo = Pref;
925 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
926 /// use _setjmp to implement llvm.setjmp or the non _ version.
927 /// Defaults to false.
928 void setUseUnderscoreSetJmp(bool Val) {
929 UseUnderscoreSetJmp = Val;
932 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
933 /// use _longjmp to implement llvm.longjmp or the non _ version.
934 /// Defaults to false.
935 void setUseUnderscoreLongJmp(bool Val) {
936 UseUnderscoreLongJmp = Val;
939 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
940 /// specifies the register that llvm.savestack/llvm.restorestack should save
942 void setStackPointerRegisterToSaveRestore(unsigned R) {
943 StackPointerRegisterToSaveRestore = R;
946 /// setExceptionPointerRegister - If set to a physical register, this sets
947 /// the register that receives the exception address on entry to a landing
949 void setExceptionPointerRegister(unsigned R) {
950 ExceptionPointerRegister = R;
953 /// setExceptionSelectorRegister - If set to a physical register, this sets
954 /// the register that receives the exception typeid on entry to a landing
956 void setExceptionSelectorRegister(unsigned R) {
957 ExceptionSelectorRegister = R;
960 /// SelectIsExpensive - Tells the code generator not to expand operations
961 /// into sequences that use the select operations if possible.
962 void setSelectIsExpensive() { SelectIsExpensive = true; }
964 /// setIntDivIsCheap - Tells the code generator that integer divide is
965 /// expensive, and if possible, should be replaced by an alternate sequence
966 /// of instructions not containing an integer divide.
967 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
969 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
970 /// srl/add/sra for a signed divide by power of two, and let the target handle
972 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
974 /// addRegisterClass - Add the specified register class as an available
975 /// regclass for the specified value type. This indicates the selector can
976 /// handle values of that class natively.
977 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
978 bool isSynthesizable = true) {
979 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
980 AvailableRegClasses.push_back(std::make_pair(VT, RC));
981 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
982 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
985 /// computeRegisterProperties - Once all of the register classes are added,
986 /// this allows us to compute derived properties we expose.
987 void computeRegisterProperties();
989 /// setOperationAction - Indicate that the specified operation does not work
990 /// with the specified type and indicate what to do about it.
991 void setOperationAction(unsigned Op, MVT VT,
992 LegalizeAction Action) {
993 unsigned I = (unsigned)VT.SimpleTy;
996 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
997 OpActions[I][Op] |= (uint64_t)Action << (J*2);
1000 /// setLoadExtAction - Indicate that the specified load with extension does
1001 /// not work with the specified type and indicate what to do about it.
1002 void setLoadExtAction(unsigned ExtType, MVT VT,
1003 LegalizeAction Action) {
1004 assert((unsigned)VT.SimpleTy*2 < 63 &&
1005 ExtType < array_lengthof(LoadExtActions) &&
1006 "Table isn't big enough!");
1007 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1008 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
1011 /// setTruncStoreAction - Indicate that the specified truncating store does
1012 /// not work with the specified type and indicate what to do about it.
1013 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1014 LegalizeAction Action) {
1015 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
1016 (unsigned)MemVT.SimpleTy*2 < 63 &&
1017 "Table isn't big enough!");
1018 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
1019 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
1022 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1023 /// does not work with the specified type and indicate what to do abort
1024 /// it. NOTE: All indexed mode loads are initialized to Expand in
1025 /// TargetLowering.cpp
1026 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1027 LegalizeAction Action) {
1028 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1029 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1030 "Table isn't big enough!");
1031 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1034 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1035 /// does not work with the specified type and indicate what to do about
1036 /// it. NOTE: All indexed mode stores are initialized to Expand in
1037 /// TargetLowering.cpp
1038 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1039 LegalizeAction Action) {
1040 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1041 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1042 "Table isn't big enough!");
1043 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1046 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1047 /// supported on the target and indicate what to do about it.
1048 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1049 LegalizeAction Action) {
1050 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1051 (unsigned)CC < array_lengthof(CondCodeActions) &&
1052 "Table isn't big enough!");
1053 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1054 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1057 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1058 /// promotion code defaults to trying a larger integer/fp until it can find
1059 /// one that works. If that default is insufficient, this method can be used
1060 /// by the target to override the default.
1061 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1062 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1065 /// setTargetDAGCombine - Targets should invoke this method for each target
1066 /// independent node that they want to provide a custom DAG combiner for by
1067 /// implementing the PerformDAGCombine virtual method.
1068 void setTargetDAGCombine(ISD::NodeType NT) {
1069 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1070 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1073 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1074 /// bytes); default is 200
1075 void setJumpBufSize(unsigned Size) {
1079 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1080 /// alignment (in bytes); default is 0
1081 void setJumpBufAlignment(unsigned Align) {
1082 JumpBufAlignment = Align;
1085 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1086 /// limit (in number of instructions); default is 2.
1087 void setIfCvtBlockSizeLimit(unsigned Limit) {
1088 IfCvtBlockSizeLimit = Limit;
1091 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1092 /// of instructions) to be considered for code duplication during
1093 /// if-conversion; default is 2.
1094 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1095 IfCvtDupBlockSizeLimit = Limit;
1098 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1099 /// alignment is zero, it means the target does not care about loop alignment.
1100 void setPrefLoopAlignment(unsigned Align) {
1101 PrefLoopAlignment = Align;
1105 //===--------------------------------------------------------------------===//
1106 // Lowering methods - These methods must be implemented by targets so that
1107 // the SelectionDAGLowering code knows how to lower these.
1110 /// LowerFormalArguments - This hook must be implemented to lower the
1111 /// incoming (formal) arguments, described by the Ins array, into the
1112 /// specified DAG. The implementation should fill in the InVals array
1113 /// with legal-type argument values, and return the resulting token
1117 LowerFormalArguments(SDValue Chain,
1118 CallingConv::ID CallConv, bool isVarArg,
1119 const SmallVectorImpl<ISD::InputArg> &Ins,
1120 DebugLoc dl, SelectionDAG &DAG,
1121 SmallVectorImpl<SDValue> &InVals) const {
1122 assert(0 && "Not Implemented");
1123 return SDValue(); // this is here to silence compiler errors
1126 /// LowerCallTo - This function lowers an abstract call to a function into an
1127 /// actual call. This returns a pair of operands. The first element is the
1128 /// return value for the function (if RetTy is not VoidTy). The second
1129 /// element is the outgoing token chain. It calls LowerCall to do the actual
1131 struct ArgListEntry {
1142 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1143 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1145 typedef std::vector<ArgListEntry> ArgListTy;
1146 std::pair<SDValue, SDValue>
1147 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1148 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1149 CallingConv::ID CallConv, bool isTailCall,
1150 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1151 SelectionDAG &DAG, DebugLoc dl) const;
1153 /// LowerCall - This hook must be implemented to lower calls into the
1154 /// the specified DAG. The outgoing arguments to the call are described
1155 /// by the Outs array, and the values to be returned by the call are
1156 /// described by the Ins array. The implementation should fill in the
1157 /// InVals array with legal-type return values from the call, and return
1158 /// the resulting token chain value.
1160 LowerCall(SDValue Chain, SDValue Callee,
1161 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1162 const SmallVectorImpl<ISD::OutputArg> &Outs,
1163 const SmallVectorImpl<ISD::InputArg> &Ins,
1164 DebugLoc dl, SelectionDAG &DAG,
1165 SmallVectorImpl<SDValue> &InVals) const {
1166 assert(0 && "Not Implemented");
1167 return SDValue(); // this is here to silence compiler errors
1170 /// CanLowerReturn - This hook should be implemented to check whether the
1171 /// return values described by the Outs array can fit into the return
1172 /// registers. If false is returned, an sret-demotion is performed.
1174 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1175 const SmallVectorImpl<EVT> &OutTys,
1176 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1177 SelectionDAG &DAG) const
1179 // Return true by default to get preexisting behavior.
1183 /// LowerReturn - This hook must be implemented to lower outgoing
1184 /// return values, described by the Outs array, into the specified
1185 /// DAG. The implementation should return the resulting token chain
1189 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1190 const SmallVectorImpl<ISD::OutputArg> &Outs,
1191 DebugLoc dl, SelectionDAG &DAG) const {
1192 assert(0 && "Not Implemented");
1193 return SDValue(); // this is here to silence compiler errors
1196 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1197 /// to legalize nodes with an illegal operand type but legal result types.
1198 /// It replaces the LowerOperation callback in the type Legalizer.
1199 /// The reason we can not do away with LowerOperation entirely is that
1200 /// LegalizeDAG isn't yet ready to use this callback.
1201 /// TODO: Consider merging with ReplaceNodeResults.
1203 /// The target places new result values for the node in Results (their number
1204 /// and types must exactly match those of the original return values of
1205 /// the node), or leaves Results empty, which indicates that the node is not
1206 /// to be custom lowered after all.
1207 /// The default implementation calls LowerOperation.
1208 virtual void LowerOperationWrapper(SDNode *N,
1209 SmallVectorImpl<SDValue> &Results,
1210 SelectionDAG &DAG) const;
1212 /// LowerOperation - This callback is invoked for operations that are
1213 /// unsupported by the target, which are registered to use 'custom' lowering,
1214 /// and whose defined values are all legal.
1215 /// If the target has no operations that require custom lowering, it need not
1216 /// implement this. The default implementation of this aborts.
1217 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1219 /// ReplaceNodeResults - This callback is invoked when a node result type is
1220 /// illegal for the target, and the operation was registered to use 'custom'
1221 /// lowering for that result type. The target places new result values for
1222 /// the node in Results (their number and types must exactly match those of
1223 /// the original return values of the node), or leaves Results empty, which
1224 /// indicates that the node is not to be custom lowered after all.
1226 /// If the target has no operations that require custom lowering, it need not
1227 /// implement this. The default implementation aborts.
1228 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1229 SelectionDAG &DAG) const {
1230 assert(0 && "ReplaceNodeResults not implemented for this target!");
1233 /// getTargetNodeName() - This method returns the name of a target specific
1235 virtual const char *getTargetNodeName(unsigned Opcode) const;
1237 /// createFastISel - This method returns a target specific FastISel object,
1238 /// or null if the target does not support "fast" ISel.
1240 createFastISel(MachineFunction &,
1241 DenseMap<const Value *, unsigned> &,
1242 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1243 DenseMap<const AllocaInst *, int> &,
1244 std::vector<std::pair<MachineInstr*, unsigned> > &
1246 , SmallSet<const Instruction *, 8> &CatchInfoLost
1252 //===--------------------------------------------------------------------===//
1253 // Inline Asm Support hooks
1256 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1257 /// call to be explicit llvm code if it wants to. This is useful for
1258 /// turning simple inline asms into LLVM intrinsics, which gives the
1259 /// compiler more information about the behavior of the code.
1260 virtual bool ExpandInlineAsm(CallInst *CI) const {
1264 enum ConstraintType {
1265 C_Register, // Constraint represents specific register(s).
1266 C_RegisterClass, // Constraint represents any of register(s) in class.
1267 C_Memory, // Memory constraint.
1268 C_Other, // Something else.
1269 C_Unknown // Unsupported constraint.
1272 /// AsmOperandInfo - This contains information for each constraint that we are
1274 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1275 /// ConstraintCode - This contains the actual string for the code, like "m".
1276 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1277 /// most closely matches the operand.
1278 std::string ConstraintCode;
1280 /// ConstraintType - Information about the constraint code, e.g. Register,
1281 /// RegisterClass, Memory, Other, Unknown.
1282 TargetLowering::ConstraintType ConstraintType;
1284 /// CallOperandval - If this is the result output operand or a
1285 /// clobber, this is null, otherwise it is the incoming operand to the
1286 /// CallInst. This gets modified as the asm is processed.
1287 Value *CallOperandVal;
1289 /// ConstraintVT - The ValueType for the operand value.
1292 /// isMatchingInputConstraint - Return true of this is an input operand that
1293 /// is a matching constraint like "4".
1294 bool isMatchingInputConstraint() const;
1296 /// getMatchedOperand - If this is an input matching constraint, this method
1297 /// returns the output operand it matches.
1298 unsigned getMatchedOperand() const;
1300 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1301 : InlineAsm::ConstraintInfo(info),
1302 ConstraintType(TargetLowering::C_Unknown),
1303 CallOperandVal(0), ConstraintVT(MVT::Other) {
1307 /// ComputeConstraintToUse - Determines the constraint code and constraint
1308 /// type to use for the specific AsmOperandInfo, setting
1309 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1310 /// being passed in is available, it can be passed in as Op, otherwise an
1311 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1312 /// constraint of the inline asm instruction being processed is 'm'.
1313 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1316 SelectionDAG *DAG = 0) const;
1318 /// getConstraintType - Given a constraint, return the type of constraint it
1319 /// is for this target.
1320 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1322 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1323 /// return a list of registers that can be used to satisfy the constraint.
1324 /// This should only be used for C_RegisterClass constraints.
1325 virtual std::vector<unsigned>
1326 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1329 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1330 /// {edx}), return the register number and the register class for the
1333 /// Given a register class constraint, like 'r', if this corresponds directly
1334 /// to an LLVM register class, return a register of 0 and the register class
1337 /// This should only be used for C_Register constraints. On error,
1338 /// this returns a register number of 0 and a null register class pointer..
1339 virtual std::pair<unsigned, const TargetRegisterClass*>
1340 getRegForInlineAsmConstraint(const std::string &Constraint,
1343 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1344 /// with another that has more specific requirements based on the type of the
1345 /// corresponding operand. This returns null if there is no replacement to
1347 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1349 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1350 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1351 /// it means one of the asm constraint of the inline asm instruction being
1352 /// processed is 'm'.
1353 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1355 std::vector<SDValue> &Ops,
1356 SelectionDAG &DAG) const;
1358 //===--------------------------------------------------------------------===//
1359 // Instruction Emitting Hooks
1362 // EmitInstrWithCustomInserter - This method should be implemented by targets
1363 // that mark instructions with the 'usesCustomInserter' flag. These
1364 // instructions are special in various ways, which require special support to
1365 // insert. The specified MachineInstr is created but not inserted into any
1366 // basic blocks, and this method is called to expand it into a sequence of
1367 // instructions, potentially also creating new basic blocks and control flow.
1368 virtual MachineBasicBlock *
1369 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1371 //===--------------------------------------------------------------------===//
1372 // Addressing mode description hooks (used by LSR etc).
1375 /// AddrMode - This represents an addressing mode of:
1376 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1377 /// If BaseGV is null, there is no BaseGV.
1378 /// If BaseOffs is zero, there is no base offset.
1379 /// If HasBaseReg is false, there is no base register.
1380 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1384 GlobalValue *BaseGV;
1388 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1391 /// isLegalAddressingMode - Return true if the addressing mode represented by
1392 /// AM is legal for this target, for a load/store of the specified type.
1393 /// The type may be VoidTy, in which case only return true if the addressing
1394 /// mode is legal for a load/store of any legal type.
1395 /// TODO: Handle pre/postinc as well.
1396 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1398 /// isTruncateFree - Return true if it's free to truncate a value of
1399 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1400 /// register EAX to i16 by referencing its sub-register AX.
1401 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1405 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1409 /// isZExtFree - Return true if any actual instruction that defines a
1410 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1411 /// register. This does not necessarily include registers defined in
1412 /// unknown ways, such as incoming arguments, or copies from unknown
1413 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1414 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1415 /// all instructions that define 32-bit values implicit zero-extend the
1416 /// result out to 64 bits.
1417 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1421 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1425 /// isNarrowingProfitable - Return true if it's profitable to narrow
1426 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1427 /// from i32 to i8 but not from i32 to i16.
1428 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1432 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1433 /// icmp immediate, that is the target has icmp instructions which can compare
1434 /// a register against the immediate without having to materialize the
1435 /// immediate into a register.
1436 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1440 //===--------------------------------------------------------------------===//
1441 // Div utility functions
1443 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1444 std::vector<SDNode*>* Created) const;
1445 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1446 std::vector<SDNode*>* Created) const;
1449 //===--------------------------------------------------------------------===//
1450 // Runtime Library hooks
1453 /// setLibcallName - Rename the default libcall routine name for the specified
1455 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1456 LibcallRoutineNames[Call] = Name;
1459 /// getLibcallName - Get the libcall routine name for the specified libcall.
1461 const char *getLibcallName(RTLIB::Libcall Call) const {
1462 return LibcallRoutineNames[Call];
1465 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1466 /// result of the comparison libcall against zero.
1467 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1468 CmpLibcallCCs[Call] = CC;
1471 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1472 /// the comparison libcall against zero.
1473 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1474 return CmpLibcallCCs[Call];
1477 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1478 /// specified libcall.
1479 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1480 LibcallCallingConvs[Call] = CC;
1483 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1484 /// specified libcall.
1485 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1486 return LibcallCallingConvs[Call];
1490 const TargetMachine &TM;
1491 const TargetData *TD;
1492 const TargetLoweringObjectFile &TLOF;
1494 /// PointerTy - The type to use for pointers, usually i32 or i64.
1498 /// IsLittleEndian - True if this is a little endian target.
1500 bool IsLittleEndian;
1502 /// SelectIsExpensive - Tells the code generator not to expand operations
1503 /// into sequences that use the select operations if possible.
1504 bool SelectIsExpensive;
1506 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1507 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1508 /// a real cost model is in place. If we ever optimize for size, this will be
1509 /// set to true unconditionally.
1512 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1513 /// srl/add/sra for a signed divide by power of two, and let the target handle
1515 bool Pow2DivIsCheap;
1517 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1518 /// llvm.setjmp. Defaults to false.
1519 bool UseUnderscoreSetJmp;
1521 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1522 /// llvm.longjmp. Defaults to false.
1523 bool UseUnderscoreLongJmp;
1525 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1529 /// BooleanContents - Information about the contents of the high-bits in
1530 /// boolean values held in a type wider than i1. See getBooleanContents.
1531 BooleanContent BooleanContents;
1533 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1534 /// total cycles or lowest register usage.
1535 SchedPreference SchedPreferenceInfo;
1537 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1538 unsigned JumpBufSize;
1540 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1542 unsigned JumpBufAlignment;
1544 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1546 unsigned IfCvtBlockSizeLimit;
1548 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1549 /// duplicated during if-conversion.
1550 unsigned IfCvtDupBlockSizeLimit;
1552 /// PrefLoopAlignment - The perferred loop alignment.
1554 unsigned PrefLoopAlignment;
1556 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1557 /// specifies the register that llvm.savestack/llvm.restorestack should save
1559 unsigned StackPointerRegisterToSaveRestore;
1561 /// ExceptionPointerRegister - If set to a physical register, this specifies
1562 /// the register that receives the exception address on entry to a landing
1564 unsigned ExceptionPointerRegister;
1566 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1567 /// the register that receives the exception typeid on entry to a landing
1569 unsigned ExceptionSelectorRegister;
1571 /// RegClassForVT - This indicates the default register class to use for
1572 /// each ValueType the target supports natively.
1573 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1574 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1575 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1577 /// Synthesizable indicates whether it is OK for the compiler to create new
1578 /// operations using this type. All Legal types are Synthesizable except
1579 /// MMX types on X86. Non-Legal types are not Synthesizable.
1580 bool Synthesizable[MVT::LAST_VALUETYPE];
1582 /// TransformToType - For any value types we are promoting or expanding, this
1583 /// contains the value type that we are changing to. For Expanded types, this
1584 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1585 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1586 /// by the system, this holds the same type (e.g. i32 -> i32).
1587 EVT TransformToType[MVT::LAST_VALUETYPE];
1589 /// OpActions - For each operation and each value type, keep a LegalizeAction
1590 /// that indicates how instruction selection should deal with the operation.
1591 /// Most operations are Legal (aka, supported natively by the target), but
1592 /// operations that are not should be described. Note that operations on
1593 /// non-legal value types are not described here.
1594 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1595 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1596 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)]
1597 [ISD::BUILTIN_OP_END];
1599 /// LoadExtActions - For each load of load extension type and each value type,
1600 /// keep a LegalizeAction that indicates how instruction selection should deal
1602 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1604 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1605 /// indicates how instruction selection should deal with the store.
1606 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1608 /// IndexedModeActions - For each indexed mode and each value type,
1609 /// keep a pair of LegalizeAction that indicates how instruction
1610 /// selection should deal with the load / store. The first
1611 /// dimension is now the value_type for the reference. The second
1612 /// dimension is the load [0] vs. store[1]. The third dimension
1613 /// represents the various modes for load store.
1614 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1616 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1617 /// LegalizeAction that indicates how instruction selection should
1618 /// deal with the condition code.
1619 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1621 ValueTypeActionImpl ValueTypeActions;
1623 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1625 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1626 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1627 /// which sets a bit in this array.
1629 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1631 /// PromoteToType - For operations that must be promoted to a specific type,
1632 /// this holds the destination type. This map should be sparse, so don't hold
1635 /// Targets add entries to this map with AddPromotedToType(..), clients access
1636 /// this with getTypeToPromoteTo(..).
1637 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1640 /// LibcallRoutineNames - Stores the name each libcall.
1642 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1644 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1645 /// of each of the comparison libcall against zero.
1646 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1648 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1650 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1653 /// When lowering \@llvm.memset this field specifies the maximum number of
1654 /// store operations that may be substituted for the call to memset. Targets
1655 /// must set this value based on the cost threshold for that target. Targets
1656 /// should assume that the memset will be done using as many of the largest
1657 /// store operations first, followed by smaller ones, if necessary, per
1658 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1659 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1660 /// store. This only applies to setting a constant array of a constant size.
1661 /// @brief Specify maximum number of store instructions per memset call.
1662 unsigned maxStoresPerMemset;
1664 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1665 /// store operations that may be substituted for a call to memcpy. Targets
1666 /// must set this value based on the cost threshold for that target. Targets
1667 /// should assume that the memcpy will be done using as many of the largest
1668 /// store operations first, followed by smaller ones, if necessary, per
1669 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1670 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1671 /// and one 1-byte store. This only applies to copying a constant array of
1673 /// @brief Specify maximum bytes of store instructions per memcpy call.
1674 unsigned maxStoresPerMemcpy;
1676 /// When lowering \@llvm.memmove this field specifies the maximum number of
1677 /// store instructions that may be substituted for a call to memmove. Targets
1678 /// must set this value based on the cost threshold for that target. Targets
1679 /// should assume that the memmove will be done using as many of the largest
1680 /// store operations first, followed by smaller ones, if necessary, per
1681 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1682 /// with 8-bit alignment would result in nine 1-byte stores. This only
1683 /// applies to copying a constant array of constant size.
1684 /// @brief Specify maximum bytes of store instructions per memmove call.
1685 unsigned maxStoresPerMemmove;
1687 /// This field specifies whether the target can benefit from code placement
1689 bool benefitFromCodePlacementOpt;
1691 } // end llvm namespace