1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 class TargetRegisterClass;
38 class MachineBasicBlock;
41 //===----------------------------------------------------------------------===//
42 /// TargetLowering - This class defines information used to lower LLVM code to
43 /// legal SelectionDAG operators that the target instruction selector can accept
46 /// This class also defines callbacks that targets must implement to lower
47 /// target-specific constructs to SelectionDAG operators.
49 class TargetLowering {
51 /// LegalizeAction - This enum indicates whether operations are valid for a
52 /// target, and if not, what action should be used to make them valid.
54 Legal, // The target natively supports this operation.
55 Promote, // This operation should be executed in a larger type.
56 Expand, // Try to expand this to other ops, otherwise use a libcall.
57 Custom // Use the LowerOperation hook to implement custom lowering.
60 enum OutOfRangeShiftAmount {
61 Undefined, // Oversized shift amounts are undefined (default).
62 Mask, // Shift amounts are auto masked (anded) to value size.
63 Extend // Oversized shift pulls in zeros or sign bits.
66 enum SetCCResultValue {
67 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
68 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
69 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
72 enum SchedPreference {
73 SchedulingForLatency, // Scheduling for shortest total latency.
74 SchedulingForRegPressure // Scheduling for lowest register pressure.
77 TargetLowering(TargetMachine &TM);
78 virtual ~TargetLowering();
80 TargetMachine &getTargetMachine() const { return TM; }
81 const TargetData *getTargetData() const { return TD; }
83 bool isLittleEndian() const { return IsLittleEndian; }
84 MVT::ValueType getPointerTy() const { return PointerTy; }
85 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
86 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
88 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
90 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
92 /// isSetCCExpensive - Return true if the setcc operation is expensive for
94 bool isSetCCExpensive() const { return SetCCIsExpensive; }
96 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
97 /// a sequence of several shifts, adds, and multiplies for this target.
98 bool isIntDivCheap() const { return IntDivIsCheap; }
100 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
102 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
104 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
106 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
108 /// getSetCCResultContents - For targets without boolean registers, this flag
109 /// returns information about the contents of the high-bits in the setcc
111 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
113 /// getSchedulingPreference - Return target scheduling preference.
114 SchedPreference getSchedulingPreference() const {
115 return SchedPreferenceInfo;
118 /// getRegClassFor - Return the register class that should be used for the
119 /// specified value type. This may only be called on legal types.
120 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
121 TargetRegisterClass *RC = RegClassForVT[VT];
122 assert(RC && "This value type is not natively supported!");
126 /// isTypeLegal - Return true if the target has native support for the
127 /// specified value type. This means that it has a register that directly
128 /// holds it without promotions or expansions.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return RegClassForVT[VT] != 0;
133 class ValueTypeActionImpl {
134 /// ValueTypeActions - This is a bitvector that contains two bits for each
135 /// value type, where the two bits correspond to the LegalizeAction enum.
136 /// This can be queried with "getTypeAction(VT)".
137 uint32_t ValueTypeActions[2];
139 ValueTypeActionImpl() {
140 ValueTypeActions[0] = ValueTypeActions[1] = 0;
142 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
143 ValueTypeActions[0] = RHS.ValueTypeActions[0];
144 ValueTypeActions[1] = RHS.ValueTypeActions[1];
147 LegalizeAction getTypeAction(MVT::ValueType VT) const {
148 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
150 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
151 assert(unsigned(VT >> 4) <
152 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
153 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
157 const ValueTypeActionImpl &getValueTypeActions() const {
158 return ValueTypeActions;
161 /// getTypeAction - Return how we should legalize values of this type, either
162 /// it is already legal (return 'Legal') or we need to promote it to a larger
163 /// type (return 'Promote'), or we need to expand it into multiple registers
164 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
165 LegalizeAction getTypeAction(MVT::ValueType VT) const {
166 return ValueTypeActions.getTypeAction(VT);
169 /// getTypeToTransformTo - For types supported by the target, this is an
170 /// identity function. For types that must be promoted to larger types, this
171 /// returns the larger type to promote to. For types that are larger than the
172 /// largest integer register, this contains one step in the expansion to get
173 /// to the smaller register.
174 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
175 return TransformToType[VT];
178 /// getPackedTypeBreakdown - Packed types are broken down into some number of
179 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
180 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
181 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
183 /// This method returns the number of registers needed, and the VT for each
184 /// register. It also returns the VT of the PackedType elements before they
185 /// are promoted/expanded.
187 unsigned getPackedTypeBreakdown(const PackedType *PTy,
188 MVT::ValueType &PTyElementVT,
189 MVT::ValueType &PTyLegalElementVT) const;
191 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
192 legal_fpimm_iterator legal_fpimm_begin() const {
193 return LegalFPImmediates.begin();
195 legal_fpimm_iterator legal_fpimm_end() const {
196 return LegalFPImmediates.end();
199 /// isShuffleMaskLegal - Targets can use this to indicate that they only
200 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
201 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
202 /// are assumed to be legal.
203 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
207 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
208 /// used by Targets can use this to indicate if there is a suitable
209 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
211 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
213 SelectionDAG &DAG) const {
217 /// getOperationAction - Return how this operation should be treated: either
218 /// it is legal, needs to be promoted to a larger size, needs to be
219 /// expanded to some other code sequence, or the target has a custom expander
221 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
222 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
225 /// isOperationLegal - Return true if the specified operation is legal on this
227 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
228 return getOperationAction(Op, VT) == Legal ||
229 getOperationAction(Op, VT) == Custom;
232 /// getLoadXAction - Return how this load with extension should be treated:
233 /// either it is legal, needs to be promoted to a larger size, needs to be
234 /// expanded to some other code sequence, or the target has a custom expander
236 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
237 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
240 /// isLoadXLegal - Return true if the specified load with extension is legal
241 /// is legal on this target.
242 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
243 return getLoadXAction(LType, VT) == Legal ||
244 getLoadXAction(LType, VT) == Custom;
247 /// getTypeToPromoteTo - If the action for this operation is to promote, this
248 /// method returns the ValueType to promote to.
249 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
250 assert(getOperationAction(Op, VT) == Promote &&
251 "This operation isn't promoted!");
253 // See if this has an explicit type specified.
254 std::map<std::pair<unsigned, MVT::ValueType>,
255 MVT::ValueType>::const_iterator PTTI =
256 PromoteToType.find(std::make_pair(Op, VT));
257 if (PTTI != PromoteToType.end()) return PTTI->second;
259 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
260 "Cannot autopromote this type, add it with AddPromotedToType.");
262 MVT::ValueType NVT = VT;
264 NVT = (MVT::ValueType)(NVT+1);
265 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
266 "Didn't find type to promote to!");
267 } while (!isTypeLegal(NVT) ||
268 getOperationAction(Op, NVT) == Promote);
272 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
273 /// This is fixed by the LLVM operations except for the pointer size.
274 MVT::ValueType getValueType(const Type *Ty) const {
275 switch (Ty->getTypeID()) {
276 default: assert(0 && "Unknown type!");
277 case Type::VoidTyID: return MVT::isVoid;
278 case Type::BoolTyID: return MVT::i1;
279 case Type::UByteTyID:
280 case Type::SByteTyID: return MVT::i8;
281 case Type::ShortTyID:
282 case Type::UShortTyID: return MVT::i16;
284 case Type::UIntTyID: return MVT::i32;
286 case Type::ULongTyID: return MVT::i64;
287 case Type::FloatTyID: return MVT::f32;
288 case Type::DoubleTyID: return MVT::f64;
289 case Type::PointerTyID: return PointerTy;
290 case Type::PackedTyID: return MVT::Vector;
294 /// getNumElements - Return the number of registers that this ValueType will
295 /// eventually require. This is always one for all non-integer types, is
296 /// one for any types promoted to live in larger registers, but may be more
297 /// than one for types (like i64) that are split into pieces.
298 unsigned getNumElements(MVT::ValueType VT) const {
299 return NumElementsForVT[VT];
302 /// hasTargetDAGCombine - If true, the target has custom DAG combine
303 /// transformations that it can perform for the specified node.
304 bool hasTargetDAGCombine(ISD::NodeType NT) const {
305 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
308 /// This function returns the maximum number of store operations permitted
309 /// to replace a call to llvm.memset. The value is set by the target at the
310 /// performance threshold for such a replacement.
311 /// @brief Get maximum # of store operations permitted for llvm.memset
312 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
314 /// This function returns the maximum number of store operations permitted
315 /// to replace a call to llvm.memcpy. The value is set by the target at the
316 /// performance threshold for such a replacement.
317 /// @brief Get maximum # of store operations permitted for llvm.memcpy
318 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
320 /// This function returns the maximum number of store operations permitted
321 /// to replace a call to llvm.memmove. The value is set by the target at the
322 /// performance threshold for such a replacement.
323 /// @brief Get maximum # of store operations permitted for llvm.memmove
324 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
326 /// This function returns true if the target allows unaligned memory accesses.
327 /// This is used, for example, in situations where an array copy/move/set is
328 /// converted to a sequence of store operations. It's use helps to ensure that
329 /// such replacements don't generate code that causes an alignment error
330 /// (trap) on the target machine.
331 /// @brief Determine if the target supports unaligned memory accesses.
332 bool allowsUnalignedMemoryAccesses() const {
333 return allowUnalignedMemoryAccesses;
336 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
337 /// to implement llvm.setjmp.
338 bool usesUnderscoreSetJmpLongJmp() const {
339 return UseUnderscoreSetJmpLongJmp;
342 /// getStackPointerRegisterToSaveRestore - If a physical register, this
343 /// specifies the register that llvm.savestack/llvm.restorestack should save
345 unsigned getStackPointerRegisterToSaveRestore() const {
346 return StackPointerRegisterToSaveRestore;
349 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
350 /// set, the default is 200)
351 unsigned getJumpBufSize() const {
355 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
356 /// (if never set, the default is 0)
357 unsigned getJumpBufAlignment() const {
358 return JumpBufAlignment;
361 //===--------------------------------------------------------------------===//
362 // TargetLowering Optimization Methods
365 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
366 /// SDOperands for returning information from TargetLowering to its clients
367 /// that want to combine
368 struct TargetLoweringOpt {
373 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
375 bool CombineTo(SDOperand O, SDOperand N) {
381 /// ShrinkDemandedConstant - Check to see if the specified operand of the
382 /// specified instruction is a constant integer. If so, check to see if there
383 /// are any bits set in the constant that are not demanded. If so, shrink the
384 /// constant and return true.
385 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
388 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
389 /// use this predicate to simplify operations downstream. Op and Mask are
390 /// known to be the same type.
391 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
394 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
395 /// known to be either zero or one and return them in the KnownZero/KnownOne
396 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
397 /// processing. Targets can implement the computeMaskedBitsForTargetNode
398 /// method, to allow target nodes to be understood.
399 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
400 uint64_t &KnownOne, unsigned Depth = 0) const;
402 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
403 /// DemandedMask bits of the result of Op are ever used downstream. If we can
404 /// use this information to simplify Op, create a new simplified DAG node and
405 /// return true, returning the original and new nodes in Old and New.
406 /// Otherwise, analyze the expression and return a mask of KnownOne and
407 /// KnownZero bits for the expression (used to simplify the caller).
408 /// The KnownZero/One bits may only be accurate for those bits in the
410 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
411 uint64_t &KnownZero, uint64_t &KnownOne,
412 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
414 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
415 /// Mask are known to be either zero or one and return them in the
416 /// KnownZero/KnownOne bitsets.
417 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
421 unsigned Depth = 0) const;
423 /// ComputeNumSignBits - Return the number of times the sign bit of the
424 /// register is replicated into the other bits. We know that at least 1 bit
425 /// is always equal to the sign bit (itself), but other cases can give us
426 /// information. For example, immediately after an "SRA X, 2", we know that
427 /// the top 3 bits are all equal to each other, so we return 3.
428 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
430 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
431 /// targets that want to expose additional information about sign bits to the
433 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
434 unsigned Depth = 0) const;
436 struct DAGCombinerInfo {
437 void *DC; // The DAG Combiner object.
442 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
443 : DC(dc), BeforeLegalize(bl), DAG(dag) {}
445 bool isBeforeLegalize() const { return BeforeLegalize; }
447 void AddToWorklist(SDNode *N);
448 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
449 SDOperand CombineTo(SDNode *N, SDOperand Res);
450 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
453 /// PerformDAGCombine - This method will be invoked for all target nodes and
454 /// for any target-independent nodes that the target has registered with
457 /// The semantics are as follows:
459 /// SDOperand.Val == 0 - No change was made
460 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
461 /// otherwise - N should be replaced by the returned Operand.
463 /// In addition, methods provided by DAGCombinerInfo may be used to perform
464 /// more complex transformations.
466 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
468 //===--------------------------------------------------------------------===//
469 // TargetLowering Configuration Methods - These methods should be invoked by
470 // the derived class constructor to configure this object for the target.
474 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
475 /// GOT for PC-relative code.
476 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
478 /// setShiftAmountType - Describe the type that should be used for shift
479 /// amounts. This type defaults to the pointer type.
480 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
482 /// setSetCCResultType - Describe the type that shoudl be used as the result
483 /// of a setcc operation. This defaults to the pointer type.
484 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
486 /// setSetCCResultContents - Specify how the target extends the result of a
487 /// setcc operation in a register.
488 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
490 /// setSchedulingPreference - Specify the target scheduling preference.
491 void setSchedulingPreference(SchedPreference Pref) {
492 SchedPreferenceInfo = Pref;
495 /// setShiftAmountFlavor - Describe how the target handles out of range shift
497 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
498 ShiftAmtHandling = OORSA;
501 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
502 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
503 /// the non _ versions. Defaults to false.
504 void setUseUnderscoreSetJmpLongJmp(bool Val) {
505 UseUnderscoreSetJmpLongJmp = Val;
508 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
509 /// specifies the register that llvm.savestack/llvm.restorestack should save
511 void setStackPointerRegisterToSaveRestore(unsigned R) {
512 StackPointerRegisterToSaveRestore = R;
515 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
516 /// setcc as a conditional branch. This encourages the code generator to fold
517 /// setcc operations into other operations if possible.
518 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
520 /// setIntDivIsCheap - Tells the code generator that integer divide is
521 /// expensive, and if possible, should be replaced by an alternate sequence
522 /// of instructions not containing an integer divide.
523 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
525 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
526 /// srl/add/sra for a signed divide by power of two, and let the target handle
528 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
530 /// addRegisterClass - Add the specified register class as an available
531 /// regclass for the specified value type. This indicates the selector can
532 /// handle values of that class natively.
533 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
534 AvailableRegClasses.push_back(std::make_pair(VT, RC));
535 RegClassForVT[VT] = RC;
538 /// computeRegisterProperties - Once all of the register classes are added,
539 /// this allows us to compute derived properties we expose.
540 void computeRegisterProperties();
542 /// setOperationAction - Indicate that the specified operation does not work
543 /// with the specified type and indicate what to do about it.
544 void setOperationAction(unsigned Op, MVT::ValueType VT,
545 LegalizeAction Action) {
546 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
547 "Table isn't big enough!");
548 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
549 OpActions[Op] |= (uint64_t)Action << VT*2;
552 /// setLoadXAction - Indicate that the specified load with extension does not
553 /// work with the with specified type and indicate what to do about it.
554 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
555 LegalizeAction Action) {
556 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
557 "Table isn't big enough!");
558 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
559 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
562 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
563 /// promotion code defaults to trying a larger integer/fp until it can find
564 /// one that works. If that default is insufficient, this method can be used
565 /// by the target to override the default.
566 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
567 MVT::ValueType DestVT) {
568 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
571 /// addLegalFPImmediate - Indicate that this target can instruction select
572 /// the specified FP immediate natively.
573 void addLegalFPImmediate(double Imm) {
574 LegalFPImmediates.push_back(Imm);
577 /// setTargetDAGCombine - Targets should invoke this method for each target
578 /// independent node that they want to provide a custom DAG combiner for by
579 /// implementing the PerformDAGCombine virtual method.
580 void setTargetDAGCombine(ISD::NodeType NT) {
581 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
584 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
585 /// bytes); default is 200
586 void setJumpBufSize(unsigned Size) {
590 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
591 /// alignment (in bytes); default is 0
592 void setJumpBufAlignment(unsigned Align) {
593 JumpBufAlignment = Align;
598 //===--------------------------------------------------------------------===//
599 // Lowering methods - These methods must be implemented by targets so that
600 // the SelectionDAGLowering code knows how to lower these.
603 /// LowerArguments - This hook must be implemented to indicate how we should
604 /// lower the arguments for the specified function, into the specified DAG.
605 virtual std::vector<SDOperand>
606 LowerArguments(Function &F, SelectionDAG &DAG);
608 /// LowerCallTo - This hook lowers an abstract call to a function into an
609 /// actual call. This returns a pair of operands. The first element is the
610 /// return value for the function (if RetTy is not VoidTy). The second
611 /// element is the outgoing token chain.
612 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
613 virtual std::pair<SDOperand, SDOperand>
614 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
615 unsigned CallingConv, bool isTailCall, SDOperand Callee,
616 ArgListTy &Args, SelectionDAG &DAG);
618 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
619 /// llvm.frameaddress (depending on the value of the first argument). The
620 /// return values are the result pointer and the resultant token chain. If
621 /// not implemented, both of these intrinsics will return null.
622 virtual std::pair<SDOperand, SDOperand>
623 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
626 /// LowerOperation - This callback is invoked for operations that are
627 /// unsupported by the target, which are registered to use 'custom' lowering,
628 /// and whose defined values are all legal.
629 /// If the target has no operations that require custom lowering, it need not
630 /// implement this. The default implementation of this aborts.
631 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
633 /// CustomPromoteOperation - This callback is invoked for operations that are
634 /// unsupported by the target, are registered to use 'custom' lowering, and
635 /// whose type needs to be promoted.
636 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
638 /// getTargetNodeName() - This method returns the name of a target specific
640 virtual const char *getTargetNodeName(unsigned Opcode) const;
642 //===--------------------------------------------------------------------===//
643 // Inline Asm Support hooks
646 enum ConstraintType {
647 C_Register, // Constraint represents a single register.
648 C_RegisterClass, // Constraint represents one or more registers.
649 C_Memory, // Memory constraint.
650 C_Other, // Something else.
651 C_Unknown // Unsupported constraint.
654 /// getConstraintType - Given a constraint letter, return the type of
655 /// constraint it is for this target.
656 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
659 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
660 /// return a list of registers that can be used to satisfy the constraint.
661 /// This should only be used for C_RegisterClass constraints.
662 virtual std::vector<unsigned>
663 getRegClassForInlineAsmConstraint(const std::string &Constraint,
664 MVT::ValueType VT) const;
666 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
667 /// {edx}), return the register number and the register class for the
668 /// register. This should only be used for C_Register constraints. On error,
669 /// this returns a register number of 0.
670 virtual std::pair<unsigned, const TargetRegisterClass*>
671 getRegForInlineAsmConstraint(const std::string &Constraint,
672 MVT::ValueType VT) const;
675 /// isOperandValidForConstraint - Return true if the specified SDOperand is
676 /// valid for the specified target constraint letter.
677 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
679 //===--------------------------------------------------------------------===//
683 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
684 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
685 // instructions are special in various ways, which require special support to
686 // insert. The specified MachineInstr is created but not inserted into any
687 // basic blocks, and the scheduler passes ownership of it to this method.
688 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
689 MachineBasicBlock *MBB);
691 //===--------------------------------------------------------------------===//
692 // Loop Strength Reduction hooks
695 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
696 /// can be used as the offset of the target addressing mode.
697 virtual bool isLegalAddressImmediate(int64_t V) const;
698 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
700 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator;
701 legal_am_scale_iterator legal_am_scale_begin() const {
702 return LegalAddressScales.begin();
704 legal_am_scale_iterator legal_am_scale_end() const {
705 return LegalAddressScales.end();
708 //===--------------------------------------------------------------------===//
709 // Div utility functions
711 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
712 std::vector<SDNode*>* Created) const;
713 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
714 std::vector<SDNode*>* Created) const;
718 /// addLegalAddressScale - Add a integer (> 1) value which can be used as
719 /// scale in the target addressing mode. Note: the ordering matters so the
720 /// least efficient ones should be entered first.
721 void addLegalAddressScale(unsigned Scale) {
722 LegalAddressScales.push_back(Scale);
726 std::vector<unsigned> LegalAddressScales;
729 const TargetData *TD;
731 /// IsLittleEndian - True if this is a little endian target.
735 /// PointerTy - The type to use for pointers, usually i32 or i64.
737 MVT::ValueType PointerTy;
739 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
741 bool UsesGlobalOffsetTable;
743 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
745 MVT::ValueType ShiftAmountTy;
747 OutOfRangeShiftAmount ShiftAmtHandling;
749 /// SetCCIsExpensive - This is a short term hack for targets that codegen
750 /// setcc as a conditional branch. This encourages the code generator to fold
751 /// setcc operations into other operations if possible.
752 bool SetCCIsExpensive;
754 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
755 /// constants into a sequence of muls, adds, and shifts. This is a hack until
756 /// a real cost model is in place. If we ever optimize for size, this will be
757 /// set to true unconditionally.
760 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
761 /// srl/add/sra for a signed divide by power of two, and let the target handle
765 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
767 MVT::ValueType SetCCResultTy;
769 /// SetCCResultContents - Information about the contents of the high-bits in
770 /// the result of a setcc comparison operation.
771 SetCCResultValue SetCCResultContents;
773 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
774 /// total cycles or lowest register usage.
775 SchedPreference SchedPreferenceInfo;
777 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
778 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
779 bool UseUnderscoreSetJmpLongJmp;
781 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
782 unsigned JumpBufSize;
784 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
786 unsigned JumpBufAlignment;
788 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
789 /// specifies the register that llvm.savestack/llvm.restorestack should save
791 unsigned StackPointerRegisterToSaveRestore;
793 /// RegClassForVT - This indicates the default register class to use for
794 /// each ValueType the target supports natively.
795 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
796 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
798 /// TransformToType - For any value types we are promoting or expanding, this
799 /// contains the value type that we are changing to. For Expanded types, this
800 /// contains one step of the expand (e.g. i64 -> i32), even if there are
801 /// multiple steps required (e.g. i64 -> i16). For types natively supported
802 /// by the system, this holds the same type (e.g. i32 -> i32).
803 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
805 /// OpActions - For each operation and each value type, keep a LegalizeAction
806 /// that indicates how instruction selection should deal with the operation.
807 /// Most operations are Legal (aka, supported natively by the target), but
808 /// operations that are not should be described. Note that operations on
809 /// non-legal value types are not described here.
810 uint64_t OpActions[156];
812 /// LoadXActions - For each load of load extension type and each value type,
813 /// keep a LegalizeAction that indicates how instruction selection should deal
815 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
817 ValueTypeActionImpl ValueTypeActions;
819 std::vector<double> LegalFPImmediates;
821 std::vector<std::pair<MVT::ValueType,
822 TargetRegisterClass*> > AvailableRegClasses;
824 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
825 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
826 /// which sets a bit in this array.
827 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
829 /// PromoteToType - For operations that must be promoted to a specific type,
830 /// this holds the destination type. This map should be sparse, so don't hold
833 /// Targets add entries to this map with AddPromotedToType(..), clients access
834 /// this with getTypeToPromoteTo(..).
835 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
838 /// When lowering %llvm.memset this field specifies the maximum number of
839 /// store operations that may be substituted for the call to memset. Targets
840 /// must set this value based on the cost threshold for that target. Targets
841 /// should assume that the memset will be done using as many of the largest
842 /// store operations first, followed by smaller ones, if necessary, per
843 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
844 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
845 /// store. This only applies to setting a constant array of a constant size.
846 /// @brief Specify maximum number of store instructions per memset call.
847 unsigned maxStoresPerMemset;
849 /// When lowering %llvm.memcpy this field specifies the maximum number of
850 /// store operations that may be substituted for a call to memcpy. Targets
851 /// must set this value based on the cost threshold for that target. Targets
852 /// should assume that the memcpy will be done using as many of the largest
853 /// store operations first, followed by smaller ones, if necessary, per
854 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
855 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
856 /// and one 1-byte store. This only applies to copying a constant array of
858 /// @brief Specify maximum bytes of store instructions per memcpy call.
859 unsigned maxStoresPerMemcpy;
861 /// When lowering %llvm.memmove this field specifies the maximum number of
862 /// store instructions that may be substituted for a call to memmove. Targets
863 /// must set this value based on the cost threshold for that target. Targets
864 /// should assume that the memmove will be done using as many of the largest
865 /// store operations first, followed by smaller ones, if necessary, per
866 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
867 /// with 8-bit alignment would result in nine 1-byte stores. This only
868 /// applies to copying a constant array of constant size.
869 /// @brief Specify maximum bytes of store instructions per memmove call.
870 unsigned maxStoresPerMemmove;
872 /// This field specifies whether the target machine permits unaligned memory
873 /// accesses. This is used, for example, to determine the size of store
874 /// operations when copying small arrays and other similar tasks.
875 /// @brief Indicate whether the target permits unaligned memory accesses.
876 bool allowUnalignedMemoryAccesses;
878 } // end llvm namespace