1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/DebugLoc.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFunction;
50 class MachineFrameInfo;
52 class MachineJumpTableInfo;
60 class TargetRegisterClass;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 /// NOTE: The constructor takes ownership of TLOF.
104 explicit TargetLowering(const TargetMachine &TM,
105 const TargetLoweringObjectFile *TLOF);
106 virtual ~TargetLowering();
108 const TargetMachine &getTargetMachine() const { return TM; }
109 const TargetData *getTargetData() const { return TD; }
110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT getPointerTy() const { return PointerTy; }
115 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 /// isSelectExpensive - Return true if the select operation is expensive for
119 bool isSelectExpensive() const { return SelectIsExpensive; }
121 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
122 /// a sequence of several shifts, adds, and multiplies for this target.
123 bool isIntDivCheap() const { return IntDivIsCheap; }
125 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
127 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
129 /// getSetCCResultType - Return the ValueType of the result of SETCC
130 /// operations. Also used to obtain the target's preferred type for
131 /// the condition operand of SELECT and BRCOND nodes. In the case of
132 /// BRCOND the argument passed is MVT::Other since there are no other
133 /// operands to get a type hint from.
135 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
137 /// getCmpLibcallReturnType - Return the ValueType for comparison
138 /// libcalls. Comparions libcalls include floating point comparion calls,
139 /// and Ordered/Unordered check calls on floating point numbers.
141 MVT::SimpleValueType getCmpLibcallReturnType() const;
143 /// getBooleanContents - For targets without i1 registers, this gives the
144 /// nature of the high-bits of boolean values held in types wider than i1.
145 /// "Boolean values" are special true/false values produced by nodes like
146 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
147 /// Not to be confused with general values promoted from i1.
148 BooleanContent getBooleanContents() const { return BooleanContents;}
150 /// getSchedulingPreference - Return target scheduling preference.
151 Sched::Preference getSchedulingPreference() const {
152 return SchedPreferenceInfo;
155 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
156 /// different scheduling heuristics for different nodes. This function returns
157 /// the preference (or none) for the given node.
158 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
162 /// getRegClassFor - Return the register class that should be used for the
163 /// specified value type.
164 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
165 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
166 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
167 assert(RC && "This value type is not natively supported!");
171 /// getRepRegClassFor - Return the 'representative' register class for the
172 /// specified value type. The 'representative' register class is the largest
173 /// legal super-reg register class for the register class of the value type.
174 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
175 /// while the rep register class is GR64 on x86_64.
176 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
177 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
178 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
182 /// getRepRegClassCostFor - Return the cost of the 'representative' register
183 /// class for the specified value type.
184 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
185 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
186 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
189 /// getRegPressureLimit - Return the register pressure "high water mark" for
190 /// the specific register class. The scheduler is in high register pressure
191 /// mode (for the specific register class) if it goes over the limit.
192 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
193 MachineFunction &MF) const {
197 /// isTypeLegal - Return true if the target has native support for the
198 /// specified value type. This means that it has a register that directly
199 /// holds it without promotions or expansions.
200 bool isTypeLegal(EVT VT) const {
201 assert(!VT.isSimple() ||
202 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
203 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
206 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
207 /// new operations of this type. All Legal types are synthesizable except
208 /// MMX vector types on X86. Non-Legal types are not synthesizable.
209 bool isTypeSynthesizable(EVT VT) const {
210 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
213 class ValueTypeActionImpl {
214 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
215 /// that indicates how instruction selection should deal with the type.
216 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
218 ValueTypeActionImpl() {
219 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
221 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
222 if (VT.isExtended()) {
224 return VT.isPow2VectorType() ? Expand : Promote;
227 // First promote to a power-of-two size, then expand if necessary.
228 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
229 assert(0 && "Unsupported extended type!");
232 unsigned I = VT.getSimpleVT().SimpleTy;
233 return (LegalizeAction)ValueTypeActions[I];
235 void setTypeAction(EVT VT, LegalizeAction Action) {
236 unsigned I = VT.getSimpleVT().SimpleTy;
237 ValueTypeActions[I] = Action;
241 const ValueTypeActionImpl &getValueTypeActions() const {
242 return ValueTypeActions;
245 /// getTypeAction - Return how we should legalize values of this type, either
246 /// it is already legal (return 'Legal') or we need to promote it to a larger
247 /// type (return 'Promote'), or we need to expand it into multiple registers
248 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
249 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
250 return ValueTypeActions.getTypeAction(Context, VT);
253 /// getTypeToTransformTo - For types supported by the target, this is an
254 /// identity function. For types that must be promoted to larger types, this
255 /// returns the larger type to promote to. For integer types that are larger
256 /// than the largest integer register, this contains one step in the expansion
257 /// to get to the smaller register. For illegal floating point types, this
258 /// returns the integer type to transform to.
259 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
261 assert((unsigned)VT.getSimpleVT().SimpleTy <
262 array_lengthof(TransformToType));
263 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
264 assert(getTypeAction(Context, NVT) != Promote &&
265 "Promote may not follow Expand or Promote");
270 EVT NVT = VT.getPow2VectorType(Context);
272 // Vector length is a power of 2 - split to half the size.
273 unsigned NumElts = VT.getVectorNumElements();
274 EVT EltVT = VT.getVectorElementType();
275 return (NumElts == 1) ?
276 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
278 // Promote to a power of two size, avoiding multi-step promotion.
279 return getTypeAction(Context, NVT) == Promote ?
280 getTypeToTransformTo(Context, NVT) : NVT;
281 } else if (VT.isInteger()) {
282 EVT NVT = VT.getRoundIntegerType(Context);
284 // Size is a power of two - expand to half the size.
285 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
287 // Promote to a power of two size, avoiding multi-step promotion.
288 return getTypeAction(Context, NVT) == Promote ?
289 getTypeToTransformTo(Context, NVT) : NVT;
291 assert(0 && "Unsupported extended type!");
292 return MVT(MVT::Other); // Not reached
295 /// getTypeToExpandTo - For types supported by the target, this is an
296 /// identity function. For types that must be expanded (i.e. integer types
297 /// that are larger than the largest integer register or illegal floating
298 /// point types), this returns the largest legal type it will be expanded to.
299 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
300 assert(!VT.isVector());
302 switch (getTypeAction(Context, VT)) {
306 VT = getTypeToTransformTo(Context, VT);
309 assert(false && "Type is not legal nor is it to be expanded!");
316 /// getVectorTypeBreakdown - Vector types are broken down into some number of
317 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
318 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
319 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
321 /// This method returns the number of registers needed, and the VT for each
322 /// register. It also returns the VT and quantity of the intermediate values
323 /// before they are promoted/expanded.
325 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
327 unsigned &NumIntermediates,
328 EVT &RegisterVT) const;
330 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
331 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
332 /// this is the case, it returns true and store the intrinsic
333 /// information into the IntrinsicInfo that was passed to the function.
334 struct IntrinsicInfo {
335 unsigned opc; // target opcode
336 EVT memVT; // memory VT
337 const Value* ptrVal; // value representing memory location
338 int offset; // offset off of ptrVal
339 unsigned align; // alignment
340 bool vol; // is volatile?
341 bool readMem; // reads memory?
342 bool writeMem; // writes memory?
345 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
346 const CallInst &I, unsigned Intrinsic) const {
350 /// isFPImmLegal - Returns true if the target can instruction select the
351 /// specified FP immediate natively. If false, the legalizer will materialize
352 /// the FP immediate as a load from a constant pool.
353 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
357 /// isShuffleMaskLegal - Targets can use this to indicate that they only
358 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
359 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
360 /// are assumed to be legal.
361 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
366 /// canOpTrap - Returns true if the operation can trap for the value type.
367 /// VT must be a legal type. By default, we optimistically assume most
368 /// operations don't trap except for divide and remainder.
369 virtual bool canOpTrap(unsigned Op, EVT VT) const;
371 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
372 /// used by Targets can use this to indicate if there is a suitable
373 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
375 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
380 /// getOperationAction - Return how this operation should be treated: either
381 /// it is legal, needs to be promoted to a larger size, needs to be
382 /// expanded to some other code sequence, or the target has a custom expander
384 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
385 if (VT.isExtended()) return Expand;
386 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
387 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
388 return (LegalizeAction)OpActions[I][Op];
391 /// isOperationLegalOrCustom - Return true if the specified operation is
392 /// legal on this target or can be made legal with custom lowering. This
393 /// is used to help guide high-level lowering decisions.
394 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
395 return (VT == MVT::Other || isTypeLegal(VT)) &&
396 (getOperationAction(Op, VT) == Legal ||
397 getOperationAction(Op, VT) == Custom);
400 /// isOperationLegal - Return true if the specified operation is legal on this
402 bool isOperationLegal(unsigned Op, EVT VT) const {
403 return (VT == MVT::Other || isTypeLegal(VT)) &&
404 getOperationAction(Op, VT) == Legal;
407 /// getLoadExtAction - Return how this load with extension should be treated:
408 /// either it is legal, needs to be promoted to a larger size, needs to be
409 /// expanded to some other code sequence, or the target has a custom expander
411 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
412 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
413 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
414 "Table isn't big enough!");
415 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
418 /// isLoadExtLegal - Return true if the specified load with extension is legal
420 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
421 return VT.isSimple() &&
422 (getLoadExtAction(ExtType, VT) == Legal ||
423 getLoadExtAction(ExtType, VT) == Custom);
426 /// getTruncStoreAction - Return how this store with truncation should be
427 /// treated: either it is legal, needs to be promoted to a larger size, needs
428 /// to be expanded to some other code sequence, or the target has a custom
430 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
431 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
432 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
433 "Table isn't big enough!");
434 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
435 [MemVT.getSimpleVT().SimpleTy];
438 /// isTruncStoreLegal - Return true if the specified store with truncation is
439 /// legal on this target.
440 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
441 return isTypeLegal(ValVT) && MemVT.isSimple() &&
442 (getTruncStoreAction(ValVT, MemVT) == Legal ||
443 getTruncStoreAction(ValVT, MemVT) == Custom);
446 /// getIndexedLoadAction - Return how the indexed load should be treated:
447 /// either it is legal, needs to be promoted to a larger size, needs to be
448 /// expanded to some other code sequence, or the target has a custom expander
451 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
452 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
453 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
454 "Table isn't big enough!");
455 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
456 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
459 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
461 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
462 return VT.isSimple() &&
463 (getIndexedLoadAction(IdxMode, VT) == Legal ||
464 getIndexedLoadAction(IdxMode, VT) == Custom);
467 /// getIndexedStoreAction - Return how the indexed store should be treated:
468 /// either it is legal, needs to be promoted to a larger size, needs to be
469 /// expanded to some other code sequence, or the target has a custom expander
472 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
473 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
474 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
475 "Table isn't big enough!");
476 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
477 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
480 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
482 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
483 return VT.isSimple() &&
484 (getIndexedStoreAction(IdxMode, VT) == Legal ||
485 getIndexedStoreAction(IdxMode, VT) == Custom);
488 /// getCondCodeAction - Return how the condition code should be treated:
489 /// either it is legal, needs to be expanded to some other code sequence,
490 /// or the target has a custom expander for it.
492 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
493 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
494 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
495 "Table isn't big enough!");
496 LegalizeAction Action = (LegalizeAction)
497 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
498 assert(Action != Promote && "Can't promote condition code!");
502 /// isCondCodeLegal - Return true if the specified condition code is legal
504 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
505 return getCondCodeAction(CC, VT) == Legal ||
506 getCondCodeAction(CC, VT) == Custom;
510 /// getTypeToPromoteTo - If the action for this operation is to promote, this
511 /// method returns the ValueType to promote to.
512 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
513 assert(getOperationAction(Op, VT) == Promote &&
514 "This operation isn't promoted!");
516 // See if this has an explicit type specified.
517 std::map<std::pair<unsigned, MVT::SimpleValueType>,
518 MVT::SimpleValueType>::const_iterator PTTI =
519 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
520 if (PTTI != PromoteToType.end()) return PTTI->second;
522 assert((VT.isInteger() || VT.isFloatingPoint()) &&
523 "Cannot autopromote this type, add it with AddPromotedToType.");
527 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
528 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
529 "Didn't find type to promote to!");
530 } while (!isTypeLegal(NVT) ||
531 getOperationAction(Op, NVT) == Promote);
535 /// getValueType - Return the EVT corresponding to this LLVM type.
536 /// This is fixed by the LLVM operations except for the pointer size. If
537 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
538 /// counterpart (e.g. structs), otherwise it will assert.
539 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
540 EVT VT = EVT::getEVT(Ty, AllowUnknown);
541 return VT == MVT::iPTR ? PointerTy : VT;
544 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
545 /// function arguments in the caller parameter area. This is the actual
546 /// alignment, not its logarithm.
547 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
549 /// getRegisterType - Return the type of registers that this ValueType will
550 /// eventually require.
551 EVT getRegisterType(MVT VT) const {
552 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
553 return RegisterTypeForVT[VT.SimpleTy];
556 /// getRegisterType - Return the type of registers that this ValueType will
557 /// eventually require.
558 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
560 assert((unsigned)VT.getSimpleVT().SimpleTy <
561 array_lengthof(RegisterTypeForVT));
562 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
566 unsigned NumIntermediates;
567 (void)getVectorTypeBreakdown(Context, VT, VT1,
568 NumIntermediates, RegisterVT);
571 if (VT.isInteger()) {
572 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
574 assert(0 && "Unsupported extended type!");
575 return EVT(MVT::Other); // Not reached
578 /// getNumRegisters - Return the number of registers that this ValueType will
579 /// eventually require. This is one for any types promoted to live in larger
580 /// registers, but may be more than one for types (like i64) that are split
581 /// into pieces. For types like i140, which are first promoted then expanded,
582 /// it is the number of registers needed to hold all the bits of the original
583 /// type. For an i140 on a 32 bit machine this means 5 registers.
584 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
586 assert((unsigned)VT.getSimpleVT().SimpleTy <
587 array_lengthof(NumRegistersForVT));
588 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
592 unsigned NumIntermediates;
593 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
595 if (VT.isInteger()) {
596 unsigned BitWidth = VT.getSizeInBits();
597 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
598 return (BitWidth + RegWidth - 1) / RegWidth;
600 assert(0 && "Unsupported extended type!");
601 return 0; // Not reached
604 /// ShouldShrinkFPConstant - If true, then instruction selection should
605 /// seek to shrink the FP constant of the specified type to a smaller type
606 /// in order to save space and / or reduce runtime.
607 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
609 /// hasTargetDAGCombine - If true, the target has custom DAG combine
610 /// transformations that it can perform for the specified node.
611 bool hasTargetDAGCombine(ISD::NodeType NT) const {
612 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
613 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
616 /// This function returns the maximum number of store operations permitted
617 /// to replace a call to llvm.memset. The value is set by the target at the
618 /// performance threshold for such a replacement.
619 /// @brief Get maximum # of store operations permitted for llvm.memset
620 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
622 /// This function returns the maximum number of store operations permitted
623 /// to replace a call to llvm.memcpy. The value is set by the target at the
624 /// performance threshold for such a replacement.
625 /// @brief Get maximum # of store operations permitted for llvm.memcpy
626 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
628 /// This function returns the maximum number of store operations permitted
629 /// to replace a call to llvm.memmove. The value is set by the target at the
630 /// performance threshold for such a replacement.
631 /// @brief Get maximum # of store operations permitted for llvm.memmove
632 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
634 /// This function returns true if the target allows unaligned memory accesses.
635 /// of the specified type. This is used, for example, in situations where an
636 /// array copy/move/set is converted to a sequence of store operations. It's
637 /// use helps to ensure that such replacements don't generate code that causes
638 /// an alignment error (trap) on the target machine.
639 /// @brief Determine if the target supports unaligned memory accesses.
640 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
644 /// This function returns true if the target would benefit from code placement
646 /// @brief Determine if the target should perform code placement optimization.
647 bool shouldOptimizeCodePlacement() const {
648 return benefitFromCodePlacementOpt;
651 /// getOptimalMemOpType - Returns the target specific optimal type for load
652 /// and store operations as a result of memset, memcpy, and memmove
653 /// lowering. If DstAlign is zero that means it's safe to destination
654 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
655 /// means there isn't a need to check it against alignment requirement,
656 /// probably because the source does not need to be loaded. If
657 /// 'NonScalarIntSafe' is true, that means it's safe to return a
658 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
659 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
660 /// constant so it does not need to be loaded.
661 /// It returns EVT::Other if the type should be determined using generic
662 /// target-independent logic.
663 virtual EVT getOptimalMemOpType(uint64_t Size,
664 unsigned DstAlign, unsigned SrcAlign,
665 bool NonScalarIntSafe, bool MemcpyStrSrc,
666 MachineFunction &MF) const {
670 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
671 /// to implement llvm.setjmp.
672 bool usesUnderscoreSetJmp() const {
673 return UseUnderscoreSetJmp;
676 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
677 /// to implement llvm.longjmp.
678 bool usesUnderscoreLongJmp() const {
679 return UseUnderscoreLongJmp;
682 /// getStackPointerRegisterToSaveRestore - If a physical register, this
683 /// specifies the register that llvm.savestack/llvm.restorestack should save
685 unsigned getStackPointerRegisterToSaveRestore() const {
686 return StackPointerRegisterToSaveRestore;
689 /// getExceptionAddressRegister - If a physical register, this returns
690 /// the register that receives the exception address on entry to a landing
692 unsigned getExceptionAddressRegister() const {
693 return ExceptionPointerRegister;
696 /// getExceptionSelectorRegister - If a physical register, this returns
697 /// the register that receives the exception typeid on entry to a landing
699 unsigned getExceptionSelectorRegister() const {
700 return ExceptionSelectorRegister;
703 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
704 /// set, the default is 200)
705 unsigned getJumpBufSize() const {
709 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
710 /// (if never set, the default is 0)
711 unsigned getJumpBufAlignment() const {
712 return JumpBufAlignment;
715 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
717 unsigned getMinStackArgumentAlignment() const {
718 return MinStackArgumentAlignment;
721 /// getPrefLoopAlignment - return the preferred loop alignment.
723 unsigned getPrefLoopAlignment() const {
724 return PrefLoopAlignment;
727 /// getShouldFoldAtomicFences - return whether the combiner should fold
728 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
730 bool getShouldFoldAtomicFences() const {
731 return ShouldFoldAtomicFences;
734 /// getPreIndexedAddressParts - returns true by value, base pointer and
735 /// offset pointer and addressing mode by reference if the node's address
736 /// can be legally represented as pre-indexed load / store address.
737 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
739 ISD::MemIndexedMode &AM,
740 SelectionDAG &DAG) const {
744 /// getPostIndexedAddressParts - returns true by value, base pointer and
745 /// offset pointer and addressing mode by reference if this node can be
746 /// combined with a load / store to form a post-indexed load / store.
747 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
748 SDValue &Base, SDValue &Offset,
749 ISD::MemIndexedMode &AM,
750 SelectionDAG &DAG) const {
754 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
755 /// current function. The returned value is a member of the
756 /// MachineJumpTableInfo::JTEntryKind enum.
757 virtual unsigned getJumpTableEncoding() const;
759 virtual const MCExpr *
760 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
761 const MachineBasicBlock *MBB, unsigned uid,
762 MCContext &Ctx) const {
763 assert(0 && "Need to implement this hook if target has custom JTIs");
767 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
769 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
770 SelectionDAG &DAG) const;
772 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
773 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
775 virtual const MCExpr *
776 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
777 unsigned JTI, MCContext &Ctx) const;
779 /// isOffsetFoldingLegal - Return true if folding a constant offset
780 /// with the given GlobalAddress is legal. It is frequently not legal in
781 /// PIC relocation models.
782 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
784 /// getFunctionAlignment - Return the Log2 alignment of this function.
785 virtual unsigned getFunctionAlignment(const Function *) const = 0;
787 /// getStackCookieLocation - Return true if the target stores stack
788 /// protector cookies at a fixed offset in some non-standard address
789 /// space, and populates the address space and offset as
791 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
795 //===--------------------------------------------------------------------===//
796 // TargetLowering Optimization Methods
799 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
800 /// SDValues for returning information from TargetLowering to its clients
801 /// that want to combine
802 struct TargetLoweringOpt {
809 explicit TargetLoweringOpt(SelectionDAG &InDAG,
811 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
813 bool LegalTypes() const { return LegalTys; }
814 bool LegalOperations() const { return LegalOps; }
816 bool CombineTo(SDValue O, SDValue N) {
822 /// ShrinkDemandedConstant - Check to see if the specified operand of the
823 /// specified instruction is a constant integer. If so, check to see if
824 /// there are any bits set in the constant that are not demanded. If so,
825 /// shrink the constant and return true.
826 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
828 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
829 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
830 /// cast, but it could be generalized for targets with other types of
831 /// implicit widening casts.
832 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
836 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
837 /// DemandedMask bits of the result of Op are ever used downstream. If we can
838 /// use this information to simplify Op, create a new simplified DAG node and
839 /// return true, returning the original and new nodes in Old and New.
840 /// Otherwise, analyze the expression and return a mask of KnownOne and
841 /// KnownZero bits for the expression (used to simplify the caller).
842 /// The KnownZero/One bits may only be accurate for those bits in the
844 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
845 APInt &KnownZero, APInt &KnownOne,
846 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
848 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
849 /// Mask are known to be either zero or one and return them in the
850 /// KnownZero/KnownOne bitsets.
851 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
855 const SelectionDAG &DAG,
856 unsigned Depth = 0) const;
858 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
859 /// targets that want to expose additional information about sign bits to the
861 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
862 unsigned Depth = 0) const;
864 struct DAGCombinerInfo {
865 void *DC; // The DAG Combiner object.
867 bool BeforeLegalizeOps;
868 bool CalledByLegalizer;
872 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
873 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
874 CalledByLegalizer(cl), DAG(dag) {}
876 bool isBeforeLegalize() const { return BeforeLegalize; }
877 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
878 bool isCalledByLegalizer() const { return CalledByLegalizer; }
880 void AddToWorklist(SDNode *N);
881 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
883 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
884 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
886 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
889 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
890 /// and cc. If it is unable to simplify it, return a null SDValue.
891 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
892 ISD::CondCode Cond, bool foldBooleans,
893 DAGCombinerInfo &DCI, DebugLoc dl) const;
895 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
896 /// node is a GlobalAddress + offset.
898 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
900 /// PerformDAGCombine - This method will be invoked for all target nodes and
901 /// for any target-independent nodes that the target has registered with
904 /// The semantics are as follows:
906 /// SDValue.Val == 0 - No change was made
907 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
908 /// otherwise - N should be replaced by the returned Operand.
910 /// In addition, methods provided by DAGCombinerInfo may be used to perform
911 /// more complex transformations.
913 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
915 /// isTypeDesirableForOp - Return true if the target has native support for
916 /// the specified value type and it is 'desirable' to use the type for the
917 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
918 /// instruction encodings are longer and some i16 instructions are slow.
919 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
920 // By default, assume all legal types are desirable.
921 return isTypeLegal(VT);
924 /// IsDesirableToPromoteOp - This method query the target whether it is
925 /// beneficial for dag combiner to promote the specified node. If true, it
926 /// should return the desired promotion type by reference.
927 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
931 //===--------------------------------------------------------------------===//
932 // TargetLowering Configuration Methods - These methods should be invoked by
933 // the derived class constructor to configure this object for the target.
937 /// setShiftAmountType - Describe the type that should be used for shift
938 /// amounts. This type defaults to the pointer type.
939 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
941 /// setBooleanContents - Specify how the target extends the result of a
942 /// boolean value from i1 to a wider type. See getBooleanContents.
943 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
945 /// setSchedulingPreference - Specify the target scheduling preference.
946 void setSchedulingPreference(Sched::Preference Pref) {
947 SchedPreferenceInfo = Pref;
950 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
951 /// use _setjmp to implement llvm.setjmp or the non _ version.
952 /// Defaults to false.
953 void setUseUnderscoreSetJmp(bool Val) {
954 UseUnderscoreSetJmp = Val;
957 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
958 /// use _longjmp to implement llvm.longjmp or the non _ version.
959 /// Defaults to false.
960 void setUseUnderscoreLongJmp(bool Val) {
961 UseUnderscoreLongJmp = Val;
964 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
965 /// specifies the register that llvm.savestack/llvm.restorestack should save
967 void setStackPointerRegisterToSaveRestore(unsigned R) {
968 StackPointerRegisterToSaveRestore = R;
971 /// setExceptionPointerRegister - If set to a physical register, this sets
972 /// the register that receives the exception address on entry to a landing
974 void setExceptionPointerRegister(unsigned R) {
975 ExceptionPointerRegister = R;
978 /// setExceptionSelectorRegister - If set to a physical register, this sets
979 /// the register that receives the exception typeid on entry to a landing
981 void setExceptionSelectorRegister(unsigned R) {
982 ExceptionSelectorRegister = R;
985 /// SelectIsExpensive - Tells the code generator not to expand operations
986 /// into sequences that use the select operations if possible.
987 void setSelectIsExpensive() { SelectIsExpensive = true; }
989 /// setIntDivIsCheap - Tells the code generator that integer divide is
990 /// expensive, and if possible, should be replaced by an alternate sequence
991 /// of instructions not containing an integer divide.
992 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
994 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
995 /// srl/add/sra for a signed divide by power of two, and let the target handle
997 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
999 /// addRegisterClass - Add the specified register class as an available
1000 /// regclass for the specified value type. This indicates the selector can
1001 /// handle values of that class natively.
1002 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
1003 bool isSynthesizable = true) {
1004 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1005 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1006 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1007 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
1010 /// findRepresentativeClass - Return the largest legal super-reg register class
1011 /// of the register class for the specified type and its associated "cost".
1012 virtual std::pair<const TargetRegisterClass*, uint8_t>
1013 findRepresentativeClass(EVT VT) const;
1015 /// computeRegisterProperties - Once all of the register classes are added,
1016 /// this allows us to compute derived properties we expose.
1017 void computeRegisterProperties();
1019 /// setOperationAction - Indicate that the specified operation does not work
1020 /// with the specified type and indicate what to do about it.
1021 void setOperationAction(unsigned Op, MVT VT,
1022 LegalizeAction Action) {
1023 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1024 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1027 /// setLoadExtAction - Indicate that the specified load with extension does
1028 /// not work with the specified type and indicate what to do about it.
1029 void setLoadExtAction(unsigned ExtType, MVT VT,
1030 LegalizeAction Action) {
1031 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
1032 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1033 "Table isn't big enough!");
1034 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1037 /// setTruncStoreAction - Indicate that the specified truncating store does
1038 /// not work with the specified type and indicate what to do about it.
1039 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1040 LegalizeAction Action) {
1041 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1042 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1043 "Table isn't big enough!");
1044 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1047 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1048 /// does not work with the specified type and indicate what to do abort
1049 /// it. NOTE: All indexed mode loads are initialized to Expand in
1050 /// TargetLowering.cpp
1051 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1052 LegalizeAction Action) {
1053 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1054 IdxMode < ISD::LAST_INDEXED_MODE &&
1055 (unsigned)Action < 0xf &&
1056 "Table isn't big enough!");
1057 // Load action are kept in the upper half.
1058 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1059 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1062 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1063 /// does not work with the specified type and indicate what to do about
1064 /// it. NOTE: All indexed mode stores are initialized to Expand in
1065 /// TargetLowering.cpp
1066 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1067 LegalizeAction Action) {
1068 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1069 IdxMode < ISD::LAST_INDEXED_MODE &&
1070 (unsigned)Action < 0xf &&
1071 "Table isn't big enough!");
1072 // Store action are kept in the lower half.
1073 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1074 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1077 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1078 /// supported on the target and indicate what to do about it.
1079 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1080 LegalizeAction Action) {
1081 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1082 (unsigned)CC < array_lengthof(CondCodeActions) &&
1083 "Table isn't big enough!");
1084 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1085 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1088 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1089 /// promotion code defaults to trying a larger integer/fp until it can find
1090 /// one that works. If that default is insufficient, this method can be used
1091 /// by the target to override the default.
1092 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1093 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1096 /// setTargetDAGCombine - Targets should invoke this method for each target
1097 /// independent node that they want to provide a custom DAG combiner for by
1098 /// implementing the PerformDAGCombine virtual method.
1099 void setTargetDAGCombine(ISD::NodeType NT) {
1100 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1101 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1104 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1105 /// bytes); default is 200
1106 void setJumpBufSize(unsigned Size) {
1110 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1111 /// alignment (in bytes); default is 0
1112 void setJumpBufAlignment(unsigned Align) {
1113 JumpBufAlignment = Align;
1116 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1117 /// alignment is zero, it means the target does not care about loop alignment.
1118 void setPrefLoopAlignment(unsigned Align) {
1119 PrefLoopAlignment = Align;
1122 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1124 void setMinStackArgumentAlignment(unsigned Align) {
1125 MinStackArgumentAlignment = Align;
1128 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1129 /// atomic operation intrinsics includes locking. Default is false.
1130 void setShouldFoldAtomicFences(bool fold) {
1131 ShouldFoldAtomicFences = fold;
1135 //===--------------------------------------------------------------------===//
1136 // Lowering methods - These methods must be implemented by targets so that
1137 // the SelectionDAGLowering code knows how to lower these.
1140 /// LowerFormalArguments - This hook must be implemented to lower the
1141 /// incoming (formal) arguments, described by the Ins array, into the
1142 /// specified DAG. The implementation should fill in the InVals array
1143 /// with legal-type argument values, and return the resulting token
1147 LowerFormalArguments(SDValue Chain,
1148 CallingConv::ID CallConv, bool isVarArg,
1149 const SmallVectorImpl<ISD::InputArg> &Ins,
1150 DebugLoc dl, SelectionDAG &DAG,
1151 SmallVectorImpl<SDValue> &InVals) const {
1152 assert(0 && "Not Implemented");
1153 return SDValue(); // this is here to silence compiler errors
1156 /// LowerCallTo - This function lowers an abstract call to a function into an
1157 /// actual call. This returns a pair of operands. The first element is the
1158 /// return value for the function (if RetTy is not VoidTy). The second
1159 /// element is the outgoing token chain. It calls LowerCall to do the actual
1161 struct ArgListEntry {
1172 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1173 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1175 typedef std::vector<ArgListEntry> ArgListTy;
1176 std::pair<SDValue, SDValue>
1177 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1178 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1179 CallingConv::ID CallConv, bool isTailCall,
1180 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1181 SelectionDAG &DAG, DebugLoc dl) const;
1183 /// LowerCall - This hook must be implemented to lower calls into the
1184 /// the specified DAG. The outgoing arguments to the call are described
1185 /// by the Outs array, and the values to be returned by the call are
1186 /// described by the Ins array. The implementation should fill in the
1187 /// InVals array with legal-type return values from the call, and return
1188 /// the resulting token chain value.
1190 LowerCall(SDValue Chain, SDValue Callee,
1191 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1192 const SmallVectorImpl<ISD::OutputArg> &Outs,
1193 const SmallVectorImpl<SDValue> &OutVals,
1194 const SmallVectorImpl<ISD::InputArg> &Ins,
1195 DebugLoc dl, SelectionDAG &DAG,
1196 SmallVectorImpl<SDValue> &InVals) const {
1197 assert(0 && "Not Implemented");
1198 return SDValue(); // this is here to silence compiler errors
1201 /// CanLowerReturn - This hook should be implemented to check whether the
1202 /// return values described by the Outs array can fit into the return
1203 /// registers. If false is returned, an sret-demotion is performed.
1205 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1206 const SmallVectorImpl<ISD::OutputArg> &Outs,
1207 LLVMContext &Context) const
1209 // Return true by default to get preexisting behavior.
1213 /// LowerReturn - This hook must be implemented to lower outgoing
1214 /// return values, described by the Outs array, into the specified
1215 /// DAG. The implementation should return the resulting token chain
1219 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1220 const SmallVectorImpl<ISD::OutputArg> &Outs,
1221 const SmallVectorImpl<SDValue> &OutVals,
1222 DebugLoc dl, SelectionDAG &DAG) const {
1223 assert(0 && "Not Implemented");
1224 return SDValue(); // this is here to silence compiler errors
1227 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1228 /// to legalize nodes with an illegal operand type but legal result types.
1229 /// It replaces the LowerOperation callback in the type Legalizer.
1230 /// The reason we can not do away with LowerOperation entirely is that
1231 /// LegalizeDAG isn't yet ready to use this callback.
1232 /// TODO: Consider merging with ReplaceNodeResults.
1234 /// The target places new result values for the node in Results (their number
1235 /// and types must exactly match those of the original return values of
1236 /// the node), or leaves Results empty, which indicates that the node is not
1237 /// to be custom lowered after all.
1238 /// The default implementation calls LowerOperation.
1239 virtual void LowerOperationWrapper(SDNode *N,
1240 SmallVectorImpl<SDValue> &Results,
1241 SelectionDAG &DAG) const;
1243 /// LowerOperation - This callback is invoked for operations that are
1244 /// unsupported by the target, which are registered to use 'custom' lowering,
1245 /// and whose defined values are all legal.
1246 /// If the target has no operations that require custom lowering, it need not
1247 /// implement this. The default implementation of this aborts.
1248 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1250 /// ReplaceNodeResults - This callback is invoked when a node result type is
1251 /// illegal for the target, and the operation was registered to use 'custom'
1252 /// lowering for that result type. The target places new result values for
1253 /// the node in Results (their number and types must exactly match those of
1254 /// the original return values of the node), or leaves Results empty, which
1255 /// indicates that the node is not to be custom lowered after all.
1257 /// If the target has no operations that require custom lowering, it need not
1258 /// implement this. The default implementation aborts.
1259 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1260 SelectionDAG &DAG) const {
1261 assert(0 && "ReplaceNodeResults not implemented for this target!");
1264 /// getTargetNodeName() - This method returns the name of a target specific
1266 virtual const char *getTargetNodeName(unsigned Opcode) const;
1268 /// createFastISel - This method returns a target specific FastISel object,
1269 /// or null if the target does not support "fast" ISel.
1270 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1274 //===--------------------------------------------------------------------===//
1275 // Inline Asm Support hooks
1278 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1279 /// call to be explicit llvm code if it wants to. This is useful for
1280 /// turning simple inline asms into LLVM intrinsics, which gives the
1281 /// compiler more information about the behavior of the code.
1282 virtual bool ExpandInlineAsm(CallInst *CI) const {
1286 enum ConstraintType {
1287 C_Register, // Constraint represents specific register(s).
1288 C_RegisterClass, // Constraint represents any of register(s) in class.
1289 C_Memory, // Memory constraint.
1290 C_Other, // Something else.
1291 C_Unknown // Unsupported constraint.
1294 /// AsmOperandInfo - This contains information for each constraint that we are
1296 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1297 /// ConstraintCode - This contains the actual string for the code, like "m".
1298 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1299 /// most closely matches the operand.
1300 std::string ConstraintCode;
1302 /// ConstraintType - Information about the constraint code, e.g. Register,
1303 /// RegisterClass, Memory, Other, Unknown.
1304 TargetLowering::ConstraintType ConstraintType;
1306 /// CallOperandval - If this is the result output operand or a
1307 /// clobber, this is null, otherwise it is the incoming operand to the
1308 /// CallInst. This gets modified as the asm is processed.
1309 Value *CallOperandVal;
1311 /// ConstraintVT - The ValueType for the operand value.
1314 /// isMatchingInputConstraint - Return true of this is an input operand that
1315 /// is a matching constraint like "4".
1316 bool isMatchingInputConstraint() const;
1318 /// getMatchedOperand - If this is an input matching constraint, this method
1319 /// returns the output operand it matches.
1320 unsigned getMatchedOperand() const;
1322 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1323 : InlineAsm::ConstraintInfo(info),
1324 ConstraintType(TargetLowering::C_Unknown),
1325 CallOperandVal(0), ConstraintVT(MVT::Other) {
1329 /// ComputeConstraintToUse - Determines the constraint code and constraint
1330 /// type to use for the specific AsmOperandInfo, setting
1331 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1332 /// being passed in is available, it can be passed in as Op, otherwise an
1333 /// empty SDValue can be passed.
1334 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1336 SelectionDAG *DAG = 0) const;
1338 /// getConstraintType - Given a constraint, return the type of constraint it
1339 /// is for this target.
1340 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1342 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1343 /// return a list of registers that can be used to satisfy the constraint.
1344 /// This should only be used for C_RegisterClass constraints.
1345 virtual std::vector<unsigned>
1346 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1349 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1350 /// {edx}), return the register number and the register class for the
1353 /// Given a register class constraint, like 'r', if this corresponds directly
1354 /// to an LLVM register class, return a register of 0 and the register class
1357 /// This should only be used for C_Register constraints. On error,
1358 /// this returns a register number of 0 and a null register class pointer..
1359 virtual std::pair<unsigned, const TargetRegisterClass*>
1360 getRegForInlineAsmConstraint(const std::string &Constraint,
1363 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1364 /// with another that has more specific requirements based on the type of the
1365 /// corresponding operand. This returns null if there is no replacement to
1367 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1369 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1370 /// vector. If it is invalid, don't add anything to Ops.
1371 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1372 std::vector<SDValue> &Ops,
1373 SelectionDAG &DAG) const;
1375 //===--------------------------------------------------------------------===//
1376 // Instruction Emitting Hooks
1379 // EmitInstrWithCustomInserter - This method should be implemented by targets
1380 // that mark instructions with the 'usesCustomInserter' flag. These
1381 // instructions are special in various ways, which require special support to
1382 // insert. The specified MachineInstr is created but not inserted into any
1383 // basic blocks, and this method is called to expand it into a sequence of
1384 // instructions, potentially also creating new basic blocks and control flow.
1385 virtual MachineBasicBlock *
1386 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1388 //===--------------------------------------------------------------------===//
1389 // Addressing mode description hooks (used by LSR etc).
1392 /// AddrMode - This represents an addressing mode of:
1393 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1394 /// If BaseGV is null, there is no BaseGV.
1395 /// If BaseOffs is zero, there is no base offset.
1396 /// If HasBaseReg is false, there is no base register.
1397 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1401 GlobalValue *BaseGV;
1405 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1408 /// isLegalAddressingMode - Return true if the addressing mode represented by
1409 /// AM is legal for this target, for a load/store of the specified type.
1410 /// The type may be VoidTy, in which case only return true if the addressing
1411 /// mode is legal for a load/store of any legal type.
1412 /// TODO: Handle pre/postinc as well.
1413 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1415 /// isTruncateFree - Return true if it's free to truncate a value of
1416 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1417 /// register EAX to i16 by referencing its sub-register AX.
1418 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1422 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1426 /// isZExtFree - Return true if any actual instruction that defines a
1427 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1428 /// register. This does not necessarily include registers defined in
1429 /// unknown ways, such as incoming arguments, or copies from unknown
1430 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1431 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1432 /// all instructions that define 32-bit values implicit zero-extend the
1433 /// result out to 64 bits.
1434 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1438 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1442 /// isNarrowingProfitable - Return true if it's profitable to narrow
1443 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1444 /// from i32 to i8 but not from i32 to i16.
1445 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1449 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1450 /// icmp immediate, that is the target has icmp instructions which can compare
1451 /// a register against the immediate without having to materialize the
1452 /// immediate into a register.
1453 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1457 //===--------------------------------------------------------------------===//
1458 // Div utility functions
1460 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1461 std::vector<SDNode*>* Created) const;
1462 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1463 std::vector<SDNode*>* Created) const;
1466 //===--------------------------------------------------------------------===//
1467 // Runtime Library hooks
1470 /// setLibcallName - Rename the default libcall routine name for the specified
1472 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1473 LibcallRoutineNames[Call] = Name;
1476 /// getLibcallName - Get the libcall routine name for the specified libcall.
1478 const char *getLibcallName(RTLIB::Libcall Call) const {
1479 return LibcallRoutineNames[Call];
1482 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1483 /// result of the comparison libcall against zero.
1484 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1485 CmpLibcallCCs[Call] = CC;
1488 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1489 /// the comparison libcall against zero.
1490 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1491 return CmpLibcallCCs[Call];
1494 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1495 /// specified libcall.
1496 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1497 LibcallCallingConvs[Call] = CC;
1500 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1501 /// specified libcall.
1502 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1503 return LibcallCallingConvs[Call];
1507 const TargetMachine &TM;
1508 const TargetData *TD;
1509 const TargetLoweringObjectFile &TLOF;
1511 /// PointerTy - The type to use for pointers, usually i32 or i64.
1515 /// IsLittleEndian - True if this is a little endian target.
1517 bool IsLittleEndian;
1519 /// SelectIsExpensive - Tells the code generator not to expand operations
1520 /// into sequences that use the select operations if possible.
1521 bool SelectIsExpensive;
1523 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1524 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1525 /// a real cost model is in place. If we ever optimize for size, this will be
1526 /// set to true unconditionally.
1529 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1530 /// srl/add/sra for a signed divide by power of two, and let the target handle
1532 bool Pow2DivIsCheap;
1534 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1535 /// llvm.setjmp. Defaults to false.
1536 bool UseUnderscoreSetJmp;
1538 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1539 /// llvm.longjmp. Defaults to false.
1540 bool UseUnderscoreLongJmp;
1542 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1546 /// BooleanContents - Information about the contents of the high-bits in
1547 /// boolean values held in a type wider than i1. See getBooleanContents.
1548 BooleanContent BooleanContents;
1550 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1551 /// total cycles or lowest register usage.
1552 Sched::Preference SchedPreferenceInfo;
1554 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1555 unsigned JumpBufSize;
1557 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1559 unsigned JumpBufAlignment;
1561 /// MinStackArgumentAlignment - The minimum alignment that any argument
1562 /// on the stack needs to have.
1564 unsigned MinStackArgumentAlignment;
1566 /// PrefLoopAlignment - The perferred loop alignment.
1568 unsigned PrefLoopAlignment;
1570 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1571 /// be folded into the enclosed atomic intrinsic instruction by the
1573 bool ShouldFoldAtomicFences;
1575 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1576 /// specifies the register that llvm.savestack/llvm.restorestack should save
1578 unsigned StackPointerRegisterToSaveRestore;
1580 /// ExceptionPointerRegister - If set to a physical register, this specifies
1581 /// the register that receives the exception address on entry to a landing
1583 unsigned ExceptionPointerRegister;
1585 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1586 /// the register that receives the exception typeid on entry to a landing
1588 unsigned ExceptionSelectorRegister;
1590 /// RegClassForVT - This indicates the default register class to use for
1591 /// each ValueType the target supports natively.
1592 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1593 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1594 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1596 /// RepRegClassForVT - This indicates the "representative" register class to
1597 /// use for each ValueType the target supports natively. This information is
1598 /// used by the scheduler to track register pressure. By default, the
1599 /// representative register class is the largest legal super-reg register
1600 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1601 /// and i32's representative class would be GR32.
1602 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1604 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1605 /// register class for each ValueType. The cost is used by the scheduler to
1606 /// approximate register pressure.
1607 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1609 /// Synthesizable indicates whether it is OK for the compiler to create new
1610 /// operations using this type. All Legal types are Synthesizable except
1611 /// MMX types on X86. Non-Legal types are not Synthesizable.
1612 bool Synthesizable[MVT::LAST_VALUETYPE];
1614 /// TransformToType - For any value types we are promoting or expanding, this
1615 /// contains the value type that we are changing to. For Expanded types, this
1616 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1617 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1618 /// by the system, this holds the same type (e.g. i32 -> i32).
1619 EVT TransformToType[MVT::LAST_VALUETYPE];
1621 /// OpActions - For each operation and each value type, keep a LegalizeAction
1622 /// that indicates how instruction selection should deal with the operation.
1623 /// Most operations are Legal (aka, supported natively by the target), but
1624 /// operations that are not should be described. Note that operations on
1625 /// non-legal value types are not described here.
1626 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1628 /// LoadExtActions - For each load extension type and each value type,
1629 /// keep a LegalizeAction that indicates how instruction selection should deal
1630 /// with a load of a specific value type and extension type.
1631 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1633 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1634 /// indicates whether a truncating store of a specific value type and
1635 /// truncating type is legal.
1636 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1638 /// IndexedModeActions - For each indexed mode and each value type,
1639 /// keep a pair of LegalizeAction that indicates how instruction
1640 /// selection should deal with the load / store. The first dimension is the
1641 /// value_type for the reference. The second dimension represents the various
1642 /// modes for load store.
1643 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1645 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1646 /// LegalizeAction that indicates how instruction selection should
1647 /// deal with the condition code.
1648 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1650 ValueTypeActionImpl ValueTypeActions;
1652 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1654 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1655 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1656 /// which sets a bit in this array.
1658 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1660 /// PromoteToType - For operations that must be promoted to a specific type,
1661 /// this holds the destination type. This map should be sparse, so don't hold
1664 /// Targets add entries to this map with AddPromotedToType(..), clients access
1665 /// this with getTypeToPromoteTo(..).
1666 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1669 /// LibcallRoutineNames - Stores the name each libcall.
1671 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1673 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1674 /// of each of the comparison libcall against zero.
1675 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1677 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1679 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1682 /// When lowering \@llvm.memset this field specifies the maximum number of
1683 /// store operations that may be substituted for the call to memset. Targets
1684 /// must set this value based on the cost threshold for that target. Targets
1685 /// should assume that the memset will be done using as many of the largest
1686 /// store operations first, followed by smaller ones, if necessary, per
1687 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1688 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1689 /// store. This only applies to setting a constant array of a constant size.
1690 /// @brief Specify maximum number of store instructions per memset call.
1691 unsigned maxStoresPerMemset;
1693 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1694 /// store operations that may be substituted for a call to memcpy. Targets
1695 /// must set this value based on the cost threshold for that target. Targets
1696 /// should assume that the memcpy will be done using as many of the largest
1697 /// store operations first, followed by smaller ones, if necessary, per
1698 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1699 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1700 /// and one 1-byte store. This only applies to copying a constant array of
1702 /// @brief Specify maximum bytes of store instructions per memcpy call.
1703 unsigned maxStoresPerMemcpy;
1705 /// When lowering \@llvm.memmove this field specifies the maximum number of
1706 /// store instructions that may be substituted for a call to memmove. Targets
1707 /// must set this value based on the cost threshold for that target. Targets
1708 /// should assume that the memmove will be done using as many of the largest
1709 /// store operations first, followed by smaller ones, if necessary, per
1710 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1711 /// with 8-bit alignment would result in nine 1-byte stores. This only
1712 /// applies to copying a constant array of constant size.
1713 /// @brief Specify maximum bytes of store instructions per memmove call.
1714 unsigned maxStoresPerMemmove;
1716 /// This field specifies whether the target can benefit from code placement
1718 bool benefitFromCodePlacementOpt;
1721 /// isLegalRC - Return true if the value types that can be represented by the
1722 /// specified register class are all legal.
1723 bool isLegalRC(const TargetRegisterClass *RC) const;
1725 /// hasLegalSuperRegRegClasses - Return true if the specified register class
1726 /// has one or more super-reg register classes that are legal.
1727 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
1730 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1731 /// compute the return value EVTs and flags, and optionally also
1732 /// the offsets, if the return value is being lowered to memory.
1733 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1734 SmallVectorImpl<ISD::OutputArg> &Outs,
1735 const TargetLowering &TLI,
1736 SmallVectorImpl<uint64_t> *Offsets = 0);
1738 } // end llvm namespace