1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/DebugLoc.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
49 class MachineBasicBlock;
50 class MachineFunction;
51 class MachineFrameInfo;
53 class MachineJumpTableInfo;
61 class TargetRegisterClass;
62 class TargetLoweringObjectFile;
65 // FIXME: should this be here?
74 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
77 //===----------------------------------------------------------------------===//
78 /// TargetLowering - This class defines information used to lower LLVM code to
79 /// legal SelectionDAG operators that the target instruction selector can accept
82 /// This class also defines callbacks that targets must implement to lower
83 /// target-specific constructs to SelectionDAG operators.
85 class TargetLowering {
86 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
87 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
89 /// LegalizeAction - This enum indicates whether operations are valid for a
90 /// target, and if not, what action should be used to make them valid.
92 Legal, // The target natively supports this operation.
93 Promote, // This operation should be executed in a larger type.
94 Expand, // Try to expand this to other ops, otherwise use a libcall.
95 Custom // Use the LowerOperation hook to implement custom lowering.
98 enum BooleanContent { // How the target represents true/false values.
99 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
100 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
101 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
104 /// NOTE: The constructor takes ownership of TLOF.
105 explicit TargetLowering(const TargetMachine &TM,
106 const TargetLoweringObjectFile *TLOF);
107 virtual ~TargetLowering();
109 const TargetMachine &getTargetMachine() const { return TM; }
110 const TargetData *getTargetData() const { return TD; }
111 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
113 bool isBigEndian() const { return !IsLittleEndian; }
114 bool isLittleEndian() const { return IsLittleEndian; }
115 MVT getPointerTy() const { return PointerTy; }
116 MVT getShiftAmountTy() const { return ShiftAmountTy; }
118 /// isSelectExpensive - Return true if the select operation is expensive for
120 bool isSelectExpensive() const { return SelectIsExpensive; }
122 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
123 /// a sequence of several shifts, adds, and multiplies for this target.
124 bool isIntDivCheap() const { return IntDivIsCheap; }
126 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
128 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
130 /// getSetCCResultType - Return the ValueType of the result of SETCC
131 /// operations. Also used to obtain the target's preferred type for
132 /// the condition operand of SELECT and BRCOND nodes. In the case of
133 /// BRCOND the argument passed is MVT::Other since there are no other
134 /// operands to get a type hint from.
136 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
138 /// getCmpLibcallReturnType - Return the ValueType for comparison
139 /// libcalls. Comparions libcalls include floating point comparion calls,
140 /// and Ordered/Unordered check calls on floating point numbers.
142 MVT::SimpleValueType getCmpLibcallReturnType() const;
144 /// getBooleanContents - For targets without i1 registers, this gives the
145 /// nature of the high-bits of boolean values held in types wider than i1.
146 /// "Boolean values" are special true/false values produced by nodes like
147 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
148 /// Not to be confused with general values promoted from i1.
149 BooleanContent getBooleanContents() const { return BooleanContents;}
151 /// getSchedulingPreference - Return target scheduling preference.
152 Sched::Preference getSchedulingPreference() const {
153 return SchedPreferenceInfo;
156 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
157 /// different scheduling heuristics for different nodes. This function returns
158 /// the preference (or none) for the given node.
159 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
163 /// getRegClassFor - Return the register class that should be used for the
164 /// specified value type.
165 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
166 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
167 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
168 assert(RC && "This value type is not natively supported!");
172 /// getRepRegClassFor - Return the 'representative' register class for the
173 /// specified value type. The 'representative' register class is the largest
174 /// legal super-reg register class for the register class of the value type.
175 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
176 /// while the rep register class is GR64 on x86_64.
177 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
178 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
179 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
183 /// getRepRegClassCostFor - Return the cost of the 'representative' register
184 /// class for the specified value type.
185 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
186 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
187 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
190 /// getRegPressureLimit - Return the register pressure "high water mark" for
191 /// the specific register class. The scheduler is in high register pressure
192 /// mode (for the specific register class) if it goes over the limit.
193 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
194 MachineFunction &MF) const {
198 /// isTypeLegal - Return true if the target has native support for the
199 /// specified value type. This means that it has a register that directly
200 /// holds it without promotions or expansions.
201 bool isTypeLegal(EVT VT) const {
202 assert(!VT.isSimple() ||
203 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
204 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
207 class ValueTypeActionImpl {
208 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
209 /// that indicates how instruction selection should deal with the type.
210 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
212 LegalizeAction getExtendedTypeAction(EVT VT) const {
213 // Handle non-vector integers.
214 if (!VT.isVector()) {
215 assert(VT.isInteger() && "Unsupported extended type!");
216 unsigned BitSize = VT.getSizeInBits();
217 // First promote to a power-of-two size, then expand if necessary.
218 if (BitSize < 8 || !isPowerOf2_32(BitSize))
223 // If this is a type smaller than a legal vector type, promote to that
224 // type, e.g. <2 x float> -> <4 x float>.
225 if (VT.getVectorElementType().isSimple() &&
226 VT.getVectorNumElements() != 1) {
227 MVT EltType = VT.getVectorElementType().getSimpleVT();
228 unsigned NumElts = VT.getVectorNumElements();
230 // Round up to the nearest power of 2.
231 NumElts = (unsigned)NextPowerOf2(NumElts);
233 MVT LargerVector = MVT::getVectorVT(EltType, NumElts);
234 if (LargerVector == MVT()) break;
236 // If this the larger type is legal, promote to it.
237 if (getTypeAction(LargerVector) == Legal) return Promote;
241 return VT.isPow2VectorType() ? Expand : Promote;
244 ValueTypeActionImpl() {
245 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
248 LegalizeAction getTypeAction(EVT VT) const {
249 if (!VT.isExtended())
250 return getTypeAction(VT.getSimpleVT());
251 return getExtendedTypeAction(VT);
254 LegalizeAction getTypeAction(MVT VT) const {
255 return (LegalizeAction)ValueTypeActions[VT.SimpleTy];
258 void setTypeAction(EVT VT, LegalizeAction Action) {
259 unsigned I = VT.getSimpleVT().SimpleTy;
260 ValueTypeActions[I] = Action;
264 const ValueTypeActionImpl &getValueTypeActions() const {
265 return ValueTypeActions;
268 /// getTypeAction - Return how we should legalize values of this type, either
269 /// it is already legal (return 'Legal') or we need to promote it to a larger
270 /// type (return 'Promote'), or we need to expand it into multiple registers
271 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
272 LegalizeAction getTypeAction(EVT VT) const {
273 return ValueTypeActions.getTypeAction(VT);
275 LegalizeAction getTypeAction(MVT VT) const {
276 return ValueTypeActions.getTypeAction(VT);
279 /// getTypeToTransformTo - For types supported by the target, this is an
280 /// identity function. For types that must be promoted to larger types, this
281 /// returns the larger type to promote to. For integer types that are larger
282 /// than the largest integer register, this contains one step in the expansion
283 /// to get to the smaller register. For illegal floating point types, this
284 /// returns the integer type to transform to.
285 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
287 assert((unsigned)VT.getSimpleVT().SimpleTy <
288 array_lengthof(TransformToType));
289 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
290 assert(getTypeAction(NVT) != Promote &&
291 "Promote may not follow Expand or Promote");
296 EVT NVT = VT.getPow2VectorType(Context);
298 // Vector length is a power of 2 - split to half the size.
299 unsigned NumElts = VT.getVectorNumElements();
300 EVT EltVT = VT.getVectorElementType();
301 return (NumElts == 1) ?
302 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
304 // Promote to a power of two size, avoiding multi-step promotion.
305 return getTypeAction(NVT) == Promote ?
306 getTypeToTransformTo(Context, NVT) : NVT;
307 } else if (VT.isInteger()) {
308 EVT NVT = VT.getRoundIntegerType(Context);
309 if (NVT == VT) // Size is a power of two - expand to half the size.
310 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
312 // Promote to a power of two size, avoiding multi-step promotion.
313 return getTypeAction(NVT) == Promote ?
314 getTypeToTransformTo(Context, NVT) : NVT;
316 assert(0 && "Unsupported extended type!");
317 return MVT(MVT::Other); // Not reached
320 /// getTypeToExpandTo - For types supported by the target, this is an
321 /// identity function. For types that must be expanded (i.e. integer types
322 /// that are larger than the largest integer register or illegal floating
323 /// point types), this returns the largest legal type it will be expanded to.
324 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
325 assert(!VT.isVector());
327 switch (getTypeAction(VT)) {
331 VT = getTypeToTransformTo(Context, VT);
334 assert(false && "Type is not legal nor is it to be expanded!");
341 /// getVectorTypeBreakdown - Vector types are broken down into some number of
342 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
343 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
344 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
346 /// This method returns the number of registers needed, and the VT for each
347 /// register. It also returns the VT and quantity of the intermediate values
348 /// before they are promoted/expanded.
350 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
352 unsigned &NumIntermediates,
353 EVT &RegisterVT) const;
355 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
356 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
357 /// this is the case, it returns true and store the intrinsic
358 /// information into the IntrinsicInfo that was passed to the function.
359 struct IntrinsicInfo {
360 unsigned opc; // target opcode
361 EVT memVT; // memory VT
362 const Value* ptrVal; // value representing memory location
363 int offset; // offset off of ptrVal
364 unsigned align; // alignment
365 bool vol; // is volatile?
366 bool readMem; // reads memory?
367 bool writeMem; // writes memory?
370 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
371 const CallInst &I, unsigned Intrinsic) const {
375 /// isFPImmLegal - Returns true if the target can instruction select the
376 /// specified FP immediate natively. If false, the legalizer will materialize
377 /// the FP immediate as a load from a constant pool.
378 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
382 /// isShuffleMaskLegal - Targets can use this to indicate that they only
383 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
384 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
385 /// are assumed to be legal.
386 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
391 /// canOpTrap - Returns true if the operation can trap for the value type.
392 /// VT must be a legal type. By default, we optimistically assume most
393 /// operations don't trap except for divide and remainder.
394 virtual bool canOpTrap(unsigned Op, EVT VT) const;
396 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
397 /// used by Targets can use this to indicate if there is a suitable
398 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
400 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
405 /// getOperationAction - Return how this operation should be treated: either
406 /// it is legal, needs to be promoted to a larger size, needs to be
407 /// expanded to some other code sequence, or the target has a custom expander
409 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
410 if (VT.isExtended()) return Expand;
411 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
412 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
413 return (LegalizeAction)OpActions[I][Op];
416 /// isOperationLegalOrCustom - Return true if the specified operation is
417 /// legal on this target or can be made legal with custom lowering. This
418 /// is used to help guide high-level lowering decisions.
419 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
420 return (VT == MVT::Other || isTypeLegal(VT)) &&
421 (getOperationAction(Op, VT) == Legal ||
422 getOperationAction(Op, VT) == Custom);
425 /// isOperationLegal - Return true if the specified operation is legal on this
427 bool isOperationLegal(unsigned Op, EVT VT) const {
428 return (VT == MVT::Other || isTypeLegal(VT)) &&
429 getOperationAction(Op, VT) == Legal;
432 /// getLoadExtAction - Return how this load with extension should be treated:
433 /// either it is legal, needs to be promoted to a larger size, needs to be
434 /// expanded to some other code sequence, or the target has a custom expander
436 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
437 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
438 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
439 "Table isn't big enough!");
440 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
443 /// isLoadExtLegal - Return true if the specified load with extension is legal
445 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
446 return VT.isSimple() &&
447 (getLoadExtAction(ExtType, VT) == Legal ||
448 getLoadExtAction(ExtType, VT) == Custom);
451 /// getTruncStoreAction - Return how this store with truncation should be
452 /// treated: either it is legal, needs to be promoted to a larger size, needs
453 /// to be expanded to some other code sequence, or the target has a custom
455 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
456 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
457 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
458 "Table isn't big enough!");
459 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
460 [MemVT.getSimpleVT().SimpleTy];
463 /// isTruncStoreLegal - Return true if the specified store with truncation is
464 /// legal on this target.
465 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
466 return isTypeLegal(ValVT) && MemVT.isSimple() &&
467 (getTruncStoreAction(ValVT, MemVT) == Legal ||
468 getTruncStoreAction(ValVT, MemVT) == Custom);
471 /// getIndexedLoadAction - Return how the indexed load should be treated:
472 /// either it is legal, needs to be promoted to a larger size, needs to be
473 /// expanded to some other code sequence, or the target has a custom expander
476 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
477 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
478 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
479 "Table isn't big enough!");
480 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
481 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
484 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
486 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
487 return VT.isSimple() &&
488 (getIndexedLoadAction(IdxMode, VT) == Legal ||
489 getIndexedLoadAction(IdxMode, VT) == Custom);
492 /// getIndexedStoreAction - Return how the indexed store should be treated:
493 /// either it is legal, needs to be promoted to a larger size, needs to be
494 /// expanded to some other code sequence, or the target has a custom expander
497 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
498 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
499 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
500 "Table isn't big enough!");
501 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
502 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
505 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
507 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
508 return VT.isSimple() &&
509 (getIndexedStoreAction(IdxMode, VT) == Legal ||
510 getIndexedStoreAction(IdxMode, VT) == Custom);
513 /// getCondCodeAction - Return how the condition code should be treated:
514 /// either it is legal, needs to be expanded to some other code sequence,
515 /// or the target has a custom expander for it.
517 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
518 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
519 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
520 "Table isn't big enough!");
521 LegalizeAction Action = (LegalizeAction)
522 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
523 assert(Action != Promote && "Can't promote condition code!");
527 /// isCondCodeLegal - Return true if the specified condition code is legal
529 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
530 return getCondCodeAction(CC, VT) == Legal ||
531 getCondCodeAction(CC, VT) == Custom;
535 /// getTypeToPromoteTo - If the action for this operation is to promote, this
536 /// method returns the ValueType to promote to.
537 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
538 assert(getOperationAction(Op, VT) == Promote &&
539 "This operation isn't promoted!");
541 // See if this has an explicit type specified.
542 std::map<std::pair<unsigned, MVT::SimpleValueType>,
543 MVT::SimpleValueType>::const_iterator PTTI =
544 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
545 if (PTTI != PromoteToType.end()) return PTTI->second;
547 assert((VT.isInteger() || VT.isFloatingPoint()) &&
548 "Cannot autopromote this type, add it with AddPromotedToType.");
552 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
553 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
554 "Didn't find type to promote to!");
555 } while (!isTypeLegal(NVT) ||
556 getOperationAction(Op, NVT) == Promote);
560 /// getValueType - Return the EVT corresponding to this LLVM type.
561 /// This is fixed by the LLVM operations except for the pointer size. If
562 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
563 /// counterpart (e.g. structs), otherwise it will assert.
564 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
565 EVT VT = EVT::getEVT(Ty, AllowUnknown);
566 return VT == MVT::iPTR ? PointerTy : VT;
569 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
570 /// function arguments in the caller parameter area. This is the actual
571 /// alignment, not its logarithm.
572 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
574 /// getRegisterType - Return the type of registers that this ValueType will
575 /// eventually require.
576 EVT getRegisterType(MVT VT) const {
577 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
578 return RegisterTypeForVT[VT.SimpleTy];
581 /// getRegisterType - Return the type of registers that this ValueType will
582 /// eventually require.
583 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
585 assert((unsigned)VT.getSimpleVT().SimpleTy <
586 array_lengthof(RegisterTypeForVT));
587 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
591 unsigned NumIntermediates;
592 (void)getVectorTypeBreakdown(Context, VT, VT1,
593 NumIntermediates, RegisterVT);
596 if (VT.isInteger()) {
597 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
599 assert(0 && "Unsupported extended type!");
600 return EVT(MVT::Other); // Not reached
603 /// getNumRegisters - Return the number of registers that this ValueType will
604 /// eventually require. This is one for any types promoted to live in larger
605 /// registers, but may be more than one for types (like i64) that are split
606 /// into pieces. For types like i140, which are first promoted then expanded,
607 /// it is the number of registers needed to hold all the bits of the original
608 /// type. For an i140 on a 32 bit machine this means 5 registers.
609 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
611 assert((unsigned)VT.getSimpleVT().SimpleTy <
612 array_lengthof(NumRegistersForVT));
613 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
617 unsigned NumIntermediates;
618 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
620 if (VT.isInteger()) {
621 unsigned BitWidth = VT.getSizeInBits();
622 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
623 return (BitWidth + RegWidth - 1) / RegWidth;
625 assert(0 && "Unsupported extended type!");
626 return 0; // Not reached
629 /// ShouldShrinkFPConstant - If true, then instruction selection should
630 /// seek to shrink the FP constant of the specified type to a smaller type
631 /// in order to save space and / or reduce runtime.
632 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
634 /// hasTargetDAGCombine - If true, the target has custom DAG combine
635 /// transformations that it can perform for the specified node.
636 bool hasTargetDAGCombine(ISD::NodeType NT) const {
637 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
638 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
641 /// This function returns the maximum number of store operations permitted
642 /// to replace a call to llvm.memset. The value is set by the target at the
643 /// performance threshold for such a replacement.
644 /// @brief Get maximum # of store operations permitted for llvm.memset
645 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
647 /// This function returns the maximum number of store operations permitted
648 /// to replace a call to llvm.memcpy. The value is set by the target at the
649 /// performance threshold for such a replacement.
650 /// @brief Get maximum # of store operations permitted for llvm.memcpy
651 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
653 /// This function returns the maximum number of store operations permitted
654 /// to replace a call to llvm.memmove. The value is set by the target at the
655 /// performance threshold for such a replacement.
656 /// @brief Get maximum # of store operations permitted for llvm.memmove
657 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
659 /// This function returns true if the target allows unaligned memory accesses.
660 /// of the specified type. This is used, for example, in situations where an
661 /// array copy/move/set is converted to a sequence of store operations. It's
662 /// use helps to ensure that such replacements don't generate code that causes
663 /// an alignment error (trap) on the target machine.
664 /// @brief Determine if the target supports unaligned memory accesses.
665 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
669 /// This function returns true if the target would benefit from code placement
671 /// @brief Determine if the target should perform code placement optimization.
672 bool shouldOptimizeCodePlacement() const {
673 return benefitFromCodePlacementOpt;
676 /// getOptimalMemOpType - Returns the target specific optimal type for load
677 /// and store operations as a result of memset, memcpy, and memmove
678 /// lowering. If DstAlign is zero that means it's safe to destination
679 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
680 /// means there isn't a need to check it against alignment requirement,
681 /// probably because the source does not need to be loaded. If
682 /// 'NonScalarIntSafe' is true, that means it's safe to return a
683 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
684 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
685 /// constant so it does not need to be loaded.
686 /// It returns EVT::Other if the type should be determined using generic
687 /// target-independent logic.
688 virtual EVT getOptimalMemOpType(uint64_t Size,
689 unsigned DstAlign, unsigned SrcAlign,
690 bool NonScalarIntSafe, bool MemcpyStrSrc,
691 MachineFunction &MF) const {
695 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
696 /// to implement llvm.setjmp.
697 bool usesUnderscoreSetJmp() const {
698 return UseUnderscoreSetJmp;
701 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
702 /// to implement llvm.longjmp.
703 bool usesUnderscoreLongJmp() const {
704 return UseUnderscoreLongJmp;
707 /// getStackPointerRegisterToSaveRestore - If a physical register, this
708 /// specifies the register that llvm.savestack/llvm.restorestack should save
710 unsigned getStackPointerRegisterToSaveRestore() const {
711 return StackPointerRegisterToSaveRestore;
714 /// getExceptionAddressRegister - If a physical register, this returns
715 /// the register that receives the exception address on entry to a landing
717 unsigned getExceptionAddressRegister() const {
718 return ExceptionPointerRegister;
721 /// getExceptionSelectorRegister - If a physical register, this returns
722 /// the register that receives the exception typeid on entry to a landing
724 unsigned getExceptionSelectorRegister() const {
725 return ExceptionSelectorRegister;
728 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
729 /// set, the default is 200)
730 unsigned getJumpBufSize() const {
734 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
735 /// (if never set, the default is 0)
736 unsigned getJumpBufAlignment() const {
737 return JumpBufAlignment;
740 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
742 unsigned getMinStackArgumentAlignment() const {
743 return MinStackArgumentAlignment;
746 /// getPrefLoopAlignment - return the preferred loop alignment.
748 unsigned getPrefLoopAlignment() const {
749 return PrefLoopAlignment;
752 /// getShouldFoldAtomicFences - return whether the combiner should fold
753 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
755 bool getShouldFoldAtomicFences() const {
756 return ShouldFoldAtomicFences;
759 /// getPreIndexedAddressParts - returns true by value, base pointer and
760 /// offset pointer and addressing mode by reference if the node's address
761 /// can be legally represented as pre-indexed load / store address.
762 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
764 ISD::MemIndexedMode &AM,
765 SelectionDAG &DAG) const {
769 /// getPostIndexedAddressParts - returns true by value, base pointer and
770 /// offset pointer and addressing mode by reference if this node can be
771 /// combined with a load / store to form a post-indexed load / store.
772 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
773 SDValue &Base, SDValue &Offset,
774 ISD::MemIndexedMode &AM,
775 SelectionDAG &DAG) const {
779 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
780 /// current function. The returned value is a member of the
781 /// MachineJumpTableInfo::JTEntryKind enum.
782 virtual unsigned getJumpTableEncoding() const;
784 virtual const MCExpr *
785 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
786 const MachineBasicBlock *MBB, unsigned uid,
787 MCContext &Ctx) const {
788 assert(0 && "Need to implement this hook if target has custom JTIs");
792 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
794 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
795 SelectionDAG &DAG) const;
797 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
798 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
800 virtual const MCExpr *
801 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
802 unsigned JTI, MCContext &Ctx) const;
804 /// isOffsetFoldingLegal - Return true if folding a constant offset
805 /// with the given GlobalAddress is legal. It is frequently not legal in
806 /// PIC relocation models.
807 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
809 /// getFunctionAlignment - Return the Log2 alignment of this function.
810 virtual unsigned getFunctionAlignment(const Function *) const = 0;
812 /// getStackCookieLocation - Return true if the target stores stack
813 /// protector cookies at a fixed offset in some non-standard address
814 /// space, and populates the address space and offset as
816 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
820 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
821 /// used for loads / stores from the global.
822 virtual unsigned getMaximalGlobalOffset() const {
826 //===--------------------------------------------------------------------===//
827 // TargetLowering Optimization Methods
830 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
831 /// SDValues for returning information from TargetLowering to its clients
832 /// that want to combine
833 struct TargetLoweringOpt {
840 explicit TargetLoweringOpt(SelectionDAG &InDAG,
842 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
844 bool LegalTypes() const { return LegalTys; }
845 bool LegalOperations() const { return LegalOps; }
847 bool CombineTo(SDValue O, SDValue N) {
853 /// ShrinkDemandedConstant - Check to see if the specified operand of the
854 /// specified instruction is a constant integer. If so, check to see if
855 /// there are any bits set in the constant that are not demanded. If so,
856 /// shrink the constant and return true.
857 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
859 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
860 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
861 /// cast, but it could be generalized for targets with other types of
862 /// implicit widening casts.
863 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
867 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
868 /// DemandedMask bits of the result of Op are ever used downstream. If we can
869 /// use this information to simplify Op, create a new simplified DAG node and
870 /// return true, returning the original and new nodes in Old and New.
871 /// Otherwise, analyze the expression and return a mask of KnownOne and
872 /// KnownZero bits for the expression (used to simplify the caller).
873 /// The KnownZero/One bits may only be accurate for those bits in the
875 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
876 APInt &KnownZero, APInt &KnownOne,
877 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
879 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
880 /// Mask are known to be either zero or one and return them in the
881 /// KnownZero/KnownOne bitsets.
882 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
886 const SelectionDAG &DAG,
887 unsigned Depth = 0) const;
889 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
890 /// targets that want to expose additional information about sign bits to the
892 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
893 unsigned Depth = 0) const;
895 struct DAGCombinerInfo {
896 void *DC; // The DAG Combiner object.
898 bool BeforeLegalizeOps;
899 bool CalledByLegalizer;
903 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
904 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
905 CalledByLegalizer(cl), DAG(dag) {}
907 bool isBeforeLegalize() const { return BeforeLegalize; }
908 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
909 bool isCalledByLegalizer() const { return CalledByLegalizer; }
911 void AddToWorklist(SDNode *N);
912 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
914 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
915 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
917 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
920 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
921 /// and cc. If it is unable to simplify it, return a null SDValue.
922 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
923 ISD::CondCode Cond, bool foldBooleans,
924 DAGCombinerInfo &DCI, DebugLoc dl) const;
926 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
927 /// node is a GlobalAddress + offset.
929 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
931 /// PerformDAGCombine - This method will be invoked for all target nodes and
932 /// for any target-independent nodes that the target has registered with
935 /// The semantics are as follows:
937 /// SDValue.Val == 0 - No change was made
938 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
939 /// otherwise - N should be replaced by the returned Operand.
941 /// In addition, methods provided by DAGCombinerInfo may be used to perform
942 /// more complex transformations.
944 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
946 /// isTypeDesirableForOp - Return true if the target has native support for
947 /// the specified value type and it is 'desirable' to use the type for the
948 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
949 /// instruction encodings are longer and some i16 instructions are slow.
950 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
951 // By default, assume all legal types are desirable.
952 return isTypeLegal(VT);
955 /// IsDesirableToPromoteOp - This method query the target whether it is
956 /// beneficial for dag combiner to promote the specified node. If true, it
957 /// should return the desired promotion type by reference.
958 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
962 //===--------------------------------------------------------------------===//
963 // TargetLowering Configuration Methods - These methods should be invoked by
964 // the derived class constructor to configure this object for the target.
968 /// setShiftAmountType - Describe the type that should be used for shift
969 /// amounts. This type defaults to the pointer type.
970 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
972 /// setBooleanContents - Specify how the target extends the result of a
973 /// boolean value from i1 to a wider type. See getBooleanContents.
974 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
976 /// setSchedulingPreference - Specify the target scheduling preference.
977 void setSchedulingPreference(Sched::Preference Pref) {
978 SchedPreferenceInfo = Pref;
981 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
982 /// use _setjmp to implement llvm.setjmp or the non _ version.
983 /// Defaults to false.
984 void setUseUnderscoreSetJmp(bool Val) {
985 UseUnderscoreSetJmp = Val;
988 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
989 /// use _longjmp to implement llvm.longjmp or the non _ version.
990 /// Defaults to false.
991 void setUseUnderscoreLongJmp(bool Val) {
992 UseUnderscoreLongJmp = Val;
995 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
996 /// specifies the register that llvm.savestack/llvm.restorestack should save
998 void setStackPointerRegisterToSaveRestore(unsigned R) {
999 StackPointerRegisterToSaveRestore = R;
1002 /// setExceptionPointerRegister - If set to a physical register, this sets
1003 /// the register that receives the exception address on entry to a landing
1005 void setExceptionPointerRegister(unsigned R) {
1006 ExceptionPointerRegister = R;
1009 /// setExceptionSelectorRegister - If set to a physical register, this sets
1010 /// the register that receives the exception typeid on entry to a landing
1012 void setExceptionSelectorRegister(unsigned R) {
1013 ExceptionSelectorRegister = R;
1016 /// SelectIsExpensive - Tells the code generator not to expand operations
1017 /// into sequences that use the select operations if possible.
1018 void setSelectIsExpensive() { SelectIsExpensive = true; }
1020 /// setIntDivIsCheap - Tells the code generator that integer divide is
1021 /// expensive, and if possible, should be replaced by an alternate sequence
1022 /// of instructions not containing an integer divide.
1023 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1025 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1026 /// srl/add/sra for a signed divide by power of two, and let the target handle
1028 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1030 /// addRegisterClass - Add the specified register class as an available
1031 /// regclass for the specified value type. This indicates the selector can
1032 /// handle values of that class natively.
1033 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
1034 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1035 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1036 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1039 /// findRepresentativeClass - Return the largest legal super-reg register class
1040 /// of the register class for the specified type and its associated "cost".
1041 virtual std::pair<const TargetRegisterClass*, uint8_t>
1042 findRepresentativeClass(EVT VT) const;
1044 /// computeRegisterProperties - Once all of the register classes are added,
1045 /// this allows us to compute derived properties we expose.
1046 void computeRegisterProperties();
1048 /// setOperationAction - Indicate that the specified operation does not work
1049 /// with the specified type and indicate what to do about it.
1050 void setOperationAction(unsigned Op, MVT VT,
1051 LegalizeAction Action) {
1052 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1053 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1056 /// setLoadExtAction - Indicate that the specified load with extension does
1057 /// not work with the specified type and indicate what to do about it.
1058 void setLoadExtAction(unsigned ExtType, MVT VT,
1059 LegalizeAction Action) {
1060 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
1061 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1062 "Table isn't big enough!");
1063 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1066 /// setTruncStoreAction - Indicate that the specified truncating store does
1067 /// not work with the specified type and indicate what to do about it.
1068 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1069 LegalizeAction Action) {
1070 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1071 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1072 "Table isn't big enough!");
1073 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1076 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1077 /// does not work with the specified type and indicate what to do abort
1078 /// it. NOTE: All indexed mode loads are initialized to Expand in
1079 /// TargetLowering.cpp
1080 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1081 LegalizeAction Action) {
1082 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1083 IdxMode < ISD::LAST_INDEXED_MODE &&
1084 (unsigned)Action < 0xf &&
1085 "Table isn't big enough!");
1086 // Load action are kept in the upper half.
1087 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1088 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1091 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1092 /// does not work with the specified type and indicate what to do about
1093 /// it. NOTE: All indexed mode stores are initialized to Expand in
1094 /// TargetLowering.cpp
1095 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1096 LegalizeAction Action) {
1097 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1098 IdxMode < ISD::LAST_INDEXED_MODE &&
1099 (unsigned)Action < 0xf &&
1100 "Table isn't big enough!");
1101 // Store action are kept in the lower half.
1102 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1103 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1106 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1107 /// supported on the target and indicate what to do about it.
1108 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1109 LegalizeAction Action) {
1110 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1111 (unsigned)CC < array_lengthof(CondCodeActions) &&
1112 "Table isn't big enough!");
1113 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1114 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1117 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1118 /// promotion code defaults to trying a larger integer/fp until it can find
1119 /// one that works. If that default is insufficient, this method can be used
1120 /// by the target to override the default.
1121 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1122 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1125 /// setTargetDAGCombine - Targets should invoke this method for each target
1126 /// independent node that they want to provide a custom DAG combiner for by
1127 /// implementing the PerformDAGCombine virtual method.
1128 void setTargetDAGCombine(ISD::NodeType NT) {
1129 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1130 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1133 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1134 /// bytes); default is 200
1135 void setJumpBufSize(unsigned Size) {
1139 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1140 /// alignment (in bytes); default is 0
1141 void setJumpBufAlignment(unsigned Align) {
1142 JumpBufAlignment = Align;
1145 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1146 /// alignment is zero, it means the target does not care about loop alignment.
1147 void setPrefLoopAlignment(unsigned Align) {
1148 PrefLoopAlignment = Align;
1151 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1153 void setMinStackArgumentAlignment(unsigned Align) {
1154 MinStackArgumentAlignment = Align;
1157 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1158 /// atomic operation intrinsics includes locking. Default is false.
1159 void setShouldFoldAtomicFences(bool fold) {
1160 ShouldFoldAtomicFences = fold;
1164 //===--------------------------------------------------------------------===//
1165 // Lowering methods - These methods must be implemented by targets so that
1166 // the SelectionDAGLowering code knows how to lower these.
1169 /// LowerFormalArguments - This hook must be implemented to lower the
1170 /// incoming (formal) arguments, described by the Ins array, into the
1171 /// specified DAG. The implementation should fill in the InVals array
1172 /// with legal-type argument values, and return the resulting token
1176 LowerFormalArguments(SDValue Chain,
1177 CallingConv::ID CallConv, bool isVarArg,
1178 const SmallVectorImpl<ISD::InputArg> &Ins,
1179 DebugLoc dl, SelectionDAG &DAG,
1180 SmallVectorImpl<SDValue> &InVals) const {
1181 assert(0 && "Not Implemented");
1182 return SDValue(); // this is here to silence compiler errors
1185 /// LowerCallTo - This function lowers an abstract call to a function into an
1186 /// actual call. This returns a pair of operands. The first element is the
1187 /// return value for the function (if RetTy is not VoidTy). The second
1188 /// element is the outgoing token chain. It calls LowerCall to do the actual
1190 struct ArgListEntry {
1201 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1202 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1204 typedef std::vector<ArgListEntry> ArgListTy;
1205 std::pair<SDValue, SDValue>
1206 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1207 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1208 CallingConv::ID CallConv, bool isTailCall,
1209 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1210 SelectionDAG &DAG, DebugLoc dl) const;
1212 /// LowerCall - This hook must be implemented to lower calls into the
1213 /// the specified DAG. The outgoing arguments to the call are described
1214 /// by the Outs array, and the values to be returned by the call are
1215 /// described by the Ins array. The implementation should fill in the
1216 /// InVals array with legal-type return values from the call, and return
1217 /// the resulting token chain value.
1219 LowerCall(SDValue Chain, SDValue Callee,
1220 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1221 const SmallVectorImpl<ISD::OutputArg> &Outs,
1222 const SmallVectorImpl<SDValue> &OutVals,
1223 const SmallVectorImpl<ISD::InputArg> &Ins,
1224 DebugLoc dl, SelectionDAG &DAG,
1225 SmallVectorImpl<SDValue> &InVals) const {
1226 assert(0 && "Not Implemented");
1227 return SDValue(); // this is here to silence compiler errors
1230 /// CanLowerReturn - This hook should be implemented to check whether the
1231 /// return values described by the Outs array can fit into the return
1232 /// registers. If false is returned, an sret-demotion is performed.
1234 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1235 const SmallVectorImpl<ISD::OutputArg> &Outs,
1236 LLVMContext &Context) const
1238 // Return true by default to get preexisting behavior.
1242 /// LowerReturn - This hook must be implemented to lower outgoing
1243 /// return values, described by the Outs array, into the specified
1244 /// DAG. The implementation should return the resulting token chain
1248 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1249 const SmallVectorImpl<ISD::OutputArg> &Outs,
1250 const SmallVectorImpl<SDValue> &OutVals,
1251 DebugLoc dl, SelectionDAG &DAG) const {
1252 assert(0 && "Not Implemented");
1253 return SDValue(); // this is here to silence compiler errors
1256 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1257 /// to legalize nodes with an illegal operand type but legal result types.
1258 /// It replaces the LowerOperation callback in the type Legalizer.
1259 /// The reason we can not do away with LowerOperation entirely is that
1260 /// LegalizeDAG isn't yet ready to use this callback.
1261 /// TODO: Consider merging with ReplaceNodeResults.
1263 /// The target places new result values for the node in Results (their number
1264 /// and types must exactly match those of the original return values of
1265 /// the node), or leaves Results empty, which indicates that the node is not
1266 /// to be custom lowered after all.
1267 /// The default implementation calls LowerOperation.
1268 virtual void LowerOperationWrapper(SDNode *N,
1269 SmallVectorImpl<SDValue> &Results,
1270 SelectionDAG &DAG) const;
1272 /// LowerOperation - This callback is invoked for operations that are
1273 /// unsupported by the target, which are registered to use 'custom' lowering,
1274 /// and whose defined values are all legal.
1275 /// If the target has no operations that require custom lowering, it need not
1276 /// implement this. The default implementation of this aborts.
1277 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1279 /// ReplaceNodeResults - This callback is invoked when a node result type is
1280 /// illegal for the target, and the operation was registered to use 'custom'
1281 /// lowering for that result type. The target places new result values for
1282 /// the node in Results (their number and types must exactly match those of
1283 /// the original return values of the node), or leaves Results empty, which
1284 /// indicates that the node is not to be custom lowered after all.
1286 /// If the target has no operations that require custom lowering, it need not
1287 /// implement this. The default implementation aborts.
1288 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1289 SelectionDAG &DAG) const {
1290 assert(0 && "ReplaceNodeResults not implemented for this target!");
1293 /// getTargetNodeName() - This method returns the name of a target specific
1295 virtual const char *getTargetNodeName(unsigned Opcode) const;
1297 /// createFastISel - This method returns a target specific FastISel object,
1298 /// or null if the target does not support "fast" ISel.
1299 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1303 //===--------------------------------------------------------------------===//
1304 // Inline Asm Support hooks
1307 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1308 /// call to be explicit llvm code if it wants to. This is useful for
1309 /// turning simple inline asms into LLVM intrinsics, which gives the
1310 /// compiler more information about the behavior of the code.
1311 virtual bool ExpandInlineAsm(CallInst *CI) const {
1315 enum ConstraintType {
1316 C_Register, // Constraint represents specific register(s).
1317 C_RegisterClass, // Constraint represents any of register(s) in class.
1318 C_Memory, // Memory constraint.
1319 C_Other, // Something else.
1320 C_Unknown // Unsupported constraint.
1323 enum ConstraintWeight {
1325 CW_Invalid = -1, // No match.
1326 CW_Okay = 0, // Acceptable.
1327 CW_Good = 1, // Good weight.
1328 CW_Better = 2, // Better weight.
1329 CW_Best = 3, // Best weight.
1331 // Well-known weights.
1332 CW_SpecificReg = CW_Okay, // Specific register operands.
1333 CW_Register = CW_Good, // Register operands.
1334 CW_Memory = CW_Better, // Memory operands.
1335 CW_Constant = CW_Best, // Constant operand.
1336 CW_Default = CW_Okay // Default or don't know type.
1339 /// AsmOperandInfo - This contains information for each constraint that we are
1341 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1342 /// ConstraintCode - This contains the actual string for the code, like "m".
1343 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1344 /// most closely matches the operand.
1345 std::string ConstraintCode;
1347 /// ConstraintType - Information about the constraint code, e.g. Register,
1348 /// RegisterClass, Memory, Other, Unknown.
1349 TargetLowering::ConstraintType ConstraintType;
1351 /// CallOperandval - If this is the result output operand or a
1352 /// clobber, this is null, otherwise it is the incoming operand to the
1353 /// CallInst. This gets modified as the asm is processed.
1354 Value *CallOperandVal;
1356 /// ConstraintVT - The ValueType for the operand value.
1359 /// isMatchingInputConstraint - Return true of this is an input operand that
1360 /// is a matching constraint like "4".
1361 bool isMatchingInputConstraint() const;
1363 /// getMatchedOperand - If this is an input matching constraint, this method
1364 /// returns the output operand it matches.
1365 unsigned getMatchedOperand() const;
1367 /// Copy constructor for copying from an AsmOperandInfo.
1368 AsmOperandInfo(const AsmOperandInfo &info)
1369 : InlineAsm::ConstraintInfo(info),
1370 ConstraintCode(info.ConstraintCode),
1371 ConstraintType(info.ConstraintType),
1372 CallOperandVal(info.CallOperandVal),
1373 ConstraintVT(info.ConstraintVT) {
1376 /// Copy constructor for copying from a ConstraintInfo.
1377 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1378 : InlineAsm::ConstraintInfo(info),
1379 ConstraintType(TargetLowering::C_Unknown),
1380 CallOperandVal(0), ConstraintVT(MVT::Other) {
1384 typedef SmallVector<AsmOperandInfo,16> AsmOperandInfoVector;
1386 /// ParseConstraints - Split up the constraint string from the inline
1387 /// assembly value into the specific constraints and their prefixes,
1388 /// and also tie in the associated operand values.
1389 /// If this returns an empty vector, and if the constraint string itself
1390 /// isn't empty, there was an error parsing.
1391 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
1393 /// Examine constraint type and operand type and determine a weight value.
1394 /// The operand object must already have been set up with the operand type.
1395 virtual ConstraintWeight getMultipleConstraintMatchWeight(
1396 AsmOperandInfo &info, int maIndex) const;
1398 /// Examine constraint string and operand type and determine a weight value.
1399 /// The operand object must already have been set up with the operand type.
1400 virtual ConstraintWeight getSingleConstraintMatchWeight(
1401 AsmOperandInfo &info, const char *constraint) const;
1403 /// ComputeConstraintToUse - Determines the constraint code and constraint
1404 /// type to use for the specific AsmOperandInfo, setting
1405 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1406 /// being passed in is available, it can be passed in as Op, otherwise an
1407 /// empty SDValue can be passed.
1408 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1410 SelectionDAG *DAG = 0) const;
1412 /// getConstraintType - Given a constraint, return the type of constraint it
1413 /// is for this target.
1414 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1416 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1417 /// return a list of registers that can be used to satisfy the constraint.
1418 /// This should only be used for C_RegisterClass constraints.
1419 virtual std::vector<unsigned>
1420 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1423 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1424 /// {edx}), return the register number and the register class for the
1427 /// Given a register class constraint, like 'r', if this corresponds directly
1428 /// to an LLVM register class, return a register of 0 and the register class
1431 /// This should only be used for C_Register constraints. On error,
1432 /// this returns a register number of 0 and a null register class pointer..
1433 virtual std::pair<unsigned, const TargetRegisterClass*>
1434 getRegForInlineAsmConstraint(const std::string &Constraint,
1437 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1438 /// with another that has more specific requirements based on the type of the
1439 /// corresponding operand. This returns null if there is no replacement to
1441 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1443 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1444 /// vector. If it is invalid, don't add anything to Ops.
1445 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1446 std::vector<SDValue> &Ops,
1447 SelectionDAG &DAG) const;
1449 //===--------------------------------------------------------------------===//
1450 // Instruction Emitting Hooks
1453 // EmitInstrWithCustomInserter - This method should be implemented by targets
1454 // that mark instructions with the 'usesCustomInserter' flag. These
1455 // instructions are special in various ways, which require special support to
1456 // insert. The specified MachineInstr is created but not inserted into any
1457 // basic blocks, and this method is called to expand it into a sequence of
1458 // instructions, potentially also creating new basic blocks and control flow.
1459 virtual MachineBasicBlock *
1460 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1462 //===--------------------------------------------------------------------===//
1463 // Addressing mode description hooks (used by LSR etc).
1466 /// AddrMode - This represents an addressing mode of:
1467 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1468 /// If BaseGV is null, there is no BaseGV.
1469 /// If BaseOffs is zero, there is no base offset.
1470 /// If HasBaseReg is false, there is no base register.
1471 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1475 GlobalValue *BaseGV;
1479 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1482 /// isLegalAddressingMode - Return true if the addressing mode represented by
1483 /// AM is legal for this target, for a load/store of the specified type.
1484 /// The type may be VoidTy, in which case only return true if the addressing
1485 /// mode is legal for a load/store of any legal type.
1486 /// TODO: Handle pre/postinc as well.
1487 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1489 /// isTruncateFree - Return true if it's free to truncate a value of
1490 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1491 /// register EAX to i16 by referencing its sub-register AX.
1492 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1496 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1500 /// isZExtFree - Return true if any actual instruction that defines a
1501 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1502 /// register. This does not necessarily include registers defined in
1503 /// unknown ways, such as incoming arguments, or copies from unknown
1504 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1505 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1506 /// all instructions that define 32-bit values implicit zero-extend the
1507 /// result out to 64 bits.
1508 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1512 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1516 /// isNarrowingProfitable - Return true if it's profitable to narrow
1517 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1518 /// from i32 to i8 but not from i32 to i16.
1519 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1523 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1524 /// icmp immediate, that is the target has icmp instructions which can compare
1525 /// a register against the immediate without having to materialize the
1526 /// immediate into a register.
1527 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1531 //===--------------------------------------------------------------------===//
1532 // Div utility functions
1534 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1535 std::vector<SDNode*>* Created) const;
1536 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1537 std::vector<SDNode*>* Created) const;
1540 //===--------------------------------------------------------------------===//
1541 // Runtime Library hooks
1544 /// setLibcallName - Rename the default libcall routine name for the specified
1546 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1547 LibcallRoutineNames[Call] = Name;
1550 /// getLibcallName - Get the libcall routine name for the specified libcall.
1552 const char *getLibcallName(RTLIB::Libcall Call) const {
1553 return LibcallRoutineNames[Call];
1556 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1557 /// result of the comparison libcall against zero.
1558 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1559 CmpLibcallCCs[Call] = CC;
1562 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1563 /// the comparison libcall against zero.
1564 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1565 return CmpLibcallCCs[Call];
1568 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1569 /// specified libcall.
1570 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1571 LibcallCallingConvs[Call] = CC;
1574 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1575 /// specified libcall.
1576 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1577 return LibcallCallingConvs[Call];
1581 const TargetMachine &TM;
1582 const TargetData *TD;
1583 const TargetLoweringObjectFile &TLOF;
1585 /// PointerTy - The type to use for pointers, usually i32 or i64.
1589 /// IsLittleEndian - True if this is a little endian target.
1591 bool IsLittleEndian;
1593 /// SelectIsExpensive - Tells the code generator not to expand operations
1594 /// into sequences that use the select operations if possible.
1595 bool SelectIsExpensive;
1597 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1598 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1599 /// a real cost model is in place. If we ever optimize for size, this will be
1600 /// set to true unconditionally.
1603 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1604 /// srl/add/sra for a signed divide by power of two, and let the target handle
1606 bool Pow2DivIsCheap;
1608 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1609 /// llvm.setjmp. Defaults to false.
1610 bool UseUnderscoreSetJmp;
1612 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1613 /// llvm.longjmp. Defaults to false.
1614 bool UseUnderscoreLongJmp;
1616 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1620 /// BooleanContents - Information about the contents of the high-bits in
1621 /// boolean values held in a type wider than i1. See getBooleanContents.
1622 BooleanContent BooleanContents;
1624 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1625 /// total cycles or lowest register usage.
1626 Sched::Preference SchedPreferenceInfo;
1628 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1629 unsigned JumpBufSize;
1631 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1633 unsigned JumpBufAlignment;
1635 /// MinStackArgumentAlignment - The minimum alignment that any argument
1636 /// on the stack needs to have.
1638 unsigned MinStackArgumentAlignment;
1640 /// PrefLoopAlignment - The perferred loop alignment.
1642 unsigned PrefLoopAlignment;
1644 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1645 /// be folded into the enclosed atomic intrinsic instruction by the
1647 bool ShouldFoldAtomicFences;
1649 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1650 /// specifies the register that llvm.savestack/llvm.restorestack should save
1652 unsigned StackPointerRegisterToSaveRestore;
1654 /// ExceptionPointerRegister - If set to a physical register, this specifies
1655 /// the register that receives the exception address on entry to a landing
1657 unsigned ExceptionPointerRegister;
1659 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1660 /// the register that receives the exception typeid on entry to a landing
1662 unsigned ExceptionSelectorRegister;
1664 /// RegClassForVT - This indicates the default register class to use for
1665 /// each ValueType the target supports natively.
1666 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1667 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1668 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1670 /// RepRegClassForVT - This indicates the "representative" register class to
1671 /// use for each ValueType the target supports natively. This information is
1672 /// used by the scheduler to track register pressure. By default, the
1673 /// representative register class is the largest legal super-reg register
1674 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1675 /// and i32's representative class would be GR32.
1676 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1678 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1679 /// register class for each ValueType. The cost is used by the scheduler to
1680 /// approximate register pressure.
1681 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1683 /// TransformToType - For any value types we are promoting or expanding, this
1684 /// contains the value type that we are changing to. For Expanded types, this
1685 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1686 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1687 /// by the system, this holds the same type (e.g. i32 -> i32).
1688 EVT TransformToType[MVT::LAST_VALUETYPE];
1690 /// OpActions - For each operation and each value type, keep a LegalizeAction
1691 /// that indicates how instruction selection should deal with the operation.
1692 /// Most operations are Legal (aka, supported natively by the target), but
1693 /// operations that are not should be described. Note that operations on
1694 /// non-legal value types are not described here.
1695 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1697 /// LoadExtActions - For each load extension type and each value type,
1698 /// keep a LegalizeAction that indicates how instruction selection should deal
1699 /// with a load of a specific value type and extension type.
1700 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1702 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1703 /// indicates whether a truncating store of a specific value type and
1704 /// truncating type is legal.
1705 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1707 /// IndexedModeActions - For each indexed mode and each value type,
1708 /// keep a pair of LegalizeAction that indicates how instruction
1709 /// selection should deal with the load / store. The first dimension is the
1710 /// value_type for the reference. The second dimension represents the various
1711 /// modes for load store.
1712 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1714 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1715 /// LegalizeAction that indicates how instruction selection should
1716 /// deal with the condition code.
1717 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1719 ValueTypeActionImpl ValueTypeActions;
1721 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1723 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1724 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1725 /// which sets a bit in this array.
1727 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1729 /// PromoteToType - For operations that must be promoted to a specific type,
1730 /// this holds the destination type. This map should be sparse, so don't hold
1733 /// Targets add entries to this map with AddPromotedToType(..), clients access
1734 /// this with getTypeToPromoteTo(..).
1735 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1738 /// LibcallRoutineNames - Stores the name each libcall.
1740 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1742 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1743 /// of each of the comparison libcall against zero.
1744 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1746 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1748 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1751 /// When lowering \@llvm.memset this field specifies the maximum number of
1752 /// store operations that may be substituted for the call to memset. Targets
1753 /// must set this value based on the cost threshold for that target. Targets
1754 /// should assume that the memset will be done using as many of the largest
1755 /// store operations first, followed by smaller ones, if necessary, per
1756 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1757 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1758 /// store. This only applies to setting a constant array of a constant size.
1759 /// @brief Specify maximum number of store instructions per memset call.
1760 unsigned maxStoresPerMemset;
1762 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1763 /// store operations that may be substituted for a call to memcpy. Targets
1764 /// must set this value based on the cost threshold for that target. Targets
1765 /// should assume that the memcpy will be done using as many of the largest
1766 /// store operations first, followed by smaller ones, if necessary, per
1767 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1768 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1769 /// and one 1-byte store. This only applies to copying a constant array of
1771 /// @brief Specify maximum bytes of store instructions per memcpy call.
1772 unsigned maxStoresPerMemcpy;
1774 /// When lowering \@llvm.memmove this field specifies the maximum number of
1775 /// store instructions that may be substituted for a call to memmove. Targets
1776 /// must set this value based on the cost threshold for that target. Targets
1777 /// should assume that the memmove will be done using as many of the largest
1778 /// store operations first, followed by smaller ones, if necessary, per
1779 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1780 /// with 8-bit alignment would result in nine 1-byte stores. This only
1781 /// applies to copying a constant array of constant size.
1782 /// @brief Specify maximum bytes of store instructions per memmove call.
1783 unsigned maxStoresPerMemmove;
1785 /// This field specifies whether the target can benefit from code placement
1787 bool benefitFromCodePlacementOpt;
1790 /// isLegalRC - Return true if the value types that can be represented by the
1791 /// specified register class are all legal.
1792 bool isLegalRC(const TargetRegisterClass *RC) const;
1794 /// hasLegalSuperRegRegClasses - Return true if the specified register class
1795 /// has one or more super-reg register classes that are legal.
1796 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
1799 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1800 /// compute the return value EVTs and flags, and optionally also
1801 /// the offsets, if the return value is being lowered to memory.
1802 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1803 SmallVectorImpl<ISD::OutputArg> &Outs,
1804 const TargetLowering &TLI,
1805 SmallVectorImpl<uint64_t> *Offsets = 0);
1807 } // end llvm namespace