1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Constants.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/ADT/APFloat.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/STLExtras.h"
41 class MachineBasicBlock;
42 class MachineFunction;
43 class MachineFrameInfo;
45 class MachineModuleInfo;
51 class TargetRegisterClass;
52 class TargetSubtarget;
56 //===----------------------------------------------------------------------===//
57 /// TargetLowering - This class defines information used to lower LLVM code to
58 /// legal SelectionDAG operators that the target instruction selector can accept
61 /// This class also defines callbacks that targets must implement to lower
62 /// target-specific constructs to SelectionDAG operators.
64 class TargetLowering {
66 /// LegalizeAction - This enum indicates whether operations are valid for a
67 /// target, and if not, what action should be used to make them valid.
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand, // Try to expand this to other ops, otherwise use a libcall.
72 Custom // Use the LowerOperation hook to implement custom lowering.
75 enum OutOfRangeShiftAmount {
76 Undefined, // Oversized shift amounts are undefined (default).
77 Mask, // Shift amounts are auto masked (anded) to value size.
78 Extend // Oversized shift pulls in zeros or sign bits.
81 enum BooleanContent { // How the target represents true/false values.
82 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
83 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
84 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
87 enum SchedPreference {
88 SchedulingForLatency, // Scheduling for shortest total latency.
89 SchedulingForRegPressure // Scheduling for lowest register pressure.
92 explicit TargetLowering(TargetMachine &TM);
93 virtual ~TargetLowering();
95 TargetMachine &getTargetMachine() const { return TM; }
96 const TargetData *getTargetData() const { return TD; }
98 bool isBigEndian() const { return !IsLittleEndian; }
99 bool isLittleEndian() const { return IsLittleEndian; }
100 MVT getPointerTy() const { return PointerTy; }
101 MVT getShiftAmountTy() const { return ShiftAmountTy; }
102 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
104 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
106 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
108 /// isSelectExpensive - Return true if the select operation is expensive for
110 bool isSelectExpensive() const { return SelectIsExpensive; }
112 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
113 /// a sequence of several shifts, adds, and multiplies for this target.
114 bool isIntDivCheap() const { return IntDivIsCheap; }
116 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
118 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
120 /// getSetCCResultType - Return the ValueType of the result of setcc
122 virtual MVT getSetCCResultType(MVT VT) const;
124 /// getBooleanContents - For targets without i1 registers, this gives the
125 /// nature of the high-bits of boolean values held in types wider than i1.
126 /// "Boolean values" are special true/false values produced by nodes like
127 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
128 /// Not to be confused with general values promoted from i1.
129 BooleanContent getBooleanContents() const { return BooleanContents;}
131 /// getSchedulingPreference - Return target scheduling preference.
132 SchedPreference getSchedulingPreference() const {
133 return SchedPreferenceInfo;
136 /// getRegClassFor - Return the register class that should be used for the
137 /// specified value type. This may only be called on legal types.
138 TargetRegisterClass *getRegClassFor(MVT VT) const {
139 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
140 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
141 assert(RC && "This value type is not natively supported!");
145 /// isTypeLegal - Return true if the target has native support for the
146 /// specified value type. This means that it has a register that directly
147 /// holds it without promotions or expansions.
148 bool isTypeLegal(MVT VT) const {
149 assert(!VT.isSimple() ||
150 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
151 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
154 class ValueTypeActionImpl {
155 /// ValueTypeActions - This is a bitvector that contains two bits for each
156 /// value type, where the two bits correspond to the LegalizeAction enum.
157 /// This can be queried with "getTypeAction(VT)".
158 uint32_t ValueTypeActions[2];
160 ValueTypeActionImpl() {
161 ValueTypeActions[0] = ValueTypeActions[1] = 0;
163 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
164 ValueTypeActions[0] = RHS.ValueTypeActions[0];
165 ValueTypeActions[1] = RHS.ValueTypeActions[1];
168 LegalizeAction getTypeAction(MVT VT) const {
169 if (VT.isExtended()) {
171 return VT.isPow2VectorType() ? Expand : Promote;
174 // First promote to a power-of-two size, then expand if necessary.
175 return VT == VT.getRoundIntegerType() ? Expand : Promote;
176 assert(0 && "Unsupported extended type!");
179 unsigned I = VT.getSimpleVT();
180 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
181 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
183 void setTypeAction(MVT VT, LegalizeAction Action) {
184 unsigned I = VT.getSimpleVT();
185 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
186 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
190 const ValueTypeActionImpl &getValueTypeActions() const {
191 return ValueTypeActions;
194 /// getTypeAction - Return how we should legalize values of this type, either
195 /// it is already legal (return 'Legal') or we need to promote it to a larger
196 /// type (return 'Promote'), or we need to expand it into multiple registers
197 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
198 LegalizeAction getTypeAction(MVT VT) const {
199 return ValueTypeActions.getTypeAction(VT);
202 /// getTypeToTransformTo - For types supported by the target, this is an
203 /// identity function. For types that must be promoted to larger types, this
204 /// returns the larger type to promote to. For integer types that are larger
205 /// than the largest integer register, this contains one step in the expansion
206 /// to get to the smaller register. For illegal floating point types, this
207 /// returns the integer type to transform to.
208 MVT getTypeToTransformTo(MVT VT) const {
210 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
211 MVT NVT = TransformToType[VT.getSimpleVT()];
212 assert(getTypeAction(NVT) != Promote &&
213 "Promote may not follow Expand or Promote");
218 MVT NVT = VT.getPow2VectorType();
220 // Vector length is a power of 2 - split to half the size.
221 unsigned NumElts = VT.getVectorNumElements();
222 MVT EltVT = VT.getVectorElementType();
223 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
225 // Promote to a power of two size, avoiding multi-step promotion.
226 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
227 } else if (VT.isInteger()) {
228 MVT NVT = VT.getRoundIntegerType();
230 // Size is a power of two - expand to half the size.
231 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
233 // Promote to a power of two size, avoiding multi-step promotion.
234 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
236 assert(0 && "Unsupported extended type!");
237 return MVT(); // Not reached
240 /// getTypeToExpandTo - For types supported by the target, this is an
241 /// identity function. For types that must be expanded (i.e. integer types
242 /// that are larger than the largest integer register or illegal floating
243 /// point types), this returns the largest legal type it will be expanded to.
244 MVT getTypeToExpandTo(MVT VT) const {
245 assert(!VT.isVector());
247 switch (getTypeAction(VT)) {
251 VT = getTypeToTransformTo(VT);
254 assert(false && "Type is not legal nor is it to be expanded!");
261 /// getVectorTypeBreakdown - Vector types are broken down into some number of
262 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
263 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
264 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
266 /// This method returns the number of registers needed, and the VT for each
267 /// register. It also returns the VT and quantity of the intermediate values
268 /// before they are promoted/expanded.
270 unsigned getVectorTypeBreakdown(MVT VT,
272 unsigned &NumIntermediates,
273 MVT &RegisterVT) const;
275 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
276 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
277 /// this is the case, it returns true and store the intrinsic
278 /// information into the IntrinsicInfo that was passed to the function.
279 typedef struct IntrinsicInfo {
280 unsigned opc; // target opcode
281 MVT memVT; // memory VT
282 const Value* ptrVal; // value representing memory location
283 int offset; // offset off of ptrVal
284 unsigned align; // alignment
285 bool vol; // is volatile?
286 bool readMem; // reads memory?
287 bool writeMem; // writes memory?
290 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
291 CallInst &I, unsigned Intrinsic) {
295 /// getWidenVectorType: given a vector type, returns the type to widen to
296 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
297 /// If there is no vector type that we want to widen to, returns MVT::Other
298 /// When and were to widen is target dependent based on the cost of
299 /// scalarizing vs using the wider vector type.
300 virtual MVT getWidenVectorType(MVT VT);
302 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
303 legal_fpimm_iterator legal_fpimm_begin() const {
304 return LegalFPImmediates.begin();
306 legal_fpimm_iterator legal_fpimm_end() const {
307 return LegalFPImmediates.end();
310 /// isShuffleMaskLegal - Targets can use this to indicate that they only
311 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
312 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
313 /// are assumed to be legal.
314 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
318 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
319 /// used by Targets can use this to indicate if there is a suitable
320 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
322 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
324 SelectionDAG &DAG) const {
328 /// getOperationAction - Return how this operation should be treated: either
329 /// it is legal, needs to be promoted to a larger size, needs to be
330 /// expanded to some other code sequence, or the target has a custom expander
332 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
333 if (VT.isExtended()) return Expand;
334 assert(Op < array_lengthof(OpActions) &&
335 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
336 "Table isn't big enough!");
337 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
340 /// isOperationLegal - Return true if the specified operation is legal on this
342 bool isOperationLegal(unsigned Op, MVT VT) const {
343 return (VT == MVT::Other || isTypeLegal(VT)) &&
344 (getOperationAction(Op, VT) == Legal ||
345 getOperationAction(Op, VT) == Custom);
348 /// getLoadExtAction - Return how this load with extension should be treated:
349 /// either it is legal, needs to be promoted to a larger size, needs to be
350 /// expanded to some other code sequence, or the target has a custom expander
352 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
353 assert(LType < array_lengthof(LoadExtActions) &&
354 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
355 "Table isn't big enough!");
356 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
359 /// isLoadExtLegal - Return true if the specified load with extension is legal
361 bool isLoadExtLegal(unsigned LType, MVT VT) const {
362 return VT.isSimple() &&
363 (getLoadExtAction(LType, VT) == Legal ||
364 getLoadExtAction(LType, VT) == Custom);
367 /// getTruncStoreAction - Return how this store with truncation should be
368 /// treated: either it is legal, needs to be promoted to a larger size, needs
369 /// to be expanded to some other code sequence, or the target has a custom
371 LegalizeAction getTruncStoreAction(MVT ValVT,
373 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
374 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
375 "Table isn't big enough!");
376 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
377 (2*MemVT.getSimpleVT())) & 3);
380 /// isTruncStoreLegal - Return true if the specified store with truncation is
381 /// legal on this target.
382 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
383 return isTypeLegal(ValVT) && MemVT.isSimple() &&
384 (getTruncStoreAction(ValVT, MemVT) == Legal ||
385 getTruncStoreAction(ValVT, MemVT) == Custom);
388 /// getIndexedLoadAction - Return how the indexed load should be treated:
389 /// either it is legal, needs to be promoted to a larger size, needs to be
390 /// expanded to some other code sequence, or the target has a custom expander
393 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
394 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
395 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
396 "Table isn't big enough!");
397 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
398 (2*VT.getSimpleVT())) & 3);
401 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
403 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
404 return VT.isSimple() &&
405 (getIndexedLoadAction(IdxMode, VT) == Legal ||
406 getIndexedLoadAction(IdxMode, VT) == Custom);
409 /// getIndexedStoreAction - Return how the indexed store should be treated:
410 /// either it is legal, needs to be promoted to a larger size, needs to be
411 /// expanded to some other code sequence, or the target has a custom expander
414 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
415 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
416 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
417 "Table isn't big enough!");
418 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
419 (2*VT.getSimpleVT())) & 3);
422 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
424 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
425 return VT.isSimple() &&
426 (getIndexedStoreAction(IdxMode, VT) == Legal ||
427 getIndexedStoreAction(IdxMode, VT) == Custom);
430 /// getConvertAction - Return how the conversion should be treated:
431 /// either it is legal, needs to be promoted to a larger size, needs to be
432 /// expanded to some other code sequence, or the target has a custom expander
435 getConvertAction(MVT FromVT, MVT ToVT) const {
436 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
437 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
438 "Table isn't big enough!");
439 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
440 (2*ToVT.getSimpleVT())) & 3);
443 /// isConvertLegal - Return true if the specified conversion is legal
445 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
446 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
447 (getConvertAction(FromVT, ToVT) == Legal ||
448 getConvertAction(FromVT, ToVT) == Custom);
451 /// getCondCodeAction - Return how the condition code should be treated:
452 /// either it is legal, needs to be expanded to some other code sequence,
453 /// or the target has a custom expander for it.
455 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
456 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
457 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
458 "Table isn't big enough!");
459 LegalizeAction Action = (LegalizeAction)
460 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
461 assert(Action != Promote && "Can't promote condition code!");
465 /// isCondCodeLegal - Return true if the specified condition code is legal
467 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
468 return getCondCodeAction(CC, VT) == Legal ||
469 getCondCodeAction(CC, VT) == Custom;
473 /// getTypeToPromoteTo - If the action for this operation is to promote, this
474 /// method returns the ValueType to promote to.
475 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
476 assert(getOperationAction(Op, VT) == Promote &&
477 "This operation isn't promoted!");
479 // See if this has an explicit type specified.
480 std::map<std::pair<unsigned, MVT::SimpleValueType>,
481 MVT::SimpleValueType>::const_iterator PTTI =
482 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
483 if (PTTI != PromoteToType.end()) return PTTI->second;
485 assert((VT.isInteger() || VT.isFloatingPoint()) &&
486 "Cannot autopromote this type, add it with AddPromotedToType.");
490 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
491 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
492 "Didn't find type to promote to!");
493 } while (!isTypeLegal(NVT) ||
494 getOperationAction(Op, NVT) == Promote);
498 /// getValueType - Return the MVT corresponding to this LLVM type.
499 /// This is fixed by the LLVM operations except for the pointer size. If
500 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
501 /// counterpart (e.g. structs), otherwise it will assert.
502 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
503 MVT VT = MVT::getMVT(Ty, AllowUnknown);
504 return VT == MVT::iPTR ? PointerTy : VT;
507 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
508 /// function arguments in the caller parameter area. This is the actual
509 /// alignment, not its logarithm.
510 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
512 /// getRegisterType - Return the type of registers that this ValueType will
513 /// eventually require.
514 MVT getRegisterType(MVT VT) const {
516 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
517 return RegisterTypeForVT[VT.getSimpleVT()];
521 unsigned NumIntermediates;
522 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
525 if (VT.isInteger()) {
526 return getRegisterType(getTypeToTransformTo(VT));
528 assert(0 && "Unsupported extended type!");
529 return MVT(); // Not reached
532 /// getNumRegisters - Return the number of registers that this ValueType will
533 /// eventually require. This is one for any types promoted to live in larger
534 /// registers, but may be more than one for types (like i64) that are split
535 /// into pieces. For types like i140, which are first promoted then expanded,
536 /// it is the number of registers needed to hold all the bits of the original
537 /// type. For an i140 on a 32 bit machine this means 5 registers.
538 unsigned getNumRegisters(MVT VT) const {
540 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
541 return NumRegistersForVT[VT.getSimpleVT()];
545 unsigned NumIntermediates;
546 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
548 if (VT.isInteger()) {
549 unsigned BitWidth = VT.getSizeInBits();
550 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
551 return (BitWidth + RegWidth - 1) / RegWidth;
553 assert(0 && "Unsupported extended type!");
554 return 0; // Not reached
557 /// ShouldShrinkFPConstant - If true, then instruction selection should
558 /// seek to shrink the FP constant of the specified type to a smaller type
559 /// in order to save space and / or reduce runtime.
560 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
562 /// hasTargetDAGCombine - If true, the target has custom DAG combine
563 /// transformations that it can perform for the specified node.
564 bool hasTargetDAGCombine(ISD::NodeType NT) const {
565 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
566 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
569 /// This function returns the maximum number of store operations permitted
570 /// to replace a call to llvm.memset. The value is set by the target at the
571 /// performance threshold for such a replacement.
572 /// @brief Get maximum # of store operations permitted for llvm.memset
573 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
575 /// This function returns the maximum number of store operations permitted
576 /// to replace a call to llvm.memcpy. The value is set by the target at the
577 /// performance threshold for such a replacement.
578 /// @brief Get maximum # of store operations permitted for llvm.memcpy
579 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
581 /// This function returns the maximum number of store operations permitted
582 /// to replace a call to llvm.memmove. The value is set by the target at the
583 /// performance threshold for such a replacement.
584 /// @brief Get maximum # of store operations permitted for llvm.memmove
585 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
587 /// This function returns true if the target allows unaligned memory accesses.
588 /// This is used, for example, in situations where an array copy/move/set is
589 /// converted to a sequence of store operations. It's use helps to ensure that
590 /// such replacements don't generate code that causes an alignment error
591 /// (trap) on the target machine.
592 /// @brief Determine if the target supports unaligned memory accesses.
593 bool allowsUnalignedMemoryAccesses() const {
594 return allowUnalignedMemoryAccesses;
597 /// getOptimalMemOpType - Returns the target specific optimal type for load
598 /// and store operations as a result of memset, memcpy, and memmove lowering.
599 /// It returns MVT::iAny if SelectionDAG should be responsible for
601 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
602 bool isSrcConst, bool isSrcStr) const {
606 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
607 /// to implement llvm.setjmp.
608 bool usesUnderscoreSetJmp() const {
609 return UseUnderscoreSetJmp;
612 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
613 /// to implement llvm.longjmp.
614 bool usesUnderscoreLongJmp() const {
615 return UseUnderscoreLongJmp;
618 /// getStackPointerRegisterToSaveRestore - If a physical register, this
619 /// specifies the register that llvm.savestack/llvm.restorestack should save
621 unsigned getStackPointerRegisterToSaveRestore() const {
622 return StackPointerRegisterToSaveRestore;
625 /// getExceptionAddressRegister - If a physical register, this returns
626 /// the register that receives the exception address on entry to a landing
628 unsigned getExceptionAddressRegister() const {
629 return ExceptionPointerRegister;
632 /// getExceptionSelectorRegister - If a physical register, this returns
633 /// the register that receives the exception typeid on entry to a landing
635 unsigned getExceptionSelectorRegister() const {
636 return ExceptionSelectorRegister;
639 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
640 /// set, the default is 200)
641 unsigned getJumpBufSize() const {
645 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
646 /// (if never set, the default is 0)
647 unsigned getJumpBufAlignment() const {
648 return JumpBufAlignment;
651 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
652 /// limit. Any block whose size is greater should not be predicated.
653 unsigned getIfCvtBlockSizeLimit() const {
654 return IfCvtBlockSizeLimit;
657 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
658 /// block to be considered for duplication. Any block whose size is greater
659 /// should not be duplicated to facilitate its predication.
660 unsigned getIfCvtDupBlockSizeLimit() const {
661 return IfCvtDupBlockSizeLimit;
664 /// getPrefLoopAlignment - return the preferred loop alignment.
666 unsigned getPrefLoopAlignment() const {
667 return PrefLoopAlignment;
670 /// getPreIndexedAddressParts - returns true by value, base pointer and
671 /// offset pointer and addressing mode by reference if the node's address
672 /// can be legally represented as pre-indexed load / store address.
673 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
675 ISD::MemIndexedMode &AM,
680 /// getPostIndexedAddressParts - returns true by value, base pointer and
681 /// offset pointer and addressing mode by reference if this node can be
682 /// combined with a load / store to form a post-indexed load / store.
683 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
684 SDValue &Base, SDValue &Offset,
685 ISD::MemIndexedMode &AM,
690 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
692 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
693 SelectionDAG &DAG) const;
695 /// isOffsetFoldingLegal - Return true if folding a constant offset
696 /// with the given GlobalAddress is legal. It is frequently not legal in
697 /// PIC relocation models.
698 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
700 //===--------------------------------------------------------------------===//
701 // TargetLowering Optimization Methods
704 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
705 /// SDValues for returning information from TargetLowering to its clients
706 /// that want to combine
707 struct TargetLoweringOpt {
712 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
714 bool CombineTo(SDValue O, SDValue N) {
720 /// ShrinkDemandedConstant - Check to see if the specified operand of the
721 /// specified instruction is a constant integer. If so, check to see if
722 /// there are any bits set in the constant that are not demanded. If so,
723 /// shrink the constant and return true.
724 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
727 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
728 /// DemandedMask bits of the result of Op are ever used downstream. If we can
729 /// use this information to simplify Op, create a new simplified DAG node and
730 /// return true, returning the original and new nodes in Old and New.
731 /// Otherwise, analyze the expression and return a mask of KnownOne and
732 /// KnownZero bits for the expression (used to simplify the caller).
733 /// The KnownZero/One bits may only be accurate for those bits in the
735 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
736 APInt &KnownZero, APInt &KnownOne,
737 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
739 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
740 /// Mask are known to be either zero or one and return them in the
741 /// KnownZero/KnownOne bitsets.
742 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
746 const SelectionDAG &DAG,
747 unsigned Depth = 0) const;
749 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
750 /// targets that want to expose additional information about sign bits to the
752 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
753 unsigned Depth = 0) const;
755 struct DAGCombinerInfo {
756 void *DC; // The DAG Combiner object.
758 bool CalledByLegalizer;
762 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
763 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
765 bool isBeforeLegalize() const { return BeforeLegalize; }
766 bool isCalledByLegalizer() const { return CalledByLegalizer; }
768 void AddToWorklist(SDNode *N);
769 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
770 SDValue CombineTo(SDNode *N, SDValue Res);
771 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
774 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
775 /// and cc. If it is unable to simplify it, return a null SDValue.
776 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
777 ISD::CondCode Cond, bool foldBooleans,
778 DAGCombinerInfo &DCI) const;
780 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
781 /// node is a GlobalAddress + offset.
783 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
785 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
786 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
787 /// location that the 'Base' load is loading from.
788 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
789 const MachineFrameInfo *MFI) const;
791 /// PerformDAGCombine - This method will be invoked for all target nodes and
792 /// for any target-independent nodes that the target has registered with
795 /// The semantics are as follows:
797 /// SDValue.Val == 0 - No change was made
798 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
799 /// otherwise - N should be replaced by the returned Operand.
801 /// In addition, methods provided by DAGCombinerInfo may be used to perform
802 /// more complex transformations.
804 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
806 //===--------------------------------------------------------------------===//
807 // TargetLowering Configuration Methods - These methods should be invoked by
808 // the derived class constructor to configure this object for the target.
812 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
813 /// GOT for PC-relative code.
814 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
816 /// setShiftAmountType - Describe the type that should be used for shift
817 /// amounts. This type defaults to the pointer type.
818 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
820 /// setBooleanContents - Specify how the target extends the result of a
821 /// boolean value from i1 to a wider type. See getBooleanContents.
822 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
824 /// setSchedulingPreference - Specify the target scheduling preference.
825 void setSchedulingPreference(SchedPreference Pref) {
826 SchedPreferenceInfo = Pref;
829 /// setShiftAmountFlavor - Describe how the target handles out of range shift
831 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
832 ShiftAmtHandling = OORSA;
835 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
836 /// use _setjmp to implement llvm.setjmp or the non _ version.
837 /// Defaults to false.
838 void setUseUnderscoreSetJmp(bool Val) {
839 UseUnderscoreSetJmp = Val;
842 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
843 /// use _longjmp to implement llvm.longjmp or the non _ version.
844 /// Defaults to false.
845 void setUseUnderscoreLongJmp(bool Val) {
846 UseUnderscoreLongJmp = Val;
849 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
850 /// specifies the register that llvm.savestack/llvm.restorestack should save
852 void setStackPointerRegisterToSaveRestore(unsigned R) {
853 StackPointerRegisterToSaveRestore = R;
856 /// setExceptionPointerRegister - If set to a physical register, this sets
857 /// the register that receives the exception address on entry to a landing
859 void setExceptionPointerRegister(unsigned R) {
860 ExceptionPointerRegister = R;
863 /// setExceptionSelectorRegister - If set to a physical register, this sets
864 /// the register that receives the exception typeid on entry to a landing
866 void setExceptionSelectorRegister(unsigned R) {
867 ExceptionSelectorRegister = R;
870 /// SelectIsExpensive - Tells the code generator not to expand operations
871 /// into sequences that use the select operations if possible.
872 void setSelectIsExpensive() { SelectIsExpensive = true; }
874 /// setIntDivIsCheap - Tells the code generator that integer divide is
875 /// expensive, and if possible, should be replaced by an alternate sequence
876 /// of instructions not containing an integer divide.
877 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
879 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
880 /// srl/add/sra for a signed divide by power of two, and let the target handle
882 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
884 /// addRegisterClass - Add the specified register class as an available
885 /// regclass for the specified value type. This indicates the selector can
886 /// handle values of that class natively.
887 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
888 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
889 AvailableRegClasses.push_back(std::make_pair(VT, RC));
890 RegClassForVT[VT.getSimpleVT()] = RC;
893 /// computeRegisterProperties - Once all of the register classes are added,
894 /// this allows us to compute derived properties we expose.
895 void computeRegisterProperties();
897 /// setOperationAction - Indicate that the specified operation does not work
898 /// with the specified type and indicate what to do about it.
899 void setOperationAction(unsigned Op, MVT VT,
900 LegalizeAction Action) {
901 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
902 Op < array_lengthof(OpActions) && "Table isn't big enough!");
903 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
904 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
907 /// setLoadExtAction - Indicate that the specified load with extension does
908 /// not work with the with specified type and indicate what to do about it.
909 void setLoadExtAction(unsigned ExtType, MVT VT,
910 LegalizeAction Action) {
911 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
912 ExtType < array_lengthof(LoadExtActions) &&
913 "Table isn't big enough!");
914 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
915 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
918 /// setTruncStoreAction - Indicate that the specified truncating store does
919 /// not work with the with specified type and indicate what to do about it.
920 void setTruncStoreAction(MVT ValVT, MVT MemVT,
921 LegalizeAction Action) {
922 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
923 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
924 "Table isn't big enough!");
925 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
926 MemVT.getSimpleVT()*2);
927 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
928 MemVT.getSimpleVT()*2;
931 /// setIndexedLoadAction - Indicate that the specified indexed load does or
932 /// does not work with the with specified type and indicate what to do abort
933 /// it. NOTE: All indexed mode loads are initialized to Expand in
934 /// TargetLowering.cpp
935 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
936 LegalizeAction Action) {
937 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
938 IdxMode < array_lengthof(IndexedModeActions[0]) &&
939 "Table isn't big enough!");
940 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
941 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
944 /// setIndexedStoreAction - Indicate that the specified indexed store does or
945 /// does not work with the with specified type and indicate what to do about
946 /// it. NOTE: All indexed mode stores are initialized to Expand in
947 /// TargetLowering.cpp
948 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
949 LegalizeAction Action) {
950 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
951 IdxMode < array_lengthof(IndexedModeActions[1]) &&
952 "Table isn't big enough!");
953 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
954 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
957 /// setConvertAction - Indicate that the specified conversion does or does
958 /// not work with the with specified type and indicate what to do about it.
959 void setConvertAction(MVT FromVT, MVT ToVT,
960 LegalizeAction Action) {
961 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
962 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
963 "Table isn't big enough!");
964 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
965 ToVT.getSimpleVT()*2);
966 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
967 ToVT.getSimpleVT()*2;
970 /// setCondCodeAction - Indicate that the specified condition code is or isn't
971 /// supported on the target and indicate what to do about it.
972 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
973 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
974 (unsigned)CC < array_lengthof(CondCodeActions) &&
975 "Table isn't big enough!");
976 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
977 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
980 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
981 /// promotion code defaults to trying a larger integer/fp until it can find
982 /// one that works. If that default is insufficient, this method can be used
983 /// by the target to override the default.
984 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
985 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
986 DestVT.getSimpleVT();
989 /// addLegalFPImmediate - Indicate that this target can instruction select
990 /// the specified FP immediate natively.
991 void addLegalFPImmediate(const APFloat& Imm) {
992 LegalFPImmediates.push_back(Imm);
995 /// setTargetDAGCombine - Targets should invoke this method for each target
996 /// independent node that they want to provide a custom DAG combiner for by
997 /// implementing the PerformDAGCombine virtual method.
998 void setTargetDAGCombine(ISD::NodeType NT) {
999 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1000 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1003 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1004 /// bytes); default is 200
1005 void setJumpBufSize(unsigned Size) {
1009 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1010 /// alignment (in bytes); default is 0
1011 void setJumpBufAlignment(unsigned Align) {
1012 JumpBufAlignment = Align;
1015 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1016 /// limit (in number of instructions); default is 2.
1017 void setIfCvtBlockSizeLimit(unsigned Limit) {
1018 IfCvtBlockSizeLimit = Limit;
1021 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1022 /// of instructions) to be considered for code duplication during
1023 /// if-conversion; default is 2.
1024 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1025 IfCvtDupBlockSizeLimit = Limit;
1028 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1029 /// alignment is zero, it means the target does not care about loop alignment.
1030 void setPrefLoopAlignment(unsigned Align) {
1031 PrefLoopAlignment = Align;
1036 virtual const TargetSubtarget *getSubtarget() {
1037 assert(0 && "Not Implemented");
1038 return NULL; // this is here to silence compiler errors
1040 //===--------------------------------------------------------------------===//
1041 // Lowering methods - These methods must be implemented by targets so that
1042 // the SelectionDAGLowering code knows how to lower these.
1045 /// LowerArguments - This hook must be implemented to indicate how we should
1046 /// lower the arguments for the specified function, into the specified DAG.
1048 LowerArguments(Function &F, SelectionDAG &DAG,
1049 SmallVectorImpl<SDValue>& ArgValues);
1051 /// LowerCallTo - This hook lowers an abstract call to a function into an
1052 /// actual call. This returns a pair of operands. The first element is the
1053 /// return value for the function (if RetTy is not VoidTy). The second
1054 /// element is the outgoing token chain.
1055 struct ArgListEntry {
1066 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1067 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1069 typedef std::vector<ArgListEntry> ArgListTy;
1070 virtual std::pair<SDValue, SDValue>
1071 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1072 bool isVarArg, bool isInreg, unsigned CallingConv,
1073 bool isTailCall, SDValue Callee, ArgListTy &Args,
1076 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1077 /// memcpy. This can be used by targets to provide code sequences for cases
1078 /// that don't fit the target's parameters for simple loads/stores and can be
1079 /// more efficient than using a library call. This function can return a null
1080 /// SDValue if the target declines to use custom code and a different
1081 /// lowering strategy should be used.
1083 /// If AlwaysInline is true, the size is constant and the target should not
1084 /// emit any calls and is strongly encouraged to attempt to emit inline code
1085 /// even if it is beyond the usual threshold because this intrinsic is being
1086 /// expanded in a place where calls are not feasible (e.g. within the prologue
1087 /// for another call). If the target chooses to decline an AlwaysInline
1088 /// request here, legalize will resort to using simple loads and stores.
1090 EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1092 SDValue Op1, SDValue Op2,
1093 SDValue Op3, unsigned Align,
1095 const Value *DstSV, uint64_t DstOff,
1096 const Value *SrcSV, uint64_t SrcOff) {
1100 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1101 /// memmove. This can be used by targets to provide code sequences for cases
1102 /// that don't fit the target's parameters for simple loads/stores and can be
1103 /// more efficient than using a library call. This function can return a null
1104 /// SDValue if the target declines to use custom code and a different
1105 /// lowering strategy should be used.
1107 EmitTargetCodeForMemmove(SelectionDAG &DAG,
1109 SDValue Op1, SDValue Op2,
1110 SDValue Op3, unsigned Align,
1111 const Value *DstSV, uint64_t DstOff,
1112 const Value *SrcSV, uint64_t SrcOff) {
1116 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1117 /// memset. This can be used by targets to provide code sequences for cases
1118 /// that don't fit the target's parameters for simple stores and can be more
1119 /// efficient than using a library call. This function can return a null
1120 /// SDValue if the target declines to use custom code and a different
1121 /// lowering strategy should be used.
1123 EmitTargetCodeForMemset(SelectionDAG &DAG,
1125 SDValue Op1, SDValue Op2,
1126 SDValue Op3, unsigned Align,
1127 const Value *DstSV, uint64_t DstOff) {
1131 /// LowerOperation - This callback is invoked for operations that are
1132 /// unsupported by the target, which are registered to use 'custom' lowering,
1133 /// and whose defined values are all legal.
1134 /// If the target has no operations that require custom lowering, it need not
1135 /// implement this. The default implementation of this aborts.
1136 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1138 /// ReplaceNodeResults - This callback is invoked when a node result type is
1139 /// illegal for the target, and the operation was registered to use 'custom'
1140 /// lowering for that result type. The target places new result values for
1141 /// the node in Results (their number and types must exactly match those of
1142 /// the original return values of the node), or leaves Results empty, which
1143 /// indicates that the node is not to be custom lowered after all.
1145 /// If the target has no operations that require custom lowering, it need not
1146 /// implement this. The default implementation aborts.
1147 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1148 SelectionDAG &DAG) {
1149 assert(0 && "ReplaceNodeResults not implemented for this target!");
1152 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1153 /// tail call optimization. Targets which want to do tail call optimization
1154 /// should override this function.
1155 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1157 SelectionDAG &DAG) const {
1161 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1162 /// preceeds the RET node and whether the return uses the result of the node
1163 /// or is a void return. This function can be used by the target to determine
1164 /// eligiblity of tail call optimization.
1165 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) {
1166 unsigned NumOps = Ret.getNumOperands();
1168 (Ret.getOperand(0) == SDValue(TheCall,1) ||
1169 Ret.getOperand(0) == SDValue(TheCall,0))) ||
1171 Ret.getOperand(0) == SDValue(TheCall,
1172 TheCall->getNumValues()-1) &&
1173 Ret.getOperand(1) == SDValue(TheCall,0)))
1178 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1179 /// it exists. Skip a possible ISD::TokenFactor.
1180 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1181 unsigned TailCallNodeOpCode) {
1182 if (Chain.getOpcode() == TailCallNodeOpCode) {
1184 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1185 if (Chain.getNumOperands() &&
1186 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1187 return Chain.getOperand(0);
1192 /// getTargetNodeName() - This method returns the name of a target specific
1194 virtual const char *getTargetNodeName(unsigned Opcode) const;
1196 /// createFastISel - This method returns a target specific FastISel object,
1197 /// or null if the target does not support "fast" ISel.
1199 createFastISel(MachineFunction &,
1200 MachineModuleInfo *,
1201 DenseMap<const Value *, unsigned> &,
1202 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1203 DenseMap<const AllocaInst *, int> &
1205 , SmallSet<Instruction*, 8> &CatchInfoLost
1211 //===--------------------------------------------------------------------===//
1212 // Inline Asm Support hooks
1215 enum ConstraintType {
1216 C_Register, // Constraint represents specific register(s).
1217 C_RegisterClass, // Constraint represents any of register(s) in class.
1218 C_Memory, // Memory constraint.
1219 C_Other, // Something else.
1220 C_Unknown // Unsupported constraint.
1223 /// AsmOperandInfo - This contains information for each constraint that we are
1225 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1226 /// ConstraintCode - This contains the actual string for the code, like "m".
1227 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1228 /// most closely matches the operand.
1229 std::string ConstraintCode;
1231 /// ConstraintType - Information about the constraint code, e.g. Register,
1232 /// RegisterClass, Memory, Other, Unknown.
1233 TargetLowering::ConstraintType ConstraintType;
1235 /// CallOperandval - If this is the result output operand or a
1236 /// clobber, this is null, otherwise it is the incoming operand to the
1237 /// CallInst. This gets modified as the asm is processed.
1238 Value *CallOperandVal;
1240 /// ConstraintVT - The ValueType for the operand value.
1243 /// isMatchingInputConstraint - Return true of this is an input operand that
1244 /// is a matching constraint like "4".
1245 bool isMatchingInputConstraint() const;
1247 /// getMatchedOperand - If this is an input matching constraint, this method
1248 /// returns the output operand it matches.
1249 unsigned getMatchedOperand() const;
1251 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1252 : InlineAsm::ConstraintInfo(info),
1253 ConstraintType(TargetLowering::C_Unknown),
1254 CallOperandVal(0), ConstraintVT(MVT::Other) {
1258 /// ComputeConstraintToUse - Determines the constraint code and constraint
1259 /// type to use for the specific AsmOperandInfo, setting
1260 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1261 /// being passed in is available, it can be passed in as Op, otherwise an
1262 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1263 /// constraint of the inline asm instruction being processed is 'm'.
1264 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1267 SelectionDAG *DAG = 0) const;
1269 /// getConstraintType - Given a constraint, return the type of constraint it
1270 /// is for this target.
1271 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1273 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1274 /// return a list of registers that can be used to satisfy the constraint.
1275 /// This should only be used for C_RegisterClass constraints.
1276 virtual std::vector<unsigned>
1277 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1280 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1281 /// {edx}), return the register number and the register class for the
1284 /// Given a register class constraint, like 'r', if this corresponds directly
1285 /// to an LLVM register class, return a register of 0 and the register class
1288 /// This should only be used for C_Register constraints. On error,
1289 /// this returns a register number of 0 and a null register class pointer..
1290 virtual std::pair<unsigned, const TargetRegisterClass*>
1291 getRegForInlineAsmConstraint(const std::string &Constraint,
1294 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1295 /// with another that has more specific requirements based on the type of the
1296 /// corresponding operand. This returns null if there is no replacement to
1298 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1300 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1301 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1302 /// it means one of the asm constraint of the inline asm instruction being
1303 /// processed is 'm'.
1304 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1306 std::vector<SDValue> &Ops,
1307 SelectionDAG &DAG) const;
1309 //===--------------------------------------------------------------------===//
1313 // EmitInstrWithCustomInserter - This method should be implemented by targets
1314 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1315 // instructions are special in various ways, which require special support to
1316 // insert. The specified MachineInstr is created but not inserted into any
1317 // basic blocks, and the scheduler passes ownership of it to this method.
1318 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1319 MachineBasicBlock *MBB);
1321 //===--------------------------------------------------------------------===//
1322 // Addressing mode description hooks (used by LSR etc).
1325 /// AddrMode - This represents an addressing mode of:
1326 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1327 /// If BaseGV is null, there is no BaseGV.
1328 /// If BaseOffs is zero, there is no base offset.
1329 /// If HasBaseReg is false, there is no base register.
1330 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1334 GlobalValue *BaseGV;
1338 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1341 /// isLegalAddressingMode - Return true if the addressing mode represented by
1342 /// AM is legal for this target, for a load/store of the specified type.
1343 /// TODO: Handle pre/postinc as well.
1344 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1346 /// isTruncateFree - Return true if it's free to truncate a value of
1347 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1348 /// register EAX to i16 by referencing its sub-register AX.
1349 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1353 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1357 //===--------------------------------------------------------------------===//
1358 // Div utility functions
1360 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1361 std::vector<SDNode*>* Created) const;
1362 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1363 std::vector<SDNode*>* Created) const;
1366 //===--------------------------------------------------------------------===//
1367 // Runtime Library hooks
1370 /// setLibcallName - Rename the default libcall routine name for the specified
1372 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1373 LibcallRoutineNames[Call] = Name;
1376 /// getLibcallName - Get the libcall routine name for the specified libcall.
1378 const char *getLibcallName(RTLIB::Libcall Call) const {
1379 return LibcallRoutineNames[Call];
1382 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1383 /// result of the comparison libcall against zero.
1384 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1385 CmpLibcallCCs[Call] = CC;
1388 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1389 /// the comparison libcall against zero.
1390 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1391 return CmpLibcallCCs[Call];
1396 const TargetData *TD;
1398 /// PointerTy - The type to use for pointers, usually i32 or i64.
1402 /// IsLittleEndian - True if this is a little endian target.
1404 bool IsLittleEndian;
1406 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1408 bool UsesGlobalOffsetTable;
1410 /// SelectIsExpensive - Tells the code generator not to expand operations
1411 /// into sequences that use the select operations if possible.
1412 bool SelectIsExpensive;
1414 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1415 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1416 /// a real cost model is in place. If we ever optimize for size, this will be
1417 /// set to true unconditionally.
1420 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1421 /// srl/add/sra for a signed divide by power of two, and let the target handle
1423 bool Pow2DivIsCheap;
1425 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1426 /// llvm.setjmp. Defaults to false.
1427 bool UseUnderscoreSetJmp;
1429 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1430 /// llvm.longjmp. Defaults to false.
1431 bool UseUnderscoreLongJmp;
1433 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1437 OutOfRangeShiftAmount ShiftAmtHandling;
1439 /// BooleanContents - Information about the contents of the high-bits in
1440 /// boolean values held in a type wider than i1. See getBooleanContents.
1441 BooleanContent BooleanContents;
1443 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1444 /// total cycles or lowest register usage.
1445 SchedPreference SchedPreferenceInfo;
1447 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1448 unsigned JumpBufSize;
1450 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1452 unsigned JumpBufAlignment;
1454 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1456 unsigned IfCvtBlockSizeLimit;
1458 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1459 /// duplicated during if-conversion.
1460 unsigned IfCvtDupBlockSizeLimit;
1462 /// PrefLoopAlignment - The perferred loop alignment.
1464 unsigned PrefLoopAlignment;
1466 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1467 /// specifies the register that llvm.savestack/llvm.restorestack should save
1469 unsigned StackPointerRegisterToSaveRestore;
1471 /// ExceptionPointerRegister - If set to a physical register, this specifies
1472 /// the register that receives the exception address on entry to a landing
1474 unsigned ExceptionPointerRegister;
1476 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1477 /// the register that receives the exception typeid on entry to a landing
1479 unsigned ExceptionSelectorRegister;
1481 /// RegClassForVT - This indicates the default register class to use for
1482 /// each ValueType the target supports natively.
1483 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1484 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1485 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1487 /// TransformToType - For any value types we are promoting or expanding, this
1488 /// contains the value type that we are changing to. For Expanded types, this
1489 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1490 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1491 /// by the system, this holds the same type (e.g. i32 -> i32).
1492 MVT TransformToType[MVT::LAST_VALUETYPE];
1494 // Defines the capacity of the TargetLowering::OpActions table
1495 static const int OpActionsCapacity = 184;
1497 /// OpActions - For each operation and each value type, keep a LegalizeAction
1498 /// that indicates how instruction selection should deal with the operation.
1499 /// Most operations are Legal (aka, supported natively by the target), but
1500 /// operations that are not should be described. Note that operations on
1501 /// non-legal value types are not described here.
1502 uint64_t OpActions[OpActionsCapacity];
1504 /// LoadExtActions - For each load of load extension type and each value type,
1505 /// keep a LegalizeAction that indicates how instruction selection should deal
1507 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1509 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1510 /// indicates how instruction selection should deal with the store.
1511 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1513 /// IndexedModeActions - For each indexed mode and each value type, keep a
1514 /// pair of LegalizeAction that indicates how instruction selection should
1515 /// deal with the load / store.
1516 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1518 /// ConvertActions - For each conversion from source type to destination type,
1519 /// keep a LegalizeAction that indicates how instruction selection should
1520 /// deal with the conversion.
1521 /// Currently, this is used only for floating->floating conversions
1522 /// (FP_EXTEND and FP_ROUND).
1523 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1525 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1526 /// LegalizeAction that indicates how instruction selection should
1527 /// deal with the condition code.
1528 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1530 ValueTypeActionImpl ValueTypeActions;
1532 std::vector<APFloat> LegalFPImmediates;
1534 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1536 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1537 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1538 /// which sets a bit in this array.
1540 TargetDAGCombineArray[OpActionsCapacity/(sizeof(unsigned char)*8)];
1542 /// PromoteToType - For operations that must be promoted to a specific type,
1543 /// this holds the destination type. This map should be sparse, so don't hold
1546 /// Targets add entries to this map with AddPromotedToType(..), clients access
1547 /// this with getTypeToPromoteTo(..).
1548 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1551 /// LibcallRoutineNames - Stores the name each libcall.
1553 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1555 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1556 /// of each of the comparison libcall against zero.
1557 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1560 /// When lowering @llvm.memset this field specifies the maximum number of
1561 /// store operations that may be substituted for the call to memset. Targets
1562 /// must set this value based on the cost threshold for that target. Targets
1563 /// should assume that the memset will be done using as many of the largest
1564 /// store operations first, followed by smaller ones, if necessary, per
1565 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1566 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1567 /// store. This only applies to setting a constant array of a constant size.
1568 /// @brief Specify maximum number of store instructions per memset call.
1569 unsigned maxStoresPerMemset;
1571 /// When lowering @llvm.memcpy this field specifies the maximum number of
1572 /// store operations that may be substituted for a call to memcpy. Targets
1573 /// must set this value based on the cost threshold for that target. Targets
1574 /// should assume that the memcpy will be done using as many of the largest
1575 /// store operations first, followed by smaller ones, if necessary, per
1576 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1577 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1578 /// and one 1-byte store. This only applies to copying a constant array of
1580 /// @brief Specify maximum bytes of store instructions per memcpy call.
1581 unsigned maxStoresPerMemcpy;
1583 /// When lowering @llvm.memmove this field specifies the maximum number of
1584 /// store instructions that may be substituted for a call to memmove. Targets
1585 /// must set this value based on the cost threshold for that target. Targets
1586 /// should assume that the memmove will be done using as many of the largest
1587 /// store operations first, followed by smaller ones, if necessary, per
1588 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1589 /// with 8-bit alignment would result in nine 1-byte stores. This only
1590 /// applies to copying a constant array of constant size.
1591 /// @brief Specify maximum bytes of store instructions per memmove call.
1592 unsigned maxStoresPerMemmove;
1594 /// This field specifies whether the target machine permits unaligned memory
1595 /// accesses. This is used, for example, to determine the size of store
1596 /// operations when copying small arrays and other similar tasks.
1597 /// @brief Indicate whether the target permits unaligned memory accesses.
1598 bool allowUnalignedMemoryAccesses;
1600 } // end llvm namespace