1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/Support/DataTypes.h"
35 class TargetRegisterClass;
39 class MachineBasicBlock;
42 //===----------------------------------------------------------------------===//
43 /// TargetLowering - This class defines information used to lower LLVM code to
44 /// legal SelectionDAG operators that the target instruction selector can accept
47 /// This class also defines callbacks that targets must implement to lower
48 /// target-specific constructs to SelectionDAG operators.
50 class TargetLowering {
52 /// LegalizeAction - This enum indicates whether operations are valid for a
53 /// target, and if not, what action should be used to make them valid.
55 Legal, // The target natively supports this operation.
56 Promote, // This operation should be executed in a larger type.
57 Expand, // Try to expand this to other ops, otherwise use a libcall.
58 Custom, // Use the LowerOperation hook to implement custom lowering.
61 enum OutOfRangeShiftAmount {
62 Undefined, // Oversized shift amounts are undefined (default).
63 Mask, // Shift amounts are auto masked (anded) to value size.
64 Extend, // Oversized shift pulls in zeros or sign bits.
67 enum SetCCResultValue {
68 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
69 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
70 ZeroOrNegativeOneSetCCResult, // SetCC returns a sign extended result.
73 enum SchedPreference {
74 SchedulingForLatency, // Scheduling for shortest total latency.
75 SchedulingForRegPressure, // Scheduling for lowest register pressure.
78 TargetLowering(TargetMachine &TM);
79 virtual ~TargetLowering();
81 TargetMachine &getTargetMachine() const { return TM; }
82 const TargetData &getTargetData() const { return TD; }
84 bool isLittleEndian() const { return IsLittleEndian; }
85 MVT::ValueType getPointerTy() const { return PointerTy; }
86 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
87 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
89 /// isSetCCExpensive - Return true if the setcc operation is expensive for
91 bool isSetCCExpensive() const { return SetCCIsExpensive; }
93 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
94 /// a sequence of several shifts, adds, and multiplies for this target.
95 bool isIntDivCheap() const { return IntDivIsCheap; }
97 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
99 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
101 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
103 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
105 /// getSetCCResultContents - For targets without boolean registers, this flag
106 /// returns information about the contents of the high-bits in the setcc
108 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
110 /// getSchedulingPreference - Return target scheduling preference.
111 SchedPreference getSchedulingPreference() const {
112 return SchedPreferenceInfo;
115 /// getRegClassFor - Return the register class that should be used for the
116 /// specified value type. This may only be called on legal types.
117 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
118 TargetRegisterClass *RC = RegClassForVT[VT];
119 assert(RC && "This value type is not natively supported!");
123 /// isTypeLegal - Return true if the target has native support for the
124 /// specified value type. This means that it has a register that directly
125 /// holds it without promotions or expansions.
126 bool isTypeLegal(MVT::ValueType VT) const {
127 return RegClassForVT[VT] != 0;
130 class ValueTypeActionImpl {
131 /// ValueTypeActions - This is a bitvector that contains two bits for each
132 /// value type, where the two bits correspond to the LegalizeAction enum.
133 /// This can be queried with "getTypeAction(VT)".
134 uint32_t ValueTypeActions[2];
136 ValueTypeActionImpl() {
137 ValueTypeActions[0] = ValueTypeActions[1] = 0;
139 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
140 ValueTypeActions[0] = RHS.ValueTypeActions[0];
141 ValueTypeActions[1] = RHS.ValueTypeActions[1];
144 LegalizeAction getTypeAction(MVT::ValueType VT) const {
145 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
147 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
148 assert(unsigned(VT >> 4) <
149 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
150 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
154 const ValueTypeActionImpl &getValueTypeActions() const {
155 return ValueTypeActions;
158 /// getTypeAction - Return how we should legalize values of this type, either
159 /// it is already legal (return 'Legal') or we need to promote it to a larger
160 /// type (return 'Promote'), or we need to expand it into multiple registers
161 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
162 LegalizeAction getTypeAction(MVT::ValueType VT) const {
163 return ValueTypeActions.getTypeAction(VT);
166 /// getTypeToTransformTo - For types supported by the target, this is an
167 /// identity function. For types that must be promoted to larger types, this
168 /// returns the larger type to promote to. For types that are larger than the
169 /// largest integer register, this contains one step in the expansion to get
170 /// to the smaller register.
171 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
172 return TransformToType[VT];
175 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
176 legal_fpimm_iterator legal_fpimm_begin() const {
177 return LegalFPImmediates.begin();
179 legal_fpimm_iterator legal_fpimm_end() const {
180 return LegalFPImmediates.end();
183 /// getOperationAction - Return how this operation should be treated: either
184 /// it is legal, needs to be promoted to a larger size, needs to be
185 /// expanded to some other code sequence, or the target has a custom expander
187 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
188 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
191 /// isOperationLegal - Return true if the specified operation is legal on this
193 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
194 return getOperationAction(Op, VT) == Legal;
197 /// getTypeToPromoteTo - If the action for this operation is to promote, this
198 /// method returns the ValueType to promote to.
199 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
200 assert(getOperationAction(Op, VT) == Promote &&
201 "This operation isn't promoted!");
202 MVT::ValueType NVT = VT;
204 NVT = (MVT::ValueType)(NVT+1);
205 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
206 "Didn't find type to promote to!");
207 } while (!isTypeLegal(NVT) ||
208 getOperationAction(Op, NVT) == Promote);
212 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
213 /// This is fixed by the LLVM operations except for the pointer size.
214 MVT::ValueType getValueType(const Type *Ty) const {
215 switch (Ty->getTypeID()) {
216 default: assert(0 && "Unknown type!");
217 case Type::VoidTyID: return MVT::isVoid;
218 case Type::BoolTyID: return MVT::i1;
219 case Type::UByteTyID:
220 case Type::SByteTyID: return MVT::i8;
221 case Type::ShortTyID:
222 case Type::UShortTyID: return MVT::i16;
224 case Type::UIntTyID: return MVT::i32;
226 case Type::ULongTyID: return MVT::i64;
227 case Type::FloatTyID: return MVT::f32;
228 case Type::DoubleTyID: return MVT::f64;
229 case Type::PointerTyID: return PointerTy;
230 case Type::PackedTyID: return MVT::Vector;
234 /// getNumElements - Return the number of registers that this ValueType will
235 /// eventually require. This is always one for all non-integer types, is
236 /// one for any types promoted to live in larger registers, but may be more
237 /// than one for types (like i64) that are split into pieces.
238 unsigned getNumElements(MVT::ValueType VT) const {
239 return NumElementsForVT[VT];
242 /// This function returns the maximum number of store operations permitted
243 /// to replace a call to llvm.memset. The value is set by the target at the
244 /// performance threshold for such a replacement.
245 /// @brief Get maximum # of store operations permitted for llvm.memset
246 unsigned getMaxStoresPerMemSet() const { return maxStoresPerMemSet; }
248 /// This function returns the maximum number of store operations permitted
249 /// to replace a call to llvm.memcpy. The value is set by the target at the
250 /// performance threshold for such a replacement.
251 /// @brief Get maximum # of store operations permitted for llvm.memcpy
252 unsigned getMaxStoresPerMemCpy() const { return maxStoresPerMemCpy; }
254 /// This function returns the maximum number of store operations permitted
255 /// to replace a call to llvm.memmove. The value is set by the target at the
256 /// performance threshold for such a replacement.
257 /// @brief Get maximum # of store operations permitted for llvm.memmove
258 unsigned getMaxStoresPerMemMove() const { return maxStoresPerMemMove; }
260 /// This function returns true if the target allows unaligned memory accesses.
261 /// This is used, for example, in situations where an array copy/move/set is
262 /// converted to a sequence of store operations. It's use helps to ensure that
263 /// such replacements don't generate code that causes an alignment error
264 /// (trap) on the target machine.
265 /// @brief Determine if the target supports unaligned memory accesses.
266 bool allowsUnalignedMemoryAccesses() const {
267 return allowUnalignedMemoryAccesses;
270 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
271 /// to implement llvm.setjmp.
272 bool usesUnderscoreSetJmpLongJmp() const {
273 return UseUnderscoreSetJmpLongJmp;
276 /// getStackPointerRegisterToSaveRestore - If a physical register, this
277 /// specifies the register that llvm.savestack/llvm.restorestack should save
279 unsigned getStackPointerRegisterToSaveRestore() const {
280 return StackPointerRegisterToSaveRestore;
283 //===--------------------------------------------------------------------===//
284 // TargetLowering Optimization Methods
287 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
288 /// use this predicate to simplify operations downstream. Op and Mask are
289 /// known to be the same type. Targets can implement the
290 /// isMaskedValueZeroForTargetNode method, to allow target nodes to be
292 bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask) const;
294 //===--------------------------------------------------------------------===//
295 // TargetLowering Configuration Methods - These methods should be invoked by
296 // the derived class constructor to configure this object for the target.
301 /// setShiftAmountType - Describe the type that should be used for shift
302 /// amounts. This type defaults to the pointer type.
303 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
305 /// setSetCCResultType - Describe the type that shoudl be used as the result
306 /// of a setcc operation. This defaults to the pointer type.
307 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
309 /// setSetCCResultContents - Specify how the target extends the result of a
310 /// setcc operation in a register.
311 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
313 /// setSchedulingPreference - Specify the target scheduling preference.
314 void setSchedulingPreference(SchedPreference Pref) {
315 SchedPreferenceInfo = Pref;
318 /// setShiftAmountFlavor - Describe how the target handles out of range shift
320 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
321 ShiftAmtHandling = OORSA;
324 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
325 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
326 /// the non _ versions. Defaults to false.
327 void setUseUnderscoreSetJmpLongJmp(bool Val) {
328 UseUnderscoreSetJmpLongJmp = Val;
331 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
332 /// specifies the register that llvm.savestack/llvm.restorestack should save
334 void setStackPointerRegisterToSaveRestore(unsigned R) {
335 StackPointerRegisterToSaveRestore = R;
338 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
339 /// setcc as a conditional branch. This encourages the code generator to fold
340 /// setcc operations into other operations if possible.
341 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
343 /// setIntDivIsCheap - Tells the code generator that integer divide is
344 /// expensive, and if possible, should be replaced by an alternate sequence
345 /// of instructions not containing an integer divide.
346 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
348 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
349 /// srl/add/sra for a signed divide by power of two, and let the target handle
351 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
353 /// addRegisterClass - Add the specified register class as an available
354 /// regclass for the specified value type. This indicates the selector can
355 /// handle values of that class natively.
356 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
357 AvailableRegClasses.push_back(std::make_pair(VT, RC));
358 RegClassForVT[VT] = RC;
361 /// computeRegisterProperties - Once all of the register classes are added,
362 /// this allows us to compute derived properties we expose.
363 void computeRegisterProperties();
365 /// setOperationAction - Indicate that the specified operation does not work
366 /// with the specified type and indicate what to do about it.
367 void setOperationAction(unsigned Op, MVT::ValueType VT,
368 LegalizeAction Action) {
369 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
370 "Table isn't big enough!");
371 OpActions[Op] |= Action << VT*2;
374 /// addLegalFPImmediate - Indicate that this target can instruction select
375 /// the specified FP immediate natively.
376 void addLegalFPImmediate(double Imm) {
377 LegalFPImmediates.push_back(Imm);
382 //===--------------------------------------------------------------------===//
383 // Lowering methods - These methods must be implemented by targets so that
384 // the SelectionDAGLowering code knows how to lower these.
387 /// LowerArguments - This hook must be implemented to indicate how we should
388 /// lower the arguments for the specified function, into the specified DAG.
389 virtual std::vector<SDOperand>
390 LowerArguments(Function &F, SelectionDAG &DAG) = 0;
392 /// LowerCallTo - This hook lowers an abstract call to a function into an
393 /// actual call. This returns a pair of operands. The first element is the
394 /// return value for the function (if RetTy is not VoidTy). The second
395 /// element is the outgoing token chain.
396 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
397 virtual std::pair<SDOperand, SDOperand>
398 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
399 unsigned CallingConv, bool isTailCall, SDOperand Callee,
400 ArgListTy &Args, SelectionDAG &DAG) = 0;
402 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
403 /// llvm.frameaddress (depending on the value of the first argument). The
404 /// return values are the result pointer and the resultant token chain. If
405 /// not implemented, both of these intrinsics will return null.
406 virtual std::pair<SDOperand, SDOperand>
407 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
410 /// LowerOperation - This callback is invoked for operations that are
411 /// unsupported by the target, which are registered to use 'custom' lowering,
412 /// and whose defined values are all legal.
413 /// If the target has no operations that require custom lowering, it need not
414 /// implement this. The default implementation of this aborts.
415 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
417 /// CustomPromoteOperation - This callback is invoked for operations that are
418 /// unsupported by the target, are registered to use 'custom' lowering, and
419 /// whose type needs to be promoted.
420 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
422 /// getTargetNodeName() - This method returns the name of a target specific
424 virtual const char *getTargetNodeName(unsigned Opcode) const;
426 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
427 /// be zero. Op is expected to be a target specific node.
428 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
429 uint64_t Mask) const;
431 //===--------------------------------------------------------------------===//
432 // Inline Asm Support hooks
435 /// getRegForInlineAsmConstraint - Given a constraint letter or register
436 /// name (e.g. "r" or "edx"), return a list of registers that can be used to
437 /// satisfy the constraint. If the constraint isn't supported, or isn't a
438 /// register constraint, return an empty list.
439 virtual std::vector<unsigned>
440 getRegForInlineAsmConstraint(const std::string &Constraint) const;
442 //===--------------------------------------------------------------------===//
446 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
447 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
448 // instructions are special in various ways, which require special support to
449 // insert. The specified MachineInstr is created but not inserted into any
450 // basic blocks, and the scheduler passes ownership of it to this method.
451 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
452 MachineBasicBlock *MBB);
456 const TargetData &TD;
458 /// IsLittleEndian - True if this is a little endian target.
462 /// PointerTy - The type to use for pointers, usually i32 or i64.
464 MVT::ValueType PointerTy;
466 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
468 MVT::ValueType ShiftAmountTy;
470 OutOfRangeShiftAmount ShiftAmtHandling;
472 /// SetCCIsExpensive - This is a short term hack for targets that codegen
473 /// setcc as a conditional branch. This encourages the code generator to fold
474 /// setcc operations into other operations if possible.
475 bool SetCCIsExpensive;
477 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
478 /// constants into a sequence of muls, adds, and shifts. This is a hack until
479 /// a real cost model is in place. If we ever optimize for size, this will be
480 /// set to true unconditionally.
483 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
484 /// srl/add/sra for a signed divide by power of two, and let the target handle
488 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
490 MVT::ValueType SetCCResultTy;
492 /// SetCCResultContents - Information about the contents of the high-bits in
493 /// the result of a setcc comparison operation.
494 SetCCResultValue SetCCResultContents;
496 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
497 /// total cycles or lowest register usage.
498 SchedPreference SchedPreferenceInfo;
500 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
501 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
502 bool UseUnderscoreSetJmpLongJmp;
504 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
505 /// specifies the register that llvm.savestack/llvm.restorestack should save
507 unsigned StackPointerRegisterToSaveRestore;
509 /// RegClassForVT - This indicates the default register class to use for
510 /// each ValueType the target supports natively.
511 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
512 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
514 /// TransformToType - For any value types we are promoting or expanding, this
515 /// contains the value type that we are changing to. For Expanded types, this
516 /// contains one step of the expand (e.g. i64 -> i32), even if there are
517 /// multiple steps required (e.g. i64 -> i16). For types natively supported
518 /// by the system, this holds the same type (e.g. i32 -> i32).
519 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
521 /// OpActions - For each operation and each value type, keep a LegalizeAction
522 /// that indicates how instruction selection should deal with the operation.
523 /// Most operations are Legal (aka, supported natively by the target), but
524 /// operations that are not should be described. Note that operations on
525 /// non-legal value types are not described here.
526 uint64_t OpActions[128];
528 ValueTypeActionImpl ValueTypeActions;
530 std::vector<double> LegalFPImmediates;
532 std::vector<std::pair<MVT::ValueType,
533 TargetRegisterClass*> > AvailableRegClasses;
536 /// When lowering %llvm.memset this field specifies the maximum number of
537 /// store operations that may be substituted for the call to memset. Targets
538 /// must set this value based on the cost threshold for that target. Targets
539 /// should assume that the memset will be done using as many of the largest
540 /// store operations first, followed by smaller ones, if necessary, per
541 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
542 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
543 /// store. This only applies to setting a constant array of a constant size.
544 /// @brief Specify maximum number of store instructions per memset call.
545 unsigned maxStoresPerMemSet;
547 /// When lowering %llvm.memcpy this field specifies the maximum number of
548 /// store operations that may be substituted for a call to memcpy. Targets
549 /// must set this value based on the cost threshold for that target. Targets
550 /// should assume that the memcpy will be done using as many of the largest
551 /// store operations first, followed by smaller ones, if necessary, per
552 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
553 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
554 /// and one 1-byte store. This only applies to copying a constant array of
556 /// @brief Specify maximum bytes of store instructions per memcpy call.
557 unsigned maxStoresPerMemCpy;
559 /// When lowering %llvm.memmove this field specifies the maximum number of
560 /// store instructions that may be substituted for a call to memmove. Targets
561 /// must set this value based on the cost threshold for that target. Targets
562 /// should assume that the memmove will be done using as many of the largest
563 /// store operations first, followed by smaller ones, if necessary, per
564 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
565 /// with 8-bit alignment would result in nine 1-byte stores. This only
566 /// applies to copying a constant array of constant size.
567 /// @brief Specify maximum bytes of store instructions per memmove call.
568 unsigned maxStoresPerMemMove;
570 /// This field specifies whether the target machine permits unaligned memory
571 /// accesses. This is used, for example, to determine the size of store
572 /// operations when copying small arrays and other similar tasks.
573 /// @brief Indicate whether the target permits unaligned memory accesses.
574 bool allowUnalignedMemoryAccesses;
576 } // end llvm namespace