1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
50 class MachineModuleInfo;
59 class TargetRegisterClass;
60 class TargetSubtarget;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 enum SchedPreference {
104 SchedulingForLatency, // Scheduling for shortest total latency.
105 SchedulingForRegPressure // Scheduling for lowest register pressure.
108 /// NOTE: The constructor takes ownership of TLOF.
109 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
110 virtual ~TargetLowering();
112 TargetMachine &getTargetMachine() const { return TM; }
113 const TargetData *getTargetData() const { return TD; }
114 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
116 bool isBigEndian() const { return !IsLittleEndian; }
117 bool isLittleEndian() const { return IsLittleEndian; }
118 MVT getPointerTy() const { return PointerTy; }
119 MVT getShiftAmountTy() const { return ShiftAmountTy; }
121 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
123 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
125 /// isSelectExpensive - Return true if the select operation is expensive for
127 bool isSelectExpensive() const { return SelectIsExpensive; }
129 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
130 /// a sequence of several shifts, adds, and multiplies for this target.
131 bool isIntDivCheap() const { return IntDivIsCheap; }
133 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
135 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
137 /// getSetCCResultType - Return the ValueType of the result of SETCC
138 /// operations. Also used to obtain the target's preferred type for
139 /// the condition operand of SELECT and BRCOND nodes. In the case of
140 /// BRCOND the argument passed is MVT::Other since there are no other
141 /// operands to get a type hint from.
143 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
145 /// getCmpLibcallReturnType - Return the ValueType for comparison
146 /// libcalls. Comparions libcalls include floating point comparion calls,
147 /// and Ordered/Unordered check calls on floating point numbers.
149 MVT::SimpleValueType getCmpLibcallReturnType() const;
151 /// getBooleanContents - For targets without i1 registers, this gives the
152 /// nature of the high-bits of boolean values held in types wider than i1.
153 /// "Boolean values" are special true/false values produced by nodes like
154 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
155 /// Not to be confused with general values promoted from i1.
156 BooleanContent getBooleanContents() const { return BooleanContents;}
158 /// getSchedulingPreference - Return target scheduling preference.
159 SchedPreference getSchedulingPreference() const {
160 return SchedPreferenceInfo;
163 /// getRegClassFor - Return the register class that should be used for the
164 /// specified value type. This may only be called on legal types.
165 TargetRegisterClass *getRegClassFor(EVT VT) const {
166 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
167 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
168 assert(RC && "This value type is not natively supported!");
172 /// isTypeLegal - Return true if the target has native support for the
173 /// specified value type. This means that it has a register that directly
174 /// holds it without promotions or expansions.
175 bool isTypeLegal(EVT VT) const {
176 assert(!VT.isSimple() ||
177 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
178 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
181 class ValueTypeActionImpl {
182 /// ValueTypeActions - This is a bitvector that contains two bits for each
183 /// value type, where the two bits correspond to the LegalizeAction enum.
184 /// This can be queried with "getTypeAction(VT)".
185 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
186 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
188 ValueTypeActionImpl() {
189 ValueTypeActions[0] = ValueTypeActions[1] = 0;
190 ValueTypeActions[2] = ValueTypeActions[3] = 0;
192 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
193 ValueTypeActions[0] = RHS.ValueTypeActions[0];
194 ValueTypeActions[1] = RHS.ValueTypeActions[1];
195 ValueTypeActions[2] = RHS.ValueTypeActions[2];
196 ValueTypeActions[3] = RHS.ValueTypeActions[3];
199 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
200 if (VT.isExtended()) {
202 return VT.isPow2VectorType() ? Expand : Promote;
205 // First promote to a power-of-two size, then expand if necessary.
206 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
207 assert(0 && "Unsupported extended type!");
210 unsigned I = VT.getSimpleVT().SimpleTy;
211 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
212 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
214 void setTypeAction(EVT VT, LegalizeAction Action) {
215 unsigned I = VT.getSimpleVT().SimpleTy;
216 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
217 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
221 const ValueTypeActionImpl &getValueTypeActions() const {
222 return ValueTypeActions;
225 /// getTypeAction - Return how we should legalize values of this type, either
226 /// it is already legal (return 'Legal') or we need to promote it to a larger
227 /// type (return 'Promote'), or we need to expand it into multiple registers
228 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
229 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
230 return ValueTypeActions.getTypeAction(Context, VT);
233 /// getTypeToTransformTo - For types supported by the target, this is an
234 /// identity function. For types that must be promoted to larger types, this
235 /// returns the larger type to promote to. For integer types that are larger
236 /// than the largest integer register, this contains one step in the expansion
237 /// to get to the smaller register. For illegal floating point types, this
238 /// returns the integer type to transform to.
239 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
241 assert((unsigned)VT.getSimpleVT().SimpleTy <
242 array_lengthof(TransformToType));
243 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
244 assert(getTypeAction(Context, NVT) != Promote &&
245 "Promote may not follow Expand or Promote");
250 EVT NVT = VT.getPow2VectorType(Context);
252 // Vector length is a power of 2 - split to half the size.
253 unsigned NumElts = VT.getVectorNumElements();
254 EVT EltVT = VT.getVectorElementType();
255 return (NumElts == 1) ?
256 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
258 // Promote to a power of two size, avoiding multi-step promotion.
259 return getTypeAction(Context, NVT) == Promote ?
260 getTypeToTransformTo(Context, NVT) : NVT;
261 } else if (VT.isInteger()) {
262 EVT NVT = VT.getRoundIntegerType(Context);
264 // Size is a power of two - expand to half the size.
265 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
267 // Promote to a power of two size, avoiding multi-step promotion.
268 return getTypeAction(Context, NVT) == Promote ?
269 getTypeToTransformTo(Context, NVT) : NVT;
271 assert(0 && "Unsupported extended type!");
272 return MVT(MVT::Other); // Not reached
275 /// getTypeToExpandTo - For types supported by the target, this is an
276 /// identity function. For types that must be expanded (i.e. integer types
277 /// that are larger than the largest integer register or illegal floating
278 /// point types), this returns the largest legal type it will be expanded to.
279 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
280 assert(!VT.isVector());
282 switch (getTypeAction(Context, VT)) {
286 VT = getTypeToTransformTo(Context, VT);
289 assert(false && "Type is not legal nor is it to be expanded!");
296 /// getVectorTypeBreakdown - Vector types are broken down into some number of
297 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
298 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
299 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
301 /// This method returns the number of registers needed, and the VT for each
302 /// register. It also returns the VT and quantity of the intermediate values
303 /// before they are promoted/expanded.
305 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
307 unsigned &NumIntermediates,
308 EVT &RegisterVT) const;
310 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
311 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
312 /// this is the case, it returns true and store the intrinsic
313 /// information into the IntrinsicInfo that was passed to the function.
314 typedef struct IntrinsicInfo {
315 unsigned opc; // target opcode
316 EVT memVT; // memory VT
317 const Value* ptrVal; // value representing memory location
318 int offset; // offset off of ptrVal
319 unsigned align; // alignment
320 bool vol; // is volatile?
321 bool readMem; // reads memory?
322 bool writeMem; // writes memory?
325 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
326 CallInst &I, unsigned Intrinsic) {
330 /// getWidenVectorType: given a vector type, returns the type to widen to
331 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
332 /// If there is no vector type that we want to widen to, returns MVT::Other
333 /// When and were to widen is target dependent based on the cost of
334 /// scalarizing vs using the wider vector type.
335 virtual EVT getWidenVectorType(EVT VT) const;
337 /// isFPImmLegal - Returns true if the target can instruction select the
338 /// specified FP immediate natively. If false, the legalizer will materialize
339 /// the FP immediate as a load from a constant pool.
340 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
344 /// isShuffleMaskLegal - Targets can use this to indicate that they only
345 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
346 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
347 /// are assumed to be legal.
348 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
353 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
354 /// used by Targets can use this to indicate if there is a suitable
355 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
357 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
362 /// getOperationAction - Return how this operation should be treated: either
363 /// it is legal, needs to be promoted to a larger size, needs to be
364 /// expanded to some other code sequence, or the target has a custom expander
366 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
367 if (VT.isExtended()) return Expand;
368 assert(Op < array_lengthof(OpActions[0]) &&
369 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
370 "Table isn't big enough!");
371 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
374 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
377 /// isOperationLegalOrCustom - Return true if the specified operation is
378 /// legal on this target or can be made legal with custom lowering. This
379 /// is used to help guide high-level lowering decisions.
380 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
381 return (VT == MVT::Other || isTypeLegal(VT)) &&
382 (getOperationAction(Op, VT) == Legal ||
383 getOperationAction(Op, VT) == Custom);
386 /// isOperationLegal - Return true if the specified operation is legal on this
388 bool isOperationLegal(unsigned Op, EVT VT) const {
389 return (VT == MVT::Other || isTypeLegal(VT)) &&
390 getOperationAction(Op, VT) == Legal;
393 /// getLoadExtAction - Return how this load with extension should be treated:
394 /// either it is legal, needs to be promoted to a larger size, needs to be
395 /// expanded to some other code sequence, or the target has a custom expander
397 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
398 assert(LType < array_lengthof(LoadExtActions) &&
399 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
400 "Table isn't big enough!");
401 return (LegalizeAction)((LoadExtActions[LType] >>
402 (2*VT.getSimpleVT().SimpleTy)) & 3);
405 /// isLoadExtLegal - Return true if the specified load with extension is legal
407 bool isLoadExtLegal(unsigned LType, EVT VT) const {
408 return VT.isSimple() &&
409 (getLoadExtAction(LType, VT) == Legal ||
410 getLoadExtAction(LType, VT) == Custom);
413 /// getTruncStoreAction - Return how this store with truncation should be
414 /// treated: either it is legal, needs to be promoted to a larger size, needs
415 /// to be expanded to some other code sequence, or the target has a custom
417 LegalizeAction getTruncStoreAction(EVT ValVT,
419 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
420 array_lengthof(TruncStoreActions) &&
421 (unsigned)MemVT.getSimpleVT().SimpleTy <
422 sizeof(TruncStoreActions[0])*4 &&
423 "Table isn't big enough!");
424 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
425 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
428 /// isTruncStoreLegal - Return true if the specified store with truncation is
429 /// legal on this target.
430 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
431 return isTypeLegal(ValVT) && MemVT.isSimple() &&
432 (getTruncStoreAction(ValVT, MemVT) == Legal ||
433 getTruncStoreAction(ValVT, MemVT) == Custom);
436 /// getIndexedLoadAction - Return how the indexed load should be treated:
437 /// either it is legal, needs to be promoted to a larger size, needs to be
438 /// expanded to some other code sequence, or the target has a custom expander
441 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
442 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
443 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
444 "Table isn't big enough!");
445 return (LegalizeAction)((IndexedModeActions[
446 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
449 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
451 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
452 return VT.isSimple() &&
453 (getIndexedLoadAction(IdxMode, VT) == Legal ||
454 getIndexedLoadAction(IdxMode, VT) == Custom);
457 /// getIndexedStoreAction - Return how the indexed store should be treated:
458 /// either it is legal, needs to be promoted to a larger size, needs to be
459 /// expanded to some other code sequence, or the target has a custom expander
462 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
463 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
464 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
465 "Table isn't big enough!");
466 return (LegalizeAction)((IndexedModeActions[
467 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
470 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
472 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
473 return VT.isSimple() &&
474 (getIndexedStoreAction(IdxMode, VT) == Legal ||
475 getIndexedStoreAction(IdxMode, VT) == Custom);
478 /// getConvertAction - Return how the conversion should be treated:
479 /// either it is legal, needs to be promoted to a larger size, needs to be
480 /// expanded to some other code sequence, or the target has a custom expander
483 getConvertAction(EVT FromVT, EVT ToVT) const {
484 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
485 array_lengthof(ConvertActions) &&
486 (unsigned)ToVT.getSimpleVT().SimpleTy <
487 sizeof(ConvertActions[0])*4 &&
488 "Table isn't big enough!");
489 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
490 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
493 /// isConvertLegal - Return true if the specified conversion is legal
495 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
496 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
497 (getConvertAction(FromVT, ToVT) == Legal ||
498 getConvertAction(FromVT, ToVT) == Custom);
501 /// getCondCodeAction - Return how the condition code should be treated:
502 /// either it is legal, needs to be expanded to some other code sequence,
503 /// or the target has a custom expander for it.
505 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
506 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
507 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
508 "Table isn't big enough!");
509 LegalizeAction Action = (LegalizeAction)
510 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
511 assert(Action != Promote && "Can't promote condition code!");
515 /// isCondCodeLegal - Return true if the specified condition code is legal
517 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
518 return getCondCodeAction(CC, VT) == Legal ||
519 getCondCodeAction(CC, VT) == Custom;
523 /// getTypeToPromoteTo - If the action for this operation is to promote, this
524 /// method returns the ValueType to promote to.
525 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
526 assert(getOperationAction(Op, VT) == Promote &&
527 "This operation isn't promoted!");
529 // See if this has an explicit type specified.
530 std::map<std::pair<unsigned, MVT::SimpleValueType>,
531 MVT::SimpleValueType>::const_iterator PTTI =
532 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
533 if (PTTI != PromoteToType.end()) return PTTI->second;
535 assert((VT.isInteger() || VT.isFloatingPoint()) &&
536 "Cannot autopromote this type, add it with AddPromotedToType.");
540 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
541 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
542 "Didn't find type to promote to!");
543 } while (!isTypeLegal(NVT) ||
544 getOperationAction(Op, NVT) == Promote);
548 /// getValueType - Return the EVT corresponding to this LLVM type.
549 /// This is fixed by the LLVM operations except for the pointer size. If
550 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
551 /// counterpart (e.g. structs), otherwise it will assert.
552 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
553 EVT VT = EVT::getEVT(Ty, AllowUnknown);
554 return VT == MVT:: iPTR ? PointerTy : VT;
557 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
558 /// function arguments in the caller parameter area. This is the actual
559 /// alignment, not its logarithm.
560 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
562 /// getRegisterType - Return the type of registers that this ValueType will
563 /// eventually require.
564 EVT getRegisterType(MVT VT) const {
565 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
566 return RegisterTypeForVT[VT.SimpleTy];
569 /// getRegisterType - Return the type of registers that this ValueType will
570 /// eventually require.
571 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
573 assert((unsigned)VT.getSimpleVT().SimpleTy <
574 array_lengthof(RegisterTypeForVT));
575 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
579 unsigned NumIntermediates;
580 (void)getVectorTypeBreakdown(Context, VT, VT1,
581 NumIntermediates, RegisterVT);
584 if (VT.isInteger()) {
585 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
587 assert(0 && "Unsupported extended type!");
588 return EVT(MVT::Other); // Not reached
591 /// getNumRegisters - Return the number of registers that this ValueType will
592 /// eventually require. This is one for any types promoted to live in larger
593 /// registers, but may be more than one for types (like i64) that are split
594 /// into pieces. For types like i140, which are first promoted then expanded,
595 /// it is the number of registers needed to hold all the bits of the original
596 /// type. For an i140 on a 32 bit machine this means 5 registers.
597 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
599 assert((unsigned)VT.getSimpleVT().SimpleTy <
600 array_lengthof(NumRegistersForVT));
601 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
605 unsigned NumIntermediates;
606 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
608 if (VT.isInteger()) {
609 unsigned BitWidth = VT.getSizeInBits();
610 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
611 return (BitWidth + RegWidth - 1) / RegWidth;
613 assert(0 && "Unsupported extended type!");
614 return 0; // Not reached
617 /// ShouldShrinkFPConstant - If true, then instruction selection should
618 /// seek to shrink the FP constant of the specified type to a smaller type
619 /// in order to save space and / or reduce runtime.
620 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
622 /// hasTargetDAGCombine - If true, the target has custom DAG combine
623 /// transformations that it can perform for the specified node.
624 bool hasTargetDAGCombine(ISD::NodeType NT) const {
625 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
626 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
629 /// This function returns the maximum number of store operations permitted
630 /// to replace a call to llvm.memset. The value is set by the target at the
631 /// performance threshold for such a replacement.
632 /// @brief Get maximum # of store operations permitted for llvm.memset
633 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
635 /// This function returns the maximum number of store operations permitted
636 /// to replace a call to llvm.memcpy. The value is set by the target at the
637 /// performance threshold for such a replacement.
638 /// @brief Get maximum # of store operations permitted for llvm.memcpy
639 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
641 /// This function returns the maximum number of store operations permitted
642 /// to replace a call to llvm.memmove. The value is set by the target at the
643 /// performance threshold for such a replacement.
644 /// @brief Get maximum # of store operations permitted for llvm.memmove
645 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
647 /// This function returns true if the target allows unaligned memory accesses.
648 /// of the specified type. This is used, for example, in situations where an
649 /// array copy/move/set is converted to a sequence of store operations. It's
650 /// use helps to ensure that such replacements don't generate code that causes
651 /// an alignment error (trap) on the target machine.
652 /// @brief Determine if the target supports unaligned memory accesses.
653 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
657 /// This function returns true if the target would benefit from code placement
659 /// @brief Determine if the target should perform code placement optimization.
660 bool shouldOptimizeCodePlacement() const {
661 return benefitFromCodePlacementOpt;
664 /// getOptimalMemOpType - Returns the target specific optimal type for load
665 /// and store operations as a result of memset, memcpy, and memmove lowering.
666 /// It returns EVT::iAny if SelectionDAG should be responsible for
668 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
669 bool isSrcConst, bool isSrcStr,
670 SelectionDAG &DAG) const {
674 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
675 /// to implement llvm.setjmp.
676 bool usesUnderscoreSetJmp() const {
677 return UseUnderscoreSetJmp;
680 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
681 /// to implement llvm.longjmp.
682 bool usesUnderscoreLongJmp() const {
683 return UseUnderscoreLongJmp;
686 /// getStackPointerRegisterToSaveRestore - If a physical register, this
687 /// specifies the register that llvm.savestack/llvm.restorestack should save
689 unsigned getStackPointerRegisterToSaveRestore() const {
690 return StackPointerRegisterToSaveRestore;
693 /// getExceptionAddressRegister - If a physical register, this returns
694 /// the register that receives the exception address on entry to a landing
696 unsigned getExceptionAddressRegister() const {
697 return ExceptionPointerRegister;
700 /// getExceptionSelectorRegister - If a physical register, this returns
701 /// the register that receives the exception typeid on entry to a landing
703 unsigned getExceptionSelectorRegister() const {
704 return ExceptionSelectorRegister;
707 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
708 /// set, the default is 200)
709 unsigned getJumpBufSize() const {
713 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
714 /// (if never set, the default is 0)
715 unsigned getJumpBufAlignment() const {
716 return JumpBufAlignment;
719 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
720 /// limit. Any block whose size is greater should not be predicated.
721 unsigned getIfCvtBlockSizeLimit() const {
722 return IfCvtBlockSizeLimit;
725 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
726 /// block to be considered for duplication. Any block whose size is greater
727 /// should not be duplicated to facilitate its predication.
728 unsigned getIfCvtDupBlockSizeLimit() const {
729 return IfCvtDupBlockSizeLimit;
732 /// getPrefLoopAlignment - return the preferred loop alignment.
734 unsigned getPrefLoopAlignment() const {
735 return PrefLoopAlignment;
738 /// getPreIndexedAddressParts - returns true by value, base pointer and
739 /// offset pointer and addressing mode by reference if the node's address
740 /// can be legally represented as pre-indexed load / store address.
741 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
743 ISD::MemIndexedMode &AM,
744 SelectionDAG &DAG) const {
748 /// getPostIndexedAddressParts - returns true by value, base pointer and
749 /// offset pointer and addressing mode by reference if this node can be
750 /// combined with a load / store to form a post-indexed load / store.
751 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
752 SDValue &Base, SDValue &Offset,
753 ISD::MemIndexedMode &AM,
754 SelectionDAG &DAG) const {
758 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
759 /// current function. The returned value is a member of the
760 /// MachineJumpTableInfo::JTEntryKind enum.
761 virtual unsigned getJumpTableEncoding() const;
763 virtual const MCExpr *
764 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
765 const MachineBasicBlock *MBB, unsigned uid,
766 MCContext &Ctx) const {
767 assert(0 && "Need to implement this hook if target has custom JTIs");
770 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
772 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
773 SelectionDAG &DAG) const;
775 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
776 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
778 virtual const MCExpr *
779 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
780 unsigned JTI, MCContext &Ctx) const;
782 /// isOffsetFoldingLegal - Return true if folding a constant offset
783 /// with the given GlobalAddress is legal. It is frequently not legal in
784 /// PIC relocation models.
785 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
787 /// getFunctionAlignment - Return the Log2 alignment of this function.
788 virtual unsigned getFunctionAlignment(const Function *) const = 0;
790 //===--------------------------------------------------------------------===//
791 // TargetLowering Optimization Methods
794 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
795 /// SDValues for returning information from TargetLowering to its clients
796 /// that want to combine
797 struct TargetLoweringOpt {
803 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) :
804 DAG(InDAG), ShrinkOps(Shrink) {}
806 bool CombineTo(SDValue O, SDValue N) {
812 /// ShrinkDemandedConstant - Check to see if the specified operand of the
813 /// specified instruction is a constant integer. If so, check to see if
814 /// there are any bits set in the constant that are not demanded. If so,
815 /// shrink the constant and return true.
816 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
818 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
819 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
820 /// cast, but it could be generalized for targets with other types of
821 /// implicit widening casts.
822 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
826 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
827 /// DemandedMask bits of the result of Op are ever used downstream. If we can
828 /// use this information to simplify Op, create a new simplified DAG node and
829 /// return true, returning the original and new nodes in Old and New.
830 /// Otherwise, analyze the expression and return a mask of KnownOne and
831 /// KnownZero bits for the expression (used to simplify the caller).
832 /// The KnownZero/One bits may only be accurate for those bits in the
834 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
835 APInt &KnownZero, APInt &KnownOne,
836 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
838 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
839 /// Mask are known to be either zero or one and return them in the
840 /// KnownZero/KnownOne bitsets.
841 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
845 const SelectionDAG &DAG,
846 unsigned Depth = 0) const;
848 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
849 /// targets that want to expose additional information about sign bits to the
851 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
852 unsigned Depth = 0) const;
854 struct DAGCombinerInfo {
855 void *DC; // The DAG Combiner object.
857 bool BeforeLegalizeOps;
858 bool CalledByLegalizer;
862 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
863 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
864 CalledByLegalizer(cl), DAG(dag) {}
866 bool isBeforeLegalize() const { return BeforeLegalize; }
867 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
868 bool isCalledByLegalizer() const { return CalledByLegalizer; }
870 void AddToWorklist(SDNode *N);
871 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
873 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
874 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
876 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
879 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
880 /// and cc. If it is unable to simplify it, return a null SDValue.
881 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
882 ISD::CondCode Cond, bool foldBooleans,
883 DAGCombinerInfo &DCI, DebugLoc dl) const;
885 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
886 /// node is a GlobalAddress + offset.
888 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
890 /// PerformDAGCombine - This method will be invoked for all target nodes and
891 /// for any target-independent nodes that the target has registered with
894 /// The semantics are as follows:
896 /// SDValue.Val == 0 - No change was made
897 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
898 /// otherwise - N should be replaced by the returned Operand.
900 /// In addition, methods provided by DAGCombinerInfo may be used to perform
901 /// more complex transformations.
903 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
905 //===--------------------------------------------------------------------===//
906 // TargetLowering Configuration Methods - These methods should be invoked by
907 // the derived class constructor to configure this object for the target.
911 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
912 /// GOT for PC-relative code.
913 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
915 /// setShiftAmountType - Describe the type that should be used for shift
916 /// amounts. This type defaults to the pointer type.
917 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
919 /// setBooleanContents - Specify how the target extends the result of a
920 /// boolean value from i1 to a wider type. See getBooleanContents.
921 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
923 /// setSchedulingPreference - Specify the target scheduling preference.
924 void setSchedulingPreference(SchedPreference Pref) {
925 SchedPreferenceInfo = Pref;
928 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
929 /// use _setjmp to implement llvm.setjmp or the non _ version.
930 /// Defaults to false.
931 void setUseUnderscoreSetJmp(bool Val) {
932 UseUnderscoreSetJmp = Val;
935 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
936 /// use _longjmp to implement llvm.longjmp or the non _ version.
937 /// Defaults to false.
938 void setUseUnderscoreLongJmp(bool Val) {
939 UseUnderscoreLongJmp = Val;
942 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
943 /// specifies the register that llvm.savestack/llvm.restorestack should save
945 void setStackPointerRegisterToSaveRestore(unsigned R) {
946 StackPointerRegisterToSaveRestore = R;
949 /// setExceptionPointerRegister - If set to a physical register, this sets
950 /// the register that receives the exception address on entry to a landing
952 void setExceptionPointerRegister(unsigned R) {
953 ExceptionPointerRegister = R;
956 /// setExceptionSelectorRegister - If set to a physical register, this sets
957 /// the register that receives the exception typeid on entry to a landing
959 void setExceptionSelectorRegister(unsigned R) {
960 ExceptionSelectorRegister = R;
963 /// SelectIsExpensive - Tells the code generator not to expand operations
964 /// into sequences that use the select operations if possible.
965 void setSelectIsExpensive() { SelectIsExpensive = true; }
967 /// setIntDivIsCheap - Tells the code generator that integer divide is
968 /// expensive, and if possible, should be replaced by an alternate sequence
969 /// of instructions not containing an integer divide.
970 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
972 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
973 /// srl/add/sra for a signed divide by power of two, and let the target handle
975 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
977 /// addRegisterClass - Add the specified register class as an available
978 /// regclass for the specified value type. This indicates the selector can
979 /// handle values of that class natively.
980 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
981 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
982 AvailableRegClasses.push_back(std::make_pair(VT, RC));
983 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
986 /// computeRegisterProperties - Once all of the register classes are added,
987 /// this allows us to compute derived properties we expose.
988 void computeRegisterProperties();
990 /// setOperationAction - Indicate that the specified operation does not work
991 /// with the specified type and indicate what to do about it.
992 void setOperationAction(unsigned Op, MVT VT,
993 LegalizeAction Action) {
994 unsigned I = (unsigned)VT.SimpleTy;
997 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
998 OpActions[I][Op] |= (uint64_t)Action << (J*2);
1001 /// setLoadExtAction - Indicate that the specified load with extension does
1002 /// not work with the with specified type and indicate what to do about it.
1003 void setLoadExtAction(unsigned ExtType, MVT VT,
1004 LegalizeAction Action) {
1005 assert((unsigned)VT.SimpleTy*2 < 63 &&
1006 ExtType < array_lengthof(LoadExtActions) &&
1007 "Table isn't big enough!");
1008 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1009 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
1012 /// setTruncStoreAction - Indicate that the specified truncating store does
1013 /// not work with the with specified type and indicate what to do about it.
1014 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1015 LegalizeAction Action) {
1016 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
1017 (unsigned)MemVT.SimpleTy*2 < 63 &&
1018 "Table isn't big enough!");
1019 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
1020 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
1023 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1024 /// does not work with the with specified type and indicate what to do abort
1025 /// it. NOTE: All indexed mode loads are initialized to Expand in
1026 /// TargetLowering.cpp
1027 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1028 LegalizeAction Action) {
1029 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1030 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1031 "Table isn't big enough!");
1032 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1035 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1036 /// does not work with the with specified type and indicate what to do about
1037 /// it. NOTE: All indexed mode stores are initialized to Expand in
1038 /// TargetLowering.cpp
1039 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1040 LegalizeAction Action) {
1041 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1042 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1043 "Table isn't big enough!");
1044 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1047 /// setConvertAction - Indicate that the specified conversion does or does
1048 /// not work with the with specified type and indicate what to do about it.
1049 void setConvertAction(MVT FromVT, MVT ToVT,
1050 LegalizeAction Action) {
1051 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1052 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
1053 "Table isn't big enough!");
1054 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1055 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
1058 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1059 /// supported on the target and indicate what to do about it.
1060 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1061 LegalizeAction Action) {
1062 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1063 (unsigned)CC < array_lengthof(CondCodeActions) &&
1064 "Table isn't big enough!");
1065 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1066 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1069 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1070 /// promotion code defaults to trying a larger integer/fp until it can find
1071 /// one that works. If that default is insufficient, this method can be used
1072 /// by the target to override the default.
1073 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1074 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1077 /// setTargetDAGCombine - Targets should invoke this method for each target
1078 /// independent node that they want to provide a custom DAG combiner for by
1079 /// implementing the PerformDAGCombine virtual method.
1080 void setTargetDAGCombine(ISD::NodeType NT) {
1081 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1082 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1085 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1086 /// bytes); default is 200
1087 void setJumpBufSize(unsigned Size) {
1091 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1092 /// alignment (in bytes); default is 0
1093 void setJumpBufAlignment(unsigned Align) {
1094 JumpBufAlignment = Align;
1097 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1098 /// limit (in number of instructions); default is 2.
1099 void setIfCvtBlockSizeLimit(unsigned Limit) {
1100 IfCvtBlockSizeLimit = Limit;
1103 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1104 /// of instructions) to be considered for code duplication during
1105 /// if-conversion; default is 2.
1106 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1107 IfCvtDupBlockSizeLimit = Limit;
1110 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1111 /// alignment is zero, it means the target does not care about loop alignment.
1112 void setPrefLoopAlignment(unsigned Align) {
1113 PrefLoopAlignment = Align;
1118 virtual const TargetSubtarget *getSubtarget() {
1119 assert(0 && "Not Implemented");
1120 return NULL; // this is here to silence compiler errors
1123 //===--------------------------------------------------------------------===//
1124 // Lowering methods - These methods must be implemented by targets so that
1125 // the SelectionDAGLowering code knows how to lower these.
1128 /// LowerFormalArguments - This hook must be implemented to lower the
1129 /// incoming (formal) arguments, described by the Ins array, into the
1130 /// specified DAG. The implementation should fill in the InVals array
1131 /// with legal-type argument values, and return the resulting token
1135 LowerFormalArguments(SDValue Chain,
1136 CallingConv::ID CallConv, bool isVarArg,
1137 const SmallVectorImpl<ISD::InputArg> &Ins,
1138 DebugLoc dl, SelectionDAG &DAG,
1139 SmallVectorImpl<SDValue> &InVals) {
1140 assert(0 && "Not Implemented");
1141 return SDValue(); // this is here to silence compiler errors
1144 /// LowerCallTo - This function lowers an abstract call to a function into an
1145 /// actual call. This returns a pair of operands. The first element is the
1146 /// return value for the function (if RetTy is not VoidTy). The second
1147 /// element is the outgoing token chain. It calls LowerCall to do the actual
1149 struct ArgListEntry {
1160 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1161 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1163 typedef std::vector<ArgListEntry> ArgListTy;
1164 std::pair<SDValue, SDValue>
1165 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1166 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1167 CallingConv::ID CallConv, bool isTailCall,
1168 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1169 SelectionDAG &DAG, DebugLoc dl, unsigned Order);
1171 /// LowerCall - This hook must be implemented to lower calls into the
1172 /// the specified DAG. The outgoing arguments to the call are described
1173 /// by the Outs array, and the values to be returned by the call are
1174 /// described by the Ins array. The implementation should fill in the
1175 /// InVals array with legal-type return values from the call, and return
1176 /// the resulting token chain value.
1178 /// The isTailCall flag here is normative. If it is true, the
1179 /// implementation must emit a tail call. The
1180 /// IsEligibleForTailCallOptimization hook should be used to catch
1181 /// cases that cannot be handled.
1184 LowerCall(SDValue Chain, SDValue Callee,
1185 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
1186 const SmallVectorImpl<ISD::OutputArg> &Outs,
1187 const SmallVectorImpl<ISD::InputArg> &Ins,
1188 DebugLoc dl, SelectionDAG &DAG,
1189 SmallVectorImpl<SDValue> &InVals) {
1190 assert(0 && "Not Implemented");
1191 return SDValue(); // this is here to silence compiler errors
1194 /// CanLowerReturn - This hook should be implemented to check whether the
1195 /// return values described by the Outs array can fit into the return
1196 /// registers. If false is returned, an sret-demotion is performed.
1198 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1199 const SmallVectorImpl<EVT> &OutTys,
1200 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1203 // Return true by default to get preexisting behavior.
1206 /// LowerReturn - This hook must be implemented to lower outgoing
1207 /// return values, described by the Outs array, into the specified
1208 /// DAG. The implementation should return the resulting token chain
1212 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1213 const SmallVectorImpl<ISD::OutputArg> &Outs,
1214 DebugLoc dl, SelectionDAG &DAG) {
1215 assert(0 && "Not Implemented");
1216 return SDValue(); // this is here to silence compiler errors
1219 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1220 /// memcpy. This can be used by targets to provide code sequences for cases
1221 /// that don't fit the target's parameters for simple loads/stores and can be
1222 /// more efficient than using a library call. This function can return a null
1223 /// SDValue if the target declines to use custom code and a different
1224 /// lowering strategy should be used.
1226 /// If AlwaysInline is true, the size is constant and the target should not
1227 /// emit any calls and is strongly encouraged to attempt to emit inline code
1228 /// even if it is beyond the usual threshold because this intrinsic is being
1229 /// expanded in a place where calls are not feasible (e.g. within the prologue
1230 /// for another call). If the target chooses to decline an AlwaysInline
1231 /// request here, legalize will resort to using simple loads and stores.
1233 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1235 SDValue Op1, SDValue Op2,
1236 SDValue Op3, unsigned Align,
1238 const Value *DstSV, uint64_t DstOff,
1239 const Value *SrcSV, uint64_t SrcOff) {
1243 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1244 /// memmove. This can be used by targets to provide code sequences for cases
1245 /// that don't fit the target's parameters for simple loads/stores and can be
1246 /// more efficient than using a library call. This function can return a null
1247 /// SDValue if the target declines to use custom code and a different
1248 /// lowering strategy should be used.
1250 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1252 SDValue Op1, SDValue Op2,
1253 SDValue Op3, unsigned Align,
1254 const Value *DstSV, uint64_t DstOff,
1255 const Value *SrcSV, uint64_t SrcOff) {
1259 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1260 /// memset. This can be used by targets to provide code sequences for cases
1261 /// that don't fit the target's parameters for simple stores and can be more
1262 /// efficient than using a library call. This function can return a null
1263 /// SDValue if the target declines to use custom code and a different
1264 /// lowering strategy should be used.
1266 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1268 SDValue Op1, SDValue Op2,
1269 SDValue Op3, unsigned Align,
1270 const Value *DstSV, uint64_t DstOff) {
1274 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1275 /// to legalize nodes with an illegal operand type but legal result types.
1276 /// It replaces the LowerOperation callback in the type Legalizer.
1277 /// The reason we can not do away with LowerOperation entirely is that
1278 /// LegalizeDAG isn't yet ready to use this callback.
1279 /// TODO: Consider merging with ReplaceNodeResults.
1281 /// The target places new result values for the node in Results (their number
1282 /// and types must exactly match those of the original return values of
1283 /// the node), or leaves Results empty, which indicates that the node is not
1284 /// to be custom lowered after all.
1285 /// The default implementation calls LowerOperation.
1286 virtual void LowerOperationWrapper(SDNode *N,
1287 SmallVectorImpl<SDValue> &Results,
1290 /// LowerOperation - This callback is invoked for operations that are
1291 /// unsupported by the target, which are registered to use 'custom' lowering,
1292 /// and whose defined values are all legal.
1293 /// If the target has no operations that require custom lowering, it need not
1294 /// implement this. The default implementation of this aborts.
1295 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1297 /// ReplaceNodeResults - This callback is invoked when a node result type is
1298 /// illegal for the target, and the operation was registered to use 'custom'
1299 /// lowering for that result type. The target places new result values for
1300 /// the node in Results (their number and types must exactly match those of
1301 /// the original return values of the node), or leaves Results empty, which
1302 /// indicates that the node is not to be custom lowered after all.
1304 /// If the target has no operations that require custom lowering, it need not
1305 /// implement this. The default implementation aborts.
1306 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1307 SelectionDAG &DAG) {
1308 assert(0 && "ReplaceNodeResults not implemented for this target!");
1311 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1312 /// tail call optimization. Targets which want to do tail call optimization
1313 /// should override this function.
1315 IsEligibleForTailCallOptimization(SDValue Callee,
1316 CallingConv::ID CalleeCC,
1318 const SmallVectorImpl<ISD::InputArg> &Ins,
1319 SelectionDAG& DAG) const {
1320 // Conservative default: no calls are eligible.
1324 /// getTargetNodeName() - This method returns the name of a target specific
1326 virtual const char *getTargetNodeName(unsigned Opcode) const;
1328 /// createFastISel - This method returns a target specific FastISel object,
1329 /// or null if the target does not support "fast" ISel.
1331 createFastISel(MachineFunction &,
1332 MachineModuleInfo *, DwarfWriter *,
1333 DenseMap<const Value *, unsigned> &,
1334 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1335 DenseMap<const AllocaInst *, int> &
1337 , SmallSet<Instruction*, 8> &CatchInfoLost
1343 //===--------------------------------------------------------------------===//
1344 // Inline Asm Support hooks
1347 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1348 /// call to be explicit llvm code if it wants to. This is useful for
1349 /// turning simple inline asms into LLVM intrinsics, which gives the
1350 /// compiler more information about the behavior of the code.
1351 virtual bool ExpandInlineAsm(CallInst *CI) const {
1355 enum ConstraintType {
1356 C_Register, // Constraint represents specific register(s).
1357 C_RegisterClass, // Constraint represents any of register(s) in class.
1358 C_Memory, // Memory constraint.
1359 C_Other, // Something else.
1360 C_Unknown // Unsupported constraint.
1363 /// AsmOperandInfo - This contains information for each constraint that we are
1365 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1366 /// ConstraintCode - This contains the actual string for the code, like "m".
1367 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1368 /// most closely matches the operand.
1369 std::string ConstraintCode;
1371 /// ConstraintType - Information about the constraint code, e.g. Register,
1372 /// RegisterClass, Memory, Other, Unknown.
1373 TargetLowering::ConstraintType ConstraintType;
1375 /// CallOperandval - If this is the result output operand or a
1376 /// clobber, this is null, otherwise it is the incoming operand to the
1377 /// CallInst. This gets modified as the asm is processed.
1378 Value *CallOperandVal;
1380 /// ConstraintVT - The ValueType for the operand value.
1383 /// isMatchingInputConstraint - Return true of this is an input operand that
1384 /// is a matching constraint like "4".
1385 bool isMatchingInputConstraint() const;
1387 /// getMatchedOperand - If this is an input matching constraint, this method
1388 /// returns the output operand it matches.
1389 unsigned getMatchedOperand() const;
1391 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1392 : InlineAsm::ConstraintInfo(info),
1393 ConstraintType(TargetLowering::C_Unknown),
1394 CallOperandVal(0), ConstraintVT(MVT::Other) {
1398 /// ComputeConstraintToUse - Determines the constraint code and constraint
1399 /// type to use for the specific AsmOperandInfo, setting
1400 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1401 /// being passed in is available, it can be passed in as Op, otherwise an
1402 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1403 /// constraint of the inline asm instruction being processed is 'm'.
1404 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1407 SelectionDAG *DAG = 0) const;
1409 /// getConstraintType - Given a constraint, return the type of constraint it
1410 /// is for this target.
1411 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1413 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1414 /// return a list of registers that can be used to satisfy the constraint.
1415 /// This should only be used for C_RegisterClass constraints.
1416 virtual std::vector<unsigned>
1417 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1420 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1421 /// {edx}), return the register number and the register class for the
1424 /// Given a register class constraint, like 'r', if this corresponds directly
1425 /// to an LLVM register class, return a register of 0 and the register class
1428 /// This should only be used for C_Register constraints. On error,
1429 /// this returns a register number of 0 and a null register class pointer..
1430 virtual std::pair<unsigned, const TargetRegisterClass*>
1431 getRegForInlineAsmConstraint(const std::string &Constraint,
1434 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1435 /// with another that has more specific requirements based on the type of the
1436 /// corresponding operand. This returns null if there is no replacement to
1438 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1440 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1441 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1442 /// it means one of the asm constraint of the inline asm instruction being
1443 /// processed is 'm'.
1444 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1446 std::vector<SDValue> &Ops,
1447 SelectionDAG &DAG) const;
1449 //===--------------------------------------------------------------------===//
1450 // Instruction Emitting Hooks
1453 // EmitInstrWithCustomInserter - This method should be implemented by targets
1454 // that mark instructions with the 'usesCustomInserter' flag. These
1455 // instructions are special in various ways, which require special support to
1456 // insert. The specified MachineInstr is created but not inserted into any
1457 // basic blocks, and this method is called to expand it into a sequence of
1458 // instructions, potentially also creating new basic blocks and control flow.
1459 // When new basic blocks are inserted and the edges from MBB to its successors
1460 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1462 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1463 MachineBasicBlock *MBB,
1464 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1466 //===--------------------------------------------------------------------===//
1467 // Addressing mode description hooks (used by LSR etc).
1470 /// AddrMode - This represents an addressing mode of:
1471 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1472 /// If BaseGV is null, there is no BaseGV.
1473 /// If BaseOffs is zero, there is no base offset.
1474 /// If HasBaseReg is false, there is no base register.
1475 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1479 GlobalValue *BaseGV;
1483 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1486 /// isLegalAddressingMode - Return true if the addressing mode represented by
1487 /// AM is legal for this target, for a load/store of the specified type.
1488 /// The type may be VoidTy, in which case only return true if the addressing
1489 /// mode is legal for a load/store of any legal type.
1490 /// TODO: Handle pre/postinc as well.
1491 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1493 /// isTruncateFree - Return true if it's free to truncate a value of
1494 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1495 /// register EAX to i16 by referencing its sub-register AX.
1496 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1500 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1504 /// isZExtFree - Return true if any actual instruction that defines a
1505 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1506 /// register. This does not necessarily include registers defined in
1507 /// unknown ways, such as incoming arguments, or copies from unknown
1508 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1509 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1510 /// all instructions that define 32-bit values implicit zero-extend the
1511 /// result out to 64 bits.
1512 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1516 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1520 /// isNarrowingProfitable - Return true if it's profitable to narrow
1521 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1522 /// from i32 to i8 but not from i32 to i16.
1523 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1527 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1528 /// icmp immediate, that is the target has icmp instructions which can compare
1529 /// a register against the immediate without having to materialize the
1530 /// immediate into a register.
1531 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1535 //===--------------------------------------------------------------------===//
1536 // Div utility functions
1538 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1539 std::vector<SDNode*>* Created) const;
1540 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1541 std::vector<SDNode*>* Created) const;
1544 //===--------------------------------------------------------------------===//
1545 // Runtime Library hooks
1548 /// setLibcallName - Rename the default libcall routine name for the specified
1550 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1551 LibcallRoutineNames[Call] = Name;
1554 /// getLibcallName - Get the libcall routine name for the specified libcall.
1556 const char *getLibcallName(RTLIB::Libcall Call) const {
1557 return LibcallRoutineNames[Call];
1560 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1561 /// result of the comparison libcall against zero.
1562 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1563 CmpLibcallCCs[Call] = CC;
1566 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1567 /// the comparison libcall against zero.
1568 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1569 return CmpLibcallCCs[Call];
1572 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1573 /// specified libcall.
1574 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1575 LibcallCallingConvs[Call] = CC;
1578 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1579 /// specified libcall.
1580 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1581 return LibcallCallingConvs[Call];
1586 const TargetData *TD;
1587 TargetLoweringObjectFile &TLOF;
1589 /// PointerTy - The type to use for pointers, usually i32 or i64.
1593 /// IsLittleEndian - True if this is a little endian target.
1595 bool IsLittleEndian;
1597 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1599 bool UsesGlobalOffsetTable;
1601 /// SelectIsExpensive - Tells the code generator not to expand operations
1602 /// into sequences that use the select operations if possible.
1603 bool SelectIsExpensive;
1605 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1606 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1607 /// a real cost model is in place. If we ever optimize for size, this will be
1608 /// set to true unconditionally.
1611 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1612 /// srl/add/sra for a signed divide by power of two, and let the target handle
1614 bool Pow2DivIsCheap;
1616 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1617 /// llvm.setjmp. Defaults to false.
1618 bool UseUnderscoreSetJmp;
1620 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1621 /// llvm.longjmp. Defaults to false.
1622 bool UseUnderscoreLongJmp;
1624 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1628 /// BooleanContents - Information about the contents of the high-bits in
1629 /// boolean values held in a type wider than i1. See getBooleanContents.
1630 BooleanContent BooleanContents;
1632 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1633 /// total cycles or lowest register usage.
1634 SchedPreference SchedPreferenceInfo;
1636 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1637 unsigned JumpBufSize;
1639 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1641 unsigned JumpBufAlignment;
1643 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1645 unsigned IfCvtBlockSizeLimit;
1647 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1648 /// duplicated during if-conversion.
1649 unsigned IfCvtDupBlockSizeLimit;
1651 /// PrefLoopAlignment - The perferred loop alignment.
1653 unsigned PrefLoopAlignment;
1655 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1656 /// specifies the register that llvm.savestack/llvm.restorestack should save
1658 unsigned StackPointerRegisterToSaveRestore;
1660 /// ExceptionPointerRegister - If set to a physical register, this specifies
1661 /// the register that receives the exception address on entry to a landing
1663 unsigned ExceptionPointerRegister;
1665 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1666 /// the register that receives the exception typeid on entry to a landing
1668 unsigned ExceptionSelectorRegister;
1670 /// RegClassForVT - This indicates the default register class to use for
1671 /// each ValueType the target supports natively.
1672 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1673 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1674 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1676 /// TransformToType - For any value types we are promoting or expanding, this
1677 /// contains the value type that we are changing to. For Expanded types, this
1678 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1679 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1680 /// by the system, this holds the same type (e.g. i32 -> i32).
1681 EVT TransformToType[MVT::LAST_VALUETYPE];
1683 /// OpActions - For each operation and each value type, keep a LegalizeAction
1684 /// that indicates how instruction selection should deal with the operation.
1685 /// Most operations are Legal (aka, supported natively by the target), but
1686 /// operations that are not should be described. Note that operations on
1687 /// non-legal value types are not described here.
1688 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1689 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1690 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1692 /// LoadExtActions - For each load of load extension type and each value type,
1693 /// keep a LegalizeAction that indicates how instruction selection should deal
1695 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1697 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1698 /// indicates how instruction selection should deal with the store.
1699 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1701 /// IndexedModeActions - For each indexed mode and each value type,
1702 /// keep a pair of LegalizeAction that indicates how instruction
1703 /// selection should deal with the load / store. The first
1704 /// dimension is now the value_type for the reference. The second
1705 /// dimension is the load [0] vs. store[1]. The third dimension
1706 /// represents the various modes for load store.
1707 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1709 /// ConvertActions - For each conversion from source type to destination type,
1710 /// keep a LegalizeAction that indicates how instruction selection should
1711 /// deal with the conversion.
1712 /// Currently, this is used only for floating->floating conversions
1713 /// (FP_EXTEND and FP_ROUND).
1714 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1716 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1717 /// LegalizeAction that indicates how instruction selection should
1718 /// deal with the condition code.
1719 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1721 ValueTypeActionImpl ValueTypeActions;
1723 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1725 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1726 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1727 /// which sets a bit in this array.
1729 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1731 /// PromoteToType - For operations that must be promoted to a specific type,
1732 /// this holds the destination type. This map should be sparse, so don't hold
1735 /// Targets add entries to this map with AddPromotedToType(..), clients access
1736 /// this with getTypeToPromoteTo(..).
1737 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1740 /// LibcallRoutineNames - Stores the name each libcall.
1742 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1744 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1745 /// of each of the comparison libcall against zero.
1746 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1748 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1750 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1753 /// When lowering \@llvm.memset this field specifies the maximum number of
1754 /// store operations that may be substituted for the call to memset. Targets
1755 /// must set this value based on the cost threshold for that target. Targets
1756 /// should assume that the memset will be done using as many of the largest
1757 /// store operations first, followed by smaller ones, if necessary, per
1758 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1759 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1760 /// store. This only applies to setting a constant array of a constant size.
1761 /// @brief Specify maximum number of store instructions per memset call.
1762 unsigned maxStoresPerMemset;
1764 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1765 /// store operations that may be substituted for a call to memcpy. Targets
1766 /// must set this value based on the cost threshold for that target. Targets
1767 /// should assume that the memcpy will be done using as many of the largest
1768 /// store operations first, followed by smaller ones, if necessary, per
1769 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1770 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1771 /// and one 1-byte store. This only applies to copying a constant array of
1773 /// @brief Specify maximum bytes of store instructions per memcpy call.
1774 unsigned maxStoresPerMemcpy;
1776 /// When lowering \@llvm.memmove this field specifies the maximum number of
1777 /// store instructions that may be substituted for a call to memmove. Targets
1778 /// must set this value based on the cost threshold for that target. Targets
1779 /// should assume that the memmove will be done using as many of the largest
1780 /// store operations first, followed by smaller ones, if necessary, per
1781 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1782 /// with 8-bit alignment would result in nine 1-byte stores. This only
1783 /// applies to copying a constant array of constant size.
1784 /// @brief Specify maximum bytes of store instructions per memmove call.
1785 unsigned maxStoresPerMemmove;
1787 /// This field specifies whether the target can benefit from code placement
1789 bool benefitFromCodePlacementOpt;
1791 } // end llvm namespace