1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 class TargetRegisterClass;
38 class MachineBasicBlock;
41 //===----------------------------------------------------------------------===//
42 /// TargetLowering - This class defines information used to lower LLVM code to
43 /// legal SelectionDAG operators that the target instruction selector can accept
46 /// This class also defines callbacks that targets must implement to lower
47 /// target-specific constructs to SelectionDAG operators.
49 class TargetLowering {
51 /// LegalizeAction - This enum indicates whether operations are valid for a
52 /// target, and if not, what action should be used to make them valid.
54 Legal, // The target natively supports this operation.
55 Promote, // This operation should be executed in a larger type.
56 Expand, // Try to expand this to other ops, otherwise use a libcall.
57 Custom // Use the LowerOperation hook to implement custom lowering.
60 enum OutOfRangeShiftAmount {
61 Undefined, // Oversized shift amounts are undefined (default).
62 Mask, // Shift amounts are auto masked (anded) to value size.
63 Extend // Oversized shift pulls in zeros or sign bits.
66 enum SetCCResultValue {
67 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
68 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
69 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
72 enum SchedPreference {
73 SchedulingForLatency, // Scheduling for shortest total latency.
74 SchedulingForRegPressure // Scheduling for lowest register pressure.
77 TargetLowering(TargetMachine &TM);
78 virtual ~TargetLowering();
80 TargetMachine &getTargetMachine() const { return TM; }
81 const TargetData *getTargetData() const { return TD; }
83 bool isLittleEndian() const { return IsLittleEndian; }
84 MVT::ValueType getPointerTy() const { return PointerTy; }
85 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
86 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
88 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
90 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
92 /// isSetCCExpensive - Return true if the setcc operation is expensive for
94 bool isSetCCExpensive() const { return SetCCIsExpensive; }
96 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
97 /// a sequence of several shifts, adds, and multiplies for this target.
98 bool isIntDivCheap() const { return IntDivIsCheap; }
100 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
102 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
104 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
106 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
108 /// getSetCCResultContents - For targets without boolean registers, this flag
109 /// returns information about the contents of the high-bits in the setcc
111 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
113 /// getSchedulingPreference - Return target scheduling preference.
114 SchedPreference getSchedulingPreference() const {
115 return SchedPreferenceInfo;
118 /// getRegClassFor - Return the register class that should be used for the
119 /// specified value type. This may only be called on legal types.
120 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
121 TargetRegisterClass *RC = RegClassForVT[VT];
122 assert(RC && "This value type is not natively supported!");
126 /// isTypeLegal - Return true if the target has native support for the
127 /// specified value type. This means that it has a register that directly
128 /// holds it without promotions or expansions.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return RegClassForVT[VT] != 0;
133 class ValueTypeActionImpl {
134 /// ValueTypeActions - This is a bitvector that contains two bits for each
135 /// value type, where the two bits correspond to the LegalizeAction enum.
136 /// This can be queried with "getTypeAction(VT)".
137 uint32_t ValueTypeActions[2];
139 ValueTypeActionImpl() {
140 ValueTypeActions[0] = ValueTypeActions[1] = 0;
142 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
143 ValueTypeActions[0] = RHS.ValueTypeActions[0];
144 ValueTypeActions[1] = RHS.ValueTypeActions[1];
147 LegalizeAction getTypeAction(MVT::ValueType VT) const {
148 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
150 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
151 assert(unsigned(VT >> 4) <
152 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
153 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
157 const ValueTypeActionImpl &getValueTypeActions() const {
158 return ValueTypeActions;
161 /// getTypeAction - Return how we should legalize values of this type, either
162 /// it is already legal (return 'Legal') or we need to promote it to a larger
163 /// type (return 'Promote'), or we need to expand it into multiple registers
164 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
165 LegalizeAction getTypeAction(MVT::ValueType VT) const {
166 return ValueTypeActions.getTypeAction(VT);
169 /// getTypeToTransformTo - For types supported by the target, this is an
170 /// identity function. For types that must be promoted to larger types, this
171 /// returns the larger type to promote to. For integer types that are larger
172 /// than the largest integer register, this contains one step in the expansion
173 /// to get to the smaller register. For illegal floating point types, this
174 /// returns the integer type to transform to.
175 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
176 return TransformToType[VT];
179 /// getPackedTypeBreakdown - Packed types are broken down into some number of
180 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
181 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
182 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
184 /// This method returns the number of registers needed, and the VT for each
185 /// register. It also returns the VT of the PackedType elements before they
186 /// are promoted/expanded.
188 unsigned getPackedTypeBreakdown(const PackedType *PTy,
189 MVT::ValueType &PTyElementVT,
190 MVT::ValueType &PTyLegalElementVT) const;
192 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
193 legal_fpimm_iterator legal_fpimm_begin() const {
194 return LegalFPImmediates.begin();
196 legal_fpimm_iterator legal_fpimm_end() const {
197 return LegalFPImmediates.end();
200 /// isShuffleMaskLegal - Targets can use this to indicate that they only
201 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
202 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
203 /// are assumed to be legal.
204 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
208 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
209 /// used by Targets can use this to indicate if there is a suitable
210 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
212 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
214 SelectionDAG &DAG) const {
218 /// getOperationAction - Return how this operation should be treated: either
219 /// it is legal, needs to be promoted to a larger size, needs to be
220 /// expanded to some other code sequence, or the target has a custom expander
222 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
223 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
226 /// isOperationLegal - Return true if the specified operation is legal on this
228 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
229 return getOperationAction(Op, VT) == Legal ||
230 getOperationAction(Op, VT) == Custom;
233 /// getLoadXAction - Return how this load with extension should be treated:
234 /// either it is legal, needs to be promoted to a larger size, needs to be
235 /// expanded to some other code sequence, or the target has a custom expander
237 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
238 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
241 /// isLoadXLegal - Return true if the specified load with extension is legal
243 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
244 return getLoadXAction(LType, VT) == Legal ||
245 getLoadXAction(LType, VT) == Custom;
248 /// getStoreXAction - Return how this store with truncation should be treated:
249 /// either it is legal, needs to be promoted to a larger size, needs to be
250 /// expanded to some other code sequence, or the target has a custom expander
252 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
253 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
256 /// isStoreXLegal - Return true if the specified store with truncation is
257 /// legal on this target.
258 bool isStoreXLegal(MVT::ValueType VT) const {
259 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
262 /// getIndexedLoadAction - Return how the indexed load should be treated:
263 /// either it is legal, needs to be promoted to a larger size, needs to be
264 /// expanded to some other code sequence, or the target has a custom expander
267 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
268 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
271 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
273 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
274 return getIndexedLoadAction(IdxMode, VT) == Legal ||
275 getIndexedLoadAction(IdxMode, VT) == Custom;
278 /// getIndexedStoreAction - Return how the indexed store should be treated:
279 /// either it is legal, needs to be promoted to a larger size, needs to be
280 /// expanded to some other code sequence, or the target has a custom expander
283 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
284 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
287 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
289 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
290 return getIndexedStoreAction(IdxMode, VT) == Legal ||
291 getIndexedStoreAction(IdxMode, VT) == Custom;
294 /// getTypeToPromoteTo - If the action for this operation is to promote, this
295 /// method returns the ValueType to promote to.
296 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
297 assert(getOperationAction(Op, VT) == Promote &&
298 "This operation isn't promoted!");
300 // See if this has an explicit type specified.
301 std::map<std::pair<unsigned, MVT::ValueType>,
302 MVT::ValueType>::const_iterator PTTI =
303 PromoteToType.find(std::make_pair(Op, VT));
304 if (PTTI != PromoteToType.end()) return PTTI->second;
306 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
307 "Cannot autopromote this type, add it with AddPromotedToType.");
309 MVT::ValueType NVT = VT;
311 NVT = (MVT::ValueType)(NVT+1);
312 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
313 "Didn't find type to promote to!");
314 } while (!isTypeLegal(NVT) ||
315 getOperationAction(Op, NVT) == Promote);
319 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
320 /// This is fixed by the LLVM operations except for the pointer size.
321 MVT::ValueType getValueType(const Type *Ty) const {
322 switch (Ty->getTypeID()) {
323 default: assert(0 && "Unknown type!");
324 case Type::VoidTyID: return MVT::isVoid;
325 case Type::BoolTyID: return MVT::i1;
326 case Type::UByteTyID:
327 case Type::SByteTyID: return MVT::i8;
328 case Type::ShortTyID:
329 case Type::UShortTyID: return MVT::i16;
331 case Type::UIntTyID: return MVT::i32;
333 case Type::ULongTyID: return MVT::i64;
334 case Type::FloatTyID: return MVT::f32;
335 case Type::DoubleTyID: return MVT::f64;
336 case Type::PointerTyID: return PointerTy;
337 case Type::PackedTyID: return MVT::Vector;
341 /// getNumElements - Return the number of registers that this ValueType will
342 /// eventually require. This is one for any types promoted to live in larger
343 /// registers, but may be more than one for types (like i64) that are split
345 unsigned getNumElements(MVT::ValueType VT) const {
346 return NumElementsForVT[VT];
349 /// hasTargetDAGCombine - If true, the target has custom DAG combine
350 /// transformations that it can perform for the specified node.
351 bool hasTargetDAGCombine(ISD::NodeType NT) const {
352 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
355 /// This function returns the maximum number of store operations permitted
356 /// to replace a call to llvm.memset. The value is set by the target at the
357 /// performance threshold for such a replacement.
358 /// @brief Get maximum # of store operations permitted for llvm.memset
359 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
361 /// This function returns the maximum number of store operations permitted
362 /// to replace a call to llvm.memcpy. The value is set by the target at the
363 /// performance threshold for such a replacement.
364 /// @brief Get maximum # of store operations permitted for llvm.memcpy
365 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
367 /// This function returns the maximum number of store operations permitted
368 /// to replace a call to llvm.memmove. The value is set by the target at the
369 /// performance threshold for such a replacement.
370 /// @brief Get maximum # of store operations permitted for llvm.memmove
371 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
373 /// This function returns true if the target allows unaligned memory accesses.
374 /// This is used, for example, in situations where an array copy/move/set is
375 /// converted to a sequence of store operations. It's use helps to ensure that
376 /// such replacements don't generate code that causes an alignment error
377 /// (trap) on the target machine.
378 /// @brief Determine if the target supports unaligned memory accesses.
379 bool allowsUnalignedMemoryAccesses() const {
380 return allowUnalignedMemoryAccesses;
383 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
384 /// to implement llvm.setjmp.
385 bool usesUnderscoreSetJmp() const {
386 return UseUnderscoreSetJmp;
389 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
390 /// to implement llvm.longjmp.
391 bool usesUnderscoreLongJmp() const {
392 return UseUnderscoreLongJmp;
395 /// getStackPointerRegisterToSaveRestore - If a physical register, this
396 /// specifies the register that llvm.savestack/llvm.restorestack should save
398 unsigned getStackPointerRegisterToSaveRestore() const {
399 return StackPointerRegisterToSaveRestore;
402 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
403 /// set, the default is 200)
404 unsigned getJumpBufSize() const {
408 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
409 /// (if never set, the default is 0)
410 unsigned getJumpBufAlignment() const {
411 return JumpBufAlignment;
414 /// getPreIndexedAddressParts - returns true by value, base pointer and
415 /// offset pointer and addressing mode by reference if the node's address
416 /// can be legally represented as pre-indexed load / store address.
417 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
419 ISD::MemIndexedMode &AM,
424 /// getPostIndexedAddressParts - returns true by value, base pointer and
425 /// offset pointer and addressing mode by reference if this node can be
426 /// combined with a load / store to form a post-indexed load / store.
427 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
428 SDOperand &Base, SDOperand &Offset,
429 ISD::MemIndexedMode &AM,
434 //===--------------------------------------------------------------------===//
435 // TargetLowering Optimization Methods
438 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
439 /// SDOperands for returning information from TargetLowering to its clients
440 /// that want to combine
441 struct TargetLoweringOpt {
446 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
448 bool CombineTo(SDOperand O, SDOperand N) {
454 /// ShrinkDemandedConstant - Check to see if the specified operand of the
455 /// specified instruction is a constant integer. If so, check to see if there
456 /// are any bits set in the constant that are not demanded. If so, shrink the
457 /// constant and return true.
458 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
461 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
462 /// use this predicate to simplify operations downstream. Op and Mask are
463 /// known to be the same type.
464 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
467 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
468 /// known to be either zero or one and return them in the KnownZero/KnownOne
469 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
470 /// processing. Targets can implement the computeMaskedBitsForTargetNode
471 /// method, to allow target nodes to be understood.
472 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
473 uint64_t &KnownOne, unsigned Depth = 0) const;
475 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
476 /// DemandedMask bits of the result of Op are ever used downstream. If we can
477 /// use this information to simplify Op, create a new simplified DAG node and
478 /// return true, returning the original and new nodes in Old and New.
479 /// Otherwise, analyze the expression and return a mask of KnownOne and
480 /// KnownZero bits for the expression (used to simplify the caller).
481 /// The KnownZero/One bits may only be accurate for those bits in the
483 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
484 uint64_t &KnownZero, uint64_t &KnownOne,
485 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
487 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
488 /// Mask are known to be either zero or one and return them in the
489 /// KnownZero/KnownOne bitsets.
490 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
494 unsigned Depth = 0) const;
496 /// ComputeNumSignBits - Return the number of times the sign bit of the
497 /// register is replicated into the other bits. We know that at least 1 bit
498 /// is always equal to the sign bit (itself), but other cases can give us
499 /// information. For example, immediately after an "SRA X, 2", we know that
500 /// the top 3 bits are all equal to each other, so we return 3.
501 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
503 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
504 /// targets that want to expose additional information about sign bits to the
506 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
507 unsigned Depth = 0) const;
509 struct DAGCombinerInfo {
510 void *DC; // The DAG Combiner object.
515 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
516 : DC(dc), BeforeLegalize(bl), DAG(dag) {}
518 bool isBeforeLegalize() const { return BeforeLegalize; }
520 void AddToWorklist(SDNode *N);
521 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
522 SDOperand CombineTo(SDNode *N, SDOperand Res);
523 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
526 /// PerformDAGCombine - This method will be invoked for all target nodes and
527 /// for any target-independent nodes that the target has registered with
530 /// The semantics are as follows:
532 /// SDOperand.Val == 0 - No change was made
533 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
534 /// otherwise - N should be replaced by the returned Operand.
536 /// In addition, methods provided by DAGCombinerInfo may be used to perform
537 /// more complex transformations.
539 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
541 //===--------------------------------------------------------------------===//
542 // TargetLowering Configuration Methods - These methods should be invoked by
543 // the derived class constructor to configure this object for the target.
547 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
548 /// GOT for PC-relative code.
549 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
551 /// setShiftAmountType - Describe the type that should be used for shift
552 /// amounts. This type defaults to the pointer type.
553 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
555 /// setSetCCResultType - Describe the type that shoudl be used as the result
556 /// of a setcc operation. This defaults to the pointer type.
557 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
559 /// setSetCCResultContents - Specify how the target extends the result of a
560 /// setcc operation in a register.
561 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
563 /// setSchedulingPreference - Specify the target scheduling preference.
564 void setSchedulingPreference(SchedPreference Pref) {
565 SchedPreferenceInfo = Pref;
568 /// setShiftAmountFlavor - Describe how the target handles out of range shift
570 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
571 ShiftAmtHandling = OORSA;
574 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
575 /// use _setjmp to implement llvm.setjmp or the non _ version.
576 /// Defaults to false.
577 void setUseUnderscoreSetJmp(bool Val) {
578 UseUnderscoreSetJmp = Val;
581 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
582 /// use _longjmp to implement llvm.longjmp or the non _ version.
583 /// Defaults to false.
584 void setUseUnderscoreLongJmp(bool Val) {
585 UseUnderscoreLongJmp = Val;
588 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
589 /// specifies the register that llvm.savestack/llvm.restorestack should save
591 void setStackPointerRegisterToSaveRestore(unsigned R) {
592 StackPointerRegisterToSaveRestore = R;
595 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
596 /// setcc as a conditional branch. This encourages the code generator to fold
597 /// setcc operations into other operations if possible.
598 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
600 /// setIntDivIsCheap - Tells the code generator that integer divide is
601 /// expensive, and if possible, should be replaced by an alternate sequence
602 /// of instructions not containing an integer divide.
603 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
605 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
606 /// srl/add/sra for a signed divide by power of two, and let the target handle
608 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
610 /// addRegisterClass - Add the specified register class as an available
611 /// regclass for the specified value type. This indicates the selector can
612 /// handle values of that class natively.
613 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
614 AvailableRegClasses.push_back(std::make_pair(VT, RC));
615 RegClassForVT[VT] = RC;
618 /// computeRegisterProperties - Once all of the register classes are added,
619 /// this allows us to compute derived properties we expose.
620 void computeRegisterProperties();
622 /// setOperationAction - Indicate that the specified operation does not work
623 /// with the specified type and indicate what to do about it.
624 void setOperationAction(unsigned Op, MVT::ValueType VT,
625 LegalizeAction Action) {
626 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
627 "Table isn't big enough!");
628 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
629 OpActions[Op] |= (uint64_t)Action << VT*2;
632 /// setLoadXAction - Indicate that the specified load with extension does not
633 /// work with the with specified type and indicate what to do about it.
634 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
635 LegalizeAction Action) {
636 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
637 "Table isn't big enough!");
638 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
639 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
642 /// setStoreXAction - Indicate that the specified store with truncation does
643 /// not work with the with specified type and indicate what to do about it.
644 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
645 assert(VT < 32 && "Table isn't big enough!");
646 StoreXActions &= ~(uint64_t(3UL) << VT*2);
647 StoreXActions |= (uint64_t)Action << VT*2;
650 /// setIndexedLoadAction - Indicate that the specified indexed load does or
651 /// does not work with the with specified type and indicate what to do abort
652 /// it. NOTE: All indexed mode loads are initialized to Expand in
653 /// TargetLowering.cpp
654 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
655 LegalizeAction Action) {
656 assert(VT < 32 && IdxMode <
657 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) &&
658 "Table isn't big enough!");
659 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
660 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
663 /// setIndexedStoreAction - Indicate that the specified indexed store does or
664 /// does not work with the with specified type and indicate what to do about
665 /// it. NOTE: All indexed mode stores are initialized to Expand in
666 /// TargetLowering.cpp
667 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
668 LegalizeAction Action) {
669 assert(VT < 32 && IdxMode <
670 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) &&
671 "Table isn't big enough!");
672 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
673 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
676 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
677 /// promotion code defaults to trying a larger integer/fp until it can find
678 /// one that works. If that default is insufficient, this method can be used
679 /// by the target to override the default.
680 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
681 MVT::ValueType DestVT) {
682 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
685 /// addLegalFPImmediate - Indicate that this target can instruction select
686 /// the specified FP immediate natively.
687 void addLegalFPImmediate(double Imm) {
688 LegalFPImmediates.push_back(Imm);
691 /// setTargetDAGCombine - Targets should invoke this method for each target
692 /// independent node that they want to provide a custom DAG combiner for by
693 /// implementing the PerformDAGCombine virtual method.
694 void setTargetDAGCombine(ISD::NodeType NT) {
695 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
698 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
699 /// bytes); default is 200
700 void setJumpBufSize(unsigned Size) {
704 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
705 /// alignment (in bytes); default is 0
706 void setJumpBufAlignment(unsigned Align) {
707 JumpBufAlignment = Align;
712 //===--------------------------------------------------------------------===//
713 // Lowering methods - These methods must be implemented by targets so that
714 // the SelectionDAGLowering code knows how to lower these.
717 /// LowerArguments - This hook must be implemented to indicate how we should
718 /// lower the arguments for the specified function, into the specified DAG.
719 virtual std::vector<SDOperand>
720 LowerArguments(Function &F, SelectionDAG &DAG);
722 /// LowerCallTo - This hook lowers an abstract call to a function into an
723 /// actual call. This returns a pair of operands. The first element is the
724 /// return value for the function (if RetTy is not VoidTy). The second
725 /// element is the outgoing token chain.
726 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
727 virtual std::pair<SDOperand, SDOperand>
728 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
729 unsigned CallingConv, bool isTailCall, SDOperand Callee,
730 ArgListTy &Args, SelectionDAG &DAG);
732 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
733 /// llvm.frameaddress (depending on the value of the first argument). The
734 /// return values are the result pointer and the resultant token chain. If
735 /// not implemented, both of these intrinsics will return null.
736 virtual std::pair<SDOperand, SDOperand>
737 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
740 /// LowerOperation - This callback is invoked for operations that are
741 /// unsupported by the target, which are registered to use 'custom' lowering,
742 /// and whose defined values are all legal.
743 /// If the target has no operations that require custom lowering, it need not
744 /// implement this. The default implementation of this aborts.
745 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
747 /// CustomPromoteOperation - This callback is invoked for operations that are
748 /// unsupported by the target, are registered to use 'custom' lowering, and
749 /// whose type needs to be promoted.
750 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
752 /// getTargetNodeName() - This method returns the name of a target specific
754 virtual const char *getTargetNodeName(unsigned Opcode) const;
756 //===--------------------------------------------------------------------===//
757 // Inline Asm Support hooks
760 enum ConstraintType {
761 C_Register, // Constraint represents a single register.
762 C_RegisterClass, // Constraint represents one or more registers.
763 C_Memory, // Memory constraint.
764 C_Other, // Something else.
765 C_Unknown // Unsupported constraint.
768 /// getConstraintType - Given a constraint letter, return the type of
769 /// constraint it is for this target.
770 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
773 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
774 /// return a list of registers that can be used to satisfy the constraint.
775 /// This should only be used for C_RegisterClass constraints.
776 virtual std::vector<unsigned>
777 getRegClassForInlineAsmConstraint(const std::string &Constraint,
778 MVT::ValueType VT) const;
780 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
781 /// {edx}), return the register number and the register class for the
784 /// Given a register class constraint, like 'r', if this corresponds directly
785 /// to an LLVM register class, return a register of 0 and the register class
788 /// This should only be used for C_Register constraints. On error,
789 /// this returns a register number of 0 and a null register class pointer..
790 virtual std::pair<unsigned, const TargetRegisterClass*>
791 getRegForInlineAsmConstraint(const std::string &Constraint,
792 MVT::ValueType VT) const;
795 /// isOperandValidForConstraint - Return the specified operand (possibly
796 /// modified) if the specified SDOperand is valid for the specified target
797 /// constraint letter, otherwise return null.
799 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
802 //===--------------------------------------------------------------------===//
806 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
807 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
808 // instructions are special in various ways, which require special support to
809 // insert. The specified MachineInstr is created but not inserted into any
810 // basic blocks, and the scheduler passes ownership of it to this method.
811 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
812 MachineBasicBlock *MBB);
814 //===--------------------------------------------------------------------===//
815 // Loop Strength Reduction hooks
818 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
819 /// can be used as the offset of the target addressing mode.
820 virtual bool isLegalAddressImmediate(int64_t V) const;
821 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
823 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator;
824 legal_am_scale_iterator legal_am_scale_begin() const {
825 return LegalAddressScales.begin();
827 legal_am_scale_iterator legal_am_scale_end() const {
828 return LegalAddressScales.end();
831 //===--------------------------------------------------------------------===//
832 // Div utility functions
834 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
835 std::vector<SDNode*>* Created) const;
836 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
837 std::vector<SDNode*>* Created) const;
841 /// addLegalAddressScale - Add a integer (> 1) value which can be used as
842 /// scale in the target addressing mode. Note: the ordering matters so the
843 /// least efficient ones should be entered first.
844 void addLegalAddressScale(unsigned Scale) {
845 LegalAddressScales.push_back(Scale);
849 std::vector<unsigned> LegalAddressScales;
852 const TargetData *TD;
854 /// IsLittleEndian - True if this is a little endian target.
858 /// PointerTy - The type to use for pointers, usually i32 or i64.
860 MVT::ValueType PointerTy;
862 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
864 bool UsesGlobalOffsetTable;
866 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
868 MVT::ValueType ShiftAmountTy;
870 OutOfRangeShiftAmount ShiftAmtHandling;
872 /// SetCCIsExpensive - This is a short term hack for targets that codegen
873 /// setcc as a conditional branch. This encourages the code generator to fold
874 /// setcc operations into other operations if possible.
875 bool SetCCIsExpensive;
877 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
878 /// constants into a sequence of muls, adds, and shifts. This is a hack until
879 /// a real cost model is in place. If we ever optimize for size, this will be
880 /// set to true unconditionally.
883 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
884 /// srl/add/sra for a signed divide by power of two, and let the target handle
888 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
890 MVT::ValueType SetCCResultTy;
892 /// SetCCResultContents - Information about the contents of the high-bits in
893 /// the result of a setcc comparison operation.
894 SetCCResultValue SetCCResultContents;
896 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
897 /// total cycles or lowest register usage.
898 SchedPreference SchedPreferenceInfo;
900 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
901 /// llvm.setjmp. Defaults to false.
902 bool UseUnderscoreSetJmp;
904 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
905 /// llvm.longjmp. Defaults to false.
906 bool UseUnderscoreLongJmp;
908 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
909 unsigned JumpBufSize;
911 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
913 unsigned JumpBufAlignment;
915 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
916 /// specifies the register that llvm.savestack/llvm.restorestack should save
918 unsigned StackPointerRegisterToSaveRestore;
920 /// RegClassForVT - This indicates the default register class to use for
921 /// each ValueType the target supports natively.
922 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
923 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
925 /// TransformToType - For any value types we are promoting or expanding, this
926 /// contains the value type that we are changing to. For Expanded types, this
927 /// contains one step of the expand (e.g. i64 -> i32), even if there are
928 /// multiple steps required (e.g. i64 -> i16). For types natively supported
929 /// by the system, this holds the same type (e.g. i32 -> i32).
930 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
932 /// OpActions - For each operation and each value type, keep a LegalizeAction
933 /// that indicates how instruction selection should deal with the operation.
934 /// Most operations are Legal (aka, supported natively by the target), but
935 /// operations that are not should be described. Note that operations on
936 /// non-legal value types are not described here.
937 uint64_t OpActions[156];
939 /// LoadXActions - For each load of load extension type and each value type,
940 /// keep a LegalizeAction that indicates how instruction selection should deal
942 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
944 /// StoreXActions - For each store with truncation of each value type, keep a
945 /// LegalizeAction that indicates how instruction selection should deal with
947 uint64_t StoreXActions;
949 /// IndexedModeActions - For each indexed mode and each value type, keep a
950 /// pair of LegalizeAction that indicates how instruction selection should
951 /// deal with the load / store.
952 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
954 ValueTypeActionImpl ValueTypeActions;
956 std::vector<double> LegalFPImmediates;
958 std::vector<std::pair<MVT::ValueType,
959 TargetRegisterClass*> > AvailableRegClasses;
961 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
962 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
963 /// which sets a bit in this array.
964 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
966 /// PromoteToType - For operations that must be promoted to a specific type,
967 /// this holds the destination type. This map should be sparse, so don't hold
970 /// Targets add entries to this map with AddPromotedToType(..), clients access
971 /// this with getTypeToPromoteTo(..).
972 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
975 /// When lowering %llvm.memset this field specifies the maximum number of
976 /// store operations that may be substituted for the call to memset. Targets
977 /// must set this value based on the cost threshold for that target. Targets
978 /// should assume that the memset will be done using as many of the largest
979 /// store operations first, followed by smaller ones, if necessary, per
980 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
981 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
982 /// store. This only applies to setting a constant array of a constant size.
983 /// @brief Specify maximum number of store instructions per memset call.
984 unsigned maxStoresPerMemset;
986 /// When lowering %llvm.memcpy this field specifies the maximum number of
987 /// store operations that may be substituted for a call to memcpy. Targets
988 /// must set this value based on the cost threshold for that target. Targets
989 /// should assume that the memcpy will be done using as many of the largest
990 /// store operations first, followed by smaller ones, if necessary, per
991 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
992 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
993 /// and one 1-byte store. This only applies to copying a constant array of
995 /// @brief Specify maximum bytes of store instructions per memcpy call.
996 unsigned maxStoresPerMemcpy;
998 /// When lowering %llvm.memmove this field specifies the maximum number of
999 /// store instructions that may be substituted for a call to memmove. Targets
1000 /// must set this value based on the cost threshold for that target. Targets
1001 /// should assume that the memmove will be done using as many of the largest
1002 /// store operations first, followed by smaller ones, if necessary, per
1003 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1004 /// with 8-bit alignment would result in nine 1-byte stores. This only
1005 /// applies to copying a constant array of constant size.
1006 /// @brief Specify maximum bytes of store instructions per memmove call.
1007 unsigned maxStoresPerMemmove;
1009 /// This field specifies whether the target machine permits unaligned memory
1010 /// accesses. This is used, for example, to determine the size of store
1011 /// operations when copying small arrays and other similar tasks.
1012 /// @brief Indicate whether the target permits unaligned memory accesses.
1013 bool allowUnalignedMemoryAccesses;
1015 } // end llvm namespace