1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they
130 /// should expand to.
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
165 virtual bool useSoftFloat() const { return false; }
167 /// Return the pointer type for the given address space, defaults to
168 /// the pointer type from the data layout.
169 /// FIXME: The default needs to be removed once all the code is updated.
170 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
171 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
173 virtual MVT getScalarShiftAmountTy(const DataLayout &) const;
175 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
177 /// Returns the type to be used for the index operand of:
178 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
179 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
180 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
181 return getPointerTy(DL);
184 /// Return true if the select operation is expensive for this target.
185 bool isSelectExpensive() const { return SelectIsExpensive; }
187 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
191 /// Return true if multiple condition registers are available.
192 bool hasMultipleConditionRegisters() const {
193 return HasMultipleConditionRegisters;
196 /// Return true if the target has BitExtract instructions.
197 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
199 /// Return the preferred vector type legalization action.
200 virtual TargetLoweringBase::LegalizeTypeAction
201 getPreferredVectorAction(EVT VT) const {
202 // The default action for one element vectors is to scalarize
203 if (VT.getVectorNumElements() == 1)
204 return TypeScalarizeVector;
205 // The default action for other vectors is to promote
206 return TypePromoteInteger;
209 // There are two general methods for expanding a BUILD_VECTOR node:
210 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
212 // 2. Build the vector on the stack and then load it.
213 // If this function returns true, then method (1) will be used, subject to
214 // the constraint that all of the necessary shuffles are legal (as determined
215 // by isShuffleMaskLegal). If this function returns false, then method (2) is
216 // always used. The vector type, and the number of defined values, are
219 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
220 unsigned DefinedValues) const {
221 return DefinedValues < 3;
224 /// Return true if integer divide is usually cheaper than a sequence of
225 /// several shifts, adds, and multiplies for this target.
226 bool isIntDivCheap() const { return IntDivIsCheap; }
228 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
229 bool isFsqrtCheap() const {
233 /// Returns true if target has indicated at least one type should be bypassed.
234 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
236 /// Returns map of slow types for division or remainder with corresponding
238 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
239 return BypassSlowDivWidths;
242 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
243 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
245 /// Return true if Flow Control is an expensive operation that should be
247 bool isJumpExpensive() const { return JumpIsExpensive; }
249 /// Return true if selects are only cheaper than branches if the branch is
250 /// unlikely to be predicted right.
251 bool isPredictableSelectExpensive() const {
252 return PredictableSelectIsExpensive;
255 /// isLoadBitCastBeneficial() - Return true if the following transform
257 /// fold (conv (load x)) -> (load (conv*)x)
258 /// On architectures that don't natively support some vector loads
259 /// efficiently, casting the load to a smaller vector of larger types and
260 /// loading is more efficient, however, this can be undone by optimizations in
262 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
263 EVT /* Bitcast */) const {
267 /// Return true if it is expected to be cheaper to do a store of a non-zero
268 /// vector constant with the given size and type for the address space than to
269 /// store the individual scalar element constants.
270 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
272 unsigned AddrSpace) const {
276 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
277 virtual bool isCheapToSpeculateCttz() const {
281 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
282 virtual bool isCheapToSpeculateCtlz() const {
286 /// \brief Return if the target supports combining a
289 /// %andResult = and %val1, #imm-with-one-bit-set;
290 /// %icmpResult = icmp %andResult, 0
291 /// br i1 %icmpResult, label %dest1, label %dest2
293 /// into a single machine instruction of a form like:
295 /// brOnBitSet %register, #bitNumber, dest
297 bool isMaskAndBranchFoldingLegal() const {
298 return MaskAndBranchFoldingIsLegal;
301 /// \brief Return true if the target wants to use the optimization that
302 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
303 /// promotedInst1(...(promotedInstN(ext(load)))).
304 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
306 /// Return true if the target can combine store(extractelement VectorTy,
308 /// \p Cost[out] gives the cost of that transformation when this is true.
309 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
310 unsigned &Cost) const {
314 /// Return true if target supports floating point exceptions.
315 bool hasFloatingPointExceptions() const {
316 return HasFloatingPointExceptions;
319 /// Return true if target always beneficiates from combining into FMA for a
320 /// given value type. This must typically return false on targets where FMA
321 /// takes more cycles to execute than FADD.
322 virtual bool enableAggressiveFMAFusion(EVT VT) const {
326 /// Return the ValueType of the result of SETCC operations.
327 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
330 /// Return the ValueType for comparison libcalls. Comparions libcalls include
331 /// floating point comparion calls, and Ordered/Unordered check calls on
332 /// floating point numbers.
334 MVT::SimpleValueType getCmpLibcallReturnType() const;
336 /// For targets without i1 registers, this gives the nature of the high-bits
337 /// of boolean values held in types wider than i1.
339 /// "Boolean values" are special true/false values produced by nodes like
340 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
341 /// Not to be confused with general values promoted from i1. Some cpus
342 /// distinguish between vectors of boolean and scalars; the isVec parameter
343 /// selects between the two kinds. For example on X86 a scalar boolean should
344 /// be zero extended from i1, while the elements of a vector of booleans
345 /// should be sign extended from i1.
347 /// Some cpus also treat floating point types the same way as they treat
348 /// vectors instead of the way they treat scalars.
349 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
351 return BooleanVectorContents;
352 return isFloat ? BooleanFloatContents : BooleanContents;
355 BooleanContent getBooleanContents(EVT Type) const {
356 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
359 /// Return target scheduling preference.
360 Sched::Preference getSchedulingPreference() const {
361 return SchedPreferenceInfo;
364 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
365 /// for different nodes. This function returns the preference (or none) for
367 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
371 /// Return the register class that should be used for the specified value
373 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
374 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
375 assert(RC && "This value type is not natively supported!");
379 /// Return the 'representative' register class for the specified value
382 /// The 'representative' register class is the largest legal super-reg
383 /// register class for the register class of the value type. For example, on
384 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
385 /// register class is GR64 on x86_64.
386 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
387 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
391 /// Return the cost of the 'representative' register class for the specified
393 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
394 return RepRegClassCostForVT[VT.SimpleTy];
397 /// Return true if the target has native support for the specified value type.
398 /// This means that it has a register that directly holds it without
399 /// promotions or expansions.
400 bool isTypeLegal(EVT VT) const {
401 assert(!VT.isSimple() ||
402 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
403 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
406 class ValueTypeActionImpl {
407 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
408 /// that indicates how instruction selection should deal with the type.
409 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
412 ValueTypeActionImpl() {
413 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
416 LegalizeTypeAction getTypeAction(MVT VT) const {
417 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
420 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
421 unsigned I = VT.SimpleTy;
422 ValueTypeActions[I] = Action;
426 const ValueTypeActionImpl &getValueTypeActions() const {
427 return ValueTypeActions;
430 /// Return how we should legalize values of this type, either it is already
431 /// legal (return 'Legal') or we need to promote it to a larger type (return
432 /// 'Promote'), or we need to expand it into multiple registers of smaller
433 /// integer type (return 'Expand'). 'Custom' is not an option.
434 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
435 return getTypeConversion(Context, VT).first;
437 LegalizeTypeAction getTypeAction(MVT VT) const {
438 return ValueTypeActions.getTypeAction(VT);
441 /// For types supported by the target, this is an identity function. For
442 /// types that must be promoted to larger types, this returns the larger type
443 /// to promote to. For integer types that are larger than the largest integer
444 /// register, this contains one step in the expansion to get to the smaller
445 /// register. For illegal floating point types, this returns the integer type
447 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
448 return getTypeConversion(Context, VT).second;
451 /// For types supported by the target, this is an identity function. For
452 /// types that must be expanded (i.e. integer types that are larger than the
453 /// largest integer register or illegal floating point types), this returns
454 /// the largest legal type it will be expanded to.
455 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
456 assert(!VT.isVector());
458 switch (getTypeAction(Context, VT)) {
461 case TypeExpandInteger:
462 VT = getTypeToTransformTo(Context, VT);
465 llvm_unreachable("Type is not legal nor is it to be expanded!");
470 /// Vector types are broken down into some number of legal first class types.
471 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
472 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
473 /// turns into 4 EVT::i32 values with both PPC and X86.
475 /// This method returns the number of registers needed, and the VT for each
476 /// register. It also returns the VT and quantity of the intermediate values
477 /// before they are promoted/expanded.
478 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
480 unsigned &NumIntermediates,
481 MVT &RegisterVT) const;
483 struct IntrinsicInfo {
484 unsigned opc; // target opcode
485 EVT memVT; // memory VT
486 const Value* ptrVal; // value representing memory location
487 int offset; // offset off of ptrVal
488 unsigned size; // the size of the memory location
489 // (taken from memVT if zero)
490 unsigned align; // alignment
491 bool vol; // is volatile?
492 bool readMem; // reads memory?
493 bool writeMem; // writes memory?
495 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
496 vol(false), readMem(false), writeMem(false) {}
499 /// Given an intrinsic, checks if on the target the intrinsic will need to map
500 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
501 /// true and store the intrinsic information into the IntrinsicInfo that was
502 /// passed to the function.
503 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
504 unsigned /*Intrinsic*/) const {
508 /// Returns true if the target can instruction select the specified FP
509 /// immediate natively. If false, the legalizer will materialize the FP
510 /// immediate as a load from a constant pool.
511 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
515 /// Targets can use this to indicate that they only support *some*
516 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
517 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
519 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
524 /// Returns true if the operation can trap for the value type.
526 /// VT must be a legal type. By default, we optimistically assume most
527 /// operations don't trap except for divide and remainder.
528 virtual bool canOpTrap(unsigned Op, EVT VT) const;
530 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
531 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
532 /// a VAND with a constant pool entry.
533 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
538 /// Return how this operation should be treated: either it is legal, needs to
539 /// be promoted to a larger size, needs to be expanded to some other code
540 /// sequence, or the target has a custom expander for it.
541 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
542 if (VT.isExtended()) return Expand;
543 // If a target-specific SDNode requires legalization, require the target
544 // to provide custom legalization for it.
545 if (Op > array_lengthof(OpActions[0])) return Custom;
546 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
547 return (LegalizeAction)OpActions[I][Op];
550 /// Return true if the specified operation is legal on this target or can be
551 /// made legal with custom lowering. This is used to help guide high-level
552 /// lowering decisions.
553 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
554 return (VT == MVT::Other || isTypeLegal(VT)) &&
555 (getOperationAction(Op, VT) == Legal ||
556 getOperationAction(Op, VT) == Custom);
559 /// Return true if the specified operation is legal on this target or can be
560 /// made legal using promotion. This is used to help guide high-level lowering
562 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
563 return (VT == MVT::Other || isTypeLegal(VT)) &&
564 (getOperationAction(Op, VT) == Legal ||
565 getOperationAction(Op, VT) == Promote);
568 /// Return true if the specified operation is illegal on this target or
569 /// unlikely to be made legal with custom lowering. This is used to help guide
570 /// high-level lowering decisions.
571 bool isOperationExpand(unsigned Op, EVT VT) const {
572 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
575 /// Return true if the specified operation is legal on this target.
576 bool isOperationLegal(unsigned Op, EVT VT) const {
577 return (VT == MVT::Other || isTypeLegal(VT)) &&
578 getOperationAction(Op, VT) == Legal;
581 /// Return how this load with extension should be treated: either it is legal,
582 /// needs to be promoted to a larger size, needs to be expanded to some other
583 /// code sequence, or the target has a custom expander for it.
584 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
586 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
587 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
588 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
589 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
590 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
591 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
594 /// Return true if the specified load with extension is legal on this target.
595 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
596 return ValVT.isSimple() && MemVT.isSimple() &&
597 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
600 /// Return true if the specified load with extension is legal or custom
602 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
603 return ValVT.isSimple() && MemVT.isSimple() &&
604 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
605 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
608 /// Return how this store with truncation should be treated: either it is
609 /// legal, needs to be promoted to a larger size, needs to be expanded to some
610 /// other code sequence, or the target has a custom expander for it.
611 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
612 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
613 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
614 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
615 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
616 "Table isn't big enough!");
617 return (LegalizeAction)TruncStoreActions[ValI][MemI];
620 /// Return true if the specified store with truncation is legal on this
622 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
623 return isTypeLegal(ValVT) && MemVT.isSimple() &&
624 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
627 /// Return how the indexed load should be treated: either it is legal, needs
628 /// to be promoted to a larger size, needs to be expanded to some other code
629 /// sequence, or the target has a custom expander for it.
631 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
632 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
633 "Table isn't big enough!");
634 unsigned Ty = (unsigned)VT.SimpleTy;
635 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
638 /// Return true if the specified indexed load is legal on this target.
639 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
640 return VT.isSimple() &&
641 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
642 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
645 /// Return how the indexed store should be treated: either it is legal, needs
646 /// to be promoted to a larger size, needs to be expanded to some other code
647 /// sequence, or the target has a custom expander for it.
649 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
650 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
651 "Table isn't big enough!");
652 unsigned Ty = (unsigned)VT.SimpleTy;
653 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
656 /// Return true if the specified indexed load is legal on this target.
657 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
658 return VT.isSimple() &&
659 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
660 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
663 /// Return how the condition code should be treated: either it is legal, needs
664 /// to be expanded to some other code sequence, or the target has a custom
667 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
668 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
669 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
670 "Table isn't big enough!");
671 // See setCondCodeAction for how this is encoded.
672 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
673 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
674 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
675 assert(Action != Promote && "Can't promote condition code!");
679 /// Return true if the specified condition code is legal on this target.
680 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
682 getCondCodeAction(CC, VT) == Legal ||
683 getCondCodeAction(CC, VT) == Custom;
687 /// If the action for this operation is to promote, this method returns the
688 /// ValueType to promote to.
689 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
690 assert(getOperationAction(Op, VT) == Promote &&
691 "This operation isn't promoted!");
693 // See if this has an explicit type specified.
694 std::map<std::pair<unsigned, MVT::SimpleValueType>,
695 MVT::SimpleValueType>::const_iterator PTTI =
696 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
697 if (PTTI != PromoteToType.end()) return PTTI->second;
699 assert((VT.isInteger() || VT.isFloatingPoint()) &&
700 "Cannot autopromote this type, add it with AddPromotedToType.");
704 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
705 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
706 "Didn't find type to promote to!");
707 } while (!isTypeLegal(NVT) ||
708 getOperationAction(Op, NVT) == Promote);
712 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
713 /// operations except for the pointer size. If AllowUnknown is true, this
714 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
715 /// otherwise it will assert.
716 EVT getValueType(const DataLayout &DL, Type *Ty,
717 bool AllowUnknown = false) const {
718 // Lower scalar pointers to native pointer types.
719 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
720 return getPointerTy(DL, PTy->getAddressSpace());
722 if (Ty->isVectorTy()) {
723 VectorType *VTy = cast<VectorType>(Ty);
724 Type *Elm = VTy->getElementType();
725 // Lower vectors of pointers to native pointer types.
726 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
727 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
728 Elm = PointerTy.getTypeForEVT(Ty->getContext());
731 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
732 VTy->getNumElements());
734 return EVT::getEVT(Ty, AllowUnknown);
737 /// Return the MVT corresponding to this LLVM type. See getValueType.
738 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
739 bool AllowUnknown = false) const {
740 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
743 /// Return the desired alignment for ByVal or InAlloca aggregate function
744 /// arguments in the caller parameter area. This is the actual alignment, not
746 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
748 /// Return the type of registers that this ValueType will eventually require.
749 MVT getRegisterType(MVT VT) const {
750 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
751 return RegisterTypeForVT[VT.SimpleTy];
754 /// Return the type of registers that this ValueType will eventually require.
755 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
757 assert((unsigned)VT.getSimpleVT().SimpleTy <
758 array_lengthof(RegisterTypeForVT));
759 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
764 unsigned NumIntermediates;
765 (void)getVectorTypeBreakdown(Context, VT, VT1,
766 NumIntermediates, RegisterVT);
769 if (VT.isInteger()) {
770 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
772 llvm_unreachable("Unsupported extended type!");
775 /// Return the number of registers that this ValueType will eventually
778 /// This is one for any types promoted to live in larger registers, but may be
779 /// more than one for types (like i64) that are split into pieces. For types
780 /// like i140, which are first promoted then expanded, it is the number of
781 /// registers needed to hold all the bits of the original type. For an i140
782 /// on a 32 bit machine this means 5 registers.
783 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
785 assert((unsigned)VT.getSimpleVT().SimpleTy <
786 array_lengthof(NumRegistersForVT));
787 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
792 unsigned NumIntermediates;
793 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
795 if (VT.isInteger()) {
796 unsigned BitWidth = VT.getSizeInBits();
797 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
798 return (BitWidth + RegWidth - 1) / RegWidth;
800 llvm_unreachable("Unsupported extended type!");
803 /// If true, then instruction selection should seek to shrink the FP constant
804 /// of the specified type to a smaller type in order to save space and / or
806 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
808 // Return true if it is profitable to reduce the given load node to a smaller
811 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
812 virtual bool shouldReduceLoadWidth(SDNode *Load,
813 ISD::LoadExtType ExtTy,
818 /// When splitting a value of the specified type into parts, does the Lo
819 /// or Hi part come first? This usually follows the endianness, except
820 /// for ppcf128, where the Hi part always comes first.
821 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
822 return DL.isBigEndian() || VT == MVT::ppcf128;
825 /// If true, the target has custom DAG combine transformations that it can
826 /// perform for the specified node.
827 bool hasTargetDAGCombine(ISD::NodeType NT) const {
828 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
829 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
832 /// \brief Get maximum # of store operations permitted for llvm.memset
834 /// This function returns the maximum number of store operations permitted
835 /// to replace a call to llvm.memset. The value is set by the target at the
836 /// performance threshold for such a replacement. If OptSize is true,
837 /// return the limit for functions that have OptSize attribute.
838 unsigned getMaxStoresPerMemset(bool OptSize) const {
839 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
842 /// \brief Get maximum # of store operations permitted for llvm.memcpy
844 /// This function returns the maximum number of store operations permitted
845 /// to replace a call to llvm.memcpy. The value is set by the target at the
846 /// performance threshold for such a replacement. If OptSize is true,
847 /// return the limit for functions that have OptSize attribute.
848 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
849 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
852 /// \brief Get maximum # of store operations permitted for llvm.memmove
854 /// This function returns the maximum number of store operations permitted
855 /// to replace a call to llvm.memmove. The value is set by the target at the
856 /// performance threshold for such a replacement. If OptSize is true,
857 /// return the limit for functions that have OptSize attribute.
858 unsigned getMaxStoresPerMemmove(bool OptSize) const {
859 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
862 /// \brief Determine if the target supports unaligned memory accesses.
864 /// This function returns true if the target allows unaligned memory accesses
865 /// of the specified type in the given address space. If true, it also returns
866 /// whether the unaligned memory access is "fast" in the last argument by
867 /// reference. This is used, for example, in situations where an array
868 /// copy/move/set is converted to a sequence of store operations. Its use
869 /// helps to ensure that such replacements don't generate code that causes an
870 /// alignment error (trap) on the target machine.
871 virtual bool allowsMisalignedMemoryAccesses(EVT,
872 unsigned AddrSpace = 0,
874 bool * /*Fast*/ = nullptr) const {
878 /// Returns the target specific optimal type for load and store operations as
879 /// a result of memset, memcpy, and memmove lowering.
881 /// If DstAlign is zero that means it's safe to destination alignment can
882 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
883 /// a need to check it against alignment requirement, probably because the
884 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
885 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
886 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
887 /// does not need to be loaded. It returns EVT::Other if the type should be
888 /// determined using generic target-independent logic.
889 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
890 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
893 bool /*MemcpyStrSrc*/,
894 MachineFunction &/*MF*/) const {
898 /// Returns true if it's safe to use load / store of the specified type to
899 /// expand memcpy / memset inline.
901 /// This is mostly true for all types except for some special cases. For
902 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
903 /// fstpl which also does type conversion. Note the specified type doesn't
904 /// have to be legal as the hook is used before type legalization.
905 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
907 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
908 bool usesUnderscoreSetJmp() const {
909 return UseUnderscoreSetJmp;
912 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
913 bool usesUnderscoreLongJmp() const {
914 return UseUnderscoreLongJmp;
917 /// Return integer threshold on number of blocks to use jump tables rather
918 /// than if sequence.
919 int getMinimumJumpTableEntries() const {
920 return MinimumJumpTableEntries;
923 /// If a physical register, this specifies the register that
924 /// llvm.savestack/llvm.restorestack should save and restore.
925 unsigned getStackPointerRegisterToSaveRestore() const {
926 return StackPointerRegisterToSaveRestore;
929 /// If a physical register, this returns the register that receives the
930 /// exception address on entry to a landing pad.
931 unsigned getExceptionPointerRegister() const {
932 return ExceptionPointerRegister;
935 /// If a physical register, this returns the register that receives the
936 /// exception typeid on entry to a landing pad.
937 unsigned getExceptionSelectorRegister() const {
938 return ExceptionSelectorRegister;
941 /// Returns the target's jmp_buf size in bytes (if never set, the default is
943 unsigned getJumpBufSize() const {
947 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
949 unsigned getJumpBufAlignment() const {
950 return JumpBufAlignment;
953 /// Return the minimum stack alignment of an argument.
954 unsigned getMinStackArgumentAlignment() const {
955 return MinStackArgumentAlignment;
958 /// Return the minimum function alignment.
959 unsigned getMinFunctionAlignment() const {
960 return MinFunctionAlignment;
963 /// Return the preferred function alignment.
964 unsigned getPrefFunctionAlignment() const {
965 return PrefFunctionAlignment;
968 /// Return the preferred loop alignment.
969 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
970 return PrefLoopAlignment;
973 /// Return whether the DAG builder should automatically insert fences and
974 /// reduce ordering for atomics.
975 bool getInsertFencesForAtomic() const {
976 return InsertFencesForAtomic;
979 /// Return true if the target stores stack protector cookies at a fixed offset
980 /// in some non-standard address space, and populates the address space and
981 /// offset as appropriate.
982 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
983 unsigned &/*Offset*/) const {
987 /// Returns true if a cast between SrcAS and DestAS is a noop.
988 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
992 /// Return true if the pointer arguments to CI should be aligned by aligning
993 /// the object whose address is being passed. If so then MinSize is set to the
994 /// minimum size the object must be to be aligned and PrefAlign is set to the
995 /// preferred alignment.
996 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
997 unsigned & /*PrefAlign*/) const {
1001 //===--------------------------------------------------------------------===//
1002 /// \name Helpers for TargetTransformInfo implementations
1005 /// Get the ISD node that corresponds to the Instruction class opcode.
1006 int InstructionOpcodeToISD(unsigned Opcode) const;
1008 /// Estimate the cost of type-legalization and the legalized type.
1009 std::pair<unsigned, MVT> getTypeLegalizationCost(const DataLayout &DL,
1014 //===--------------------------------------------------------------------===//
1015 /// \name Helpers for atomic expansion.
1018 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1019 /// and expand AtomicCmpXchgInst.
1020 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1022 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1023 /// corresponding pointee type. This may entail some non-trivial operations to
1024 /// truncate or reconstruct types that will be illegal in the backend. See
1025 /// ARMISelLowering for an example implementation.
1026 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1027 AtomicOrdering Ord) const {
1028 llvm_unreachable("Load linked unimplemented on this target");
1031 /// Perform a store-conditional operation to Addr. Return the status of the
1032 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1033 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1034 Value *Addr, AtomicOrdering Ord) const {
1035 llvm_unreachable("Store conditional unimplemented on this target");
1038 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1039 /// It is called by AtomicExpandPass before expanding an
1040 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1041 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1042 /// This function should either return a nullptr, or a pointer to an IR-level
1043 /// Instruction*. Even complex fence sequences can be represented by a
1044 /// single Instruction* through an intrinsic to be lowered later.
1045 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1046 /// Backends should override this method to produce target-specific intrinsic
1047 /// for their fences.
1048 /// FIXME: Please note that the default implementation here in terms of
1049 /// IR-level fences exists for historical/compatibility reasons and is
1050 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1051 /// consistency. For example, consider the following example:
1052 /// atomic<int> x = y = 0;
1053 /// int r1, r2, r3, r4;
1064 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1065 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1066 /// IR-level fences can prevent it.
1068 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1069 AtomicOrdering Ord, bool IsStore,
1070 bool IsLoad) const {
1071 if (!getInsertFencesForAtomic())
1074 if (isAtLeastRelease(Ord) && IsStore)
1075 return Builder.CreateFence(Ord);
1080 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1081 AtomicOrdering Ord, bool IsStore,
1082 bool IsLoad) const {
1083 if (!getInsertFencesForAtomic())
1086 if (isAtLeastAcquire(Ord))
1087 return Builder.CreateFence(Ord);
1093 /// Returns true if the given (atomic) store should be expanded by the
1094 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1095 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1099 /// Returns true if arguments should be sign-extended in lib calls.
1100 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1104 /// Returns true if the given (atomic) load should be expanded by the
1105 /// IR-level AtomicExpand pass into a load-linked instruction
1106 /// (through emitLoadLinked()).
1107 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1109 /// Returns how the IR-level AtomicExpand pass should expand the given
1110 /// AtomicRMW, if at all. Default is to never expand.
1111 virtual AtomicRMWExpansionKind
1112 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1113 return AtomicRMWExpansionKind::None;
1116 /// On some platforms, an AtomicRMW that never actually modifies the value
1117 /// (such as fetch_add of 0) can be turned into a fence followed by an
1118 /// atomic load. This may sound useless, but it makes it possible for the
1119 /// processor to keep the cacheline shared, dramatically improving
1120 /// performance. And such idempotent RMWs are useful for implementing some
1121 /// kinds of locks, see for example (justification + benchmarks):
1122 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1123 /// This method tries doing that transformation, returning the atomic load if
1124 /// it succeeds, and nullptr otherwise.
1125 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1126 /// another round of expansion.
1128 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1132 /// Returns true if we should normalize
1133 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1134 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1135 /// that it saves us from materializing N0 and N1 in an integer register.
1136 /// Targets that are able to perform and/or on flags should return false here.
1137 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1139 // If a target has multiple condition registers, then it likely has logical
1140 // operations on those registers.
1141 if (hasMultipleConditionRegisters())
1143 // Only do the transform if the value won't be split into multiple
1145 LegalizeTypeAction Action = getTypeAction(Context, VT);
1146 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1147 Action != TypeSplitVector;
1150 //===--------------------------------------------------------------------===//
1151 // TargetLowering Configuration Methods - These methods should be invoked by
1152 // the derived class constructor to configure this object for the target.
1155 /// Specify how the target extends the result of integer and floating point
1156 /// boolean values from i1 to a wider type. See getBooleanContents.
1157 void setBooleanContents(BooleanContent Ty) {
1158 BooleanContents = Ty;
1159 BooleanFloatContents = Ty;
1162 /// Specify how the target extends the result of integer and floating point
1163 /// boolean values from i1 to a wider type. See getBooleanContents.
1164 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1165 BooleanContents = IntTy;
1166 BooleanFloatContents = FloatTy;
1169 /// Specify how the target extends the result of a vector boolean value from a
1170 /// vector of i1 to a wider type. See getBooleanContents.
1171 void setBooleanVectorContents(BooleanContent Ty) {
1172 BooleanVectorContents = Ty;
1175 /// Specify the target scheduling preference.
1176 void setSchedulingPreference(Sched::Preference Pref) {
1177 SchedPreferenceInfo = Pref;
1180 /// Indicate whether this target prefers to use _setjmp to implement
1181 /// llvm.setjmp or the version without _. Defaults to false.
1182 void setUseUnderscoreSetJmp(bool Val) {
1183 UseUnderscoreSetJmp = Val;
1186 /// Indicate whether this target prefers to use _longjmp to implement
1187 /// llvm.longjmp or the version without _. Defaults to false.
1188 void setUseUnderscoreLongJmp(bool Val) {
1189 UseUnderscoreLongJmp = Val;
1192 /// Indicate the number of blocks to generate jump tables rather than if
1194 void setMinimumJumpTableEntries(int Val) {
1195 MinimumJumpTableEntries = Val;
1198 /// If set to a physical register, this specifies the register that
1199 /// llvm.savestack/llvm.restorestack should save and restore.
1200 void setStackPointerRegisterToSaveRestore(unsigned R) {
1201 StackPointerRegisterToSaveRestore = R;
1204 /// If set to a physical register, this sets the register that receives the
1205 /// exception address on entry to a landing pad.
1206 void setExceptionPointerRegister(unsigned R) {
1207 ExceptionPointerRegister = R;
1210 /// If set to a physical register, this sets the register that receives the
1211 /// exception typeid on entry to a landing pad.
1212 void setExceptionSelectorRegister(unsigned R) {
1213 ExceptionSelectorRegister = R;
1216 /// Tells the code generator not to expand operations into sequences that use
1217 /// the select operations if possible.
1218 void setSelectIsExpensive(bool isExpensive = true) {
1219 SelectIsExpensive = isExpensive;
1222 /// Tells the code generator that the target has multiple (allocatable)
1223 /// condition registers that can be used to store the results of comparisons
1224 /// for use by selects and conditional branches. With multiple condition
1225 /// registers, the code generator will not aggressively sink comparisons into
1226 /// the blocks of their users.
1227 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1228 HasMultipleConditionRegisters = hasManyRegs;
1231 /// Tells the code generator that the target has BitExtract instructions.
1232 /// The code generator will aggressively sink "shift"s into the blocks of
1233 /// their users if the users will generate "and" instructions which can be
1234 /// combined with "shift" to BitExtract instructions.
1235 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1236 HasExtractBitsInsn = hasExtractInsn;
1239 /// Tells the code generator not to expand logic operations on comparison
1240 /// predicates into separate sequences that increase the amount of flow
1242 void setJumpIsExpensive(bool isExpensive = true);
1244 /// Tells the code generator that integer divide is expensive, and if
1245 /// possible, should be replaced by an alternate sequence of instructions not
1246 /// containing an integer divide.
1247 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1249 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1250 /// with an alternative sequence of instructions.
1251 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1253 /// Tells the code generator that this target supports floating point
1254 /// exceptions and cares about preserving floating point exception behavior.
1255 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1256 HasFloatingPointExceptions = FPExceptions;
1259 /// Tells the code generator which bitwidths to bypass.
1260 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1261 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1264 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1265 /// signed divide by power of two; let the target handle it.
1266 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1268 /// Add the specified register class as an available regclass for the
1269 /// specified value type. This indicates the selector can handle values of
1270 /// that class natively.
1271 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1272 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1273 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1274 RegClassForVT[VT.SimpleTy] = RC;
1277 /// Remove all register classes.
1278 void clearRegisterClasses() {
1279 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1281 AvailableRegClasses.clear();
1284 /// \brief Remove all operation actions.
1285 void clearOperationActions() {
1288 /// Return the largest legal super-reg register class of the register class
1289 /// for the specified type and its associated "cost".
1290 virtual std::pair<const TargetRegisterClass *, uint8_t>
1291 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1293 /// Once all of the register classes are added, this allows us to compute
1294 /// derived properties we expose.
1295 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1297 /// Indicate that the specified operation does not work with the specified
1298 /// type and indicate what to do about it.
1299 void setOperationAction(unsigned Op, MVT VT,
1300 LegalizeAction Action) {
1301 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1302 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1305 /// Indicate that the specified load with extension does not work with the
1306 /// specified type and indicate what to do about it.
1307 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1308 LegalizeAction Action) {
1309 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1310 MemVT.isValid() && "Table isn't big enough!");
1311 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1314 /// Indicate that the specified truncating store does not work with the
1315 /// specified type and indicate what to do about it.
1316 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1317 LegalizeAction Action) {
1318 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1319 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1322 /// Indicate that the specified indexed load does or does not work with the
1323 /// specified type and indicate what to do abort it.
1325 /// NOTE: All indexed mode loads are initialized to Expand in
1326 /// TargetLowering.cpp
1327 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1328 LegalizeAction Action) {
1329 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1330 (unsigned)Action < 0xf && "Table isn't big enough!");
1331 // Load action are kept in the upper half.
1332 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1333 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1336 /// Indicate that the specified indexed store does or does not work with the
1337 /// specified type and indicate what to do about it.
1339 /// NOTE: All indexed mode stores are initialized to Expand in
1340 /// TargetLowering.cpp
1341 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1342 LegalizeAction Action) {
1343 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1344 (unsigned)Action < 0xf && "Table isn't big enough!");
1345 // Store action are kept in the lower half.
1346 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1347 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1350 /// Indicate that the specified condition code is or isn't supported on the
1351 /// target and indicate what to do about it.
1352 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1353 LegalizeAction Action) {
1354 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1355 "Table isn't big enough!");
1356 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1357 /// value and the upper 27 bits index into the second dimension of the array
1358 /// to select what 32-bit value to use.
1359 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1360 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1361 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1364 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1365 /// to trying a larger integer/fp until it can find one that works. If that
1366 /// default is insufficient, this method can be used by the target to override
1368 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1369 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1372 /// Targets should invoke this method for each target independent node that
1373 /// they want to provide a custom DAG combiner for by implementing the
1374 /// PerformDAGCombine virtual method.
1375 void setTargetDAGCombine(ISD::NodeType NT) {
1376 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1377 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1380 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1381 void setJumpBufSize(unsigned Size) {
1385 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1387 void setJumpBufAlignment(unsigned Align) {
1388 JumpBufAlignment = Align;
1391 /// Set the target's minimum function alignment (in log2(bytes))
1392 void setMinFunctionAlignment(unsigned Align) {
1393 MinFunctionAlignment = Align;
1396 /// Set the target's preferred function alignment. This should be set if
1397 /// there is a performance benefit to higher-than-minimum alignment (in
1399 void setPrefFunctionAlignment(unsigned Align) {
1400 PrefFunctionAlignment = Align;
1403 /// Set the target's preferred loop alignment. Default alignment is zero, it
1404 /// means the target does not care about loop alignment. The alignment is
1405 /// specified in log2(bytes). The target may also override
1406 /// getPrefLoopAlignment to provide per-loop values.
1407 void setPrefLoopAlignment(unsigned Align) {
1408 PrefLoopAlignment = Align;
1411 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1412 void setMinStackArgumentAlignment(unsigned Align) {
1413 MinStackArgumentAlignment = Align;
1416 /// Set if the DAG builder should automatically insert fences and reduce the
1417 /// order of atomic memory operations to Monotonic.
1418 void setInsertFencesForAtomic(bool fence) {
1419 InsertFencesForAtomic = fence;
1423 //===--------------------------------------------------------------------===//
1424 // Addressing mode description hooks (used by LSR etc).
1427 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1428 /// instructions reading the address. This allows as much computation as
1429 /// possible to be done in the address mode for that operand. This hook lets
1430 /// targets also pass back when this should be done on intrinsics which
1432 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1433 SmallVectorImpl<Value*> &/*Ops*/,
1434 Type *&/*AccessTy*/,
1435 unsigned AddrSpace = 0) const {
1439 /// This represents an addressing mode of:
1440 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1441 /// If BaseGV is null, there is no BaseGV.
1442 /// If BaseOffs is zero, there is no base offset.
1443 /// If HasBaseReg is false, there is no base register.
1444 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1447 GlobalValue *BaseGV;
1451 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1454 /// Return true if the addressing mode represented by AM is legal for this
1455 /// target, for a load/store of the specified type.
1457 /// The type may be VoidTy, in which case only return true if the addressing
1458 /// mode is legal for a load/store of any legal type. TODO: Handle
1459 /// pre/postinc as well.
1461 /// If the address space cannot be determined, it will be -1.
1463 /// TODO: Remove default argument
1464 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1465 Type *Ty, unsigned AddrSpace) const;
1467 /// \brief Return the cost of the scaling factor used in the addressing mode
1468 /// represented by AM for this target, for a load/store of the specified type.
1470 /// If the AM is supported, the return value must be >= 0.
1471 /// If the AM is not supported, it returns a negative value.
1472 /// TODO: Handle pre/postinc as well.
1473 /// TODO: Remove default argument
1474 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1475 Type *Ty, unsigned AS = 0) const {
1476 // Default: assume that any scaling factor used in a legal AM is free.
1477 if (isLegalAddressingMode(DL, AM, Ty, AS))
1482 /// Return true if the specified immediate is legal icmp immediate, that is
1483 /// the target has icmp instructions which can compare a register against the
1484 /// immediate without having to materialize the immediate into a register.
1485 virtual bool isLegalICmpImmediate(int64_t) const {
1489 /// Return true if the specified immediate is legal add immediate, that is the
1490 /// target has add instructions which can add a register with the immediate
1491 /// without having to materialize the immediate into a register.
1492 virtual bool isLegalAddImmediate(int64_t) const {
1496 /// Return true if it's significantly cheaper to shift a vector by a uniform
1497 /// scalar than by an amount which will vary across each lane. On x86, for
1498 /// example, there is a "psllw" instruction for the former case, but no simple
1499 /// instruction for a general "a << b" operation on vectors.
1500 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1504 /// Return true if it's free to truncate a value of type Ty1 to type
1505 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1506 /// by referencing its sub-register AX.
1507 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1511 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1512 /// whether a call is in tail position. Typically this means that both results
1513 /// would be assigned to the same register or stack slot, but it could mean
1514 /// the target performs adequate checks of its own before proceeding with the
1516 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1520 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1524 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1526 /// Return true if the extension represented by \p I is free.
1527 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1528 /// this method can use the context provided by \p I to decide
1529 /// whether or not \p I is free.
1530 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1531 /// In other words, if is[Z|FP]Free returns true, then this method
1532 /// returns true as well. The converse is not true.
1533 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1534 /// \pre \p I must be a sign, zero, or fp extension.
1535 bool isExtFree(const Instruction *I) const {
1536 switch (I->getOpcode()) {
1537 case Instruction::FPExt:
1538 if (isFPExtFree(EVT::getEVT(I->getType())))
1541 case Instruction::ZExt:
1542 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1545 case Instruction::SExt:
1548 llvm_unreachable("Instruction is not an extension");
1550 return isExtFreeImpl(I);
1553 /// Return true if any actual instruction that defines a value of type Ty1
1554 /// implicitly zero-extends the value to Ty2 in the result register.
1556 /// This does not necessarily include registers defined in unknown ways, such
1557 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1558 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1559 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1560 /// values implicit zero-extend the result out to 64 bits.
1561 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1565 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1569 /// Return true if the target supplies and combines to a paired load
1570 /// two loaded values of type LoadedType next to each other in memory.
1571 /// RequiredAlignment gives the minimal alignment constraints that must be met
1572 /// to be able to select this paired load.
1574 /// This information is *not* used to generate actual paired loads, but it is
1575 /// used to generate a sequence of loads that is easier to combine into a
1577 /// For instance, something like this:
1578 /// a = load i64* addr
1579 /// b = trunc i64 a to i32
1580 /// c = lshr i64 a, 32
1581 /// d = trunc i64 c to i32
1582 /// will be optimized into:
1583 /// b = load i32* addr1
1584 /// d = load i32* addr2
1585 /// Where addr1 = addr2 +/- sizeof(i32).
1587 /// In other words, unless the target performs a post-isel load combining,
1588 /// this information should not be provided because it will generate more
1590 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1591 unsigned & /*RequiredAligment*/) const {
1595 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1596 unsigned & /*RequiredAligment*/) const {
1600 /// \brief Get the maximum supported factor for interleaved memory accesses.
1601 /// Default to be the minimum interleave factor: 2.
1602 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1604 /// \brief Lower an interleaved load to target specific intrinsics. Return
1605 /// true on success.
1607 /// \p LI is the vector load instruction.
1608 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1609 /// \p Indices is the corresponding indices for each shufflevector.
1610 /// \p Factor is the interleave factor.
1611 virtual bool lowerInterleavedLoad(LoadInst *LI,
1612 ArrayRef<ShuffleVectorInst *> Shuffles,
1613 ArrayRef<unsigned> Indices,
1614 unsigned Factor) const {
1618 /// \brief Lower an interleaved store to target specific intrinsics. Return
1619 /// true on success.
1621 /// \p SI is the vector store instruction.
1622 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1623 /// \p Factor is the interleave factor.
1624 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1625 unsigned Factor) const {
1629 /// Return true if zero-extending the specific node Val to type VT2 is free
1630 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1631 /// because it's folded such as X86 zero-extending loads).
1632 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1633 return isZExtFree(Val.getValueType(), VT2);
1636 /// Return true if an fpext operation is free (for instance, because
1637 /// single-precision floating-point numbers are implicitly extended to
1638 /// double-precision).
1639 virtual bool isFPExtFree(EVT VT) const {
1640 assert(VT.isFloatingPoint());
1644 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1645 /// extend node) is profitable.
1646 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1648 /// Return true if an fneg operation is free to the point where it is never
1649 /// worthwhile to replace it with a bitwise operation.
1650 virtual bool isFNegFree(EVT VT) const {
1651 assert(VT.isFloatingPoint());
1655 /// Return true if an fabs operation is free to the point where it is never
1656 /// worthwhile to replace it with a bitwise operation.
1657 virtual bool isFAbsFree(EVT VT) const {
1658 assert(VT.isFloatingPoint());
1662 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1663 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1664 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1666 /// NOTE: This may be called before legalization on types for which FMAs are
1667 /// not legal, but should return true if those types will eventually legalize
1668 /// to types that support FMAs. After legalization, it will only be called on
1669 /// types that support FMAs (via Legal or Custom actions)
1670 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1674 /// Return true if it's profitable to narrow operations of type VT1 to
1675 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1677 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1681 /// \brief Return true if it is beneficial to convert a load of a constant to
1682 /// just the constant itself.
1683 /// On some targets it might be more efficient to use a combination of
1684 /// arithmetic instructions to materialize the constant instead of loading it
1685 /// from a constant pool.
1686 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1691 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1692 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1693 /// has custom lowering that depends on the index of the first element,
1694 /// and only the target knows which lowering is cheap.
1695 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1699 //===--------------------------------------------------------------------===//
1700 // Runtime Library hooks
1703 /// Rename the default libcall routine name for the specified libcall.
1704 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1705 LibcallRoutineNames[Call] = Name;
1708 /// Get the libcall routine name for the specified libcall.
1709 const char *getLibcallName(RTLIB::Libcall Call) const {
1710 return LibcallRoutineNames[Call];
1713 /// Override the default CondCode to be used to test the result of the
1714 /// comparison libcall against zero.
1715 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1716 CmpLibcallCCs[Call] = CC;
1719 /// Get the CondCode that's to be used to test the result of the comparison
1720 /// libcall against zero.
1721 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1722 return CmpLibcallCCs[Call];
1725 /// Set the CallingConv that should be used for the specified libcall.
1726 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1727 LibcallCallingConvs[Call] = CC;
1730 /// Get the CallingConv that should be used for the specified libcall.
1731 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1732 return LibcallCallingConvs[Call];
1736 const TargetMachine &TM;
1738 /// Tells the code generator not to expand operations into sequences that use
1739 /// the select operations if possible.
1740 bool SelectIsExpensive;
1742 /// Tells the code generator that the target has multiple (allocatable)
1743 /// condition registers that can be used to store the results of comparisons
1744 /// for use by selects and conditional branches. With multiple condition
1745 /// registers, the code generator will not aggressively sink comparisons into
1746 /// the blocks of their users.
1747 bool HasMultipleConditionRegisters;
1749 /// Tells the code generator that the target has BitExtract instructions.
1750 /// The code generator will aggressively sink "shift"s into the blocks of
1751 /// their users if the users will generate "and" instructions which can be
1752 /// combined with "shift" to BitExtract instructions.
1753 bool HasExtractBitsInsn;
1755 /// Tells the code generator not to expand integer divides by constants into a
1756 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1757 /// model is in place. If we ever optimize for size, this will be set to true
1758 /// unconditionally.
1761 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1764 /// Tells the code generator to bypass slow divide or remainder
1765 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1766 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1767 /// div/rem when the operands are positive and less than 256.
1768 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1770 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1771 /// signed divide by power of two; let the target handle it.
1772 bool Pow2SDivIsCheap;
1774 /// Tells the code generator that it shouldn't generate extra flow control
1775 /// instructions and should attempt to combine flow control instructions via
1777 bool JumpIsExpensive;
1779 /// Whether the target supports or cares about preserving floating point
1780 /// exception behavior.
1781 bool HasFloatingPointExceptions;
1783 /// This target prefers to use _setjmp to implement llvm.setjmp.
1785 /// Defaults to false.
1786 bool UseUnderscoreSetJmp;
1788 /// This target prefers to use _longjmp to implement llvm.longjmp.
1790 /// Defaults to false.
1791 bool UseUnderscoreLongJmp;
1793 /// Number of blocks threshold to use jump tables.
1794 int MinimumJumpTableEntries;
1796 /// Information about the contents of the high-bits in boolean values held in
1797 /// a type wider than i1. See getBooleanContents.
1798 BooleanContent BooleanContents;
1800 /// Information about the contents of the high-bits in boolean values held in
1801 /// a type wider than i1. See getBooleanContents.
1802 BooleanContent BooleanFloatContents;
1804 /// Information about the contents of the high-bits in boolean vector values
1805 /// when the element type is wider than i1. See getBooleanContents.
1806 BooleanContent BooleanVectorContents;
1808 /// The target scheduling preference: shortest possible total cycles or lowest
1810 Sched::Preference SchedPreferenceInfo;
1812 /// The size, in bytes, of the target's jmp_buf buffers
1813 unsigned JumpBufSize;
1815 /// The alignment, in bytes, of the target's jmp_buf buffers
1816 unsigned JumpBufAlignment;
1818 /// The minimum alignment that any argument on the stack needs to have.
1819 unsigned MinStackArgumentAlignment;
1821 /// The minimum function alignment (used when optimizing for size, and to
1822 /// prevent explicitly provided alignment from leading to incorrect code).
1823 unsigned MinFunctionAlignment;
1825 /// The preferred function alignment (used when alignment unspecified and
1826 /// optimizing for speed).
1827 unsigned PrefFunctionAlignment;
1829 /// The preferred loop alignment.
1830 unsigned PrefLoopAlignment;
1832 /// Whether the DAG builder should automatically insert fences and reduce
1833 /// ordering for atomics. (This will be set for for most architectures with
1834 /// weak memory ordering.)
1835 bool InsertFencesForAtomic;
1837 /// If set to a physical register, this specifies the register that
1838 /// llvm.savestack/llvm.restorestack should save and restore.
1839 unsigned StackPointerRegisterToSaveRestore;
1841 /// If set to a physical register, this specifies the register that receives
1842 /// the exception address on entry to a landing pad.
1843 unsigned ExceptionPointerRegister;
1845 /// If set to a physical register, this specifies the register that receives
1846 /// the exception typeid on entry to a landing pad.
1847 unsigned ExceptionSelectorRegister;
1849 /// This indicates the default register class to use for each ValueType the
1850 /// target supports natively.
1851 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1852 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1853 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1855 /// This indicates the "representative" register class to use for each
1856 /// ValueType the target supports natively. This information is used by the
1857 /// scheduler to track register pressure. By default, the representative
1858 /// register class is the largest legal super-reg register class of the
1859 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1860 /// representative class would be GR32.
1861 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1863 /// This indicates the "cost" of the "representative" register class for each
1864 /// ValueType. The cost is used by the scheduler to approximate register
1866 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1868 /// For any value types we are promoting or expanding, this contains the value
1869 /// type that we are changing to. For Expanded types, this contains one step
1870 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1871 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1872 /// the same type (e.g. i32 -> i32).
1873 MVT TransformToType[MVT::LAST_VALUETYPE];
1875 /// For each operation and each value type, keep a LegalizeAction that
1876 /// indicates how instruction selection should deal with the operation. Most
1877 /// operations are Legal (aka, supported natively by the target), but
1878 /// operations that are not should be described. Note that operations on
1879 /// non-legal value types are not described here.
1880 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1882 /// For each load extension type and each value type, keep a LegalizeAction
1883 /// that indicates how instruction selection should deal with a load of a
1884 /// specific value type and extension type.
1885 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1886 [ISD::LAST_LOADEXT_TYPE];
1888 /// For each value type pair keep a LegalizeAction that indicates whether a
1889 /// truncating store of a specific value type and truncating type is legal.
1890 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1892 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1893 /// that indicates how instruction selection should deal with the load /
1896 /// The first dimension is the value_type for the reference. The second
1897 /// dimension represents the various modes for load store.
1898 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1900 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1901 /// indicates how instruction selection should deal with the condition code.
1903 /// Because each CC action takes up 2 bits, we need to have the array size be
1904 /// large enough to fit all of the value types. This can be done by rounding
1905 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1906 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1908 ValueTypeActionImpl ValueTypeActions;
1911 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1914 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1916 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1917 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1920 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1922 /// For operations that must be promoted to a specific type, this holds the
1923 /// destination type. This map should be sparse, so don't hold it as an
1926 /// Targets add entries to this map with AddPromotedToType(..), clients access
1927 /// this with getTypeToPromoteTo(..).
1928 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1931 /// Stores the name each libcall.
1932 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1934 /// The ISD::CondCode that should be used to test the result of each of the
1935 /// comparison libcall against zero.
1936 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1938 /// Stores the CallingConv that should be used for each libcall.
1939 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1942 /// Return true if the extension represented by \p I is free.
1943 /// \pre \p I is a sign, zero, or fp extension and
1944 /// is[Z|FP]ExtFree of the related types is not true.
1945 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1947 /// \brief Specify maximum number of store instructions per memset call.
1949 /// When lowering \@llvm.memset this field specifies the maximum number of
1950 /// store operations that may be substituted for the call to memset. Targets
1951 /// must set this value based on the cost threshold for that target. Targets
1952 /// should assume that the memset will be done using as many of the largest
1953 /// store operations first, followed by smaller ones, if necessary, per
1954 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1955 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1956 /// store. This only applies to setting a constant array of a constant size.
1957 unsigned MaxStoresPerMemset;
1959 /// Maximum number of stores operations that may be substituted for the call
1960 /// to memset, used for functions with OptSize attribute.
1961 unsigned MaxStoresPerMemsetOptSize;
1963 /// \brief Specify maximum bytes of store instructions per memcpy call.
1965 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1966 /// store operations that may be substituted for a call to memcpy. Targets
1967 /// must set this value based on the cost threshold for that target. Targets
1968 /// should assume that the memcpy will be done using as many of the largest
1969 /// store operations first, followed by smaller ones, if necessary, per
1970 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1971 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1972 /// and one 1-byte store. This only applies to copying a constant array of
1974 unsigned MaxStoresPerMemcpy;
1976 /// Maximum number of store operations that may be substituted for a call to
1977 /// memcpy, used for functions with OptSize attribute.
1978 unsigned MaxStoresPerMemcpyOptSize;
1980 /// \brief Specify maximum bytes of store instructions per memmove call.
1982 /// When lowering \@llvm.memmove this field specifies the maximum number of
1983 /// store instructions that may be substituted for a call to memmove. Targets
1984 /// must set this value based on the cost threshold for that target. Targets
1985 /// should assume that the memmove will be done using as many of the largest
1986 /// store operations first, followed by smaller ones, if necessary, per
1987 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1988 /// with 8-bit alignment would result in nine 1-byte stores. This only
1989 /// applies to copying a constant array of constant size.
1990 unsigned MaxStoresPerMemmove;
1992 /// Maximum number of store instructions that may be substituted for a call to
1993 /// memmove, used for functions with OpSize attribute.
1994 unsigned MaxStoresPerMemmoveOptSize;
1996 /// Tells the code generator that select is more expensive than a branch if
1997 /// the branch is usually predicted right.
1998 bool PredictableSelectIsExpensive;
2000 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
2001 /// a mask of a single bit, a compare, and a branch into a single instruction.
2002 bool MaskAndBranchFoldingIsLegal;
2004 /// \see enableExtLdPromotion.
2005 bool EnableExtLdPromotion;
2008 /// Return true if the value types that can be represented by the specified
2009 /// register class are all legal.
2010 bool isLegalRC(const TargetRegisterClass *RC) const;
2012 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2013 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2014 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
2015 MachineBasicBlock *MBB) const;
2018 /// This class defines information used to lower LLVM code to legal SelectionDAG
2019 /// operators that the target instruction selector can accept natively.
2021 /// This class also defines callbacks that targets must implement to lower
2022 /// target-specific constructs to SelectionDAG operators.
2023 class TargetLowering : public TargetLoweringBase {
2024 TargetLowering(const TargetLowering&) = delete;
2025 void operator=(const TargetLowering&) = delete;
2028 /// NOTE: The TargetMachine owns TLOF.
2029 explicit TargetLowering(const TargetMachine &TM);
2031 /// Returns true by value, base pointer and offset pointer and addressing mode
2032 /// by reference if the node's address can be legally represented as
2033 /// pre-indexed load / store address.
2034 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2035 SDValue &/*Offset*/,
2036 ISD::MemIndexedMode &/*AM*/,
2037 SelectionDAG &/*DAG*/) const {
2041 /// Returns true by value, base pointer and offset pointer and addressing mode
2042 /// by reference if this node can be combined with a load / store to form a
2043 /// post-indexed load / store.
2044 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2046 SDValue &/*Offset*/,
2047 ISD::MemIndexedMode &/*AM*/,
2048 SelectionDAG &/*DAG*/) const {
2052 /// Return the entry encoding for a jump table in the current function. The
2053 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2054 virtual unsigned getJumpTableEncoding() const;
2056 virtual const MCExpr *
2057 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2058 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2059 MCContext &/*Ctx*/) const {
2060 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2063 /// Returns relocation base for the given PIC jumptable.
2064 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2065 SelectionDAG &DAG) const;
2067 /// This returns the relocation base for the given PIC jumptable, the same as
2068 /// getPICJumpTableRelocBase, but as an MCExpr.
2069 virtual const MCExpr *
2070 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2071 unsigned JTI, MCContext &Ctx) const;
2073 /// Return true if folding a constant offset with the given GlobalAddress is
2074 /// legal. It is frequently not legal in PIC relocation models.
2075 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2077 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2078 SDValue &Chain) const;
2080 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2081 SDValue &NewLHS, SDValue &NewRHS,
2082 ISD::CondCode &CCCode, SDLoc DL) const;
2084 /// Returns a pair of (return value, chain).
2085 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2086 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2087 EVT RetVT, const SDValue *Ops,
2088 unsigned NumOps, bool isSigned,
2089 SDLoc dl, bool doesNotReturn = false,
2090 bool isReturnValueUsed = true) const;
2092 //===--------------------------------------------------------------------===//
2093 // TargetLowering Optimization Methods
2096 /// A convenience struct that encapsulates a DAG, and two SDValues for
2097 /// returning information from TargetLowering to its clients that want to
2099 struct TargetLoweringOpt {
2106 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2108 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2110 bool LegalTypes() const { return LegalTys; }
2111 bool LegalOperations() const { return LegalOps; }
2113 bool CombineTo(SDValue O, SDValue N) {
2119 /// Check to see if the specified operand of the specified instruction is a
2120 /// constant integer. If so, check to see if there are any bits set in the
2121 /// constant that are not demanded. If so, shrink the constant and return
2123 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2125 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2126 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2127 /// generalized for targets with other types of implicit widening casts.
2128 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2132 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2133 /// result of Op are ever used downstream. If we can use this information to
2134 /// simplify Op, create a new simplified DAG node and return true, returning
2135 /// the original and new nodes in Old and New. Otherwise, analyze the
2136 /// expression and return a mask of KnownOne and KnownZero bits for the
2137 /// expression (used to simplify the caller). The KnownZero/One bits may only
2138 /// be accurate for those bits in the DemandedMask.
2139 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2140 APInt &KnownZero, APInt &KnownOne,
2141 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2143 /// Determine which of the bits specified in Mask are known to be either zero
2144 /// or one and return them in the KnownZero/KnownOne bitsets.
2145 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2148 const SelectionDAG &DAG,
2149 unsigned Depth = 0) const;
2151 /// This method can be implemented by targets that want to expose additional
2152 /// information about sign bits to the DAG Combiner.
2153 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2154 const SelectionDAG &DAG,
2155 unsigned Depth = 0) const;
2157 struct DAGCombinerInfo {
2158 void *DC; // The DAG Combiner object.
2160 bool CalledByLegalizer;
2164 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2165 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2167 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2168 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2169 bool isAfterLegalizeVectorOps() const {
2170 return Level == AfterLegalizeDAG;
2172 CombineLevel getDAGCombineLevel() { return Level; }
2173 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2175 void AddToWorklist(SDNode *N);
2176 void RemoveFromWorklist(SDNode *N);
2177 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2178 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2179 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2181 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2184 /// Return if the N is a constant or constant vector equal to the true value
2185 /// from getBooleanContents().
2186 bool isConstTrueVal(const SDNode *N) const;
2188 /// Return if the N is a constant or constant vector equal to the false value
2189 /// from getBooleanContents().
2190 bool isConstFalseVal(const SDNode *N) const;
2192 /// Try to simplify a setcc built with the specified operands and cc. If it is
2193 /// unable to simplify it, return a null SDValue.
2194 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2195 ISD::CondCode Cond, bool foldBooleans,
2196 DAGCombinerInfo &DCI, SDLoc dl) const;
2198 /// Returns true (and the GlobalValue and the offset) if the node is a
2199 /// GlobalAddress + offset.
2201 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2203 /// This method will be invoked for all target nodes and for any
2204 /// target-independent nodes that the target has registered with invoke it
2207 /// The semantics are as follows:
2209 /// SDValue.Val == 0 - No change was made
2210 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2211 /// otherwise - N should be replaced by the returned Operand.
2213 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2214 /// more complex transformations.
2216 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2218 /// Return true if it is profitable to move a following shift through this
2219 // node, adjusting any immediate operands as necessary to preserve semantics.
2220 // This transformation may not be desirable if it disrupts a particularly
2221 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2222 // By default, it returns true.
2223 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2227 /// Return true if the target has native support for the specified value type
2228 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2229 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2230 /// and some i16 instructions are slow.
2231 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2232 // By default, assume all legal types are desirable.
2233 return isTypeLegal(VT);
2236 /// Return true if it is profitable for dag combiner to transform a floating
2237 /// point op of specified opcode to a equivalent op of an integer
2238 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2239 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2244 /// This method query the target whether it is beneficial for dag combiner to
2245 /// promote the specified node. If true, it should return the desired
2246 /// promotion type by reference.
2247 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2251 //===--------------------------------------------------------------------===//
2252 // Lowering methods - These methods must be implemented by targets so that
2253 // the SelectionDAGBuilder code knows how to lower these.
2256 /// This hook must be implemented to lower the incoming (formal) arguments,
2257 /// described by the Ins array, into the specified DAG. The implementation
2258 /// should fill in the InVals array with legal-type argument values, and
2259 /// return the resulting token chain value.
2262 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2264 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2265 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2266 SmallVectorImpl<SDValue> &/*InVals*/) const {
2267 llvm_unreachable("Not Implemented");
2270 struct ArgListEntry {
2279 bool isInAlloca : 1;
2280 bool isReturned : 1;
2283 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2284 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2285 isReturned(false), Alignment(0) { }
2287 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2289 typedef std::vector<ArgListEntry> ArgListTy;
2291 /// This structure contains all information that is necessary for lowering
2292 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2293 /// needs to lower a call, and targets will see this struct in their LowerCall
2295 struct CallLoweringInfo {
2302 bool DoesNotReturn : 1;
2303 bool IsReturnValueUsed : 1;
2305 // IsTailCall should be modified by implementations of
2306 // TargetLowering::LowerCall that perform tail call conversions.
2309 unsigned NumFixedArgs;
2310 CallingConv::ID CallConv;
2315 ImmutableCallSite *CS;
2317 SmallVector<ISD::OutputArg, 32> Outs;
2318 SmallVector<SDValue, 32> OutVals;
2319 SmallVector<ISD::InputArg, 32> Ins;
2321 CallLoweringInfo(SelectionDAG &DAG)
2322 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2323 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2324 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2325 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2327 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2332 CallLoweringInfo &setChain(SDValue InChain) {
2337 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2338 SDValue Target, ArgListTy &&ArgsList,
2339 unsigned FixedArgs = -1) {
2344 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2345 Args = std::move(ArgsList);
2349 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2350 SDValue Target, ArgListTy &&ArgsList,
2351 ImmutableCallSite &Call) {
2354 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2355 DoesNotReturn = Call.doesNotReturn();
2356 IsVarArg = FTy->isVarArg();
2357 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2358 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2359 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2363 CallConv = Call.getCallingConv();
2364 NumFixedArgs = FTy->getNumParams();
2365 Args = std::move(ArgsList);
2372 CallLoweringInfo &setInRegister(bool Value = true) {
2377 CallLoweringInfo &setNoReturn(bool Value = true) {
2378 DoesNotReturn = Value;
2382 CallLoweringInfo &setVarArg(bool Value = true) {
2387 CallLoweringInfo &setTailCall(bool Value = true) {
2392 CallLoweringInfo &setDiscardResult(bool Value = true) {
2393 IsReturnValueUsed = !Value;
2397 CallLoweringInfo &setSExtResult(bool Value = true) {
2402 CallLoweringInfo &setZExtResult(bool Value = true) {
2407 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2408 IsPatchPoint = Value;
2412 ArgListTy &getArgs() {
2418 /// This function lowers an abstract call to a function into an actual call.
2419 /// This returns a pair of operands. The first element is the return value
2420 /// for the function (if RetTy is not VoidTy). The second element is the
2421 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2422 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2424 /// This hook must be implemented to lower calls into the specified
2425 /// DAG. The outgoing arguments to the call are described by the Outs array,
2426 /// and the values to be returned by the call are described by the Ins
2427 /// array. The implementation should fill in the InVals array with legal-type
2428 /// return values from the call, and return the resulting token chain value.
2430 LowerCall(CallLoweringInfo &/*CLI*/,
2431 SmallVectorImpl<SDValue> &/*InVals*/) const {
2432 llvm_unreachable("Not Implemented");
2435 /// Target-specific cleanup for formal ByVal parameters.
2436 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2438 /// This hook should be implemented to check whether the return values
2439 /// described by the Outs array can fit into the return registers. If false
2440 /// is returned, an sret-demotion is performed.
2441 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2442 MachineFunction &/*MF*/, bool /*isVarArg*/,
2443 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2444 LLVMContext &/*Context*/) const
2446 // Return true by default to get preexisting behavior.
2450 /// This hook must be implemented to lower outgoing return values, described
2451 /// by the Outs array, into the specified DAG. The implementation should
2452 /// return the resulting token chain value.
2454 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2456 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2457 const SmallVectorImpl<SDValue> &/*OutVals*/,
2458 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2459 llvm_unreachable("Not Implemented");
2462 /// Return true if result of the specified node is used by a return node
2463 /// only. It also compute and return the input chain for the tail call.
2465 /// This is used to determine whether it is possible to codegen a libcall as
2466 /// tail call at legalization time.
2467 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2471 /// Return true if the target may be able emit the call instruction as a tail
2472 /// call. This is used by optimization passes to determine if it's profitable
2473 /// to duplicate return instructions to enable tailcall optimization.
2474 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2478 /// Return the builtin name for the __builtin___clear_cache intrinsic
2479 /// Default is to invoke the clear cache library call
2480 virtual const char * getClearCacheBuiltinName() const {
2481 return "__clear_cache";
2484 /// Return the register ID of the name passed in. Used by named register
2485 /// global variables extension. There is no target-independent behaviour
2486 /// so the default action is to bail.
2487 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2488 report_fatal_error("Named registers not implemented for this target");
2491 /// Return the type that should be used to zero or sign extend a
2492 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2493 /// convention requires the return type to be promoted, but this is not true
2494 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2495 /// calling conventions. The frontend should handle this and include all of
2496 /// the necessary information.
2497 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2498 ISD::NodeType /*ExtendKind*/) const {
2499 EVT MinVT = getRegisterType(Context, MVT::i32);
2500 return VT.bitsLT(MinVT) ? MinVT : VT;
2503 /// For some targets, an LLVM struct type must be broken down into multiple
2504 /// simple types, but the calling convention specifies that the entire struct
2505 /// must be passed in a block of consecutive registers.
2507 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2508 bool isVarArg) const {
2512 /// Returns a 0 terminated array of registers that can be safely used as
2513 /// scratch registers.
2514 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2518 /// This callback is used to prepare for a volatile or atomic load.
2519 /// It takes a chain node as input and returns the chain for the load itself.
2521 /// Having a callback like this is necessary for targets like SystemZ,
2522 /// which allows a CPU to reuse the result of a previous load indefinitely,
2523 /// even if a cache-coherent store is performed by another CPU. The default
2524 /// implementation does nothing.
2525 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2526 SelectionDAG &DAG) const {
2530 /// This callback is invoked by the type legalizer to legalize nodes with an
2531 /// illegal operand type but legal result types. It replaces the
2532 /// LowerOperation callback in the type Legalizer. The reason we can not do
2533 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2534 /// use this callback.
2536 /// TODO: Consider merging with ReplaceNodeResults.
2538 /// The target places new result values for the node in Results (their number
2539 /// and types must exactly match those of the original return values of
2540 /// the node), or leaves Results empty, which indicates that the node is not
2541 /// to be custom lowered after all.
2542 /// The default implementation calls LowerOperation.
2543 virtual void LowerOperationWrapper(SDNode *N,
2544 SmallVectorImpl<SDValue> &Results,
2545 SelectionDAG &DAG) const;
2547 /// This callback is invoked for operations that are unsupported by the
2548 /// target, which are registered to use 'custom' lowering, and whose defined
2549 /// values are all legal. If the target has no operations that require custom
2550 /// lowering, it need not implement this. The default implementation of this
2552 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2554 /// This callback is invoked when a node result type is illegal for the
2555 /// target, and the operation was registered to use 'custom' lowering for that
2556 /// result type. The target places new result values for the node in Results
2557 /// (their number and types must exactly match those of the original return
2558 /// values of the node), or leaves Results empty, which indicates that the
2559 /// node is not to be custom lowered after all.
2561 /// If the target has no operations that require custom lowering, it need not
2562 /// implement this. The default implementation aborts.
2563 virtual void ReplaceNodeResults(SDNode * /*N*/,
2564 SmallVectorImpl<SDValue> &/*Results*/,
2565 SelectionDAG &/*DAG*/) const {
2566 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2569 /// This method returns the name of a target specific DAG node.
2570 virtual const char *getTargetNodeName(unsigned Opcode) const;
2572 /// This method returns a target specific FastISel object, or null if the
2573 /// target does not support "fast" ISel.
2574 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2575 const TargetLibraryInfo *) const {
2580 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2581 SelectionDAG &DAG) const;
2583 //===--------------------------------------------------------------------===//
2584 // Inline Asm Support hooks
2587 /// This hook allows the target to expand an inline asm call to be explicit
2588 /// llvm code if it wants to. This is useful for turning simple inline asms
2589 /// into LLVM intrinsics, which gives the compiler more information about the
2590 /// behavior of the code.
2591 virtual bool ExpandInlineAsm(CallInst *) const {
2595 enum ConstraintType {
2596 C_Register, // Constraint represents specific register(s).
2597 C_RegisterClass, // Constraint represents any of register(s) in class.
2598 C_Memory, // Memory constraint.
2599 C_Other, // Something else.
2600 C_Unknown // Unsupported constraint.
2603 enum ConstraintWeight {
2605 CW_Invalid = -1, // No match.
2606 CW_Okay = 0, // Acceptable.
2607 CW_Good = 1, // Good weight.
2608 CW_Better = 2, // Better weight.
2609 CW_Best = 3, // Best weight.
2611 // Well-known weights.
2612 CW_SpecificReg = CW_Okay, // Specific register operands.
2613 CW_Register = CW_Good, // Register operands.
2614 CW_Memory = CW_Better, // Memory operands.
2615 CW_Constant = CW_Best, // Constant operand.
2616 CW_Default = CW_Okay // Default or don't know type.
2619 /// This contains information for each constraint that we are lowering.
2620 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2621 /// This contains the actual string for the code, like "m". TargetLowering
2622 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2623 /// matches the operand.
2624 std::string ConstraintCode;
2626 /// Information about the constraint code, e.g. Register, RegisterClass,
2627 /// Memory, Other, Unknown.
2628 TargetLowering::ConstraintType ConstraintType;
2630 /// If this is the result output operand or a clobber, this is null,
2631 /// otherwise it is the incoming operand to the CallInst. This gets
2632 /// modified as the asm is processed.
2633 Value *CallOperandVal;
2635 /// The ValueType for the operand value.
2638 /// Return true of this is an input operand that is a matching constraint
2640 bool isMatchingInputConstraint() const;
2642 /// If this is an input matching constraint, this method returns the output
2643 /// operand it matches.
2644 unsigned getMatchedOperand() const;
2646 /// Copy constructor for copying from a ConstraintInfo.
2647 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2648 : InlineAsm::ConstraintInfo(std::move(Info)),
2649 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2650 ConstraintVT(MVT::Other) {}
2653 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2655 /// Split up the constraint string from the inline assembly value into the
2656 /// specific constraints and their prefixes, and also tie in the associated
2657 /// operand values. If this returns an empty vector, and if the constraint
2658 /// string itself isn't empty, there was an error parsing.
2659 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2660 const TargetRegisterInfo *TRI,
2661 ImmutableCallSite CS) const;
2663 /// Examine constraint type and operand type and determine a weight value.
2664 /// The operand object must already have been set up with the operand type.
2665 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2666 AsmOperandInfo &info, int maIndex) const;
2668 /// Examine constraint string and operand type and determine a weight value.
2669 /// The operand object must already have been set up with the operand type.
2670 virtual ConstraintWeight getSingleConstraintMatchWeight(
2671 AsmOperandInfo &info, const char *constraint) const;
2673 /// Determines the constraint code and constraint type to use for the specific
2674 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2675 /// If the actual operand being passed in is available, it can be passed in as
2676 /// Op, otherwise an empty SDValue can be passed.
2677 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2679 SelectionDAG *DAG = nullptr) const;
2681 /// Given a constraint, return the type of constraint it is for this target.
2682 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2684 /// Given a physical register constraint (e.g. {edx}), return the register
2685 /// number and the register class for the register.
2687 /// Given a register class constraint, like 'r', if this corresponds directly
2688 /// to an LLVM register class, return a register of 0 and the register class
2691 /// This should only be used for C_Register constraints. On error, this
2692 /// returns a register number of 0 and a null register class pointer.
2693 virtual std::pair<unsigned, const TargetRegisterClass *>
2694 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2695 StringRef Constraint, MVT VT) const;
2697 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2698 if (ConstraintCode == "i")
2699 return InlineAsm::Constraint_i;
2700 else if (ConstraintCode == "m")
2701 return InlineAsm::Constraint_m;
2702 return InlineAsm::Constraint_Unknown;
2705 /// Try to replace an X constraint, which matches anything, with another that
2706 /// has more specific requirements based on the type of the corresponding
2707 /// operand. This returns null if there is no replacement to make.
2708 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2710 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2711 /// add anything to Ops.
2712 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2713 std::vector<SDValue> &Ops,
2714 SelectionDAG &DAG) const;
2716 //===--------------------------------------------------------------------===//
2717 // Div utility functions
2719 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2720 bool IsAfterLegalization,
2721 std::vector<SDNode *> *Created) const;
2722 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2723 bool IsAfterLegalization,
2724 std::vector<SDNode *> *Created) const;
2725 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2727 std::vector<SDNode *> *Created) const {
2731 /// Indicate whether this target prefers to combine the given number of FDIVs
2732 /// with the same divisor.
2733 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2737 /// Hooks for building estimates in place of slower divisions and square
2740 /// Return a reciprocal square root estimate value for the input operand.
2741 /// The RefinementSteps output is the number of Newton-Raphson refinement
2742 /// iterations required to generate a sufficient (though not necessarily
2743 /// IEEE-754 compliant) estimate for the value type.
2744 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2745 /// algorithm implementation that uses one constant or two constants.
2746 /// A target may choose to implement its own refinement within this function.
2747 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2748 /// any further refinement of the estimate.
2749 /// An empty SDValue return means no estimate sequence can be created.
2750 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2751 unsigned &RefinementSteps,
2752 bool &UseOneConstNR) const {
2756 /// Return a reciprocal estimate value for the input operand.
2757 /// The RefinementSteps output is the number of Newton-Raphson refinement
2758 /// iterations required to generate a sufficient (though not necessarily
2759 /// IEEE-754 compliant) estimate for the value type.
2760 /// A target may choose to implement its own refinement within this function.
2761 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2762 /// any further refinement of the estimate.
2763 /// An empty SDValue return means no estimate sequence can be created.
2764 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2765 unsigned &RefinementSteps) const {
2769 //===--------------------------------------------------------------------===//
2770 // Legalization utility functions
2773 /// Expand a MUL into two nodes. One that computes the high bits of
2774 /// the result and one that computes the low bits.
2775 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2776 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2777 /// if you want to control how low bits are extracted from the LHS.
2778 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2779 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2780 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2781 /// \returns true if the node has been expanded. false if it has not
2782 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2783 SelectionDAG &DAG, SDValue LL = SDValue(),
2784 SDValue LH = SDValue(), SDValue RL = SDValue(),
2785 SDValue RH = SDValue()) const;
2787 /// Expand float(f32) to SINT(i64) conversion
2788 /// \param N Node to expand
2789 /// \param Result output after conversion
2790 /// \returns True, if the expansion was successful, false otherwise
2791 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2793 //===--------------------------------------------------------------------===//
2794 // Instruction Emitting Hooks
2797 /// This method should be implemented by targets that mark instructions with
2798 /// the 'usesCustomInserter' flag. These instructions are special in various
2799 /// ways, which require special support to insert. The specified MachineInstr
2800 /// is created but not inserted into any basic blocks, and this method is
2801 /// called to expand it into a sequence of instructions, potentially also
2802 /// creating new basic blocks and control flow.
2803 /// As long as the returned basic block is different (i.e., we created a new
2804 /// one), the custom inserter is free to modify the rest of \p MBB.
2805 virtual MachineBasicBlock *
2806 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2808 /// This method should be implemented by targets that mark instructions with
2809 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2810 /// instruction selection by target hooks. e.g. To fill in optional defs for
2811 /// ARM 's' setting instructions.
2813 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2815 /// If this function returns true, SelectionDAGBuilder emits a
2816 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2817 virtual bool useLoadStackGuardNode() const {
2822 /// Given an LLVM IR type and return type attributes, compute the return value
2823 /// EVTs and flags, and optionally also the offsets, if the return value is
2824 /// being lowered to memory.
2825 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
2826 SmallVectorImpl<ISD::OutputArg> &Outs,
2827 const TargetLowering &TLI, const DataLayout &DL);
2829 } // end llvm namespace