1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/Support/DebugLoc.h"
34 #include "llvm/Target/TargetMachine.h"
44 class MachineBasicBlock;
45 class MachineFunction;
46 class MachineFrameInfo;
48 class MachineModuleInfo;
55 class TargetRegisterClass;
56 class TargetSubtarget;
57 class TargetLoweringObjectFile;
60 // FIXME: should this be here?
69 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
72 //===----------------------------------------------------------------------===//
73 /// TargetLowering - This class defines information used to lower LLVM code to
74 /// legal SelectionDAG operators that the target instruction selector can accept
77 /// This class also defines callbacks that targets must implement to lower
78 /// target-specific constructs to SelectionDAG operators.
80 class TargetLowering {
81 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
82 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
84 /// LegalizeAction - This enum indicates whether operations are valid for a
85 /// target, and if not, what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 enum BooleanContent { // How the target represents true/false values.
94 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
95 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
96 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
99 enum SchedPreference {
100 SchedulingForLatency, // Scheduling for shortest total latency.
101 SchedulingForRegPressure // Scheduling for lowest register pressure.
104 /// NOTE: The constructor takes ownership of TLOF.
105 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
106 virtual ~TargetLowering();
108 TargetMachine &getTargetMachine() const { return TM; }
109 const TargetData *getTargetData() const { return TD; }
110 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT::SimpleValueType getPointerTy() const { return PointerTy; }
115 MVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
117 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
119 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
121 /// isSelectExpensive - Return true if the select operation is expensive for
123 bool isSelectExpensive() const { return SelectIsExpensive; }
125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
126 /// a sequence of several shifts, adds, and multiplies for this target.
127 bool isIntDivCheap() const { return IntDivIsCheap; }
129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
131 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
133 /// getSetCCResultType - Return the ValueType of the result of SETCC
134 /// operations. Also used to obtain the target's preferred type for
135 /// the condition operand of SELECT and BRCOND nodes. In the case of
136 /// BRCOND the argument passed is MVT::Other since there are no other
137 /// operands to get a type hint from.
139 MVT::SimpleValueType getSetCCResultType(MVT VT) const;
141 /// getBooleanContents - For targets without i1 registers, this gives the
142 /// nature of the high-bits of boolean values held in types wider than i1.
143 /// "Boolean values" are special true/false values produced by nodes like
144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
145 /// Not to be confused with general values promoted from i1.
146 BooleanContent getBooleanContents() const { return BooleanContents;}
148 /// getSchedulingPreference - Return target scheduling preference.
149 SchedPreference getSchedulingPreference() const {
150 return SchedPreferenceInfo;
153 /// getRegClassFor - Return the register class that should be used for the
154 /// specified value type. This may only be called on legal types.
155 TargetRegisterClass *getRegClassFor(MVT VT) const {
156 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
157 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
158 assert(RC && "This value type is not natively supported!");
162 /// isTypeLegal - Return true if the target has native support for the
163 /// specified value type. This means that it has a register that directly
164 /// holds it without promotions or expansions.
165 bool isTypeLegal(MVT VT) const {
166 assert(!VT.isSimple() ||
167 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
168 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
171 class ValueTypeActionImpl {
172 /// ValueTypeActions - This is a bitvector that contains two bits for each
173 /// value type, where the two bits correspond to the LegalizeAction enum.
174 /// This can be queried with "getTypeAction(VT)".
175 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
176 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
178 ValueTypeActionImpl() {
179 ValueTypeActions[0] = ValueTypeActions[1] = 0;
180 ValueTypeActions[2] = ValueTypeActions[3] = 0;
182 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
183 ValueTypeActions[0] = RHS.ValueTypeActions[0];
184 ValueTypeActions[1] = RHS.ValueTypeActions[1];
185 ValueTypeActions[2] = RHS.ValueTypeActions[2];
186 ValueTypeActions[3] = RHS.ValueTypeActions[3];
189 LegalizeAction getTypeAction(MVT VT) const {
190 if (VT.isExtended()) {
192 return VT.isPow2VectorType() ? Expand : Promote;
195 // First promote to a power-of-two size, then expand if necessary.
196 return VT == VT.getRoundIntegerType() ? Expand : Promote;
197 assert(0 && "Unsupported extended type!");
200 unsigned I = VT.getSimpleVT();
201 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
202 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
204 void setTypeAction(MVT VT, LegalizeAction Action) {
205 unsigned I = VT.getSimpleVT();
206 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
207 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
211 const ValueTypeActionImpl &getValueTypeActions() const {
212 return ValueTypeActions;
215 /// getTypeAction - Return how we should legalize values of this type, either
216 /// it is already legal (return 'Legal') or we need to promote it to a larger
217 /// type (return 'Promote'), or we need to expand it into multiple registers
218 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
219 LegalizeAction getTypeAction(MVT VT) const {
220 return ValueTypeActions.getTypeAction(VT);
223 /// getTypeToTransformTo - For types supported by the target, this is an
224 /// identity function. For types that must be promoted to larger types, this
225 /// returns the larger type to promote to. For integer types that are larger
226 /// than the largest integer register, this contains one step in the expansion
227 /// to get to the smaller register. For illegal floating point types, this
228 /// returns the integer type to transform to.
229 MVT getTypeToTransformTo(MVT VT) const {
231 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
232 MVT NVT = TransformToType[VT.getSimpleVT()];
233 assert(getTypeAction(NVT) != Promote &&
234 "Promote may not follow Expand or Promote");
239 MVT NVT = VT.getPow2VectorType();
241 // Vector length is a power of 2 - split to half the size.
242 unsigned NumElts = VT.getVectorNumElements();
243 MVT EltVT = VT.getVectorElementType();
244 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
246 // Promote to a power of two size, avoiding multi-step promotion.
247 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
248 } else if (VT.isInteger()) {
249 MVT NVT = VT.getRoundIntegerType();
251 // Size is a power of two - expand to half the size.
252 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
254 // Promote to a power of two size, avoiding multi-step promotion.
255 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
257 assert(0 && "Unsupported extended type!");
258 return MVT(MVT::Other); // Not reached
261 /// getTypeToExpandTo - For types supported by the target, this is an
262 /// identity function. For types that must be expanded (i.e. integer types
263 /// that are larger than the largest integer register or illegal floating
264 /// point types), this returns the largest legal type it will be expanded to.
265 MVT getTypeToExpandTo(MVT VT) const {
266 assert(!VT.isVector());
268 switch (getTypeAction(VT)) {
272 VT = getTypeToTransformTo(VT);
275 assert(false && "Type is not legal nor is it to be expanded!");
282 /// getVectorTypeBreakdown - Vector types are broken down into some number of
283 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
284 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
285 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
287 /// This method returns the number of registers needed, and the VT for each
288 /// register. It also returns the VT and quantity of the intermediate values
289 /// before they are promoted/expanded.
291 unsigned getVectorTypeBreakdown(MVT VT,
293 unsigned &NumIntermediates,
294 MVT &RegisterVT) const;
296 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
297 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
298 /// this is the case, it returns true and store the intrinsic
299 /// information into the IntrinsicInfo that was passed to the function.
300 typedef struct IntrinsicInfo {
301 unsigned opc; // target opcode
302 MVT memVT; // memory VT
303 const Value* ptrVal; // value representing memory location
304 int offset; // offset off of ptrVal
305 unsigned align; // alignment
306 bool vol; // is volatile?
307 bool readMem; // reads memory?
308 bool writeMem; // writes memory?
311 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
312 CallInst &I, unsigned Intrinsic) {
316 /// getWidenVectorType: given a vector type, returns the type to widen to
317 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
318 /// If there is no vector type that we want to widen to, returns MVT::Other
319 /// When and were to widen is target dependent based on the cost of
320 /// scalarizing vs using the wider vector type.
321 virtual MVT getWidenVectorType(MVT VT) const;
323 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
324 legal_fpimm_iterator legal_fpimm_begin() const {
325 return LegalFPImmediates.begin();
327 legal_fpimm_iterator legal_fpimm_end() const {
328 return LegalFPImmediates.end();
331 /// isShuffleMaskLegal - Targets can use this to indicate that they only
332 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
333 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
334 /// are assumed to be legal.
335 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
340 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
341 /// used by Targets can use this to indicate if there is a suitable
342 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
344 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
349 /// getOperationAction - Return how this operation should be treated: either
350 /// it is legal, needs to be promoted to a larger size, needs to be
351 /// expanded to some other code sequence, or the target has a custom expander
353 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
354 if (VT.isExtended()) return Expand;
355 assert(Op < array_lengthof(OpActions[0]) &&
356 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
357 "Table isn't big enough!");
358 unsigned I = (unsigned) VT.getSimpleVT();
361 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
364 /// isOperationLegalOrCustom - Return true if the specified operation is
365 /// legal on this target or can be made legal with custom lowering. This
366 /// is used to help guide high-level lowering decisions.
367 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
368 return (VT == MVT::Other || isTypeLegal(VT)) &&
369 (getOperationAction(Op, VT) == Legal ||
370 getOperationAction(Op, VT) == Custom);
373 /// isOperationLegal - Return true if the specified operation is legal on this
375 bool isOperationLegal(unsigned Op, MVT VT) const {
376 return (VT == MVT::Other || isTypeLegal(VT)) &&
377 getOperationAction(Op, VT) == Legal;
380 /// getLoadExtAction - Return how this load with extension should be treated:
381 /// either it is legal, needs to be promoted to a larger size, needs to be
382 /// expanded to some other code sequence, or the target has a custom expander
384 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
385 assert(LType < array_lengthof(LoadExtActions) &&
386 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
387 "Table isn't big enough!");
388 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
391 /// isLoadExtLegal - Return true if the specified load with extension is legal
393 bool isLoadExtLegal(unsigned LType, MVT VT) const {
394 return VT.isSimple() &&
395 (getLoadExtAction(LType, VT) == Legal ||
396 getLoadExtAction(LType, VT) == Custom);
399 /// getTruncStoreAction - Return how this store with truncation should be
400 /// treated: either it is legal, needs to be promoted to a larger size, needs
401 /// to be expanded to some other code sequence, or the target has a custom
403 LegalizeAction getTruncStoreAction(MVT ValVT,
405 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
406 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
407 "Table isn't big enough!");
408 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
409 (2*MemVT.getSimpleVT())) & 3);
412 /// isTruncStoreLegal - Return true if the specified store with truncation is
413 /// legal on this target.
414 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
415 return isTypeLegal(ValVT) && MemVT.isSimple() &&
416 (getTruncStoreAction(ValVT, MemVT) == Legal ||
417 getTruncStoreAction(ValVT, MemVT) == Custom);
420 /// getIndexedLoadAction - Return how the indexed load should be treated:
421 /// either it is legal, needs to be promoted to a larger size, needs to be
422 /// expanded to some other code sequence, or the target has a custom expander
425 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
426 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
427 ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE &&
428 "Table isn't big enough!");
429 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
432 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
434 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
435 return VT.isSimple() &&
436 (getIndexedLoadAction(IdxMode, VT) == Legal ||
437 getIndexedLoadAction(IdxMode, VT) == Custom);
440 /// getIndexedStoreAction - Return how the indexed store should be treated:
441 /// either it is legal, needs to be promoted to a larger size, needs to be
442 /// expanded to some other code sequence, or the target has a custom expander
445 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
446 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
447 (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
448 "Table isn't big enough!");
449 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
452 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
454 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
455 return VT.isSimple() &&
456 (getIndexedStoreAction(IdxMode, VT) == Legal ||
457 getIndexedStoreAction(IdxMode, VT) == Custom);
460 /// getConvertAction - Return how the conversion should be treated:
461 /// either it is legal, needs to be promoted to a larger size, needs to be
462 /// expanded to some other code sequence, or the target has a custom expander
465 getConvertAction(MVT FromVT, MVT ToVT) const {
466 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
467 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
468 "Table isn't big enough!");
469 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
470 (2*ToVT.getSimpleVT())) & 3);
473 /// isConvertLegal - Return true if the specified conversion is legal
475 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
476 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
477 (getConvertAction(FromVT, ToVT) == Legal ||
478 getConvertAction(FromVT, ToVT) == Custom);
481 /// getCondCodeAction - Return how the condition code should be treated:
482 /// either it is legal, needs to be expanded to some other code sequence,
483 /// or the target has a custom expander for it.
485 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
486 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
487 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
488 "Table isn't big enough!");
489 LegalizeAction Action = (LegalizeAction)
490 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
491 assert(Action != Promote && "Can't promote condition code!");
495 /// isCondCodeLegal - Return true if the specified condition code is legal
497 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
498 return getCondCodeAction(CC, VT) == Legal ||
499 getCondCodeAction(CC, VT) == Custom;
503 /// getTypeToPromoteTo - If the action for this operation is to promote, this
504 /// method returns the ValueType to promote to.
505 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
506 assert(getOperationAction(Op, VT) == Promote &&
507 "This operation isn't promoted!");
509 // See if this has an explicit type specified.
510 std::map<std::pair<unsigned, MVT::SimpleValueType>,
511 MVT::SimpleValueType>::const_iterator PTTI =
512 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
513 if (PTTI != PromoteToType.end()) return PTTI->second;
515 assert((VT.isInteger() || VT.isFloatingPoint()) &&
516 "Cannot autopromote this type, add it with AddPromotedToType.");
520 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
521 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
522 "Didn't find type to promote to!");
523 } while (!isTypeLegal(NVT) ||
524 getOperationAction(Op, NVT) == Promote);
528 /// getValueType - Return the MVT corresponding to this LLVM type.
529 /// This is fixed by the LLVM operations except for the pointer size. If
530 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
531 /// counterpart (e.g. structs), otherwise it will assert.
532 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
533 MVT VT = MVT::getMVT(Ty, AllowUnknown);
534 return VT == MVT::iPTR ? PointerTy : VT;
537 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
538 /// function arguments in the caller parameter area. This is the actual
539 /// alignment, not its logarithm.
540 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
542 /// getRegisterType - Return the type of registers that this ValueType will
543 /// eventually require.
544 MVT getRegisterType(MVT VT) const {
546 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
547 return RegisterTypeForVT[VT.getSimpleVT()];
551 unsigned NumIntermediates;
552 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
555 if (VT.isInteger()) {
556 return getRegisterType(getTypeToTransformTo(VT));
558 assert(0 && "Unsupported extended type!");
559 return MVT(MVT::Other); // Not reached
562 /// getNumRegisters - Return the number of registers that this ValueType will
563 /// eventually require. This is one for any types promoted to live in larger
564 /// registers, but may be more than one for types (like i64) that are split
565 /// into pieces. For types like i140, which are first promoted then expanded,
566 /// it is the number of registers needed to hold all the bits of the original
567 /// type. For an i140 on a 32 bit machine this means 5 registers.
568 unsigned getNumRegisters(MVT VT) const {
570 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
571 return NumRegistersForVT[VT.getSimpleVT()];
575 unsigned NumIntermediates;
576 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
578 if (VT.isInteger()) {
579 unsigned BitWidth = VT.getSizeInBits();
580 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
581 return (BitWidth + RegWidth - 1) / RegWidth;
583 assert(0 && "Unsupported extended type!");
584 return 0; // Not reached
587 /// ShouldShrinkFPConstant - If true, then instruction selection should
588 /// seek to shrink the FP constant of the specified type to a smaller type
589 /// in order to save space and / or reduce runtime.
590 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
592 /// hasTargetDAGCombine - If true, the target has custom DAG combine
593 /// transformations that it can perform for the specified node.
594 bool hasTargetDAGCombine(ISD::NodeType NT) const {
595 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
596 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
599 /// This function returns the maximum number of store operations permitted
600 /// to replace a call to llvm.memset. The value is set by the target at the
601 /// performance threshold for such a replacement.
602 /// @brief Get maximum # of store operations permitted for llvm.memset
603 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
605 /// This function returns the maximum number of store operations permitted
606 /// to replace a call to llvm.memcpy. The value is set by the target at the
607 /// performance threshold for such a replacement.
608 /// @brief Get maximum # of store operations permitted for llvm.memcpy
609 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
611 /// This function returns the maximum number of store operations permitted
612 /// to replace a call to llvm.memmove. The value is set by the target at the
613 /// performance threshold for such a replacement.
614 /// @brief Get maximum # of store operations permitted for llvm.memmove
615 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
617 /// This function returns true if the target allows unaligned memory accesses.
618 /// This is used, for example, in situations where an array copy/move/set is
619 /// converted to a sequence of store operations. It's use helps to ensure that
620 /// such replacements don't generate code that causes an alignment error
621 /// (trap) on the target machine.
622 /// @brief Determine if the target supports unaligned memory accesses.
623 bool allowsUnalignedMemoryAccesses() const {
624 return allowUnalignedMemoryAccesses;
627 /// This function returns true if the target would benefit from code placement
629 /// @brief Determine if the target should perform code placement optimization.
630 bool shouldOptimizeCodePlacement() const {
631 return benefitFromCodePlacementOpt;
634 /// getOptimalMemOpType - Returns the target specific optimal type for load
635 /// and store operations as a result of memset, memcpy, and memmove lowering.
636 /// It returns MVT::iAny if SelectionDAG should be responsible for
638 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
639 bool isSrcConst, bool isSrcStr,
640 SelectionDAG &DAG) const {
644 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
645 /// to implement llvm.setjmp.
646 bool usesUnderscoreSetJmp() const {
647 return UseUnderscoreSetJmp;
650 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
651 /// to implement llvm.longjmp.
652 bool usesUnderscoreLongJmp() const {
653 return UseUnderscoreLongJmp;
656 /// getStackPointerRegisterToSaveRestore - If a physical register, this
657 /// specifies the register that llvm.savestack/llvm.restorestack should save
659 unsigned getStackPointerRegisterToSaveRestore() const {
660 return StackPointerRegisterToSaveRestore;
663 /// getExceptionAddressRegister - If a physical register, this returns
664 /// the register that receives the exception address on entry to a landing
666 unsigned getExceptionAddressRegister() const {
667 return ExceptionPointerRegister;
670 /// getExceptionSelectorRegister - If a physical register, this returns
671 /// the register that receives the exception typeid on entry to a landing
673 unsigned getExceptionSelectorRegister() const {
674 return ExceptionSelectorRegister;
677 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
678 /// set, the default is 200)
679 unsigned getJumpBufSize() const {
683 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
684 /// (if never set, the default is 0)
685 unsigned getJumpBufAlignment() const {
686 return JumpBufAlignment;
689 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
690 /// limit. Any block whose size is greater should not be predicated.
691 unsigned getIfCvtBlockSizeLimit() const {
692 return IfCvtBlockSizeLimit;
695 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
696 /// block to be considered for duplication. Any block whose size is greater
697 /// should not be duplicated to facilitate its predication.
698 unsigned getIfCvtDupBlockSizeLimit() const {
699 return IfCvtDupBlockSizeLimit;
702 /// getPrefLoopAlignment - return the preferred loop alignment.
704 unsigned getPrefLoopAlignment() const {
705 return PrefLoopAlignment;
708 /// getPreIndexedAddressParts - returns true by value, base pointer and
709 /// offset pointer and addressing mode by reference if the node's address
710 /// can be legally represented as pre-indexed load / store address.
711 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
713 ISD::MemIndexedMode &AM,
714 SelectionDAG &DAG) const {
718 /// getPostIndexedAddressParts - returns true by value, base pointer and
719 /// offset pointer and addressing mode by reference if this node can be
720 /// combined with a load / store to form a post-indexed load / store.
721 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
722 SDValue &Base, SDValue &Offset,
723 ISD::MemIndexedMode &AM,
724 SelectionDAG &DAG) const {
728 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
730 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
731 SelectionDAG &DAG) const;
733 /// isOffsetFoldingLegal - Return true if folding a constant offset
734 /// with the given GlobalAddress is legal. It is frequently not legal in
735 /// PIC relocation models.
736 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
738 /// getFunctionAlignment - Return the Log2 alignment of this function.
739 virtual unsigned getFunctionAlignment(const Function *) const = 0;
741 //===--------------------------------------------------------------------===//
742 // TargetLowering Optimization Methods
745 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
746 /// SDValues for returning information from TargetLowering to its clients
747 /// that want to combine
748 struct TargetLoweringOpt {
753 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
755 bool CombineTo(SDValue O, SDValue N) {
761 /// ShrinkDemandedConstant - Check to see if the specified operand of the
762 /// specified instruction is a constant integer. If so, check to see if
763 /// there are any bits set in the constant that are not demanded. If so,
764 /// shrink the constant and return true.
765 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
767 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
768 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
769 /// cast, but it could be generalized for targets with other types of
770 /// implicit widening casts.
771 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
775 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
776 /// DemandedMask bits of the result of Op are ever used downstream. If we can
777 /// use this information to simplify Op, create a new simplified DAG node and
778 /// return true, returning the original and new nodes in Old and New.
779 /// Otherwise, analyze the expression and return a mask of KnownOne and
780 /// KnownZero bits for the expression (used to simplify the caller).
781 /// The KnownZero/One bits may only be accurate for those bits in the
783 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
784 APInt &KnownZero, APInt &KnownOne,
785 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
787 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
788 /// Mask are known to be either zero or one and return them in the
789 /// KnownZero/KnownOne bitsets.
790 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
794 const SelectionDAG &DAG,
795 unsigned Depth = 0) const;
797 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
798 /// targets that want to expose additional information about sign bits to the
800 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
801 unsigned Depth = 0) const;
803 struct DAGCombinerInfo {
804 void *DC; // The DAG Combiner object.
806 bool BeforeLegalizeOps;
807 bool CalledByLegalizer;
811 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
812 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
813 CalledByLegalizer(cl), DAG(dag) {}
815 bool isBeforeLegalize() const { return BeforeLegalize; }
816 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
817 bool isCalledByLegalizer() const { return CalledByLegalizer; }
819 void AddToWorklist(SDNode *N);
820 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
822 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
823 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
825 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
828 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
829 /// and cc. If it is unable to simplify it, return a null SDValue.
830 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
831 ISD::CondCode Cond, bool foldBooleans,
832 DAGCombinerInfo &DCI, DebugLoc dl) const;
834 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
835 /// node is a GlobalAddress + offset.
837 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
839 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
840 /// location that is 'Dist' units away from the location that the 'Base' load
842 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes,
843 int Dist, const MachineFrameInfo *MFI) const;
845 /// PerformDAGCombine - This method will be invoked for all target nodes and
846 /// for any target-independent nodes that the target has registered with
849 /// The semantics are as follows:
851 /// SDValue.Val == 0 - No change was made
852 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
853 /// otherwise - N should be replaced by the returned Operand.
855 /// In addition, methods provided by DAGCombinerInfo may be used to perform
856 /// more complex transformations.
858 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
860 //===--------------------------------------------------------------------===//
861 // TargetLowering Configuration Methods - These methods should be invoked by
862 // the derived class constructor to configure this object for the target.
866 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
867 /// GOT for PC-relative code.
868 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
870 /// setShiftAmountType - Describe the type that should be used for shift
871 /// amounts. This type defaults to the pointer type.
872 void setShiftAmountType(MVT::SimpleValueType VT) { ShiftAmountTy = VT; }
874 /// setBooleanContents - Specify how the target extends the result of a
875 /// boolean value from i1 to a wider type. See getBooleanContents.
876 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
878 /// setSchedulingPreference - Specify the target scheduling preference.
879 void setSchedulingPreference(SchedPreference Pref) {
880 SchedPreferenceInfo = Pref;
883 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
884 /// use _setjmp to implement llvm.setjmp or the non _ version.
885 /// Defaults to false.
886 void setUseUnderscoreSetJmp(bool Val) {
887 UseUnderscoreSetJmp = Val;
890 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
891 /// use _longjmp to implement llvm.longjmp or the non _ version.
892 /// Defaults to false.
893 void setUseUnderscoreLongJmp(bool Val) {
894 UseUnderscoreLongJmp = Val;
897 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
898 /// specifies the register that llvm.savestack/llvm.restorestack should save
900 void setStackPointerRegisterToSaveRestore(unsigned R) {
901 StackPointerRegisterToSaveRestore = R;
904 /// setExceptionPointerRegister - If set to a physical register, this sets
905 /// the register that receives the exception address on entry to a landing
907 void setExceptionPointerRegister(unsigned R) {
908 ExceptionPointerRegister = R;
911 /// setExceptionSelectorRegister - If set to a physical register, this sets
912 /// the register that receives the exception typeid on entry to a landing
914 void setExceptionSelectorRegister(unsigned R) {
915 ExceptionSelectorRegister = R;
918 /// SelectIsExpensive - Tells the code generator not to expand operations
919 /// into sequences that use the select operations if possible.
920 void setSelectIsExpensive() { SelectIsExpensive = true; }
922 /// setIntDivIsCheap - Tells the code generator that integer divide is
923 /// expensive, and if possible, should be replaced by an alternate sequence
924 /// of instructions not containing an integer divide.
925 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
927 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
928 /// srl/add/sra for a signed divide by power of two, and let the target handle
930 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
932 /// addRegisterClass - Add the specified register class as an available
933 /// regclass for the specified value type. This indicates the selector can
934 /// handle values of that class natively.
935 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
936 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
937 AvailableRegClasses.push_back(std::make_pair(VT, RC));
938 RegClassForVT[VT.getSimpleVT()] = RC;
941 /// computeRegisterProperties - Once all of the register classes are added,
942 /// this allows us to compute derived properties we expose.
943 void computeRegisterProperties();
945 /// setOperationAction - Indicate that the specified operation does not work
946 /// with the specified type and indicate what to do about it.
947 void setOperationAction(unsigned Op, MVT::SimpleValueType VT,
948 LegalizeAction Action) {
949 unsigned I = (unsigned)VT;
952 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
953 OpActions[I][Op] |= (uint64_t)Action << (J*2);
956 /// setLoadExtAction - Indicate that the specified load with extension does
957 /// not work with the with specified type and indicate what to do about it.
958 void setLoadExtAction(unsigned ExtType, MVT VT,
959 LegalizeAction Action) {
960 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
961 ExtType < array_lengthof(LoadExtActions) &&
962 "Table isn't big enough!");
963 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
964 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
967 /// setTruncStoreAction - Indicate that the specified truncating store does
968 /// not work with the with specified type and indicate what to do about it.
969 void setTruncStoreAction(MVT ValVT, MVT MemVT,
970 LegalizeAction Action) {
971 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
972 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
973 "Table isn't big enough!");
974 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
975 MemVT.getSimpleVT()*2);
976 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
977 MemVT.getSimpleVT()*2;
980 /// setIndexedLoadAction - Indicate that the specified indexed load does or
981 /// does not work with the with specified type and indicate what to do abort
982 /// it. NOTE: All indexed mode loads are initialized to Expand in
983 /// TargetLowering.cpp
984 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
985 LegalizeAction Action) {
986 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
987 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
988 "Table isn't big enough!");
989 IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode] = (uint8_t)Action;
992 /// setIndexedStoreAction - Indicate that the specified indexed store does or
993 /// does not work with the with specified type and indicate what to do about
994 /// it. NOTE: All indexed mode stores are initialized to Expand in
995 /// TargetLowering.cpp
996 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
997 LegalizeAction Action) {
998 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
999 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1000 "Table isn't big enough!");
1001 IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode] = (uint8_t)Action;
1004 /// setConvertAction - Indicate that the specified conversion does or does
1005 /// not work with the with specified type and indicate what to do about it.
1006 void setConvertAction(MVT FromVT, MVT ToVT,
1007 LegalizeAction Action) {
1008 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
1009 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
1010 "Table isn't big enough!");
1011 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
1012 ToVT.getSimpleVT()*2);
1013 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
1014 ToVT.getSimpleVT()*2;
1017 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1018 /// supported on the target and indicate what to do about it.
1019 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
1020 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
1021 (unsigned)CC < array_lengthof(CondCodeActions) &&
1022 "Table isn't big enough!");
1023 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
1024 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
1027 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1028 /// promotion code defaults to trying a larger integer/fp until it can find
1029 /// one that works. If that default is insufficient, this method can be used
1030 /// by the target to override the default.
1031 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1032 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
1033 DestVT.getSimpleVT();
1036 /// addLegalFPImmediate - Indicate that this target can instruction select
1037 /// the specified FP immediate natively.
1038 void addLegalFPImmediate(const APFloat& Imm) {
1039 LegalFPImmediates.push_back(Imm);
1042 /// setTargetDAGCombine - Targets should invoke this method for each target
1043 /// independent node that they want to provide a custom DAG combiner for by
1044 /// implementing the PerformDAGCombine virtual method.
1045 void setTargetDAGCombine(ISD::NodeType NT) {
1046 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1047 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1050 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1051 /// bytes); default is 200
1052 void setJumpBufSize(unsigned Size) {
1056 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1057 /// alignment (in bytes); default is 0
1058 void setJumpBufAlignment(unsigned Align) {
1059 JumpBufAlignment = Align;
1062 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1063 /// limit (in number of instructions); default is 2.
1064 void setIfCvtBlockSizeLimit(unsigned Limit) {
1065 IfCvtBlockSizeLimit = Limit;
1068 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1069 /// of instructions) to be considered for code duplication during
1070 /// if-conversion; default is 2.
1071 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1072 IfCvtDupBlockSizeLimit = Limit;
1075 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1076 /// alignment is zero, it means the target does not care about loop alignment.
1077 void setPrefLoopAlignment(unsigned Align) {
1078 PrefLoopAlignment = Align;
1083 virtual const TargetSubtarget *getSubtarget() {
1084 assert(0 && "Not Implemented");
1085 return NULL; // this is here to silence compiler errors
1088 //===--------------------------------------------------------------------===//
1089 // Lowering methods - These methods must be implemented by targets so that
1090 // the SelectionDAGLowering code knows how to lower these.
1093 /// LowerFormalArguments - This hook must be implemented to lower the
1094 /// incoming (formal) arguments, described by the Ins array, into the
1095 /// specified DAG. The implementation should fill in the InVals array
1096 /// with legal-type argument values, and return the resulting token
1100 LowerFormalArguments(SDValue Chain,
1101 unsigned CallConv, bool isVarArg,
1102 const SmallVectorImpl<ISD::InputArg> &Ins,
1103 DebugLoc dl, SelectionDAG &DAG,
1104 SmallVectorImpl<SDValue> &InVals) {
1105 assert(0 && "Not Implemented");
1106 return SDValue(); // this is here to silence compiler errors
1109 /// LowerCallTo - This function lowers an abstract call to a function into an
1110 /// actual call. This returns a pair of operands. The first element is the
1111 /// return value for the function (if RetTy is not VoidTy). The second
1112 /// element is the outgoing token chain. It calls LowerCall to do the actual
1114 struct ArgListEntry {
1125 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1126 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1128 typedef std::vector<ArgListEntry> ArgListTy;
1129 std::pair<SDValue, SDValue>
1130 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1131 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1132 unsigned CallConv, bool isTailCall, bool isReturnValueUsed,
1133 SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
1135 /// LowerCall - This hook must be implemented to lower calls into the
1136 /// the specified DAG. The outgoing arguments to the call are described
1137 /// by the Outs array, and the values to be returned by the call are
1138 /// described by the Ins array. The implementation should fill in the
1139 /// InVals array with legal-type return values from the call, and return
1140 /// the resulting token chain value.
1142 /// The isTailCall flag here is normative. If it is true, the
1143 /// implementation must emit a tail call. The
1144 /// IsEligibleForTailCallOptimization hook should be used to catch
1145 /// cases that cannot be handled.
1148 LowerCall(SDValue Chain, SDValue Callee,
1149 unsigned CallConv, bool isVarArg, bool isTailCall,
1150 const SmallVectorImpl<ISD::OutputArg> &Outs,
1151 const SmallVectorImpl<ISD::InputArg> &Ins,
1152 DebugLoc dl, SelectionDAG &DAG,
1153 SmallVectorImpl<SDValue> &InVals) {
1154 assert(0 && "Not Implemented");
1155 return SDValue(); // this is here to silence compiler errors
1158 /// LowerReturn - This hook must be implemented to lower outgoing
1159 /// return values, described by the Outs array, into the specified
1160 /// DAG. The implementation should return the resulting token chain
1164 LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg,
1165 const SmallVectorImpl<ISD::OutputArg> &Outs,
1166 DebugLoc dl, SelectionDAG &DAG) {
1167 assert(0 && "Not Implemented");
1168 return SDValue(); // this is here to silence compiler errors
1171 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1172 /// memcpy. This can be used by targets to provide code sequences for cases
1173 /// that don't fit the target's parameters for simple loads/stores and can be
1174 /// more efficient than using a library call. This function can return a null
1175 /// SDValue if the target declines to use custom code and a different
1176 /// lowering strategy should be used.
1178 /// If AlwaysInline is true, the size is constant and the target should not
1179 /// emit any calls and is strongly encouraged to attempt to emit inline code
1180 /// even if it is beyond the usual threshold because this intrinsic is being
1181 /// expanded in a place where calls are not feasible (e.g. within the prologue
1182 /// for another call). If the target chooses to decline an AlwaysInline
1183 /// request here, legalize will resort to using simple loads and stores.
1185 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1187 SDValue Op1, SDValue Op2,
1188 SDValue Op3, unsigned Align,
1190 const Value *DstSV, uint64_t DstOff,
1191 const Value *SrcSV, uint64_t SrcOff) {
1195 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1196 /// memmove. This can be used by targets to provide code sequences for cases
1197 /// that don't fit the target's parameters for simple loads/stores and can be
1198 /// more efficient than using a library call. This function can return a null
1199 /// SDValue if the target declines to use custom code and a different
1200 /// lowering strategy should be used.
1202 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1204 SDValue Op1, SDValue Op2,
1205 SDValue Op3, unsigned Align,
1206 const Value *DstSV, uint64_t DstOff,
1207 const Value *SrcSV, uint64_t SrcOff) {
1211 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1212 /// memset. This can be used by targets to provide code sequences for cases
1213 /// that don't fit the target's parameters for simple stores and can be more
1214 /// efficient than using a library call. This function can return a null
1215 /// SDValue if the target declines to use custom code and a different
1216 /// lowering strategy should be used.
1218 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1220 SDValue Op1, SDValue Op2,
1221 SDValue Op3, unsigned Align,
1222 const Value *DstSV, uint64_t DstOff) {
1226 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1227 /// to legalize nodes with an illegal operand type but legal result types.
1228 /// It replaces the LowerOperation callback in the type Legalizer.
1229 /// The reason we can not do away with LowerOperation entirely is that
1230 /// LegalizeDAG isn't yet ready to use this callback.
1231 /// TODO: Consider merging with ReplaceNodeResults.
1233 /// The target places new result values for the node in Results (their number
1234 /// and types must exactly match those of the original return values of
1235 /// the node), or leaves Results empty, which indicates that the node is not
1236 /// to be custom lowered after all.
1237 /// The default implementation calls LowerOperation.
1238 virtual void LowerOperationWrapper(SDNode *N,
1239 SmallVectorImpl<SDValue> &Results,
1242 /// LowerOperation - This callback is invoked for operations that are
1243 /// unsupported by the target, which are registered to use 'custom' lowering,
1244 /// and whose defined values are all legal.
1245 /// If the target has no operations that require custom lowering, it need not
1246 /// implement this. The default implementation of this aborts.
1247 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1249 /// ReplaceNodeResults - This callback is invoked when a node result type is
1250 /// illegal for the target, and the operation was registered to use 'custom'
1251 /// lowering for that result type. The target places new result values for
1252 /// the node in Results (their number and types must exactly match those of
1253 /// the original return values of the node), or leaves Results empty, which
1254 /// indicates that the node is not to be custom lowered after all.
1256 /// If the target has no operations that require custom lowering, it need not
1257 /// implement this. The default implementation aborts.
1258 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1259 SelectionDAG &DAG) {
1260 assert(0 && "ReplaceNodeResults not implemented for this target!");
1263 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1264 /// tail call optimization. Targets which want to do tail call optimization
1265 /// should override this function.
1267 IsEligibleForTailCallOptimization(SDValue Callee,
1270 const SmallVectorImpl<ISD::InputArg> &Ins,
1271 SelectionDAG& DAG) const {
1272 // Conservative default: no calls are eligible.
1276 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1277 /// it exists. Skip a possible ISD::TokenFactor.
1278 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1279 unsigned TailCallNodeOpCode) {
1280 if (Chain.getOpcode() == TailCallNodeOpCode) {
1282 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1283 if (Chain.getNumOperands() &&
1284 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1285 return Chain.getOperand(0);
1290 /// getTargetNodeName() - This method returns the name of a target specific
1292 virtual const char *getTargetNodeName(unsigned Opcode) const;
1294 /// createFastISel - This method returns a target specific FastISel object,
1295 /// or null if the target does not support "fast" ISel.
1297 createFastISel(MachineFunction &,
1298 MachineModuleInfo *, DwarfWriter *,
1299 DenseMap<const Value *, unsigned> &,
1300 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1301 DenseMap<const AllocaInst *, int> &
1303 , SmallSet<Instruction*, 8> &CatchInfoLost
1309 //===--------------------------------------------------------------------===//
1310 // Inline Asm Support hooks
1313 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1314 /// call to be explicit llvm code if it wants to. This is useful for
1315 /// turning simple inline asms into LLVM intrinsics, which gives the
1316 /// compiler more information about the behavior of the code.
1317 virtual bool ExpandInlineAsm(CallInst *CI) const {
1321 enum ConstraintType {
1322 C_Register, // Constraint represents specific register(s).
1323 C_RegisterClass, // Constraint represents any of register(s) in class.
1324 C_Memory, // Memory constraint.
1325 C_Other, // Something else.
1326 C_Unknown // Unsupported constraint.
1329 /// AsmOperandInfo - This contains information for each constraint that we are
1331 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1332 /// ConstraintCode - This contains the actual string for the code, like "m".
1333 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1334 /// most closely matches the operand.
1335 std::string ConstraintCode;
1337 /// ConstraintType - Information about the constraint code, e.g. Register,
1338 /// RegisterClass, Memory, Other, Unknown.
1339 TargetLowering::ConstraintType ConstraintType;
1341 /// CallOperandval - If this is the result output operand or a
1342 /// clobber, this is null, otherwise it is the incoming operand to the
1343 /// CallInst. This gets modified as the asm is processed.
1344 Value *CallOperandVal;
1346 /// ConstraintVT - The ValueType for the operand value.
1349 /// isMatchingInputConstraint - Return true of this is an input operand that
1350 /// is a matching constraint like "4".
1351 bool isMatchingInputConstraint() const;
1353 /// getMatchedOperand - If this is an input matching constraint, this method
1354 /// returns the output operand it matches.
1355 unsigned getMatchedOperand() const;
1357 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1358 : InlineAsm::ConstraintInfo(info),
1359 ConstraintType(TargetLowering::C_Unknown),
1360 CallOperandVal(0), ConstraintVT(MVT::Other) {
1364 /// ComputeConstraintToUse - Determines the constraint code and constraint
1365 /// type to use for the specific AsmOperandInfo, setting
1366 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1367 /// being passed in is available, it can be passed in as Op, otherwise an
1368 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1369 /// constraint of the inline asm instruction being processed is 'm'.
1370 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1373 SelectionDAG *DAG = 0) const;
1375 /// getConstraintType - Given a constraint, return the type of constraint it
1376 /// is for this target.
1377 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1379 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1380 /// return a list of registers that can be used to satisfy the constraint.
1381 /// This should only be used for C_RegisterClass constraints.
1382 virtual std::vector<unsigned>
1383 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1386 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1387 /// {edx}), return the register number and the register class for the
1390 /// Given a register class constraint, like 'r', if this corresponds directly
1391 /// to an LLVM register class, return a register of 0 and the register class
1394 /// This should only be used for C_Register constraints. On error,
1395 /// this returns a register number of 0 and a null register class pointer..
1396 virtual std::pair<unsigned, const TargetRegisterClass*>
1397 getRegForInlineAsmConstraint(const std::string &Constraint,
1400 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1401 /// with another that has more specific requirements based on the type of the
1402 /// corresponding operand. This returns null if there is no replacement to
1404 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1406 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1407 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1408 /// it means one of the asm constraint of the inline asm instruction being
1409 /// processed is 'm'.
1410 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1412 std::vector<SDValue> &Ops,
1413 SelectionDAG &DAG) const;
1415 //===--------------------------------------------------------------------===//
1419 // EmitInstrWithCustomInserter - This method should be implemented by targets
1420 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1421 // instructions are special in various ways, which require special support to
1422 // insert. The specified MachineInstr is created but not inserted into any
1423 // basic blocks, and the scheduler passes ownership of it to this method.
1424 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1425 MachineBasicBlock *MBB) const;
1427 //===--------------------------------------------------------------------===//
1428 // Addressing mode description hooks (used by LSR etc).
1431 /// AddrMode - This represents an addressing mode of:
1432 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1433 /// If BaseGV is null, there is no BaseGV.
1434 /// If BaseOffs is zero, there is no base offset.
1435 /// If HasBaseReg is false, there is no base register.
1436 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1440 GlobalValue *BaseGV;
1444 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1447 /// isLegalAddressingMode - Return true if the addressing mode represented by
1448 /// AM is legal for this target, for a load/store of the specified type.
1449 /// The type may be VoidTy, in which case only return true if the addressing
1450 /// mode is legal for a load/store of any legal type.
1451 /// TODO: Handle pre/postinc as well.
1452 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1454 /// isTruncateFree - Return true if it's free to truncate a value of
1455 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1456 /// register EAX to i16 by referencing its sub-register AX.
1457 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1461 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1465 /// isZExtFree - Return true if any actual instruction that defines a
1466 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1467 /// register. This does not necessarily include registers defined in
1468 /// unknown ways, such as incoming arguments, or copies from unknown
1469 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1470 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1471 /// all instructions that define 32-bit values implicit zero-extend the
1472 /// result out to 64 bits.
1473 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1477 virtual bool isZExtFree(MVT VT1, MVT VT2) const {
1481 /// isNarrowingProfitable - Return true if it's profitable to narrow
1482 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1483 /// from i32 to i8 but not from i32 to i16.
1484 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const {
1488 //===--------------------------------------------------------------------===//
1489 // Div utility functions
1491 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1492 std::vector<SDNode*>* Created) const;
1493 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1494 std::vector<SDNode*>* Created) const;
1497 //===--------------------------------------------------------------------===//
1498 // Runtime Library hooks
1501 /// setLibcallName - Rename the default libcall routine name for the specified
1503 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1504 LibcallRoutineNames[Call] = Name;
1507 /// getLibcallName - Get the libcall routine name for the specified libcall.
1509 const char *getLibcallName(RTLIB::Libcall Call) const {
1510 return LibcallRoutineNames[Call];
1513 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1514 /// result of the comparison libcall against zero.
1515 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1516 CmpLibcallCCs[Call] = CC;
1519 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1520 /// the comparison libcall against zero.
1521 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1522 return CmpLibcallCCs[Call];
1527 const TargetData *TD;
1528 TargetLoweringObjectFile &TLOF;
1530 /// PointerTy - The type to use for pointers, usually i32 or i64.
1532 MVT::SimpleValueType PointerTy;
1534 /// IsLittleEndian - True if this is a little endian target.
1536 bool IsLittleEndian;
1538 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1540 bool UsesGlobalOffsetTable;
1542 /// SelectIsExpensive - Tells the code generator not to expand operations
1543 /// into sequences that use the select operations if possible.
1544 bool SelectIsExpensive;
1546 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1547 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1548 /// a real cost model is in place. If we ever optimize for size, this will be
1549 /// set to true unconditionally.
1552 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1553 /// srl/add/sra for a signed divide by power of two, and let the target handle
1555 bool Pow2DivIsCheap;
1557 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1558 /// llvm.setjmp. Defaults to false.
1559 bool UseUnderscoreSetJmp;
1561 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1562 /// llvm.longjmp. Defaults to false.
1563 bool UseUnderscoreLongJmp;
1565 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1567 MVT::SimpleValueType ShiftAmountTy;
1569 /// BooleanContents - Information about the contents of the high-bits in
1570 /// boolean values held in a type wider than i1. See getBooleanContents.
1571 BooleanContent BooleanContents;
1573 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1574 /// total cycles or lowest register usage.
1575 SchedPreference SchedPreferenceInfo;
1577 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1578 unsigned JumpBufSize;
1580 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1582 unsigned JumpBufAlignment;
1584 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1586 unsigned IfCvtBlockSizeLimit;
1588 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1589 /// duplicated during if-conversion.
1590 unsigned IfCvtDupBlockSizeLimit;
1592 /// PrefLoopAlignment - The perferred loop alignment.
1594 unsigned PrefLoopAlignment;
1596 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1597 /// specifies the register that llvm.savestack/llvm.restorestack should save
1599 unsigned StackPointerRegisterToSaveRestore;
1601 /// ExceptionPointerRegister - If set to a physical register, this specifies
1602 /// the register that receives the exception address on entry to a landing
1604 unsigned ExceptionPointerRegister;
1606 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1607 /// the register that receives the exception typeid on entry to a landing
1609 unsigned ExceptionSelectorRegister;
1611 /// RegClassForVT - This indicates the default register class to use for
1612 /// each ValueType the target supports natively.
1613 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1614 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1615 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1617 /// TransformToType - For any value types we are promoting or expanding, this
1618 /// contains the value type that we are changing to. For Expanded types, this
1619 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1620 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1621 /// by the system, this holds the same type (e.g. i32 -> i32).
1622 MVT TransformToType[MVT::LAST_VALUETYPE];
1624 /// OpActions - For each operation and each value type, keep a LegalizeAction
1625 /// that indicates how instruction selection should deal with the operation.
1626 /// Most operations are Legal (aka, supported natively by the target), but
1627 /// operations that are not should be described. Note that operations on
1628 /// non-legal value types are not described here.
1629 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1630 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1631 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1633 /// LoadExtActions - For each load of load extension type and each value type,
1634 /// keep a LegalizeAction that indicates how instruction selection should deal
1636 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1638 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1639 /// indicates how instruction selection should deal with the store.
1640 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1642 /// IndexedModeActions - For each indexed mode and each value type,
1643 /// keep a pair of LegalizeAction that indicates how instruction
1644 /// selection should deal with the load / store. The first
1645 /// dimension is now the value_type for the reference. The second
1646 /// dimension is the load [0] vs. store[1]. The third dimension
1647 /// represents the various modes for load store.
1648 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1650 /// ConvertActions - For each conversion from source type to destination type,
1651 /// keep a LegalizeAction that indicates how instruction selection should
1652 /// deal with the conversion.
1653 /// Currently, this is used only for floating->floating conversions
1654 /// (FP_EXTEND and FP_ROUND).
1655 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1657 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1658 /// LegalizeAction that indicates how instruction selection should
1659 /// deal with the condition code.
1660 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1662 ValueTypeActionImpl ValueTypeActions;
1664 std::vector<APFloat> LegalFPImmediates;
1666 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1668 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1669 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1670 /// which sets a bit in this array.
1672 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1674 /// PromoteToType - For operations that must be promoted to a specific type,
1675 /// this holds the destination type. This map should be sparse, so don't hold
1678 /// Targets add entries to this map with AddPromotedToType(..), clients access
1679 /// this with getTypeToPromoteTo(..).
1680 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1683 /// LibcallRoutineNames - Stores the name each libcall.
1685 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1687 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1688 /// of each of the comparison libcall against zero.
1689 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1692 /// When lowering \@llvm.memset this field specifies the maximum number of
1693 /// store operations that may be substituted for the call to memset. Targets
1694 /// must set this value based on the cost threshold for that target. Targets
1695 /// should assume that the memset will be done using as many of the largest
1696 /// store operations first, followed by smaller ones, if necessary, per
1697 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1698 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1699 /// store. This only applies to setting a constant array of a constant size.
1700 /// @brief Specify maximum number of store instructions per memset call.
1701 unsigned maxStoresPerMemset;
1703 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1704 /// store operations that may be substituted for a call to memcpy. Targets
1705 /// must set this value based on the cost threshold for that target. Targets
1706 /// should assume that the memcpy will be done using as many of the largest
1707 /// store operations first, followed by smaller ones, if necessary, per
1708 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1709 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1710 /// and one 1-byte store. This only applies to copying a constant array of
1712 /// @brief Specify maximum bytes of store instructions per memcpy call.
1713 unsigned maxStoresPerMemcpy;
1715 /// When lowering \@llvm.memmove this field specifies the maximum number of
1716 /// store instructions that may be substituted for a call to memmove. Targets
1717 /// must set this value based on the cost threshold for that target. Targets
1718 /// should assume that the memmove will be done using as many of the largest
1719 /// store operations first, followed by smaller ones, if necessary, per
1720 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1721 /// with 8-bit alignment would result in nine 1-byte stores. This only
1722 /// applies to copying a constant array of constant size.
1723 /// @brief Specify maximum bytes of store instructions per memmove call.
1724 unsigned maxStoresPerMemmove;
1726 /// This field specifies whether the target machine permits unaligned memory
1727 /// accesses. This is used, for example, to determine the size of store
1728 /// operations when copying small arrays and other similar tasks.
1729 /// @brief Indicate whether the target permits unaligned memory accesses.
1730 bool allowUnalignedMemoryAccesses;
1732 /// This field specifies whether the target can benefit from code placement
1734 bool benefitFromCodePlacementOpt;
1736 } // end llvm namespace