1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/IRBuilder.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
46 class FunctionLoweringInfo;
47 class ImmutableCallSite;
49 class MachineBasicBlock;
50 class MachineFunction;
52 class MachineJumpTableInfo;
57 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLibraryInfo;
61 class TargetLoweringObjectFile;
66 None, // No preference
67 Source, // Follow source order.
68 RegPressure, // Scheduling for lowest register pressure.
69 Hybrid, // Scheduling for both latency and register pressure.
70 ILP, // Scheduling for ILP in low register pressure mode.
71 VLIW // Scheduling for VLIW targets.
75 /// This base class for TargetLowering contains the SelectionDAG-independent
76 /// parts that can be used from the rest of CodeGen.
77 class TargetLoweringBase {
78 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
79 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
82 /// This enum indicates whether operations are valid for a target, and if not,
83 /// what action should be used to make them valid.
85 Legal, // The target natively supports this operation.
86 Promote, // This operation should be executed in a larger type.
87 Expand, // Try to expand this to other ops, otherwise use a libcall.
88 Custom // Use the LowerOperation hook to implement custom lowering.
91 /// This enum indicates whether a types are legal for a target, and if not,
92 /// what action should be used to make them valid.
93 enum LegalizeTypeAction {
94 TypeLegal, // The target natively supports this type.
95 TypePromoteInteger, // Replace this integer with a larger one.
96 TypeExpandInteger, // Split this integer into two of half the size.
97 TypeSoftenFloat, // Convert this float to a same size integer type.
98 TypeExpandFloat, // Split this float into two of half the size.
99 TypeScalarizeVector, // Replace this one-element vector with its element.
100 TypeSplitVector, // Split this vector into two of half the size.
101 TypeWidenVector // This vector should be widened into a larger vector.
104 /// LegalizeKind holds the legalization kind that needs to happen to EVT
105 /// in order to type-legalize it.
106 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
108 /// Enum that describes how the target represents true/false values.
109 enum BooleanContent {
110 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
111 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
112 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
115 /// Enum that describes what type of support for selects the target has.
116 enum SelectSupportKind {
117 ScalarValSelect, // The target supports scalar selects (ex: cmov).
118 ScalarCondVectorVal, // The target supports selects with a scalar condition
119 // and vector values (ex: cmov).
120 VectorMaskSelect // The target supports vector selects with a vector
121 // mask (ex: x86 blends).
124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
126 case UndefinedBooleanContent:
127 // Extend by adding rubbish bits.
128 return ISD::ANY_EXTEND;
129 case ZeroOrOneBooleanContent:
130 // Extend by adding zero bits.
131 return ISD::ZERO_EXTEND;
132 case ZeroOrNegativeOneBooleanContent:
133 // Extend by copying the sign bit.
134 return ISD::SIGN_EXTEND;
136 llvm_unreachable("Invalid content kind");
139 /// NOTE: The constructor takes ownership of TLOF.
140 explicit TargetLoweringBase(const TargetMachine &TM,
141 const TargetLoweringObjectFile *TLOF);
142 virtual ~TargetLoweringBase();
145 /// \brief Initialize all of the actions to default values.
149 const TargetMachine &getTargetMachine() const { return TM; }
150 const DataLayout *getDataLayout() const { return DL; }
151 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
153 bool isBigEndian() const { return !IsLittleEndian; }
154 bool isLittleEndian() const { return IsLittleEndian; }
156 /// Return the pointer type for the given address space, defaults to
157 /// the pointer type from the data layout.
158 /// FIXME: The default needs to be removed once all the code is updated.
159 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
160 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
161 unsigned getPointerTypeSizeInBits(Type *Ty) const;
162 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
164 EVT getShiftAmountTy(EVT LHSTy) const;
166 /// Returns the type to be used for the index operand of:
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
169 virtual MVT getVectorIdxTy() const {
170 return getPointerTy();
173 /// Return true if the select operation is expensive for this target.
174 bool isSelectExpensive() const { return SelectIsExpensive; }
176 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
180 /// Return true if multiple condition registers are available.
181 bool hasMultipleConditionRegisters() const {
182 return HasMultipleConditionRegisters;
185 /// Return true if the target has BitExtract instructions.
186 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
188 /// Return the preferred vector type legalization action.
189 virtual TargetLoweringBase::LegalizeTypeAction
190 getPreferredVectorAction(EVT VT) const {
191 // The default action for one element vectors is to scalarize
192 if (VT.getVectorNumElements() == 1)
193 return TypeScalarizeVector;
194 // The default action for other vectors is to promote
195 return TypePromoteInteger;
198 // There are two general methods for expanding a BUILD_VECTOR node:
199 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
201 // 2. Build the vector on the stack and then load it.
202 // If this function returns true, then method (1) will be used, subject to
203 // the constraint that all of the necessary shuffles are legal (as determined
204 // by isShuffleMaskLegal). If this function returns false, then method (2) is
205 // always used. The vector type, and the number of defined values, are
208 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
209 unsigned DefinedValues) const {
210 return DefinedValues < 3;
213 /// Return true if integer divide is usually cheaper than a sequence of
214 /// several shifts, adds, and multiplies for this target.
215 bool isIntDivCheap() const { return IntDivIsCheap; }
217 /// Returns true if target has indicated at least one type should be bypassed.
218 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
220 /// Returns map of slow types for division or remainder with corresponding
222 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
223 return BypassSlowDivWidths;
226 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
227 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
229 /// Return true if Flow Control is an expensive operation that should be
231 bool isJumpExpensive() const { return JumpIsExpensive; }
233 /// Return true if selects are only cheaper than branches if the branch is
234 /// unlikely to be predicted right.
235 bool isPredictableSelectExpensive() const {
236 return PredictableSelectIsExpensive;
239 /// isLoadBitCastBeneficial() - Return true if the following transform
241 /// fold (conv (load x)) -> (load (conv*)x)
242 /// On architectures that don't natively support some vector loads efficiently,
243 /// casting the load to a smaller vector of larger types and loading
244 /// is more efficient, however, this can be undone by optimizations in
246 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
250 /// \brief Return if the target supports combining a
253 /// %andResult = and %val1, #imm-with-one-bit-set;
254 /// %icmpResult = icmp %andResult, 0
255 /// br i1 %icmpResult, label %dest1, label %dest2
257 /// into a single machine instruction of a form like:
259 /// brOnBitSet %register, #bitNumber, dest
261 bool isMaskAndBranchFoldingLegal() const {
262 return MaskAndBranchFoldingIsLegal;
265 /// Return the ValueType of the result of SETCC operations. Also used to
266 /// obtain the target's preferred type for the condition operand of SELECT and
267 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
268 /// since there are no other operands to get a type hint from.
269 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
271 /// Return the ValueType for comparison libcalls. Comparions libcalls include
272 /// floating point comparion calls, and Ordered/Unordered check calls on
273 /// floating point numbers.
275 MVT::SimpleValueType getCmpLibcallReturnType() const;
277 /// For targets without i1 registers, this gives the nature of the high-bits
278 /// of boolean values held in types wider than i1.
280 /// "Boolean values" are special true/false values produced by nodes like
281 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
282 /// Not to be confused with general values promoted from i1. Some cpus
283 /// distinguish between vectors of boolean and scalars; the isVec parameter
284 /// selects between the two kinds. For example on X86 a scalar boolean should
285 /// be zero extended from i1, while the elements of a vector of booleans
286 /// should be sign extended from i1.
287 BooleanContent getBooleanContents(bool isVec) const {
288 return isVec ? BooleanVectorContents : BooleanContents;
291 /// Return target scheduling preference.
292 Sched::Preference getSchedulingPreference() const {
293 return SchedPreferenceInfo;
296 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
297 /// for different nodes. This function returns the preference (or none) for
299 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
303 /// Return the register class that should be used for the specified value
305 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
306 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
307 assert(RC && "This value type is not natively supported!");
311 /// Return the 'representative' register class for the specified value
314 /// The 'representative' register class is the largest legal super-reg
315 /// register class for the register class of the value type. For example, on
316 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
317 /// register class is GR64 on x86_64.
318 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
319 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
323 /// Return the cost of the 'representative' register class for the specified
325 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
326 return RepRegClassCostForVT[VT.SimpleTy];
329 /// Return true if the target has native support for the specified value type.
330 /// This means that it has a register that directly holds it without
331 /// promotions or expansions.
332 bool isTypeLegal(EVT VT) const {
333 assert(!VT.isSimple() ||
334 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
335 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
338 class ValueTypeActionImpl {
339 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
340 /// that indicates how instruction selection should deal with the type.
341 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
344 ValueTypeActionImpl() {
345 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
348 LegalizeTypeAction getTypeAction(MVT VT) const {
349 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
352 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
353 unsigned I = VT.SimpleTy;
354 ValueTypeActions[I] = Action;
358 const ValueTypeActionImpl &getValueTypeActions() const {
359 return ValueTypeActions;
362 /// Return how we should legalize values of this type, either it is already
363 /// legal (return 'Legal') or we need to promote it to a larger type (return
364 /// 'Promote'), or we need to expand it into multiple registers of smaller
365 /// integer type (return 'Expand'). 'Custom' is not an option.
366 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
367 return getTypeConversion(Context, VT).first;
369 LegalizeTypeAction getTypeAction(MVT VT) const {
370 return ValueTypeActions.getTypeAction(VT);
373 /// For types supported by the target, this is an identity function. For
374 /// types that must be promoted to larger types, this returns the larger type
375 /// to promote to. For integer types that are larger than the largest integer
376 /// register, this contains one step in the expansion to get to the smaller
377 /// register. For illegal floating point types, this returns the integer type
379 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
380 return getTypeConversion(Context, VT).second;
383 /// For types supported by the target, this is an identity function. For
384 /// types that must be expanded (i.e. integer types that are larger than the
385 /// largest integer register or illegal floating point types), this returns
386 /// the largest legal type it will be expanded to.
387 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
388 assert(!VT.isVector());
390 switch (getTypeAction(Context, VT)) {
393 case TypeExpandInteger:
394 VT = getTypeToTransformTo(Context, VT);
397 llvm_unreachable("Type is not legal nor is it to be expanded!");
402 /// Vector types are broken down into some number of legal first class types.
403 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
404 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
405 /// turns into 4 EVT::i32 values with both PPC and X86.
407 /// This method returns the number of registers needed, and the VT for each
408 /// register. It also returns the VT and quantity of the intermediate values
409 /// before they are promoted/expanded.
410 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
412 unsigned &NumIntermediates,
413 MVT &RegisterVT) const;
415 struct IntrinsicInfo {
416 unsigned opc; // target opcode
417 EVT memVT; // memory VT
418 const Value* ptrVal; // value representing memory location
419 int offset; // offset off of ptrVal
420 unsigned align; // alignment
421 bool vol; // is volatile?
422 bool readMem; // reads memory?
423 bool writeMem; // writes memory?
426 /// Given an intrinsic, checks if on the target the intrinsic will need to map
427 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
428 /// true and store the intrinsic information into the IntrinsicInfo that was
429 /// passed to the function.
430 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
431 unsigned /*Intrinsic*/) const {
435 /// Returns true if the target can instruction select the specified FP
436 /// immediate natively. If false, the legalizer will materialize the FP
437 /// immediate as a load from a constant pool.
438 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
442 /// Targets can use this to indicate that they only support *some*
443 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
444 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
446 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
451 /// Returns true if the operation can trap for the value type.
453 /// VT must be a legal type. By default, we optimistically assume most
454 /// operations don't trap except for divide and remainder.
455 virtual bool canOpTrap(unsigned Op, EVT VT) const;
457 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
458 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
459 /// a VAND with a constant pool entry.
460 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
465 /// Return how this operation should be treated: either it is legal, needs to
466 /// be promoted to a larger size, needs to be expanded to some other code
467 /// sequence, or the target has a custom expander for it.
468 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
469 if (VT.isExtended()) return Expand;
470 // If a target-specific SDNode requires legalization, require the target
471 // to provide custom legalization for it.
472 if (Op > array_lengthof(OpActions[0])) return Custom;
473 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
474 return (LegalizeAction)OpActions[I][Op];
477 /// Return true if the specified operation is legal on this target or can be
478 /// made legal with custom lowering. This is used to help guide high-level
479 /// lowering decisions.
480 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
481 return (VT == MVT::Other || isTypeLegal(VT)) &&
482 (getOperationAction(Op, VT) == Legal ||
483 getOperationAction(Op, VT) == Custom);
486 /// Return true if the specified operation is legal on this target or can be
487 /// made legal using promotion. This is used to help guide high-level lowering
489 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
490 return (VT == MVT::Other || isTypeLegal(VT)) &&
491 (getOperationAction(Op, VT) == Legal ||
492 getOperationAction(Op, VT) == Promote);
495 /// Return true if the specified operation is illegal on this target or
496 /// unlikely to be made legal with custom lowering. This is used to help guide
497 /// high-level lowering decisions.
498 bool isOperationExpand(unsigned Op, EVT VT) const {
499 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
502 /// Return true if the specified operation is legal on this target.
503 bool isOperationLegal(unsigned Op, EVT VT) const {
504 return (VT == MVT::Other || isTypeLegal(VT)) &&
505 getOperationAction(Op, VT) == Legal;
508 /// Return how this load with extension should be treated: either it is legal,
509 /// needs to be promoted to a larger size, needs to be expanded to some other
510 /// code sequence, or the target has a custom expander for it.
511 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
512 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
513 "Table isn't big enough!");
514 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
517 /// Return true if the specified load with extension is legal on this target.
518 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
519 return VT.isSimple() &&
520 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
523 /// Return how this store with truncation should be treated: either it is
524 /// legal, needs to be promoted to a larger size, needs to be expanded to some
525 /// other code sequence, or the target has a custom expander for it.
526 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
527 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
528 "Table isn't big enough!");
529 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
533 /// Return true if the specified store with truncation is legal on this
535 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
536 return isTypeLegal(ValVT) && MemVT.isSimple() &&
537 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
540 /// Return how the indexed load should be treated: either it is legal, needs
541 /// to be promoted to a larger size, needs to be expanded to some other code
542 /// sequence, or the target has a custom expander for it.
544 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
545 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
546 "Table isn't big enough!");
547 unsigned Ty = (unsigned)VT.SimpleTy;
548 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
551 /// Return true if the specified indexed load is legal on this target.
552 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
553 return VT.isSimple() &&
554 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
555 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
558 /// Return how the indexed store should be treated: either it is legal, needs
559 /// to be promoted to a larger size, needs to be expanded to some other code
560 /// sequence, or the target has a custom expander for it.
562 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
563 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
564 "Table isn't big enough!");
565 unsigned Ty = (unsigned)VT.SimpleTy;
566 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
569 /// Return true if the specified indexed load is legal on this target.
570 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
571 return VT.isSimple() &&
572 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
573 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
576 /// Return how the condition code should be treated: either it is legal, needs
577 /// to be expanded to some other code sequence, or the target has a custom
580 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
581 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
582 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
583 "Table isn't big enough!");
584 // See setCondCodeAction for how this is encoded.
585 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
586 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
587 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
588 assert(Action != Promote && "Can't promote condition code!");
592 /// Return true if the specified condition code is legal on this target.
593 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
595 getCondCodeAction(CC, VT) == Legal ||
596 getCondCodeAction(CC, VT) == Custom;
600 /// If the action for this operation is to promote, this method returns the
601 /// ValueType to promote to.
602 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
603 assert(getOperationAction(Op, VT) == Promote &&
604 "This operation isn't promoted!");
606 // See if this has an explicit type specified.
607 std::map<std::pair<unsigned, MVT::SimpleValueType>,
608 MVT::SimpleValueType>::const_iterator PTTI =
609 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
610 if (PTTI != PromoteToType.end()) return PTTI->second;
612 assert((VT.isInteger() || VT.isFloatingPoint()) &&
613 "Cannot autopromote this type, add it with AddPromotedToType.");
617 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
618 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
619 "Didn't find type to promote to!");
620 } while (!isTypeLegal(NVT) ||
621 getOperationAction(Op, NVT) == Promote);
625 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
626 /// operations except for the pointer size. If AllowUnknown is true, this
627 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
628 /// otherwise it will assert.
629 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
630 // Lower scalar pointers to native pointer types.
631 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
632 return getPointerTy(PTy->getAddressSpace());
634 if (Ty->isVectorTy()) {
635 VectorType *VTy = cast<VectorType>(Ty);
636 Type *Elm = VTy->getElementType();
637 // Lower vectors of pointers to native pointer types.
638 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
639 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
640 Elm = PointerTy.getTypeForEVT(Ty->getContext());
643 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
644 VTy->getNumElements());
646 return EVT::getEVT(Ty, AllowUnknown);
649 /// Return the MVT corresponding to this LLVM type. See getValueType.
650 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
651 return getValueType(Ty, AllowUnknown).getSimpleVT();
654 /// Return the desired alignment for ByVal or InAlloca aggregate function
655 /// arguments in the caller parameter area. This is the actual alignment, not
657 virtual unsigned getByValTypeAlignment(Type *Ty) const;
659 /// Return the type of registers that this ValueType will eventually require.
660 MVT getRegisterType(MVT VT) const {
661 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
662 return RegisterTypeForVT[VT.SimpleTy];
665 /// Return the type of registers that this ValueType will eventually require.
666 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
668 assert((unsigned)VT.getSimpleVT().SimpleTy <
669 array_lengthof(RegisterTypeForVT));
670 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
675 unsigned NumIntermediates;
676 (void)getVectorTypeBreakdown(Context, VT, VT1,
677 NumIntermediates, RegisterVT);
680 if (VT.isInteger()) {
681 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
683 llvm_unreachable("Unsupported extended type!");
686 /// Return the number of registers that this ValueType will eventually
689 /// This is one for any types promoted to live in larger registers, but may be
690 /// more than one for types (like i64) that are split into pieces. For types
691 /// like i140, which are first promoted then expanded, it is the number of
692 /// registers needed to hold all the bits of the original type. For an i140
693 /// on a 32 bit machine this means 5 registers.
694 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
696 assert((unsigned)VT.getSimpleVT().SimpleTy <
697 array_lengthof(NumRegistersForVT));
698 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
703 unsigned NumIntermediates;
704 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
706 if (VT.isInteger()) {
707 unsigned BitWidth = VT.getSizeInBits();
708 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
709 return (BitWidth + RegWidth - 1) / RegWidth;
711 llvm_unreachable("Unsupported extended type!");
714 /// If true, then instruction selection should seek to shrink the FP constant
715 /// of the specified type to a smaller type in order to save space and / or
717 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
719 /// If true, the target has custom DAG combine transformations that it can
720 /// perform for the specified node.
721 bool hasTargetDAGCombine(ISD::NodeType NT) const {
722 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
723 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
726 /// \brief Get maximum # of store operations permitted for llvm.memset
728 /// This function returns the maximum number of store operations permitted
729 /// to replace a call to llvm.memset. The value is set by the target at the
730 /// performance threshold for such a replacement. If OptSize is true,
731 /// return the limit for functions that have OptSize attribute.
732 unsigned getMaxStoresPerMemset(bool OptSize) const {
733 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
736 /// \brief Get maximum # of store operations permitted for llvm.memcpy
738 /// This function returns the maximum number of store operations permitted
739 /// to replace a call to llvm.memcpy. The value is set by the target at the
740 /// performance threshold for such a replacement. If OptSize is true,
741 /// return the limit for functions that have OptSize attribute.
742 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
743 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
746 /// \brief Get maximum # of store operations permitted for llvm.memmove
748 /// This function returns the maximum number of store operations permitted
749 /// to replace a call to llvm.memmove. The value is set by the target at the
750 /// performance threshold for such a replacement. If OptSize is true,
751 /// return the limit for functions that have OptSize attribute.
752 unsigned getMaxStoresPerMemmove(bool OptSize) const {
753 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
756 /// \brief Determine if the target supports unaligned memory accesses.
758 /// This function returns true if the target allows unaligned memory accesses
759 /// of the specified type in the given address space. If true, it also returns
760 /// whether the unaligned memory access is "fast" in the third argument by
761 /// reference. This is used, for example, in situations where an array
762 /// copy/move/set is converted to a sequence of store operations. Its use
763 /// helps to ensure that such replacements don't generate code that causes an
764 /// alignment error (trap) on the target machine.
765 virtual bool allowsUnalignedMemoryAccesses(EVT,
766 unsigned AddrSpace = 0,
767 bool * /*Fast*/ = nullptr) const {
771 /// Returns the target specific optimal type for load and store operations as
772 /// a result of memset, memcpy, and memmove lowering.
774 /// If DstAlign is zero that means it's safe to destination alignment can
775 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
776 /// a need to check it against alignment requirement, probably because the
777 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
778 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
779 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
780 /// does not need to be loaded. It returns EVT::Other if the type should be
781 /// determined using generic target-independent logic.
782 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
783 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
786 bool /*MemcpyStrSrc*/,
787 MachineFunction &/*MF*/) const {
791 /// Returns true if it's safe to use load / store of the specified type to
792 /// expand memcpy / memset inline.
794 /// This is mostly true for all types except for some special cases. For
795 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
796 /// fstpl which also does type conversion. Note the specified type doesn't
797 /// have to be legal as the hook is used before type legalization.
798 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
800 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
801 bool usesUnderscoreSetJmp() const {
802 return UseUnderscoreSetJmp;
805 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
806 bool usesUnderscoreLongJmp() const {
807 return UseUnderscoreLongJmp;
810 /// Return whether the target can generate code for jump tables.
811 bool supportJumpTables() const {
812 return SupportJumpTables;
815 /// Return integer threshold on number of blocks to use jump tables rather
816 /// than if sequence.
817 int getMinimumJumpTableEntries() const {
818 return MinimumJumpTableEntries;
821 /// If a physical register, this specifies the register that
822 /// llvm.savestack/llvm.restorestack should save and restore.
823 unsigned getStackPointerRegisterToSaveRestore() const {
824 return StackPointerRegisterToSaveRestore;
827 /// If a physical register, this returns the register that receives the
828 /// exception address on entry to a landing pad.
829 unsigned getExceptionPointerRegister() const {
830 return ExceptionPointerRegister;
833 /// If a physical register, this returns the register that receives the
834 /// exception typeid on entry to a landing pad.
835 unsigned getExceptionSelectorRegister() const {
836 return ExceptionSelectorRegister;
839 /// Returns the target's jmp_buf size in bytes (if never set, the default is
841 unsigned getJumpBufSize() const {
845 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
847 unsigned getJumpBufAlignment() const {
848 return JumpBufAlignment;
851 /// Return the minimum stack alignment of an argument.
852 unsigned getMinStackArgumentAlignment() const {
853 return MinStackArgumentAlignment;
856 /// Return the minimum function alignment.
857 unsigned getMinFunctionAlignment() const {
858 return MinFunctionAlignment;
861 /// Return the preferred function alignment.
862 unsigned getPrefFunctionAlignment() const {
863 return PrefFunctionAlignment;
866 /// Return the preferred loop alignment.
867 unsigned getPrefLoopAlignment() const {
868 return PrefLoopAlignment;
871 /// Return whether the DAG builder should automatically insert fences and
872 /// reduce ordering for atomics.
873 bool getInsertFencesForAtomic() const {
874 return InsertFencesForAtomic;
877 /// Return true if the target stores stack protector cookies at a fixed offset
878 /// in some non-standard address space, and populates the address space and
879 /// offset as appropriate.
880 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
881 unsigned &/*Offset*/) const {
885 /// Returns the maximal possible offset which can be used for loads / stores
887 virtual unsigned getMaximalGlobalOffset() const {
891 /// Returns true if a cast between SrcAS and DestAS is a noop.
892 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
896 //===--------------------------------------------------------------------===//
897 /// \name Helpers for TargetTransformInfo implementations
900 /// Get the ISD node that corresponds to the Instruction class opcode.
901 int InstructionOpcodeToISD(unsigned Opcode) const;
903 /// Estimate the cost of type-legalization and the legalized type.
904 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
908 //===--------------------------------------------------------------------===//
909 /// \name Helpers for load-linked/store-conditional atomic expansion.
912 /// Perform a load-linked operation on Addr, returning a "Value *" with the
913 /// corresponding pointee type. This may entail some non-trivial operations to
914 /// truncate or reconstruct types that will be illegal in the backend. See
915 /// ARMISelLowering for an example implementation.
916 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
917 AtomicOrdering Ord) const {
918 llvm_unreachable("Load linked unimplemented on this target");
921 /// Perform a store-conditional operation to Addr. Return the status of the
922 /// store. This should be 0 if the store succeeded, non-zero otherwise.
923 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
924 Value *Addr, AtomicOrdering Ord) const {
925 llvm_unreachable("Store conditional unimplemented on this target");
928 /// Return true if the given (atomic) instruction should be expanded by the
929 /// IR-level AtomicExpandLoadLinked pass into a loop involving
930 /// load-linked/store-conditional pairs. Atomic stores will be expanded in the
931 /// same way as "atomic xchg" operations which ignore their output if needed.
932 virtual bool shouldExpandAtomicInIR(Instruction *Inst) const {
937 //===--------------------------------------------------------------------===//
938 // TargetLowering Configuration Methods - These methods should be invoked by
939 // the derived class constructor to configure this object for the target.
942 /// \brief Reset the operation actions based on target options.
943 virtual void resetOperationActions() {}
946 /// Specify how the target extends the result of a boolean value from i1 to a
947 /// wider type. See getBooleanContents.
948 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
950 /// Specify how the target extends the result of a vector boolean value from a
951 /// vector of i1 to a wider type. See getBooleanContents.
952 void setBooleanVectorContents(BooleanContent Ty) {
953 BooleanVectorContents = Ty;
956 /// Specify the target scheduling preference.
957 void setSchedulingPreference(Sched::Preference Pref) {
958 SchedPreferenceInfo = Pref;
961 /// Indicate whether this target prefers to use _setjmp to implement
962 /// llvm.setjmp or the version without _. Defaults to false.
963 void setUseUnderscoreSetJmp(bool Val) {
964 UseUnderscoreSetJmp = Val;
967 /// Indicate whether this target prefers to use _longjmp to implement
968 /// llvm.longjmp or the version without _. Defaults to false.
969 void setUseUnderscoreLongJmp(bool Val) {
970 UseUnderscoreLongJmp = Val;
973 /// Indicate whether the target can generate code for jump tables.
974 void setSupportJumpTables(bool Val) {
975 SupportJumpTables = Val;
978 /// Indicate the number of blocks to generate jump tables rather than if
980 void setMinimumJumpTableEntries(int Val) {
981 MinimumJumpTableEntries = Val;
984 /// If set to a physical register, this specifies the register that
985 /// llvm.savestack/llvm.restorestack should save and restore.
986 void setStackPointerRegisterToSaveRestore(unsigned R) {
987 StackPointerRegisterToSaveRestore = R;
990 /// If set to a physical register, this sets the register that receives the
991 /// exception address on entry to a landing pad.
992 void setExceptionPointerRegister(unsigned R) {
993 ExceptionPointerRegister = R;
996 /// If set to a physical register, this sets the register that receives the
997 /// exception typeid on entry to a landing pad.
998 void setExceptionSelectorRegister(unsigned R) {
999 ExceptionSelectorRegister = R;
1002 /// Tells the code generator not to expand operations into sequences that use
1003 /// the select operations if possible.
1004 void setSelectIsExpensive(bool isExpensive = true) {
1005 SelectIsExpensive = isExpensive;
1008 /// Tells the code generator that the target has multiple (allocatable)
1009 /// condition registers that can be used to store the results of comparisons
1010 /// for use by selects and conditional branches. With multiple condition
1011 /// registers, the code generator will not aggressively sink comparisons into
1012 /// the blocks of their users.
1013 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1014 HasMultipleConditionRegisters = hasManyRegs;
1017 /// Tells the code generator that the target has BitExtract instructions.
1018 /// The code generator will aggressively sink "shift"s into the blocks of
1019 /// their users if the users will generate "and" instructions which can be
1020 /// combined with "shift" to BitExtract instructions.
1021 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1022 HasExtractBitsInsn = hasExtractInsn;
1025 /// Tells the code generator not to expand sequence of operations into a
1026 /// separate sequences that increases the amount of flow control.
1027 void setJumpIsExpensive(bool isExpensive = true) {
1028 JumpIsExpensive = isExpensive;
1031 /// Tells the code generator that integer divide is expensive, and if
1032 /// possible, should be replaced by an alternate sequence of instructions not
1033 /// containing an integer divide.
1034 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1036 /// Tells the code generator which bitwidths to bypass.
1037 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1038 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1041 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1042 /// signed divide by power of two, and let the target handle it.
1043 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1045 /// Add the specified register class as an available regclass for the
1046 /// specified value type. This indicates the selector can handle values of
1047 /// that class natively.
1048 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1049 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1050 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1051 RegClassForVT[VT.SimpleTy] = RC;
1054 /// Remove all register classes.
1055 void clearRegisterClasses() {
1056 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1058 AvailableRegClasses.clear();
1061 /// \brief Remove all operation actions.
1062 void clearOperationActions() {
1065 /// Return the largest legal super-reg register class of the register class
1066 /// for the specified type and its associated "cost".
1067 virtual std::pair<const TargetRegisterClass*, uint8_t>
1068 findRepresentativeClass(MVT VT) const;
1070 /// Once all of the register classes are added, this allows us to compute
1071 /// derived properties we expose.
1072 void computeRegisterProperties();
1074 /// Indicate that the specified operation does not work with the specified
1075 /// type and indicate what to do about it.
1076 void setOperationAction(unsigned Op, MVT VT,
1077 LegalizeAction Action) {
1078 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1079 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1082 /// Indicate that the specified load with extension does not work with the
1083 /// specified type and indicate what to do about it.
1084 void setLoadExtAction(unsigned ExtType, MVT VT,
1085 LegalizeAction Action) {
1086 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1087 "Table isn't big enough!");
1088 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1091 /// Indicate that the specified truncating store does not work with the
1092 /// specified type and indicate what to do about it.
1093 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1094 LegalizeAction Action) {
1095 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1096 "Table isn't big enough!");
1097 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1100 /// Indicate that the specified indexed load does or does not work with the
1101 /// specified type and indicate what to do abort it.
1103 /// NOTE: All indexed mode loads are initialized to Expand in
1104 /// TargetLowering.cpp
1105 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1106 LegalizeAction Action) {
1107 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1108 (unsigned)Action < 0xf && "Table isn't big enough!");
1109 // Load action are kept in the upper half.
1110 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1111 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1114 /// Indicate that the specified indexed store does or does not work with the
1115 /// specified type and indicate what to do about it.
1117 /// NOTE: All indexed mode stores are initialized to Expand in
1118 /// TargetLowering.cpp
1119 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1120 LegalizeAction Action) {
1121 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1122 (unsigned)Action < 0xf && "Table isn't big enough!");
1123 // Store action are kept in the lower half.
1124 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1125 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1128 /// Indicate that the specified condition code is or isn't supported on the
1129 /// target and indicate what to do about it.
1130 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1131 LegalizeAction Action) {
1132 assert(VT < MVT::LAST_VALUETYPE &&
1133 (unsigned)CC < array_lengthof(CondCodeActions) &&
1134 "Table isn't big enough!");
1135 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1136 /// value and the upper 27 bits index into the second dimension of the array
1137 /// to select what 32-bit value to use.
1138 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1139 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1140 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1143 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1144 /// to trying a larger integer/fp until it can find one that works. If that
1145 /// default is insufficient, this method can be used by the target to override
1147 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1148 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1151 /// Targets should invoke this method for each target independent node that
1152 /// they want to provide a custom DAG combiner for by implementing the
1153 /// PerformDAGCombine virtual method.
1154 void setTargetDAGCombine(ISD::NodeType NT) {
1155 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1156 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1159 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1160 void setJumpBufSize(unsigned Size) {
1164 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1166 void setJumpBufAlignment(unsigned Align) {
1167 JumpBufAlignment = Align;
1170 /// Set the target's minimum function alignment (in log2(bytes))
1171 void setMinFunctionAlignment(unsigned Align) {
1172 MinFunctionAlignment = Align;
1175 /// Set the target's preferred function alignment. This should be set if
1176 /// there is a performance benefit to higher-than-minimum alignment (in
1178 void setPrefFunctionAlignment(unsigned Align) {
1179 PrefFunctionAlignment = Align;
1182 /// Set the target's preferred loop alignment. Default alignment is zero, it
1183 /// means the target does not care about loop alignment. The alignment is
1184 /// specified in log2(bytes).
1185 void setPrefLoopAlignment(unsigned Align) {
1186 PrefLoopAlignment = Align;
1189 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1190 void setMinStackArgumentAlignment(unsigned Align) {
1191 MinStackArgumentAlignment = Align;
1194 /// Set if the DAG builder should automatically insert fences and reduce the
1195 /// order of atomic memory operations to Monotonic.
1196 void setInsertFencesForAtomic(bool fence) {
1197 InsertFencesForAtomic = fence;
1201 //===--------------------------------------------------------------------===//
1202 // Addressing mode description hooks (used by LSR etc).
1205 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1206 /// instructions reading the address. This allows as much computation as
1207 /// possible to be done in the address mode for that operand. This hook lets
1208 /// targets also pass back when this should be done on intrinsics which
1210 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1211 SmallVectorImpl<Value*> &/*Ops*/,
1212 Type *&/*AccessTy*/) const {
1216 /// This represents an addressing mode of:
1217 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1218 /// If BaseGV is null, there is no BaseGV.
1219 /// If BaseOffs is zero, there is no base offset.
1220 /// If HasBaseReg is false, there is no base register.
1221 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1224 GlobalValue *BaseGV;
1228 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1231 /// Return true if the addressing mode represented by AM is legal for this
1232 /// target, for a load/store of the specified type.
1234 /// The type may be VoidTy, in which case only return true if the addressing
1235 /// mode is legal for a load/store of any legal type. TODO: Handle
1236 /// pre/postinc as well.
1237 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1239 /// \brief Return the cost of the scaling factor used in the addressing mode
1240 /// represented by AM for this target, for a load/store of the specified type.
1242 /// If the AM is supported, the return value must be >= 0.
1243 /// If the AM is not supported, it returns a negative value.
1244 /// TODO: Handle pre/postinc as well.
1245 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1246 // Default: assume that any scaling factor used in a legal AM is free.
1247 if (isLegalAddressingMode(AM, Ty)) return 0;
1251 /// Return true if the specified immediate is legal icmp immediate, that is
1252 /// the target has icmp instructions which can compare a register against the
1253 /// immediate without having to materialize the immediate into a register.
1254 virtual bool isLegalICmpImmediate(int64_t) const {
1258 /// Return true if the specified immediate is legal add immediate, that is the
1259 /// target has add instructions which can add a register with the immediate
1260 /// without having to materialize the immediate into a register.
1261 virtual bool isLegalAddImmediate(int64_t) const {
1265 /// Return true if it's significantly cheaper to shift a vector by a uniform
1266 /// scalar than by an amount which will vary across each lane. On x86, for
1267 /// example, there is a "psllw" instruction for the former case, but no simple
1268 /// instruction for a general "a << b" operation on vectors.
1269 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1273 /// Return true if it's free to truncate a value of type Ty1 to type
1274 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1275 /// by referencing its sub-register AX.
1276 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1280 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1281 /// whether a call is in tail position. Typically this means that both results
1282 /// would be assigned to the same register or stack slot, but it could mean
1283 /// the target performs adequate checks of its own before proceeding with the
1285 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1289 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1293 /// Return true if any actual instruction that defines a value of type Ty1
1294 /// implicitly zero-extends the value to Ty2 in the result register.
1296 /// This does not necessarily include registers defined in unknown ways, such
1297 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1298 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1299 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1300 /// values implicit zero-extend the result out to 64 bits.
1301 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1305 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1309 /// Return true if the target supplies and combines to a paired load
1310 /// two loaded values of type LoadedType next to each other in memory.
1311 /// RequiredAlignment gives the minimal alignment constraints that must be met
1312 /// to be able to select this paired load.
1314 /// This information is *not* used to generate actual paired loads, but it is
1315 /// used to generate a sequence of loads that is easier to combine into a
1317 /// For instance, something like this:
1318 /// a = load i64* addr
1319 /// b = trunc i64 a to i32
1320 /// c = lshr i64 a, 32
1321 /// d = trunc i64 c to i32
1322 /// will be optimized into:
1323 /// b = load i32* addr1
1324 /// d = load i32* addr2
1325 /// Where addr1 = addr2 +/- sizeof(i32).
1327 /// In other words, unless the target performs a post-isel load combining,
1328 /// this information should not be provided because it will generate more
1330 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1331 unsigned & /*RequiredAligment*/) const {
1335 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1336 unsigned & /*RequiredAligment*/) const {
1340 /// Return true if zero-extending the specific node Val to type VT2 is free
1341 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1342 /// because it's folded such as X86 zero-extending loads).
1343 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1344 return isZExtFree(Val.getValueType(), VT2);
1347 /// Return true if an fneg operation is free to the point where it is never
1348 /// worthwhile to replace it with a bitwise operation.
1349 virtual bool isFNegFree(EVT VT) const {
1350 assert(VT.isFloatingPoint());
1354 /// Return true if an fabs operation is free to the point where it is never
1355 /// worthwhile to replace it with a bitwise operation.
1356 virtual bool isFAbsFree(EVT VT) const {
1357 assert(VT.isFloatingPoint());
1361 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1362 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1363 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1365 /// NOTE: This may be called before legalization on types for which FMAs are
1366 /// not legal, but should return true if those types will eventually legalize
1367 /// to types that support FMAs. After legalization, it will only be called on
1368 /// types that support FMAs (via Legal or Custom actions)
1369 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1373 /// Return true if it's profitable to narrow operations of type VT1 to
1374 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1376 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1380 /// \brief Return true if it is beneficial to convert a load of a constant to
1381 /// just the constant itself.
1382 /// On some targets it might be more efficient to use a combination of
1383 /// arithmetic instructions to materialize the constant instead of loading it
1384 /// from a constant pool.
1385 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1389 //===--------------------------------------------------------------------===//
1390 // Runtime Library hooks
1393 /// Rename the default libcall routine name for the specified libcall.
1394 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1395 LibcallRoutineNames[Call] = Name;
1398 /// Get the libcall routine name for the specified libcall.
1399 const char *getLibcallName(RTLIB::Libcall Call) const {
1400 return LibcallRoutineNames[Call];
1403 /// Override the default CondCode to be used to test the result of the
1404 /// comparison libcall against zero.
1405 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1406 CmpLibcallCCs[Call] = CC;
1409 /// Get the CondCode that's to be used to test the result of the comparison
1410 /// libcall against zero.
1411 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1412 return CmpLibcallCCs[Call];
1415 /// Set the CallingConv that should be used for the specified libcall.
1416 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1417 LibcallCallingConvs[Call] = CC;
1420 /// Get the CallingConv that should be used for the specified libcall.
1421 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1422 return LibcallCallingConvs[Call];
1426 const TargetMachine &TM;
1427 const DataLayout *DL;
1428 const TargetLoweringObjectFile &TLOF;
1430 /// True if this is a little endian target.
1431 bool IsLittleEndian;
1433 /// Tells the code generator not to expand operations into sequences that use
1434 /// the select operations if possible.
1435 bool SelectIsExpensive;
1437 /// Tells the code generator that the target has multiple (allocatable)
1438 /// condition registers that can be used to store the results of comparisons
1439 /// for use by selects and conditional branches. With multiple condition
1440 /// registers, the code generator will not aggressively sink comparisons into
1441 /// the blocks of their users.
1442 bool HasMultipleConditionRegisters;
1444 /// Tells the code generator that the target has BitExtract instructions.
1445 /// The code generator will aggressively sink "shift"s into the blocks of
1446 /// their users if the users will generate "and" instructions which can be
1447 /// combined with "shift" to BitExtract instructions.
1448 bool HasExtractBitsInsn;
1450 /// Tells the code generator not to expand integer divides by constants into a
1451 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1452 /// model is in place. If we ever optimize for size, this will be set to true
1453 /// unconditionally.
1456 /// Tells the code generator to bypass slow divide or remainder
1457 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1458 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1459 /// div/rem when the operands are positive and less than 256.
1460 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1462 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1463 /// signed divide by power of two, and let the target handle it.
1464 bool Pow2DivIsCheap;
1466 /// Tells the code generator that it shouldn't generate extra flow control
1467 /// instructions and should attempt to combine flow control instructions via
1469 bool JumpIsExpensive;
1471 /// This target prefers to use _setjmp to implement llvm.setjmp.
1473 /// Defaults to false.
1474 bool UseUnderscoreSetJmp;
1476 /// This target prefers to use _longjmp to implement llvm.longjmp.
1478 /// Defaults to false.
1479 bool UseUnderscoreLongJmp;
1481 /// Whether the target can generate code for jumptables. If it's not true,
1482 /// then each jumptable must be lowered into if-then-else's.
1483 bool SupportJumpTables;
1485 /// Number of blocks threshold to use jump tables.
1486 int MinimumJumpTableEntries;
1488 /// Information about the contents of the high-bits in boolean values held in
1489 /// a type wider than i1. See getBooleanContents.
1490 BooleanContent BooleanContents;
1492 /// Information about the contents of the high-bits in boolean vector values
1493 /// when the element type is wider than i1. See getBooleanContents.
1494 BooleanContent BooleanVectorContents;
1496 /// The target scheduling preference: shortest possible total cycles or lowest
1498 Sched::Preference SchedPreferenceInfo;
1500 /// The size, in bytes, of the target's jmp_buf buffers
1501 unsigned JumpBufSize;
1503 /// The alignment, in bytes, of the target's jmp_buf buffers
1504 unsigned JumpBufAlignment;
1506 /// The minimum alignment that any argument on the stack needs to have.
1507 unsigned MinStackArgumentAlignment;
1509 /// The minimum function alignment (used when optimizing for size, and to
1510 /// prevent explicitly provided alignment from leading to incorrect code).
1511 unsigned MinFunctionAlignment;
1513 /// The preferred function alignment (used when alignment unspecified and
1514 /// optimizing for speed).
1515 unsigned PrefFunctionAlignment;
1517 /// The preferred loop alignment.
1518 unsigned PrefLoopAlignment;
1520 /// Whether the DAG builder should automatically insert fences and reduce
1521 /// ordering for atomics. (This will be set for for most architectures with
1522 /// weak memory ordering.)
1523 bool InsertFencesForAtomic;
1525 /// If set to a physical register, this specifies the register that
1526 /// llvm.savestack/llvm.restorestack should save and restore.
1527 unsigned StackPointerRegisterToSaveRestore;
1529 /// If set to a physical register, this specifies the register that receives
1530 /// the exception address on entry to a landing pad.
1531 unsigned ExceptionPointerRegister;
1533 /// If set to a physical register, this specifies the register that receives
1534 /// the exception typeid on entry to a landing pad.
1535 unsigned ExceptionSelectorRegister;
1537 /// This indicates the default register class to use for each ValueType the
1538 /// target supports natively.
1539 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1540 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1541 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1543 /// This indicates the "representative" register class to use for each
1544 /// ValueType the target supports natively. This information is used by the
1545 /// scheduler to track register pressure. By default, the representative
1546 /// register class is the largest legal super-reg register class of the
1547 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1548 /// representative class would be GR32.
1549 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1551 /// This indicates the "cost" of the "representative" register class for each
1552 /// ValueType. The cost is used by the scheduler to approximate register
1554 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1556 /// For any value types we are promoting or expanding, this contains the value
1557 /// type that we are changing to. For Expanded types, this contains one step
1558 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1559 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1560 /// the same type (e.g. i32 -> i32).
1561 MVT TransformToType[MVT::LAST_VALUETYPE];
1563 /// For each operation and each value type, keep a LegalizeAction that
1564 /// indicates how instruction selection should deal with the operation. Most
1565 /// operations are Legal (aka, supported natively by the target), but
1566 /// operations that are not should be described. Note that operations on
1567 /// non-legal value types are not described here.
1568 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1570 /// For each load extension type and each value type, keep a LegalizeAction
1571 /// that indicates how instruction selection should deal with a load of a
1572 /// specific value type and extension type.
1573 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1575 /// For each value type pair keep a LegalizeAction that indicates whether a
1576 /// truncating store of a specific value type and truncating type is legal.
1577 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1579 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1580 /// that indicates how instruction selection should deal with the load /
1583 /// The first dimension is the value_type for the reference. The second
1584 /// dimension represents the various modes for load store.
1585 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1587 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1588 /// indicates how instruction selection should deal with the condition code.
1590 /// Because each CC action takes up 2 bits, we need to have the array size be
1591 /// large enough to fit all of the value types. This can be done by rounding
1592 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1593 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1595 ValueTypeActionImpl ValueTypeActions;
1599 getTypeConversion(LLVMContext &Context, EVT VT) const {
1600 // If this is a simple type, use the ComputeRegisterProp mechanism.
1601 if (VT.isSimple()) {
1602 MVT SVT = VT.getSimpleVT();
1603 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1604 MVT NVT = TransformToType[SVT.SimpleTy];
1605 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1609 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1610 && "Promote may not follow Expand or Promote");
1612 if (LA == TypeSplitVector)
1613 return LegalizeKind(LA, EVT::getVectorVT(Context,
1614 SVT.getVectorElementType(),
1615 SVT.getVectorNumElements()/2));
1616 if (LA == TypeScalarizeVector)
1617 return LegalizeKind(LA, SVT.getVectorElementType());
1618 return LegalizeKind(LA, NVT);
1621 // Handle Extended Scalar Types.
1622 if (!VT.isVector()) {
1623 assert(VT.isInteger() && "Float types must be simple");
1624 unsigned BitSize = VT.getSizeInBits();
1625 // First promote to a power-of-two size, then expand if necessary.
1626 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1627 EVT NVT = VT.getRoundIntegerType(Context);
1628 assert(NVT != VT && "Unable to round integer VT");
1629 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1630 // Avoid multi-step promotion.
1631 if (NextStep.first == TypePromoteInteger) return NextStep;
1632 // Return rounded integer type.
1633 return LegalizeKind(TypePromoteInteger, NVT);
1636 return LegalizeKind(TypeExpandInteger,
1637 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1640 // Handle vector types.
1641 unsigned NumElts = VT.getVectorNumElements();
1642 EVT EltVT = VT.getVectorElementType();
1644 // Vectors with only one element are always scalarized.
1646 return LegalizeKind(TypeScalarizeVector, EltVT);
1648 // Try to widen vector elements until the element type is a power of two and
1649 // promote it to a legal type later on, for example:
1650 // <3 x i8> -> <4 x i8> -> <4 x i32>
1651 if (EltVT.isInteger()) {
1652 // Vectors with a number of elements that is not a power of two are always
1653 // widened, for example <3 x i8> -> <4 x i8>.
1654 if (!VT.isPow2VectorType()) {
1655 NumElts = (unsigned)NextPowerOf2(NumElts);
1656 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1657 return LegalizeKind(TypeWidenVector, NVT);
1660 // Examine the element type.
1661 LegalizeKind LK = getTypeConversion(Context, EltVT);
1663 // If type is to be expanded, split the vector.
1664 // <4 x i140> -> <2 x i140>
1665 if (LK.first == TypeExpandInteger)
1666 return LegalizeKind(TypeSplitVector,
1667 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1669 // Promote the integer element types until a legal vector type is found
1670 // or until the element integer type is too big. If a legal type was not
1671 // found, fallback to the usual mechanism of widening/splitting the
1673 EVT OldEltVT = EltVT;
1675 // Increase the bitwidth of the element to the next pow-of-two
1676 // (which is greater than 8 bits).
1677 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1678 ).getRoundIntegerType(Context);
1680 // Stop trying when getting a non-simple element type.
1681 // Note that vector elements may be greater than legal vector element
1682 // types. Example: X86 XMM registers hold 64bit element on 32bit
1684 if (!EltVT.isSimple()) break;
1686 // Build a new vector type and check if it is legal.
1687 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1688 // Found a legal promoted vector type.
1689 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1690 return LegalizeKind(TypePromoteInteger,
1691 EVT::getVectorVT(Context, EltVT, NumElts));
1694 // Reset the type to the unexpanded type if we did not find a legal vector
1695 // type with a promoted vector element type.
1699 // Try to widen the vector until a legal type is found.
1700 // If there is no wider legal type, split the vector.
1702 // Round up to the next power of 2.
1703 NumElts = (unsigned)NextPowerOf2(NumElts);
1705 // If there is no simple vector type with this many elements then there
1706 // cannot be a larger legal vector type. Note that this assumes that
1707 // there are no skipped intermediate vector types in the simple types.
1708 if (!EltVT.isSimple()) break;
1709 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1710 if (LargerVector == MVT()) break;
1712 // If this type is legal then widen the vector.
1713 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1714 return LegalizeKind(TypeWidenVector, LargerVector);
1717 // Widen odd vectors to next power of two.
1718 if (!VT.isPow2VectorType()) {
1719 EVT NVT = VT.getPow2VectorType(Context);
1720 return LegalizeKind(TypeWidenVector, NVT);
1723 // Vectors with illegal element types are expanded.
1724 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1725 return LegalizeKind(TypeSplitVector, NVT);
1729 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1731 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1732 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1735 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1737 /// For operations that must be promoted to a specific type, this holds the
1738 /// destination type. This map should be sparse, so don't hold it as an
1741 /// Targets add entries to this map with AddPromotedToType(..), clients access
1742 /// this with getTypeToPromoteTo(..).
1743 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1746 /// Stores the name each libcall.
1747 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1749 /// The ISD::CondCode that should be used to test the result of each of the
1750 /// comparison libcall against zero.
1751 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1753 /// Stores the CallingConv that should be used for each libcall.
1754 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1757 /// \brief Specify maximum number of store instructions per memset call.
1759 /// When lowering \@llvm.memset this field specifies the maximum number of
1760 /// store operations that may be substituted for the call to memset. Targets
1761 /// must set this value based on the cost threshold for that target. Targets
1762 /// should assume that the memset will be done using as many of the largest
1763 /// store operations first, followed by smaller ones, if necessary, per
1764 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1765 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1766 /// store. This only applies to setting a constant array of a constant size.
1767 unsigned MaxStoresPerMemset;
1769 /// Maximum number of stores operations that may be substituted for the call
1770 /// to memset, used for functions with OptSize attribute.
1771 unsigned MaxStoresPerMemsetOptSize;
1773 /// \brief Specify maximum bytes of store instructions per memcpy call.
1775 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1776 /// store operations that may be substituted for a call to memcpy. Targets
1777 /// must set this value based on the cost threshold for that target. Targets
1778 /// should assume that the memcpy will be done using as many of the largest
1779 /// store operations first, followed by smaller ones, if necessary, per
1780 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1781 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1782 /// and one 1-byte store. This only applies to copying a constant array of
1784 unsigned MaxStoresPerMemcpy;
1786 /// Maximum number of store operations that may be substituted for a call to
1787 /// memcpy, used for functions with OptSize attribute.
1788 unsigned MaxStoresPerMemcpyOptSize;
1790 /// \brief Specify maximum bytes of store instructions per memmove call.
1792 /// When lowering \@llvm.memmove this field specifies the maximum number of
1793 /// store instructions that may be substituted for a call to memmove. Targets
1794 /// must set this value based on the cost threshold for that target. Targets
1795 /// should assume that the memmove will be done using as many of the largest
1796 /// store operations first, followed by smaller ones, if necessary, per
1797 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1798 /// with 8-bit alignment would result in nine 1-byte stores. This only
1799 /// applies to copying a constant array of constant size.
1800 unsigned MaxStoresPerMemmove;
1802 /// Maximum number of store instructions that may be substituted for a call to
1803 /// memmove, used for functions with OpSize attribute.
1804 unsigned MaxStoresPerMemmoveOptSize;
1806 /// Tells the code generator that select is more expensive than a branch if
1807 /// the branch is usually predicted right.
1808 bool PredictableSelectIsExpensive;
1810 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1811 /// a mask of a single bit, a compare, and a branch into a single instruction.
1812 bool MaskAndBranchFoldingIsLegal;
1815 /// Return true if the value types that can be represented by the specified
1816 /// register class are all legal.
1817 bool isLegalRC(const TargetRegisterClass *RC) const;
1819 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1820 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1821 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1824 /// This class defines information used to lower LLVM code to legal SelectionDAG
1825 /// operators that the target instruction selector can accept natively.
1827 /// This class also defines callbacks that targets must implement to lower
1828 /// target-specific constructs to SelectionDAG operators.
1829 class TargetLowering : public TargetLoweringBase {
1830 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1831 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1834 /// NOTE: The constructor takes ownership of TLOF.
1835 explicit TargetLowering(const TargetMachine &TM,
1836 const TargetLoweringObjectFile *TLOF);
1838 /// Returns true by value, base pointer and offset pointer and addressing mode
1839 /// by reference if the node's address can be legally represented as
1840 /// pre-indexed load / store address.
1841 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1842 SDValue &/*Offset*/,
1843 ISD::MemIndexedMode &/*AM*/,
1844 SelectionDAG &/*DAG*/) const {
1848 /// Returns true by value, base pointer and offset pointer and addressing mode
1849 /// by reference if this node can be combined with a load / store to form a
1850 /// post-indexed load / store.
1851 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1853 SDValue &/*Offset*/,
1854 ISD::MemIndexedMode &/*AM*/,
1855 SelectionDAG &/*DAG*/) const {
1859 /// Return the entry encoding for a jump table in the current function. The
1860 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1861 virtual unsigned getJumpTableEncoding() const;
1863 virtual const MCExpr *
1864 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1865 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1866 MCContext &/*Ctx*/) const {
1867 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1870 /// Returns relocation base for the given PIC jumptable.
1871 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1872 SelectionDAG &DAG) const;
1874 /// This returns the relocation base for the given PIC jumptable, the same as
1875 /// getPICJumpTableRelocBase, but as an MCExpr.
1876 virtual const MCExpr *
1877 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1878 unsigned JTI, MCContext &Ctx) const;
1880 /// Return true if folding a constant offset with the given GlobalAddress is
1881 /// legal. It is frequently not legal in PIC relocation models.
1882 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1884 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1885 SDValue &Chain) const;
1887 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1888 SDValue &NewLHS, SDValue &NewRHS,
1889 ISD::CondCode &CCCode, SDLoc DL) const;
1891 /// Returns a pair of (return value, chain).
1892 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1893 EVT RetVT, const SDValue *Ops,
1894 unsigned NumOps, bool isSigned,
1895 SDLoc dl, bool doesNotReturn = false,
1896 bool isReturnValueUsed = true) const;
1898 //===--------------------------------------------------------------------===//
1899 // TargetLowering Optimization Methods
1902 /// A convenience struct that encapsulates a DAG, and two SDValues for
1903 /// returning information from TargetLowering to its clients that want to
1905 struct TargetLoweringOpt {
1912 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1914 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1916 bool LegalTypes() const { return LegalTys; }
1917 bool LegalOperations() const { return LegalOps; }
1919 bool CombineTo(SDValue O, SDValue N) {
1925 /// Check to see if the specified operand of the specified instruction is a
1926 /// constant integer. If so, check to see if there are any bits set in the
1927 /// constant that are not demanded. If so, shrink the constant and return
1929 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1931 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1932 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1933 /// generalized for targets with other types of implicit widening casts.
1934 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1938 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1939 /// result of Op are ever used downstream. If we can use this information to
1940 /// simplify Op, create a new simplified DAG node and return true, returning
1941 /// the original and new nodes in Old and New. Otherwise, analyze the
1942 /// expression and return a mask of KnownOne and KnownZero bits for the
1943 /// expression (used to simplify the caller). The KnownZero/One bits may only
1944 /// be accurate for those bits in the DemandedMask.
1945 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1946 APInt &KnownZero, APInt &KnownOne,
1947 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1949 /// Determine which of the bits specified in Mask are known to be either zero
1950 /// or one and return them in the KnownZero/KnownOne bitsets.
1951 virtual void computeKnownBitsForTargetNode(const SDValue Op,
1954 const SelectionDAG &DAG,
1955 unsigned Depth = 0) const;
1957 /// This method can be implemented by targets that want to expose additional
1958 /// information about sign bits to the DAG Combiner.
1959 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1960 const SelectionDAG &DAG,
1961 unsigned Depth = 0) const;
1963 struct DAGCombinerInfo {
1964 void *DC; // The DAG Combiner object.
1966 bool CalledByLegalizer;
1970 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1971 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1973 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1974 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1975 bool isAfterLegalizeVectorOps() const {
1976 return Level == AfterLegalizeDAG;
1978 CombineLevel getDAGCombineLevel() { return Level; }
1979 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1981 void AddToWorklist(SDNode *N);
1982 void RemoveFromWorklist(SDNode *N);
1983 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1985 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1986 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1988 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1991 /// Return if the N is a constant or constant vector equal to the true value
1992 /// from getBooleanContents().
1993 bool isConstTrueVal(const SDNode *N) const;
1995 /// Return if the N is a constant or constant vector equal to the false value
1996 /// from getBooleanContents().
1997 bool isConstFalseVal(const SDNode *N) const;
1999 /// Try to simplify a setcc built with the specified operands and cc. If it is
2000 /// unable to simplify it, return a null SDValue.
2001 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2002 ISD::CondCode Cond, bool foldBooleans,
2003 DAGCombinerInfo &DCI, SDLoc dl) const;
2005 /// Returns true (and the GlobalValue and the offset) if the node is a
2006 /// GlobalAddress + offset.
2008 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2010 /// This method will be invoked for all target nodes and for any
2011 /// target-independent nodes that the target has registered with invoke it
2014 /// The semantics are as follows:
2016 /// SDValue.Val == 0 - No change was made
2017 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2018 /// otherwise - N should be replaced by the returned Operand.
2020 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2021 /// more complex transformations.
2023 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2025 /// Return true if it is profitable to move a following shift through this
2026 // node, adjusting any immediate operands as necessary to preserve semantics.
2027 // This transformation may not be desirable if it disrupts a particularly
2028 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2029 // By default, it returns true.
2030 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2034 /// Return true if the target has native support for the specified value type
2035 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2036 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2037 /// and some i16 instructions are slow.
2038 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2039 // By default, assume all legal types are desirable.
2040 return isTypeLegal(VT);
2043 /// Return true if it is profitable for dag combiner to transform a floating
2044 /// point op of specified opcode to a equivalent op of an integer
2045 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2046 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2051 /// This method query the target whether it is beneficial for dag combiner to
2052 /// promote the specified node. If true, it should return the desired
2053 /// promotion type by reference.
2054 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2058 //===--------------------------------------------------------------------===//
2059 // Lowering methods - These methods must be implemented by targets so that
2060 // the SelectionDAGBuilder code knows how to lower these.
2063 /// This hook must be implemented to lower the incoming (formal) arguments,
2064 /// described by the Ins array, into the specified DAG. The implementation
2065 /// should fill in the InVals array with legal-type argument values, and
2066 /// return the resulting token chain value.
2069 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2071 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2072 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2073 SmallVectorImpl<SDValue> &/*InVals*/) const {
2074 llvm_unreachable("Not Implemented");
2077 struct ArgListEntry {
2086 bool isInAlloca : 1;
2087 bool isReturned : 1;
2090 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2091 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2092 isReturned(false), Alignment(0) { }
2094 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2096 typedef std::vector<ArgListEntry> ArgListTy;
2098 /// This structure contains all information that is necessary for lowering
2099 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2100 /// needs to lower a call, and targets will see this struct in their LowerCall
2102 struct CallLoweringInfo {
2109 bool DoesNotReturn : 1;
2110 bool IsReturnValueUsed : 1;
2112 // IsTailCall should be modified by implementations of
2113 // TargetLowering::LowerCall that perform tail call conversions.
2116 unsigned NumFixedArgs;
2117 CallingConv::ID CallConv;
2122 ImmutableCallSite *CS;
2123 SmallVector<ISD::OutputArg, 32> Outs;
2124 SmallVector<SDValue, 32> OutVals;
2125 SmallVector<ISD::InputArg, 32> Ins;
2127 CallLoweringInfo(SelectionDAG &DAG)
2128 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2129 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2130 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2131 DAG(DAG), CS(nullptr) {}
2133 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2138 CallLoweringInfo &setChain(SDValue InChain) {
2143 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2144 SDValue Target, ArgListTy &&ArgsList,
2145 unsigned FixedArgs = -1) {
2150 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2151 Args = std::move(ArgsList);
2155 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2156 SDValue Target, ArgListTy &&ArgsList,
2157 ImmutableCallSite &Call) {
2160 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2161 DoesNotReturn = Call.doesNotReturn();
2162 IsVarArg = FTy->isVarArg();
2163 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2164 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2165 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2169 CallConv = Call.getCallingConv();
2170 NumFixedArgs = FTy->getNumParams();
2171 Args = std::move(ArgsList);
2178 CallLoweringInfo &setInRegister(bool Value = true) {
2183 CallLoweringInfo &setNoReturn(bool Value = true) {
2184 DoesNotReturn = Value;
2188 CallLoweringInfo &setVarArg(bool Value = true) {
2193 CallLoweringInfo &setTailCall(bool Value = true) {
2198 CallLoweringInfo &setDiscardResult(bool Value = true) {
2199 IsReturnValueUsed = !Value;
2203 CallLoweringInfo &setSExtResult(bool Value = true) {
2208 CallLoweringInfo &setZExtResult(bool Value = true) {
2213 ArgListTy &getArgs() {
2218 /// This function lowers an abstract call to a function into an actual call.
2219 /// This returns a pair of operands. The first element is the return value
2220 /// for the function (if RetTy is not VoidTy). The second element is the
2221 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2222 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2224 /// This hook must be implemented to lower calls into the the specified
2225 /// DAG. The outgoing arguments to the call are described by the Outs array,
2226 /// and the values to be returned by the call are described by the Ins
2227 /// array. The implementation should fill in the InVals array with legal-type
2228 /// return values from the call, and return the resulting token chain value.
2230 LowerCall(CallLoweringInfo &/*CLI*/,
2231 SmallVectorImpl<SDValue> &/*InVals*/) const {
2232 llvm_unreachable("Not Implemented");
2235 /// Target-specific cleanup for formal ByVal parameters.
2236 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2238 /// This hook should be implemented to check whether the return values
2239 /// described by the Outs array can fit into the return registers. If false
2240 /// is returned, an sret-demotion is performed.
2241 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2242 MachineFunction &/*MF*/, bool /*isVarArg*/,
2243 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2244 LLVMContext &/*Context*/) const
2246 // Return true by default to get preexisting behavior.
2250 /// This hook must be implemented to lower outgoing return values, described
2251 /// by the Outs array, into the specified DAG. The implementation should
2252 /// return the resulting token chain value.
2254 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2256 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2257 const SmallVectorImpl<SDValue> &/*OutVals*/,
2258 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2259 llvm_unreachable("Not Implemented");
2262 /// Return true if result of the specified node is used by a return node
2263 /// only. It also compute and return the input chain for the tail call.
2265 /// This is used to determine whether it is possible to codegen a libcall as
2266 /// tail call at legalization time.
2267 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2271 /// Return true if the target may be able emit the call instruction as a tail
2272 /// call. This is used by optimization passes to determine if it's profitable
2273 /// to duplicate return instructions to enable tailcall optimization.
2274 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2278 /// Return the builtin name for the __builtin___clear_cache intrinsic
2279 /// Default is to invoke the clear cache library call
2280 virtual const char * getClearCacheBuiltinName() const {
2281 return "__clear_cache";
2284 /// Return the register ID of the name passed in. Used by named register
2285 /// global variables extension. There is no target-independent behaviour
2286 /// so the default action is to bail.
2287 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2288 report_fatal_error("Named registers not implemented for this target");
2291 /// Return the type that should be used to zero or sign extend a
2292 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2293 /// convention requires the return type to be promoted, but this is not true
2294 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2295 /// calling conventions. The frontend should handle this and include all of
2296 /// the necessary information.
2297 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2298 ISD::NodeType /*ExtendKind*/) const {
2299 MVT MinVT = getRegisterType(MVT::i32);
2300 return VT.bitsLT(MinVT) ? MinVT : VT;
2303 /// For some targets, an LLVM struct type must be broken down into multiple
2304 /// simple types, but the calling convention specifies that the entire struct
2305 /// must be passed in a block of consecutive registers.
2307 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2308 bool isVarArg) const {
2312 /// Returns a 0 terminated array of registers that can be safely used as
2313 /// scratch registers.
2314 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2318 /// This callback is used to prepare for a volatile or atomic load.
2319 /// It takes a chain node as input and returns the chain for the load itself.
2321 /// Having a callback like this is necessary for targets like SystemZ,
2322 /// which allows a CPU to reuse the result of a previous load indefinitely,
2323 /// even if a cache-coherent store is performed by another CPU. The default
2324 /// implementation does nothing.
2325 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2326 SelectionDAG &DAG) const {
2330 /// This callback is invoked by the type legalizer to legalize nodes with an
2331 /// illegal operand type but legal result types. It replaces the
2332 /// LowerOperation callback in the type Legalizer. The reason we can not do
2333 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2334 /// use this callback.
2336 /// TODO: Consider merging with ReplaceNodeResults.
2338 /// The target places new result values for the node in Results (their number
2339 /// and types must exactly match those of the original return values of
2340 /// the node), or leaves Results empty, which indicates that the node is not
2341 /// to be custom lowered after all.
2342 /// The default implementation calls LowerOperation.
2343 virtual void LowerOperationWrapper(SDNode *N,
2344 SmallVectorImpl<SDValue> &Results,
2345 SelectionDAG &DAG) const;
2347 /// This callback is invoked for operations that are unsupported by the
2348 /// target, which are registered to use 'custom' lowering, and whose defined
2349 /// values are all legal. If the target has no operations that require custom
2350 /// lowering, it need not implement this. The default implementation of this
2352 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2354 /// This callback is invoked when a node result type is illegal for the
2355 /// target, and the operation was registered to use 'custom' lowering for that
2356 /// result type. The target places new result values for the node in Results
2357 /// (their number and types must exactly match those of the original return
2358 /// values of the node), or leaves Results empty, which indicates that the
2359 /// node is not to be custom lowered after all.
2361 /// If the target has no operations that require custom lowering, it need not
2362 /// implement this. The default implementation aborts.
2363 virtual void ReplaceNodeResults(SDNode * /*N*/,
2364 SmallVectorImpl<SDValue> &/*Results*/,
2365 SelectionDAG &/*DAG*/) const {
2366 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2369 /// This method returns the name of a target specific DAG node.
2370 virtual const char *getTargetNodeName(unsigned Opcode) const;
2372 /// This method returns a target specific FastISel object, or null if the
2373 /// target does not support "fast" ISel.
2374 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2375 const TargetLibraryInfo *) const {
2380 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2381 SelectionDAG &DAG) const;
2383 //===--------------------------------------------------------------------===//
2384 // Inline Asm Support hooks
2387 /// This hook allows the target to expand an inline asm call to be explicit
2388 /// llvm code if it wants to. This is useful for turning simple inline asms
2389 /// into LLVM intrinsics, which gives the compiler more information about the
2390 /// behavior of the code.
2391 virtual bool ExpandInlineAsm(CallInst *) const {
2395 enum ConstraintType {
2396 C_Register, // Constraint represents specific register(s).
2397 C_RegisterClass, // Constraint represents any of register(s) in class.
2398 C_Memory, // Memory constraint.
2399 C_Other, // Something else.
2400 C_Unknown // Unsupported constraint.
2403 enum ConstraintWeight {
2405 CW_Invalid = -1, // No match.
2406 CW_Okay = 0, // Acceptable.
2407 CW_Good = 1, // Good weight.
2408 CW_Better = 2, // Better weight.
2409 CW_Best = 3, // Best weight.
2411 // Well-known weights.
2412 CW_SpecificReg = CW_Okay, // Specific register operands.
2413 CW_Register = CW_Good, // Register operands.
2414 CW_Memory = CW_Better, // Memory operands.
2415 CW_Constant = CW_Best, // Constant operand.
2416 CW_Default = CW_Okay // Default or don't know type.
2419 /// This contains information for each constraint that we are lowering.
2420 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2421 /// This contains the actual string for the code, like "m". TargetLowering
2422 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2423 /// matches the operand.
2424 std::string ConstraintCode;
2426 /// Information about the constraint code, e.g. Register, RegisterClass,
2427 /// Memory, Other, Unknown.
2428 TargetLowering::ConstraintType ConstraintType;
2430 /// If this is the result output operand or a clobber, this is null,
2431 /// otherwise it is the incoming operand to the CallInst. This gets
2432 /// modified as the asm is processed.
2433 Value *CallOperandVal;
2435 /// The ValueType for the operand value.
2438 /// Return true of this is an input operand that is a matching constraint
2440 bool isMatchingInputConstraint() const;
2442 /// If this is an input matching constraint, this method returns the output
2443 /// operand it matches.
2444 unsigned getMatchedOperand() const;
2446 /// Copy constructor for copying from a ConstraintInfo.
2447 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2448 : InlineAsm::ConstraintInfo(info),
2449 ConstraintType(TargetLowering::C_Unknown),
2450 CallOperandVal(nullptr), ConstraintVT(MVT::Other) {
2454 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2456 /// Split up the constraint string from the inline assembly value into the
2457 /// specific constraints and their prefixes, and also tie in the associated
2458 /// operand values. If this returns an empty vector, and if the constraint
2459 /// string itself isn't empty, there was an error parsing.
2460 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2462 /// Examine constraint type and operand type and determine a weight value.
2463 /// The operand object must already have been set up with the operand type.
2464 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2465 AsmOperandInfo &info, int maIndex) const;
2467 /// Examine constraint string and operand type and determine a weight value.
2468 /// The operand object must already have been set up with the operand type.
2469 virtual ConstraintWeight getSingleConstraintMatchWeight(
2470 AsmOperandInfo &info, const char *constraint) const;
2472 /// Determines the constraint code and constraint type to use for the specific
2473 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2474 /// If the actual operand being passed in is available, it can be passed in as
2475 /// Op, otherwise an empty SDValue can be passed.
2476 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2478 SelectionDAG *DAG = nullptr) const;
2480 /// Given a constraint, return the type of constraint it is for this target.
2481 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2483 /// Given a physical register constraint (e.g. {edx}), return the register
2484 /// number and the register class for the register.
2486 /// Given a register class constraint, like 'r', if this corresponds directly
2487 /// to an LLVM register class, return a register of 0 and the register class
2490 /// This should only be used for C_Register constraints. On error, this
2491 /// returns a register number of 0 and a null register class pointer..
2492 virtual std::pair<unsigned, const TargetRegisterClass*>
2493 getRegForInlineAsmConstraint(const std::string &Constraint,
2496 /// Try to replace an X constraint, which matches anything, with another that
2497 /// has more specific requirements based on the type of the corresponding
2498 /// operand. This returns null if there is no replacement to make.
2499 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2501 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2502 /// add anything to Ops.
2503 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2504 std::vector<SDValue> &Ops,
2505 SelectionDAG &DAG) const;
2507 //===--------------------------------------------------------------------===//
2508 // Div utility functions
2510 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2511 SelectionDAG &DAG) const;
2512 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2513 bool IsAfterLegalization,
2514 std::vector<SDNode *> *Created) const;
2515 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2516 bool IsAfterLegalization,
2517 std::vector<SDNode *> *Created) const;
2519 //===--------------------------------------------------------------------===//
2520 // Legalization utility functions
2523 /// Expand a MUL into two nodes. One that computes the high bits of
2524 /// the result and one that computes the low bits.
2525 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2526 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2527 /// if you want to control how low bits are extracted from the LHS.
2528 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2529 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2530 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2531 /// \returns true if the node has been expanded. false if it has not
2532 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2533 SelectionDAG &DAG, SDValue LL = SDValue(),
2534 SDValue LH = SDValue(), SDValue RL = SDValue(),
2535 SDValue RH = SDValue()) const;
2537 //===--------------------------------------------------------------------===//
2538 // Instruction Emitting Hooks
2541 /// This method should be implemented by targets that mark instructions with
2542 /// the 'usesCustomInserter' flag. These instructions are special in various
2543 /// ways, which require special support to insert. The specified MachineInstr
2544 /// is created but not inserted into any basic blocks, and this method is
2545 /// called to expand it into a sequence of instructions, potentially also
2546 /// creating new basic blocks and control flow.
2547 virtual MachineBasicBlock *
2548 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2550 /// This method should be implemented by targets that mark instructions with
2551 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2552 /// instruction selection by target hooks. e.g. To fill in optional defs for
2553 /// ARM 's' setting instructions.
2555 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2558 /// Given an LLVM IR type and return type attributes, compute the return value
2559 /// EVTs and flags, and optionally also the offsets, if the return value is
2560 /// being lowered to memory.
2561 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2562 SmallVectorImpl<ISD::OutputArg> &Outs,
2563 const TargetLowering &TLI);
2565 } // end llvm namespace