1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
57 class TargetRegisterClass;
58 class TargetSubtarget;
59 class TargetLoweringObjectFile;
62 // FIXME: should this be here?
71 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
74 //===----------------------------------------------------------------------===//
75 /// TargetLowering - This class defines information used to lower LLVM code to
76 /// legal SelectionDAG operators that the target instruction selector can accept
79 /// This class also defines callbacks that targets must implement to lower
80 /// target-specific constructs to SelectionDAG operators.
82 class TargetLowering {
83 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
84 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
86 /// LegalizeAction - This enum indicates whether operations are valid for a
87 /// target, and if not, what action should be used to make them valid.
89 Legal, // The target natively supports this operation.
90 Promote, // This operation should be executed in a larger type.
91 Expand, // Try to expand this to other ops, otherwise use a libcall.
92 Custom // Use the LowerOperation hook to implement custom lowering.
95 enum BooleanContent { // How the target represents true/false values.
96 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
97 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
98 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
101 enum SchedPreference {
102 SchedulingForLatency, // Scheduling for shortest total latency.
103 SchedulingForRegPressure // Scheduling for lowest register pressure.
106 /// NOTE: The constructor takes ownership of TLOF.
107 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
108 virtual ~TargetLowering();
110 TargetMachine &getTargetMachine() const { return TM; }
111 const TargetData *getTargetData() const { return TD; }
112 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
114 bool isBigEndian() const { return !IsLittleEndian; }
115 bool isLittleEndian() const { return IsLittleEndian; }
116 MVT getPointerTy() const { return PointerTy; }
117 MVT getShiftAmountTy() const { return ShiftAmountTy; }
119 /// isSelectExpensive - Return true if the select operation is expensive for
121 bool isSelectExpensive() const { return SelectIsExpensive; }
123 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
124 /// a sequence of several shifts, adds, and multiplies for this target.
125 bool isIntDivCheap() const { return IntDivIsCheap; }
127 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
129 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
131 /// getSetCCResultType - Return the ValueType of the result of SETCC
132 /// operations. Also used to obtain the target's preferred type for
133 /// the condition operand of SELECT and BRCOND nodes. In the case of
134 /// BRCOND the argument passed is MVT::Other since there are no other
135 /// operands to get a type hint from.
137 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
139 /// getCmpLibcallReturnType - Return the ValueType for comparison
140 /// libcalls. Comparions libcalls include floating point comparion calls,
141 /// and Ordered/Unordered check calls on floating point numbers.
143 MVT::SimpleValueType getCmpLibcallReturnType() const;
145 /// getBooleanContents - For targets without i1 registers, this gives the
146 /// nature of the high-bits of boolean values held in types wider than i1.
147 /// "Boolean values" are special true/false values produced by nodes like
148 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
149 /// Not to be confused with general values promoted from i1.
150 BooleanContent getBooleanContents() const { return BooleanContents;}
152 /// getSchedulingPreference - Return target scheduling preference.
153 SchedPreference getSchedulingPreference() const {
154 return SchedPreferenceInfo;
157 /// getRegClassFor - Return the register class that should be used for the
158 /// specified value type. This may only be called on legal types.
159 TargetRegisterClass *getRegClassFor(EVT VT) const {
160 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
161 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
162 assert(RC && "This value type is not natively supported!");
166 /// isTypeLegal - Return true if the target has native support for the
167 /// specified value type. This means that it has a register that directly
168 /// holds it without promotions or expansions.
169 bool isTypeLegal(EVT VT) const {
170 assert(!VT.isSimple() ||
171 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
172 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
175 class ValueTypeActionImpl {
176 /// ValueTypeActions - This is a bitvector that contains two bits for each
177 /// value type, where the two bits correspond to the LegalizeAction enum.
178 /// This can be queried with "getTypeAction(VT)".
179 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
180 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
182 ValueTypeActionImpl() {
183 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
185 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
186 if (VT.isExtended()) {
188 return VT.isPow2VectorType() ? Expand : Promote;
191 // First promote to a power-of-two size, then expand if necessary.
192 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
193 assert(0 && "Unsupported extended type!");
196 unsigned I = VT.getSimpleVT().SimpleTy;
197 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
198 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
200 void setTypeAction(EVT VT, LegalizeAction Action) {
201 unsigned I = VT.getSimpleVT().SimpleTy;
202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
203 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
207 const ValueTypeActionImpl &getValueTypeActions() const {
208 return ValueTypeActions;
211 /// getTypeAction - Return how we should legalize values of this type, either
212 /// it is already legal (return 'Legal') or we need to promote it to a larger
213 /// type (return 'Promote'), or we need to expand it into multiple registers
214 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
215 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
216 return ValueTypeActions.getTypeAction(Context, VT);
219 /// getTypeToTransformTo - For types supported by the target, this is an
220 /// identity function. For types that must be promoted to larger types, this
221 /// returns the larger type to promote to. For integer types that are larger
222 /// than the largest integer register, this contains one step in the expansion
223 /// to get to the smaller register. For illegal floating point types, this
224 /// returns the integer type to transform to.
225 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
227 assert((unsigned)VT.getSimpleVT().SimpleTy <
228 array_lengthof(TransformToType));
229 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
230 assert(getTypeAction(Context, NVT) != Promote &&
231 "Promote may not follow Expand or Promote");
236 EVT NVT = VT.getPow2VectorType(Context);
238 // Vector length is a power of 2 - split to half the size.
239 unsigned NumElts = VT.getVectorNumElements();
240 EVT EltVT = VT.getVectorElementType();
241 return (NumElts == 1) ?
242 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
244 // Promote to a power of two size, avoiding multi-step promotion.
245 return getTypeAction(Context, NVT) == Promote ?
246 getTypeToTransformTo(Context, NVT) : NVT;
247 } else if (VT.isInteger()) {
248 EVT NVT = VT.getRoundIntegerType(Context);
250 // Size is a power of two - expand to half the size.
251 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
253 // Promote to a power of two size, avoiding multi-step promotion.
254 return getTypeAction(Context, NVT) == Promote ?
255 getTypeToTransformTo(Context, NVT) : NVT;
257 assert(0 && "Unsupported extended type!");
258 return MVT(MVT::Other); // Not reached
261 /// getTypeToExpandTo - For types supported by the target, this is an
262 /// identity function. For types that must be expanded (i.e. integer types
263 /// that are larger than the largest integer register or illegal floating
264 /// point types), this returns the largest legal type it will be expanded to.
265 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
266 assert(!VT.isVector());
268 switch (getTypeAction(Context, VT)) {
272 VT = getTypeToTransformTo(Context, VT);
275 assert(false && "Type is not legal nor is it to be expanded!");
282 /// getVectorTypeBreakdown - Vector types are broken down into some number of
283 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
284 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
285 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
287 /// This method returns the number of registers needed, and the VT for each
288 /// register. It also returns the VT and quantity of the intermediate values
289 /// before they are promoted/expanded.
291 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
293 unsigned &NumIntermediates,
294 EVT &RegisterVT) const;
296 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
297 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
298 /// this is the case, it returns true and store the intrinsic
299 /// information into the IntrinsicInfo that was passed to the function.
300 struct IntrinsicInfo {
301 unsigned opc; // target opcode
302 EVT memVT; // memory VT
303 const Value* ptrVal; // value representing memory location
304 int offset; // offset off of ptrVal
305 unsigned align; // alignment
306 bool vol; // is volatile?
307 bool readMem; // reads memory?
308 bool writeMem; // writes memory?
311 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
312 const CallInst &I, unsigned Intrinsic) {
316 /// isFPImmLegal - Returns true if the target can instruction select the
317 /// specified FP immediate natively. If false, the legalizer will materialize
318 /// the FP immediate as a load from a constant pool.
319 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
323 /// isShuffleMaskLegal - Targets can use this to indicate that they only
324 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
325 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
326 /// are assumed to be legal.
327 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
332 /// canOpTrap - Returns true if the operation can trap for the value type.
333 /// VT must be a legal type. By default, we optimistically assume most
334 /// operations don't trap except for divide and remainder.
335 virtual bool canOpTrap(unsigned Op, EVT VT) const;
337 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
338 /// used by Targets can use this to indicate if there is a suitable
339 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
341 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
346 /// getOperationAction - Return how this operation should be treated: either
347 /// it is legal, needs to be promoted to a larger size, needs to be
348 /// expanded to some other code sequence, or the target has a custom expander
350 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
351 if (VT.isExtended()) return Expand;
352 assert(Op < array_lengthof(OpActions[0]) &&
353 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
354 "Table isn't big enough!");
355 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
358 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
361 /// isOperationLegalOrCustom - Return true if the specified operation is
362 /// legal on this target or can be made legal with custom lowering. This
363 /// is used to help guide high-level lowering decisions.
364 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
365 return (VT == MVT::Other || isTypeLegal(VT)) &&
366 (getOperationAction(Op, VT) == Legal ||
367 getOperationAction(Op, VT) == Custom);
370 /// isOperationLegal - Return true if the specified operation is legal on this
372 bool isOperationLegal(unsigned Op, EVT VT) const {
373 return (VT == MVT::Other || isTypeLegal(VT)) &&
374 getOperationAction(Op, VT) == Legal;
377 /// getLoadExtAction - Return how this load with extension should be treated:
378 /// either it is legal, needs to be promoted to a larger size, needs to be
379 /// expanded to some other code sequence, or the target has a custom expander
381 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
382 assert(LType < array_lengthof(LoadExtActions) &&
383 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
384 "Table isn't big enough!");
385 return (LegalizeAction)((LoadExtActions[LType] >>
386 (2*VT.getSimpleVT().SimpleTy)) & 3);
389 /// isLoadExtLegal - Return true if the specified load with extension is legal
391 bool isLoadExtLegal(unsigned LType, EVT VT) const {
392 return VT.isSimple() &&
393 (getLoadExtAction(LType, VT) == Legal ||
394 getLoadExtAction(LType, VT) == Custom);
397 /// getTruncStoreAction - Return how this store with truncation should be
398 /// treated: either it is legal, needs to be promoted to a larger size, needs
399 /// to be expanded to some other code sequence, or the target has a custom
401 LegalizeAction getTruncStoreAction(EVT ValVT,
403 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
404 array_lengthof(TruncStoreActions) &&
405 (unsigned)MemVT.getSimpleVT().SimpleTy <
406 sizeof(TruncStoreActions[0])*4 &&
407 "Table isn't big enough!");
408 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
409 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
412 /// isTruncStoreLegal - Return true if the specified store with truncation is
413 /// legal on this target.
414 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
415 return isTypeLegal(ValVT) && MemVT.isSimple() &&
416 (getTruncStoreAction(ValVT, MemVT) == Legal ||
417 getTruncStoreAction(ValVT, MemVT) == Custom);
420 /// getIndexedLoadAction - Return how the indexed load should be treated:
421 /// either it is legal, needs to be promoted to a larger size, needs to be
422 /// expanded to some other code sequence, or the target has a custom expander
425 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
426 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
427 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
428 "Table isn't big enough!");
429 return (LegalizeAction)((IndexedModeActions[
430 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
433 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
435 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
436 return VT.isSimple() &&
437 (getIndexedLoadAction(IdxMode, VT) == Legal ||
438 getIndexedLoadAction(IdxMode, VT) == Custom);
441 /// getIndexedStoreAction - Return how the indexed store should be treated:
442 /// either it is legal, needs to be promoted to a larger size, needs to be
443 /// expanded to some other code sequence, or the target has a custom expander
446 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
447 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
448 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
449 "Table isn't big enough!");
450 return (LegalizeAction)((IndexedModeActions[
451 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
454 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
456 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
457 return VT.isSimple() &&
458 (getIndexedStoreAction(IdxMode, VT) == Legal ||
459 getIndexedStoreAction(IdxMode, VT) == Custom);
462 /// getCondCodeAction - Return how the condition code should be treated:
463 /// either it is legal, needs to be expanded to some other code sequence,
464 /// or the target has a custom expander for it.
466 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
467 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
468 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
469 "Table isn't big enough!");
470 LegalizeAction Action = (LegalizeAction)
471 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
472 assert(Action != Promote && "Can't promote condition code!");
476 /// isCondCodeLegal - Return true if the specified condition code is legal
478 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
479 return getCondCodeAction(CC, VT) == Legal ||
480 getCondCodeAction(CC, VT) == Custom;
484 /// getTypeToPromoteTo - If the action for this operation is to promote, this
485 /// method returns the ValueType to promote to.
486 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
487 assert(getOperationAction(Op, VT) == Promote &&
488 "This operation isn't promoted!");
490 // See if this has an explicit type specified.
491 std::map<std::pair<unsigned, MVT::SimpleValueType>,
492 MVT::SimpleValueType>::const_iterator PTTI =
493 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
494 if (PTTI != PromoteToType.end()) return PTTI->second;
496 assert((VT.isInteger() || VT.isFloatingPoint()) &&
497 "Cannot autopromote this type, add it with AddPromotedToType.");
501 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
502 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
503 "Didn't find type to promote to!");
504 } while (!isTypeLegal(NVT) ||
505 getOperationAction(Op, NVT) == Promote);
509 /// getValueType - Return the EVT corresponding to this LLVM type.
510 /// This is fixed by the LLVM operations except for the pointer size. If
511 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
512 /// counterpart (e.g. structs), otherwise it will assert.
513 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
514 EVT VT = EVT::getEVT(Ty, AllowUnknown);
515 return VT == MVT::iPTR ? PointerTy : VT;
518 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
519 /// function arguments in the caller parameter area. This is the actual
520 /// alignment, not its logarithm.
521 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
523 /// getRegisterType - Return the type of registers that this ValueType will
524 /// eventually require.
525 EVT getRegisterType(MVT VT) const {
526 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
527 return RegisterTypeForVT[VT.SimpleTy];
530 /// getRegisterType - Return the type of registers that this ValueType will
531 /// eventually require.
532 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
534 assert((unsigned)VT.getSimpleVT().SimpleTy <
535 array_lengthof(RegisterTypeForVT));
536 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
540 unsigned NumIntermediates;
541 (void)getVectorTypeBreakdown(Context, VT, VT1,
542 NumIntermediates, RegisterVT);
545 if (VT.isInteger()) {
546 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
548 assert(0 && "Unsupported extended type!");
549 return EVT(MVT::Other); // Not reached
552 /// getNumRegisters - Return the number of registers that this ValueType will
553 /// eventually require. This is one for any types promoted to live in larger
554 /// registers, but may be more than one for types (like i64) that are split
555 /// into pieces. For types like i140, which are first promoted then expanded,
556 /// it is the number of registers needed to hold all the bits of the original
557 /// type. For an i140 on a 32 bit machine this means 5 registers.
558 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
560 assert((unsigned)VT.getSimpleVT().SimpleTy <
561 array_lengthof(NumRegistersForVT));
562 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
566 unsigned NumIntermediates;
567 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
569 if (VT.isInteger()) {
570 unsigned BitWidth = VT.getSizeInBits();
571 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
572 return (BitWidth + RegWidth - 1) / RegWidth;
574 assert(0 && "Unsupported extended type!");
575 return 0; // Not reached
578 /// ShouldShrinkFPConstant - If true, then instruction selection should
579 /// seek to shrink the FP constant of the specified type to a smaller type
580 /// in order to save space and / or reduce runtime.
581 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
583 /// hasTargetDAGCombine - If true, the target has custom DAG combine
584 /// transformations that it can perform for the specified node.
585 bool hasTargetDAGCombine(ISD::NodeType NT) const {
586 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
587 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
590 /// This function returns the maximum number of store operations permitted
591 /// to replace a call to llvm.memset. The value is set by the target at the
592 /// performance threshold for such a replacement.
593 /// @brief Get maximum # of store operations permitted for llvm.memset
594 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
596 /// This function returns the maximum number of store operations permitted
597 /// to replace a call to llvm.memcpy. The value is set by the target at the
598 /// performance threshold for such a replacement.
599 /// @brief Get maximum # of store operations permitted for llvm.memcpy
600 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
602 /// This function returns the maximum number of store operations permitted
603 /// to replace a call to llvm.memmove. The value is set by the target at the
604 /// performance threshold for such a replacement.
605 /// @brief Get maximum # of store operations permitted for llvm.memmove
606 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
608 /// This function returns true if the target allows unaligned memory accesses.
609 /// of the specified type. This is used, for example, in situations where an
610 /// array copy/move/set is converted to a sequence of store operations. It's
611 /// use helps to ensure that such replacements don't generate code that causes
612 /// an alignment error (trap) on the target machine.
613 /// @brief Determine if the target supports unaligned memory accesses.
614 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
618 /// This function returns true if the target would benefit from code placement
620 /// @brief Determine if the target should perform code placement optimization.
621 bool shouldOptimizeCodePlacement() const {
622 return benefitFromCodePlacementOpt;
625 /// getOptimalMemOpType - Returns the target specific optimal type for load
626 /// and store operations as a result of memset, memcpy, and memmove
627 /// lowering. If DstAlign is zero that means it's safe to destination
628 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
629 /// means there isn't a need to check it against alignment requirement,
630 /// probably because the source does not need to be loaded. If
631 /// 'NonScalarIntSafe' is true, that means it's safe to return a
632 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
633 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
634 /// constant so it does not need to be loaded.
635 /// It returns EVT::Other if SelectionDAG should be responsible for
636 /// determining the type.
637 virtual EVT getOptimalMemOpType(uint64_t Size,
638 unsigned DstAlign, unsigned SrcAlign,
639 bool NonScalarIntSafe, bool MemcpyStrSrc,
640 SelectionDAG &DAG) const {
644 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
645 /// to implement llvm.setjmp.
646 bool usesUnderscoreSetJmp() const {
647 return UseUnderscoreSetJmp;
650 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
651 /// to implement llvm.longjmp.
652 bool usesUnderscoreLongJmp() const {
653 return UseUnderscoreLongJmp;
656 /// getStackPointerRegisterToSaveRestore - If a physical register, this
657 /// specifies the register that llvm.savestack/llvm.restorestack should save
659 unsigned getStackPointerRegisterToSaveRestore() const {
660 return StackPointerRegisterToSaveRestore;
663 /// getExceptionAddressRegister - If a physical register, this returns
664 /// the register that receives the exception address on entry to a landing
666 unsigned getExceptionAddressRegister() const {
667 return ExceptionPointerRegister;
670 /// getExceptionSelectorRegister - If a physical register, this returns
671 /// the register that receives the exception typeid on entry to a landing
673 unsigned getExceptionSelectorRegister() const {
674 return ExceptionSelectorRegister;
677 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
678 /// set, the default is 200)
679 unsigned getJumpBufSize() const {
683 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
684 /// (if never set, the default is 0)
685 unsigned getJumpBufAlignment() const {
686 return JumpBufAlignment;
689 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
690 /// limit. Any block whose size is greater should not be predicated.
691 unsigned getIfCvtBlockSizeLimit() const {
692 return IfCvtBlockSizeLimit;
695 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
696 /// block to be considered for duplication. Any block whose size is greater
697 /// should not be duplicated to facilitate its predication.
698 unsigned getIfCvtDupBlockSizeLimit() const {
699 return IfCvtDupBlockSizeLimit;
702 /// getPrefLoopAlignment - return the preferred loop alignment.
704 unsigned getPrefLoopAlignment() const {
705 return PrefLoopAlignment;
708 /// getPreIndexedAddressParts - returns true by value, base pointer and
709 /// offset pointer and addressing mode by reference if the node's address
710 /// can be legally represented as pre-indexed load / store address.
711 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
713 ISD::MemIndexedMode &AM,
714 SelectionDAG &DAG) const {
718 /// getPostIndexedAddressParts - returns true by value, base pointer and
719 /// offset pointer and addressing mode by reference if this node can be
720 /// combined with a load / store to form a post-indexed load / store.
721 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
722 SDValue &Base, SDValue &Offset,
723 ISD::MemIndexedMode &AM,
724 SelectionDAG &DAG) const {
728 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
729 /// current function. The returned value is a member of the
730 /// MachineJumpTableInfo::JTEntryKind enum.
731 virtual unsigned getJumpTableEncoding() const;
733 virtual const MCExpr *
734 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
735 const MachineBasicBlock *MBB, unsigned uid,
736 MCContext &Ctx) const {
737 assert(0 && "Need to implement this hook if target has custom JTIs");
741 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
743 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
744 SelectionDAG &DAG) const;
746 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
747 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
749 virtual const MCExpr *
750 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
751 unsigned JTI, MCContext &Ctx) const;
753 /// isOffsetFoldingLegal - Return true if folding a constant offset
754 /// with the given GlobalAddress is legal. It is frequently not legal in
755 /// PIC relocation models.
756 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
758 /// getFunctionAlignment - Return the Log2 alignment of this function.
759 virtual unsigned getFunctionAlignment(const Function *) const = 0;
761 //===--------------------------------------------------------------------===//
762 // TargetLowering Optimization Methods
765 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
766 /// SDValues for returning information from TargetLowering to its clients
767 /// that want to combine
768 struct TargetLoweringOpt {
774 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) :
775 DAG(InDAG), ShrinkOps(Shrink) {}
777 bool CombineTo(SDValue O, SDValue N) {
783 /// ShrinkDemandedConstant - Check to see if the specified operand of the
784 /// specified instruction is a constant integer. If so, check to see if
785 /// there are any bits set in the constant that are not demanded. If so,
786 /// shrink the constant and return true.
787 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
789 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
790 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
791 /// cast, but it could be generalized for targets with other types of
792 /// implicit widening casts.
793 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
797 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
798 /// DemandedMask bits of the result of Op are ever used downstream. If we can
799 /// use this information to simplify Op, create a new simplified DAG node and
800 /// return true, returning the original and new nodes in Old and New.
801 /// Otherwise, analyze the expression and return a mask of KnownOne and
802 /// KnownZero bits for the expression (used to simplify the caller).
803 /// The KnownZero/One bits may only be accurate for those bits in the
805 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
806 APInt &KnownZero, APInt &KnownOne,
807 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
809 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
810 /// Mask are known to be either zero or one and return them in the
811 /// KnownZero/KnownOne bitsets.
812 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
816 const SelectionDAG &DAG,
817 unsigned Depth = 0) const;
819 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
820 /// targets that want to expose additional information about sign bits to the
822 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
823 unsigned Depth = 0) const;
825 struct DAGCombinerInfo {
826 void *DC; // The DAG Combiner object.
828 bool BeforeLegalizeOps;
829 bool CalledByLegalizer;
833 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
834 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
835 CalledByLegalizer(cl), DAG(dag) {}
837 bool isBeforeLegalize() const { return BeforeLegalize; }
838 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
839 bool isCalledByLegalizer() const { return CalledByLegalizer; }
841 void AddToWorklist(SDNode *N);
842 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
844 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
845 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
847 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
850 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
851 /// and cc. If it is unable to simplify it, return a null SDValue.
852 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
853 ISD::CondCode Cond, bool foldBooleans,
854 DAGCombinerInfo &DCI, DebugLoc dl) const;
856 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
857 /// node is a GlobalAddress + offset.
859 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
861 /// PerformDAGCombine - This method will be invoked for all target nodes and
862 /// for any target-independent nodes that the target has registered with
865 /// The semantics are as follows:
867 /// SDValue.Val == 0 - No change was made
868 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
869 /// otherwise - N should be replaced by the returned Operand.
871 /// In addition, methods provided by DAGCombinerInfo may be used to perform
872 /// more complex transformations.
874 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
876 /// PerformDAGCombinePromotion - This method query the target whether it is
877 /// beneficial for dag combiner to promote the specified node. If true, it
878 /// should return the desired promotion type by reference.
879 virtual bool PerformDAGCombinePromotion(SDValue Op, EVT &PVT) const {
883 //===--------------------------------------------------------------------===//
884 // TargetLowering Configuration Methods - These methods should be invoked by
885 // the derived class constructor to configure this object for the target.
889 /// setShiftAmountType - Describe the type that should be used for shift
890 /// amounts. This type defaults to the pointer type.
891 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
893 /// setBooleanContents - Specify how the target extends the result of a
894 /// boolean value from i1 to a wider type. See getBooleanContents.
895 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
897 /// setSchedulingPreference - Specify the target scheduling preference.
898 void setSchedulingPreference(SchedPreference Pref) {
899 SchedPreferenceInfo = Pref;
902 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
903 /// use _setjmp to implement llvm.setjmp or the non _ version.
904 /// Defaults to false.
905 void setUseUnderscoreSetJmp(bool Val) {
906 UseUnderscoreSetJmp = Val;
909 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
910 /// use _longjmp to implement llvm.longjmp or the non _ version.
911 /// Defaults to false.
912 void setUseUnderscoreLongJmp(bool Val) {
913 UseUnderscoreLongJmp = Val;
916 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
917 /// specifies the register that llvm.savestack/llvm.restorestack should save
919 void setStackPointerRegisterToSaveRestore(unsigned R) {
920 StackPointerRegisterToSaveRestore = R;
923 /// setExceptionPointerRegister - If set to a physical register, this sets
924 /// the register that receives the exception address on entry to a landing
926 void setExceptionPointerRegister(unsigned R) {
927 ExceptionPointerRegister = R;
930 /// setExceptionSelectorRegister - If set to a physical register, this sets
931 /// the register that receives the exception typeid on entry to a landing
933 void setExceptionSelectorRegister(unsigned R) {
934 ExceptionSelectorRegister = R;
937 /// SelectIsExpensive - Tells the code generator not to expand operations
938 /// into sequences that use the select operations if possible.
939 void setSelectIsExpensive() { SelectIsExpensive = true; }
941 /// setIntDivIsCheap - Tells the code generator that integer divide is
942 /// expensive, and if possible, should be replaced by an alternate sequence
943 /// of instructions not containing an integer divide.
944 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
946 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
947 /// srl/add/sra for a signed divide by power of two, and let the target handle
949 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
951 /// addRegisterClass - Add the specified register class as an available
952 /// regclass for the specified value type. This indicates the selector can
953 /// handle values of that class natively.
954 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
955 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
956 AvailableRegClasses.push_back(std::make_pair(VT, RC));
957 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
960 /// computeRegisterProperties - Once all of the register classes are added,
961 /// this allows us to compute derived properties we expose.
962 void computeRegisterProperties();
964 /// setOperationAction - Indicate that the specified operation does not work
965 /// with the specified type and indicate what to do about it.
966 void setOperationAction(unsigned Op, MVT VT,
967 LegalizeAction Action) {
968 unsigned I = (unsigned)VT.SimpleTy;
971 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
972 OpActions[I][Op] |= (uint64_t)Action << (J*2);
975 /// setLoadExtAction - Indicate that the specified load with extension does
976 /// not work with the specified type and indicate what to do about it.
977 void setLoadExtAction(unsigned ExtType, MVT VT,
978 LegalizeAction Action) {
979 assert((unsigned)VT.SimpleTy*2 < 63 &&
980 ExtType < array_lengthof(LoadExtActions) &&
981 "Table isn't big enough!");
982 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
983 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
986 /// setTruncStoreAction - Indicate that the specified truncating store does
987 /// not work with the specified type and indicate what to do about it.
988 void setTruncStoreAction(MVT ValVT, MVT MemVT,
989 LegalizeAction Action) {
990 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
991 (unsigned)MemVT.SimpleTy*2 < 63 &&
992 "Table isn't big enough!");
993 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
994 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
997 /// setIndexedLoadAction - Indicate that the specified indexed load does or
998 /// does not work with the specified type and indicate what to do abort
999 /// it. NOTE: All indexed mode loads are initialized to Expand in
1000 /// TargetLowering.cpp
1001 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1002 LegalizeAction Action) {
1003 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1004 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1005 "Table isn't big enough!");
1006 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1009 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1010 /// does not work with the specified type and indicate what to do about
1011 /// it. NOTE: All indexed mode stores are initialized to Expand in
1012 /// TargetLowering.cpp
1013 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1014 LegalizeAction Action) {
1015 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1016 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1017 "Table isn't big enough!");
1018 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1021 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1022 /// supported on the target and indicate what to do about it.
1023 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1024 LegalizeAction Action) {
1025 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1026 (unsigned)CC < array_lengthof(CondCodeActions) &&
1027 "Table isn't big enough!");
1028 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1029 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1032 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1033 /// promotion code defaults to trying a larger integer/fp until it can find
1034 /// one that works. If that default is insufficient, this method can be used
1035 /// by the target to override the default.
1036 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1037 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1040 /// setTargetDAGCombine - Targets should invoke this method for each target
1041 /// independent node that they want to provide a custom DAG combiner for by
1042 /// implementing the PerformDAGCombine virtual method.
1043 void setTargetDAGCombine(ISD::NodeType NT) {
1044 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1045 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1048 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1049 /// bytes); default is 200
1050 void setJumpBufSize(unsigned Size) {
1054 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1055 /// alignment (in bytes); default is 0
1056 void setJumpBufAlignment(unsigned Align) {
1057 JumpBufAlignment = Align;
1060 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1061 /// limit (in number of instructions); default is 2.
1062 void setIfCvtBlockSizeLimit(unsigned Limit) {
1063 IfCvtBlockSizeLimit = Limit;
1066 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1067 /// of instructions) to be considered for code duplication during
1068 /// if-conversion; default is 2.
1069 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1070 IfCvtDupBlockSizeLimit = Limit;
1073 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1074 /// alignment is zero, it means the target does not care about loop alignment.
1075 void setPrefLoopAlignment(unsigned Align) {
1076 PrefLoopAlignment = Align;
1081 virtual const TargetSubtarget *getSubtarget() {
1082 assert(0 && "Not Implemented");
1083 return NULL; // this is here to silence compiler errors
1086 //===--------------------------------------------------------------------===//
1087 // Lowering methods - These methods must be implemented by targets so that
1088 // the SelectionDAGLowering code knows how to lower these.
1091 /// LowerFormalArguments - This hook must be implemented to lower the
1092 /// incoming (formal) arguments, described by the Ins array, into the
1093 /// specified DAG. The implementation should fill in the InVals array
1094 /// with legal-type argument values, and return the resulting token
1098 LowerFormalArguments(SDValue Chain,
1099 CallingConv::ID CallConv, bool isVarArg,
1100 const SmallVectorImpl<ISD::InputArg> &Ins,
1101 DebugLoc dl, SelectionDAG &DAG,
1102 SmallVectorImpl<SDValue> &InVals) {
1103 assert(0 && "Not Implemented");
1104 return SDValue(); // this is here to silence compiler errors
1107 /// LowerCallTo - This function lowers an abstract call to a function into an
1108 /// actual call. This returns a pair of operands. The first element is the
1109 /// return value for the function (if RetTy is not VoidTy). The second
1110 /// element is the outgoing token chain. It calls LowerCall to do the actual
1112 struct ArgListEntry {
1123 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1124 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1126 typedef std::vector<ArgListEntry> ArgListTy;
1127 std::pair<SDValue, SDValue>
1128 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1129 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1130 CallingConv::ID CallConv, bool isTailCall,
1131 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1132 SelectionDAG &DAG, DebugLoc dl);
1134 /// LowerCall - This hook must be implemented to lower calls into the
1135 /// the specified DAG. The outgoing arguments to the call are described
1136 /// by the Outs array, and the values to be returned by the call are
1137 /// described by the Ins array. The implementation should fill in the
1138 /// InVals array with legal-type return values from the call, and return
1139 /// the resulting token chain value.
1141 LowerCall(SDValue Chain, SDValue Callee,
1142 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1143 const SmallVectorImpl<ISD::OutputArg> &Outs,
1144 const SmallVectorImpl<ISD::InputArg> &Ins,
1145 DebugLoc dl, SelectionDAG &DAG,
1146 SmallVectorImpl<SDValue> &InVals) {
1147 assert(0 && "Not Implemented");
1148 return SDValue(); // this is here to silence compiler errors
1151 /// CanLowerReturn - This hook should be implemented to check whether the
1152 /// return values described by the Outs array can fit into the return
1153 /// registers. If false is returned, an sret-demotion is performed.
1155 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1156 const SmallVectorImpl<EVT> &OutTys,
1157 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1160 // Return true by default to get preexisting behavior.
1163 /// LowerReturn - This hook must be implemented to lower outgoing
1164 /// return values, described by the Outs array, into the specified
1165 /// DAG. The implementation should return the resulting token chain
1169 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1170 const SmallVectorImpl<ISD::OutputArg> &Outs,
1171 DebugLoc dl, SelectionDAG &DAG) {
1172 assert(0 && "Not Implemented");
1173 return SDValue(); // this is here to silence compiler errors
1176 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1177 /// memcpy. This can be used by targets to provide code sequences for cases
1178 /// that don't fit the target's parameters for simple loads/stores and can be
1179 /// more efficient than using a library call. This function can return a null
1180 /// SDValue if the target declines to use custom code and a different
1181 /// lowering strategy should be used.
1183 /// If AlwaysInline is true, the size is constant and the target should not
1184 /// emit any calls and is strongly encouraged to attempt to emit inline code
1185 /// even if it is beyond the usual threshold because this intrinsic is being
1186 /// expanded in a place where calls are not feasible (e.g. within the prologue
1187 /// for another call). If the target chooses to decline an AlwaysInline
1188 /// request here, legalize will resort to using simple loads and stores.
1190 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1192 SDValue Op1, SDValue Op2,
1193 SDValue Op3, unsigned Align, bool isVolatile,
1195 const Value *DstSV, uint64_t DstOff,
1196 const Value *SrcSV, uint64_t SrcOff) {
1200 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1201 /// memmove. This can be used by targets to provide code sequences for cases
1202 /// that don't fit the target's parameters for simple loads/stores and can be
1203 /// more efficient than using a library call. This function can return a null
1204 /// SDValue if the target declines to use custom code and a different
1205 /// lowering strategy should be used.
1207 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1209 SDValue Op1, SDValue Op2,
1210 SDValue Op3, unsigned Align, bool isVolatile,
1211 const Value *DstSV, uint64_t DstOff,
1212 const Value *SrcSV, uint64_t SrcOff) {
1216 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1217 /// memset. This can be used by targets to provide code sequences for cases
1218 /// that don't fit the target's parameters for simple stores and can be more
1219 /// efficient than using a library call. This function can return a null
1220 /// SDValue if the target declines to use custom code and a different
1221 /// lowering strategy should be used.
1223 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1225 SDValue Op1, SDValue Op2,
1226 SDValue Op3, unsigned Align, bool isVolatile,
1227 const Value *DstSV, uint64_t DstOff) {
1231 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1232 /// to legalize nodes with an illegal operand type but legal result types.
1233 /// It replaces the LowerOperation callback in the type Legalizer.
1234 /// The reason we can not do away with LowerOperation entirely is that
1235 /// LegalizeDAG isn't yet ready to use this callback.
1236 /// TODO: Consider merging with ReplaceNodeResults.
1238 /// The target places new result values for the node in Results (their number
1239 /// and types must exactly match those of the original return values of
1240 /// the node), or leaves Results empty, which indicates that the node is not
1241 /// to be custom lowered after all.
1242 /// The default implementation calls LowerOperation.
1243 virtual void LowerOperationWrapper(SDNode *N,
1244 SmallVectorImpl<SDValue> &Results,
1247 /// LowerOperation - This callback is invoked for operations that are
1248 /// unsupported by the target, which are registered to use 'custom' lowering,
1249 /// and whose defined values are all legal.
1250 /// If the target has no operations that require custom lowering, it need not
1251 /// implement this. The default implementation of this aborts.
1252 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1254 /// ReplaceNodeResults - This callback is invoked when a node result type is
1255 /// illegal for the target, and the operation was registered to use 'custom'
1256 /// lowering for that result type. The target places new result values for
1257 /// the node in Results (their number and types must exactly match those of
1258 /// the original return values of the node), or leaves Results empty, which
1259 /// indicates that the node is not to be custom lowered after all.
1261 /// If the target has no operations that require custom lowering, it need not
1262 /// implement this. The default implementation aborts.
1263 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1264 SelectionDAG &DAG) {
1265 assert(0 && "ReplaceNodeResults not implemented for this target!");
1268 /// getTargetNodeName() - This method returns the name of a target specific
1270 virtual const char *getTargetNodeName(unsigned Opcode) const;
1272 /// createFastISel - This method returns a target specific FastISel object,
1273 /// or null if the target does not support "fast" ISel.
1275 createFastISel(MachineFunction &,
1276 DenseMap<const Value *, unsigned> &,
1277 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1278 DenseMap<const AllocaInst *, int> &
1280 , SmallSet<const Instruction *, 8> &CatchInfoLost
1286 //===--------------------------------------------------------------------===//
1287 // Inline Asm Support hooks
1290 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1291 /// call to be explicit llvm code if it wants to. This is useful for
1292 /// turning simple inline asms into LLVM intrinsics, which gives the
1293 /// compiler more information about the behavior of the code.
1294 virtual bool ExpandInlineAsm(CallInst *CI) const {
1298 enum ConstraintType {
1299 C_Register, // Constraint represents specific register(s).
1300 C_RegisterClass, // Constraint represents any of register(s) in class.
1301 C_Memory, // Memory constraint.
1302 C_Other, // Something else.
1303 C_Unknown // Unsupported constraint.
1306 /// AsmOperandInfo - This contains information for each constraint that we are
1308 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1309 /// ConstraintCode - This contains the actual string for the code, like "m".
1310 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1311 /// most closely matches the operand.
1312 std::string ConstraintCode;
1314 /// ConstraintType - Information about the constraint code, e.g. Register,
1315 /// RegisterClass, Memory, Other, Unknown.
1316 TargetLowering::ConstraintType ConstraintType;
1318 /// CallOperandval - If this is the result output operand or a
1319 /// clobber, this is null, otherwise it is the incoming operand to the
1320 /// CallInst. This gets modified as the asm is processed.
1321 Value *CallOperandVal;
1323 /// ConstraintVT - The ValueType for the operand value.
1326 /// isMatchingInputConstraint - Return true of this is an input operand that
1327 /// is a matching constraint like "4".
1328 bool isMatchingInputConstraint() const;
1330 /// getMatchedOperand - If this is an input matching constraint, this method
1331 /// returns the output operand it matches.
1332 unsigned getMatchedOperand() const;
1334 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1335 : InlineAsm::ConstraintInfo(info),
1336 ConstraintType(TargetLowering::C_Unknown),
1337 CallOperandVal(0), ConstraintVT(MVT::Other) {
1341 /// ComputeConstraintToUse - Determines the constraint code and constraint
1342 /// type to use for the specific AsmOperandInfo, setting
1343 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1344 /// being passed in is available, it can be passed in as Op, otherwise an
1345 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1346 /// constraint of the inline asm instruction being processed is 'm'.
1347 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1350 SelectionDAG *DAG = 0) const;
1352 /// getConstraintType - Given a constraint, return the type of constraint it
1353 /// is for this target.
1354 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1356 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1357 /// return a list of registers that can be used to satisfy the constraint.
1358 /// This should only be used for C_RegisterClass constraints.
1359 virtual std::vector<unsigned>
1360 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1363 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1364 /// {edx}), return the register number and the register class for the
1367 /// Given a register class constraint, like 'r', if this corresponds directly
1368 /// to an LLVM register class, return a register of 0 and the register class
1371 /// This should only be used for C_Register constraints. On error,
1372 /// this returns a register number of 0 and a null register class pointer..
1373 virtual std::pair<unsigned, const TargetRegisterClass*>
1374 getRegForInlineAsmConstraint(const std::string &Constraint,
1377 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1378 /// with another that has more specific requirements based on the type of the
1379 /// corresponding operand. This returns null if there is no replacement to
1381 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1383 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1384 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1385 /// it means one of the asm constraint of the inline asm instruction being
1386 /// processed is 'm'.
1387 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1389 std::vector<SDValue> &Ops,
1390 SelectionDAG &DAG) const;
1392 //===--------------------------------------------------------------------===//
1393 // Instruction Emitting Hooks
1396 // EmitInstrWithCustomInserter - This method should be implemented by targets
1397 // that mark instructions with the 'usesCustomInserter' flag. These
1398 // instructions are special in various ways, which require special support to
1399 // insert. The specified MachineInstr is created but not inserted into any
1400 // basic blocks, and this method is called to expand it into a sequence of
1401 // instructions, potentially also creating new basic blocks and control flow.
1402 // When new basic blocks are inserted and the edges from MBB to its successors
1403 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1405 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1406 MachineBasicBlock *MBB,
1407 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1409 //===--------------------------------------------------------------------===//
1410 // Addressing mode description hooks (used by LSR etc).
1413 /// AddrMode - This represents an addressing mode of:
1414 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1415 /// If BaseGV is null, there is no BaseGV.
1416 /// If BaseOffs is zero, there is no base offset.
1417 /// If HasBaseReg is false, there is no base register.
1418 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1422 GlobalValue *BaseGV;
1426 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1429 /// isLegalAddressingMode - Return true if the addressing mode represented by
1430 /// AM is legal for this target, for a load/store of the specified type.
1431 /// The type may be VoidTy, in which case only return true if the addressing
1432 /// mode is legal for a load/store of any legal type.
1433 /// TODO: Handle pre/postinc as well.
1434 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1436 /// isTruncateFree - Return true if it's free to truncate a value of
1437 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1438 /// register EAX to i16 by referencing its sub-register AX.
1439 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1443 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1447 /// isZExtFree - Return true if any actual instruction that defines a
1448 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1449 /// register. This does not necessarily include registers defined in
1450 /// unknown ways, such as incoming arguments, or copies from unknown
1451 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1452 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1453 /// all instructions that define 32-bit values implicit zero-extend the
1454 /// result out to 64 bits.
1455 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1459 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1463 /// isNarrowingProfitable - Return true if it's profitable to narrow
1464 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1465 /// from i32 to i8 but not from i32 to i16.
1466 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1470 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1471 /// icmp immediate, that is the target has icmp instructions which can compare
1472 /// a register against the immediate without having to materialize the
1473 /// immediate into a register.
1474 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1478 //===--------------------------------------------------------------------===//
1479 // Div utility functions
1481 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1482 std::vector<SDNode*>* Created) const;
1483 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1484 std::vector<SDNode*>* Created) const;
1487 //===--------------------------------------------------------------------===//
1488 // Runtime Library hooks
1491 /// setLibcallName - Rename the default libcall routine name for the specified
1493 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1494 LibcallRoutineNames[Call] = Name;
1497 /// getLibcallName - Get the libcall routine name for the specified libcall.
1499 const char *getLibcallName(RTLIB::Libcall Call) const {
1500 return LibcallRoutineNames[Call];
1503 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1504 /// result of the comparison libcall against zero.
1505 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1506 CmpLibcallCCs[Call] = CC;
1509 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1510 /// the comparison libcall against zero.
1511 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1512 return CmpLibcallCCs[Call];
1515 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1516 /// specified libcall.
1517 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1518 LibcallCallingConvs[Call] = CC;
1521 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1522 /// specified libcall.
1523 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1524 return LibcallCallingConvs[Call];
1529 const TargetData *TD;
1530 TargetLoweringObjectFile &TLOF;
1532 /// PointerTy - The type to use for pointers, usually i32 or i64.
1536 /// IsLittleEndian - True if this is a little endian target.
1538 bool IsLittleEndian;
1540 /// SelectIsExpensive - Tells the code generator not to expand operations
1541 /// into sequences that use the select operations if possible.
1542 bool SelectIsExpensive;
1544 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1545 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1546 /// a real cost model is in place. If we ever optimize for size, this will be
1547 /// set to true unconditionally.
1550 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1551 /// srl/add/sra for a signed divide by power of two, and let the target handle
1553 bool Pow2DivIsCheap;
1555 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1556 /// llvm.setjmp. Defaults to false.
1557 bool UseUnderscoreSetJmp;
1559 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1560 /// llvm.longjmp. Defaults to false.
1561 bool UseUnderscoreLongJmp;
1563 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1567 /// BooleanContents - Information about the contents of the high-bits in
1568 /// boolean values held in a type wider than i1. See getBooleanContents.
1569 BooleanContent BooleanContents;
1571 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1572 /// total cycles or lowest register usage.
1573 SchedPreference SchedPreferenceInfo;
1575 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1576 unsigned JumpBufSize;
1578 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1580 unsigned JumpBufAlignment;
1582 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1584 unsigned IfCvtBlockSizeLimit;
1586 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1587 /// duplicated during if-conversion.
1588 unsigned IfCvtDupBlockSizeLimit;
1590 /// PrefLoopAlignment - The perferred loop alignment.
1592 unsigned PrefLoopAlignment;
1594 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1595 /// specifies the register that llvm.savestack/llvm.restorestack should save
1597 unsigned StackPointerRegisterToSaveRestore;
1599 /// ExceptionPointerRegister - If set to a physical register, this specifies
1600 /// the register that receives the exception address on entry to a landing
1602 unsigned ExceptionPointerRegister;
1604 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1605 /// the register that receives the exception typeid on entry to a landing
1607 unsigned ExceptionSelectorRegister;
1609 /// RegClassForVT - This indicates the default register class to use for
1610 /// each ValueType the target supports natively.
1611 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1612 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1613 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1615 /// TransformToType - For any value types we are promoting or expanding, this
1616 /// contains the value type that we are changing to. For Expanded types, this
1617 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1618 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1619 /// by the system, this holds the same type (e.g. i32 -> i32).
1620 EVT TransformToType[MVT::LAST_VALUETYPE];
1622 /// OpActions - For each operation and each value type, keep a LegalizeAction
1623 /// that indicates how instruction selection should deal with the operation.
1624 /// Most operations are Legal (aka, supported natively by the target), but
1625 /// operations that are not should be described. Note that operations on
1626 /// non-legal value types are not described here.
1627 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1628 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1629 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1631 /// LoadExtActions - For each load of load extension type and each value type,
1632 /// keep a LegalizeAction that indicates how instruction selection should deal
1634 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1636 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1637 /// indicates how instruction selection should deal with the store.
1638 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1640 /// IndexedModeActions - For each indexed mode and each value type,
1641 /// keep a pair of LegalizeAction that indicates how instruction
1642 /// selection should deal with the load / store. The first
1643 /// dimension is now the value_type for the reference. The second
1644 /// dimension is the load [0] vs. store[1]. The third dimension
1645 /// represents the various modes for load store.
1646 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1648 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1649 /// LegalizeAction that indicates how instruction selection should
1650 /// deal with the condition code.
1651 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1653 ValueTypeActionImpl ValueTypeActions;
1655 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1657 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1658 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1659 /// which sets a bit in this array.
1661 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1663 /// PromoteToType - For operations that must be promoted to a specific type,
1664 /// this holds the destination type. This map should be sparse, so don't hold
1667 /// Targets add entries to this map with AddPromotedToType(..), clients access
1668 /// this with getTypeToPromoteTo(..).
1669 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1672 /// LibcallRoutineNames - Stores the name each libcall.
1674 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1676 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1677 /// of each of the comparison libcall against zero.
1678 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1680 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1682 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1685 /// When lowering \@llvm.memset this field specifies the maximum number of
1686 /// store operations that may be substituted for the call to memset. Targets
1687 /// must set this value based on the cost threshold for that target. Targets
1688 /// should assume that the memset will be done using as many of the largest
1689 /// store operations first, followed by smaller ones, if necessary, per
1690 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1691 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1692 /// store. This only applies to setting a constant array of a constant size.
1693 /// @brief Specify maximum number of store instructions per memset call.
1694 unsigned maxStoresPerMemset;
1696 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1697 /// store operations that may be substituted for a call to memcpy. Targets
1698 /// must set this value based on the cost threshold for that target. Targets
1699 /// should assume that the memcpy will be done using as many of the largest
1700 /// store operations first, followed by smaller ones, if necessary, per
1701 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1702 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1703 /// and one 1-byte store. This only applies to copying a constant array of
1705 /// @brief Specify maximum bytes of store instructions per memcpy call.
1706 unsigned maxStoresPerMemcpy;
1708 /// When lowering \@llvm.memmove this field specifies the maximum number of
1709 /// store instructions that may be substituted for a call to memmove. Targets
1710 /// must set this value based on the cost threshold for that target. Targets
1711 /// should assume that the memmove will be done using as many of the largest
1712 /// store operations first, followed by smaller ones, if necessary, per
1713 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1714 /// with 8-bit alignment would result in nine 1-byte stores. This only
1715 /// applies to copying a constant array of constant size.
1716 /// @brief Specify maximum bytes of store instructions per memmove call.
1717 unsigned maxStoresPerMemmove;
1719 /// This field specifies whether the target can benefit from code placement
1721 bool benefitFromCodePlacementOpt;
1723 } // end llvm namespace