1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/Support/DebugLoc.h"
34 #include "llvm/Target/TargetMachine.h"
44 class MachineBasicBlock;
45 class MachineFunction;
46 class MachineFrameInfo;
48 class MachineModuleInfo;
55 class TargetRegisterClass;
56 class TargetSubtarget;
57 class TargetLoweringObjectFile;
60 // FIXME: should this be here?
69 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
72 //===----------------------------------------------------------------------===//
73 /// TargetLowering - This class defines information used to lower LLVM code to
74 /// legal SelectionDAG operators that the target instruction selector can accept
77 /// This class also defines callbacks that targets must implement to lower
78 /// target-specific constructs to SelectionDAG operators.
80 class TargetLowering {
81 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
82 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
84 /// LegalizeAction - This enum indicates whether operations are valid for a
85 /// target, and if not, what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 enum BooleanContent { // How the target represents true/false values.
94 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
95 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
96 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
99 enum SchedPreference {
100 SchedulingForLatency, // Scheduling for shortest total latency.
101 SchedulingForRegPressure // Scheduling for lowest register pressure.
104 /// NOTE: The constructor takes ownership of TLOF.
105 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
106 virtual ~TargetLowering();
108 TargetMachine &getTargetMachine() const { return TM; }
109 const TargetData *getTargetData() const { return TD; }
110 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
112 bool isBigEndian() const { return !IsLittleEndian; }
113 bool isLittleEndian() const { return IsLittleEndian; }
114 MVT getPointerTy() const { return PointerTy; }
115 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
119 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
121 /// isSelectExpensive - Return true if the select operation is expensive for
123 bool isSelectExpensive() const { return SelectIsExpensive; }
125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
126 /// a sequence of several shifts, adds, and multiplies for this target.
127 bool isIntDivCheap() const { return IntDivIsCheap; }
129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
131 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
133 /// getSetCCResultType - Return the ValueType of the result of SETCC
134 /// operations. Also used to obtain the target's preferred type for
135 /// the condition operand of SELECT and BRCOND nodes. In the case of
136 /// BRCOND the argument passed is MVT::Other since there are no other
137 /// operands to get a type hint from.
139 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
141 /// getBooleanContents - For targets without i1 registers, this gives the
142 /// nature of the high-bits of boolean values held in types wider than i1.
143 /// "Boolean values" are special true/false values produced by nodes like
144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
145 /// Not to be confused with general values promoted from i1.
146 BooleanContent getBooleanContents() const { return BooleanContents;}
148 /// getSchedulingPreference - Return target scheduling preference.
149 SchedPreference getSchedulingPreference() const {
150 return SchedPreferenceInfo;
153 /// getRegClassFor - Return the register class that should be used for the
154 /// specified value type. This may only be called on legal types.
155 TargetRegisterClass *getRegClassFor(EVT VT) const {
156 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
157 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
158 assert(RC && "This value type is not natively supported!");
162 /// isTypeLegal - Return true if the target has native support for the
163 /// specified value type. This means that it has a register that directly
164 /// holds it without promotions or expansions.
165 bool isTypeLegal(EVT VT) const {
166 assert(!VT.isSimple() ||
167 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
168 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
171 class ValueTypeActionImpl {
172 /// ValueTypeActions - This is a bitvector that contains two bits for each
173 /// value type, where the two bits correspond to the LegalizeAction enum.
174 /// This can be queried with "getTypeAction(VT)".
175 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
176 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
178 ValueTypeActionImpl() {
179 ValueTypeActions[0] = ValueTypeActions[1] = 0;
180 ValueTypeActions[2] = ValueTypeActions[3] = 0;
182 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
183 ValueTypeActions[0] = RHS.ValueTypeActions[0];
184 ValueTypeActions[1] = RHS.ValueTypeActions[1];
185 ValueTypeActions[2] = RHS.ValueTypeActions[2];
186 ValueTypeActions[3] = RHS.ValueTypeActions[3];
189 LegalizeAction getTypeAction(EVT VT) const {
190 if (VT.isExtended()) {
192 return VT.isPow2VectorType() ? Expand : Promote;
195 // First promote to a power-of-two size, then expand if necessary.
196 return VT == VT.getRoundIntegerType() ? Expand : Promote;
197 assert(0 && "Unsupported extended type!");
200 unsigned I = VT.getSimpleVT().SimpleTy;
201 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
202 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
204 void setTypeAction(EVT VT, LegalizeAction Action) {
205 unsigned I = VT.getSimpleVT().SimpleTy;
206 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
207 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
211 const ValueTypeActionImpl &getValueTypeActions() const {
212 return ValueTypeActions;
215 /// getTypeAction - Return how we should legalize values of this type, either
216 /// it is already legal (return 'Legal') or we need to promote it to a larger
217 /// type (return 'Promote'), or we need to expand it into multiple registers
218 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
219 LegalizeAction getTypeAction(EVT VT) const {
220 return ValueTypeActions.getTypeAction(VT);
223 /// getTypeToTransformTo - For types supported by the target, this is an
224 /// identity function. For types that must be promoted to larger types, this
225 /// returns the larger type to promote to. For integer types that are larger
226 /// than the largest integer register, this contains one step in the expansion
227 /// to get to the smaller register. For illegal floating point types, this
228 /// returns the integer type to transform to.
229 EVT getTypeToTransformTo(EVT VT) const {
231 assert((unsigned)VT.getSimpleVT().SimpleTy <
232 array_lengthof(TransformToType));
233 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
234 assert(getTypeAction(NVT) != Promote &&
235 "Promote may not follow Expand or Promote");
240 EVT NVT = VT.getPow2VectorType();
242 // Vector length is a power of 2 - split to half the size.
243 unsigned NumElts = VT.getVectorNumElements();
244 EVT EltVT = VT.getVectorElementType();
245 return (NumElts == 1) ? EltVT : EVT::getVectorVT(EltVT, NumElts / 2);
247 // Promote to a power of two size, avoiding multi-step promotion.
248 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
249 } else if (VT.isInteger()) {
250 EVT NVT = VT.getRoundIntegerType();
252 // Size is a power of two - expand to half the size.
253 return EVT::getIntegerVT(VT.getSizeInBits() / 2);
255 // Promote to a power of two size, avoiding multi-step promotion.
256 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
258 assert(0 && "Unsupported extended type!");
259 return MVT(MVT::Other); // Not reached
262 /// getTypeToExpandTo - For types supported by the target, this is an
263 /// identity function. For types that must be expanded (i.e. integer types
264 /// that are larger than the largest integer register or illegal floating
265 /// point types), this returns the largest legal type it will be expanded to.
266 EVT getTypeToExpandTo(EVT VT) const {
267 assert(!VT.isVector());
269 switch (getTypeAction(VT)) {
273 VT = getTypeToTransformTo(VT);
276 assert(false && "Type is not legal nor is it to be expanded!");
283 /// getVectorTypeBreakdown - Vector types are broken down into some number of
284 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
285 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
286 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
288 /// This method returns the number of registers needed, and the VT for each
289 /// register. It also returns the VT and quantity of the intermediate values
290 /// before they are promoted/expanded.
292 unsigned getVectorTypeBreakdown(EVT VT,
294 unsigned &NumIntermediates,
295 EVT &RegisterVT) const;
297 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
298 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
299 /// this is the case, it returns true and store the intrinsic
300 /// information into the IntrinsicInfo that was passed to the function.
301 typedef struct IntrinsicInfo {
302 unsigned opc; // target opcode
303 EVT memVT; // memory VT
304 const Value* ptrVal; // value representing memory location
305 int offset; // offset off of ptrVal
306 unsigned align; // alignment
307 bool vol; // is volatile?
308 bool readMem; // reads memory?
309 bool writeMem; // writes memory?
312 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
313 CallInst &I, unsigned Intrinsic) {
317 /// getWidenVectorType: given a vector type, returns the type to widen to
318 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
319 /// If there is no vector type that we want to widen to, returns MVT::Other
320 /// When and were to widen is target dependent based on the cost of
321 /// scalarizing vs using the wider vector type.
322 virtual EVT getWidenVectorType(EVT VT) const;
324 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
325 legal_fpimm_iterator legal_fpimm_begin() const {
326 return LegalFPImmediates.begin();
328 legal_fpimm_iterator legal_fpimm_end() const {
329 return LegalFPImmediates.end();
332 /// isShuffleMaskLegal - Targets can use this to indicate that they only
333 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
334 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
335 /// are assumed to be legal.
336 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
341 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
342 /// used by Targets can use this to indicate if there is a suitable
343 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
345 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
350 /// getOperationAction - Return how this operation should be treated: either
351 /// it is legal, needs to be promoted to a larger size, needs to be
352 /// expanded to some other code sequence, or the target has a custom expander
354 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
355 if (VT.isExtended()) return Expand;
356 assert(Op < array_lengthof(OpActions[0]) &&
357 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
358 "Table isn't big enough!");
359 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
362 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
365 /// isOperationLegalOrCustom - Return true if the specified operation is
366 /// legal on this target or can be made legal with custom lowering. This
367 /// is used to help guide high-level lowering decisions.
368 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
369 return (VT == MVT::Other || isTypeLegal(VT)) &&
370 (getOperationAction(Op, VT) == Legal ||
371 getOperationAction(Op, VT) == Custom);
374 /// isOperationLegal - Return true if the specified operation is legal on this
376 bool isOperationLegal(unsigned Op, EVT VT) const {
377 return (VT == MVT::Other || isTypeLegal(VT)) &&
378 getOperationAction(Op, VT) == Legal;
381 /// getLoadExtAction - Return how this load with extension should be treated:
382 /// either it is legal, needs to be promoted to a larger size, needs to be
383 /// expanded to some other code sequence, or the target has a custom expander
385 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
386 assert(LType < array_lengthof(LoadExtActions) &&
387 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
388 "Table isn't big enough!");
389 return (LegalizeAction)((LoadExtActions[LType] >>
390 (2*VT.getSimpleVT().SimpleTy)) & 3);
393 /// isLoadExtLegal - Return true if the specified load with extension is legal
395 bool isLoadExtLegal(unsigned LType, EVT VT) const {
396 return VT.isSimple() &&
397 (getLoadExtAction(LType, VT) == Legal ||
398 getLoadExtAction(LType, VT) == Custom);
401 /// getTruncStoreAction - Return how this store with truncation should be
402 /// treated: either it is legal, needs to be promoted to a larger size, needs
403 /// to be expanded to some other code sequence, or the target has a custom
405 LegalizeAction getTruncStoreAction(EVT ValVT,
407 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
408 array_lengthof(TruncStoreActions) &&
409 (unsigned)MemVT.getSimpleVT().SimpleTy <
410 sizeof(TruncStoreActions[0])*4 &&
411 "Table isn't big enough!");
412 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
413 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
416 /// isTruncStoreLegal - Return true if the specified store with truncation is
417 /// legal on this target.
418 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
419 return isTypeLegal(ValVT) && MemVT.isSimple() &&
420 (getTruncStoreAction(ValVT, MemVT) == Legal ||
421 getTruncStoreAction(ValVT, MemVT) == Custom);
424 /// getIndexedLoadAction - Return how the indexed load should be treated:
425 /// either it is legal, needs to be promoted to a larger size, needs to be
426 /// expanded to some other code sequence, or the target has a custom expander
429 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
430 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
431 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
432 "Table isn't big enough!");
433 return (LegalizeAction)((IndexedModeActions[
434 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
437 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
439 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
440 return VT.isSimple() &&
441 (getIndexedLoadAction(IdxMode, VT) == Legal ||
442 getIndexedLoadAction(IdxMode, VT) == Custom);
445 /// getIndexedStoreAction - Return how the indexed store should be treated:
446 /// either it is legal, needs to be promoted to a larger size, needs to be
447 /// expanded to some other code sequence, or the target has a custom expander
450 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
451 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
452 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
453 "Table isn't big enough!");
454 return (LegalizeAction)((IndexedModeActions[
455 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
458 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
460 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
461 return VT.isSimple() &&
462 (getIndexedStoreAction(IdxMode, VT) == Legal ||
463 getIndexedStoreAction(IdxMode, VT) == Custom);
466 /// getConvertAction - Return how the conversion should be treated:
467 /// either it is legal, needs to be promoted to a larger size, needs to be
468 /// expanded to some other code sequence, or the target has a custom expander
471 getConvertAction(EVT FromVT, EVT ToVT) const {
472 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
473 array_lengthof(ConvertActions) &&
474 (unsigned)ToVT.getSimpleVT().SimpleTy <
475 sizeof(ConvertActions[0])*4 &&
476 "Table isn't big enough!");
477 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
478 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
481 /// isConvertLegal - Return true if the specified conversion is legal
483 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
484 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
485 (getConvertAction(FromVT, ToVT) == Legal ||
486 getConvertAction(FromVT, ToVT) == Custom);
489 /// getCondCodeAction - Return how the condition code should be treated:
490 /// either it is legal, needs to be expanded to some other code sequence,
491 /// or the target has a custom expander for it.
493 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
494 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
495 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
496 "Table isn't big enough!");
497 LegalizeAction Action = (LegalizeAction)
498 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
499 assert(Action != Promote && "Can't promote condition code!");
503 /// isCondCodeLegal - Return true if the specified condition code is legal
505 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
506 return getCondCodeAction(CC, VT) == Legal ||
507 getCondCodeAction(CC, VT) == Custom;
511 /// getTypeToPromoteTo - If the action for this operation is to promote, this
512 /// method returns the ValueType to promote to.
513 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
514 assert(getOperationAction(Op, VT) == Promote &&
515 "This operation isn't promoted!");
517 // See if this has an explicit type specified.
518 std::map<std::pair<unsigned, MVT::SimpleValueType>,
519 MVT::SimpleValueType>::const_iterator PTTI =
520 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
521 if (PTTI != PromoteToType.end()) return PTTI->second;
523 assert((VT.isInteger() || VT.isFloatingPoint()) &&
524 "Cannot autopromote this type, add it with AddPromotedToType.");
528 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
529 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
530 "Didn't find type to promote to!");
531 } while (!isTypeLegal(NVT) ||
532 getOperationAction(Op, NVT) == Promote);
536 /// getValueType - Return the EVT corresponding to this LLVM type.
537 /// This is fixed by the LLVM operations except for the pointer size. If
538 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
539 /// counterpart (e.g. structs), otherwise it will assert.
540 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
541 EVT VT = EVT::getEVT(Ty, AllowUnknown);
542 return VT == MVT:: iPTR ? PointerTy : VT;
545 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
546 /// function arguments in the caller parameter area. This is the actual
547 /// alignment, not its logarithm.
548 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
550 /// getRegisterType - Return the type of registers that this ValueType will
551 /// eventually require.
552 EVT getRegisterType(EVT VT) const {
554 assert((unsigned)VT.getSimpleVT().SimpleTy <
555 array_lengthof(RegisterTypeForVT));
556 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
560 unsigned NumIntermediates;
561 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
564 if (VT.isInteger()) {
565 return getRegisterType(getTypeToTransformTo(VT));
567 assert(0 && "Unsupported extended type!");
568 return EVT(MVT::Other); // Not reached
571 /// getNumRegisters - Return the number of registers that this ValueType will
572 /// eventually require. This is one for any types promoted to live in larger
573 /// registers, but may be more than one for types (like i64) that are split
574 /// into pieces. For types like i140, which are first promoted then expanded,
575 /// it is the number of registers needed to hold all the bits of the original
576 /// type. For an i140 on a 32 bit machine this means 5 registers.
577 unsigned getNumRegisters(EVT VT) const {
579 assert((unsigned)VT.getSimpleVT().SimpleTy <
580 array_lengthof(NumRegistersForVT));
581 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
585 unsigned NumIntermediates;
586 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
588 if (VT.isInteger()) {
589 unsigned BitWidth = VT.getSizeInBits();
590 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
591 return (BitWidth + RegWidth - 1) / RegWidth;
593 assert(0 && "Unsupported extended type!");
594 return 0; // Not reached
597 /// ShouldShrinkFPConstant - If true, then instruction selection should
598 /// seek to shrink the FP constant of the specified type to a smaller type
599 /// in order to save space and / or reduce runtime.
600 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
602 /// hasTargetDAGCombine - If true, the target has custom DAG combine
603 /// transformations that it can perform for the specified node.
604 bool hasTargetDAGCombine(ISD::NodeType NT) const {
605 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
606 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
609 /// This function returns the maximum number of store operations permitted
610 /// to replace a call to llvm.memset. The value is set by the target at the
611 /// performance threshold for such a replacement.
612 /// @brief Get maximum # of store operations permitted for llvm.memset
613 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
615 /// This function returns the maximum number of store operations permitted
616 /// to replace a call to llvm.memcpy. The value is set by the target at the
617 /// performance threshold for such a replacement.
618 /// @brief Get maximum # of store operations permitted for llvm.memcpy
619 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
621 /// This function returns the maximum number of store operations permitted
622 /// to replace a call to llvm.memmove. The value is set by the target at the
623 /// performance threshold for such a replacement.
624 /// @brief Get maximum # of store operations permitted for llvm.memmove
625 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
627 /// This function returns true if the target allows unaligned memory accesses.
628 /// This is used, for example, in situations where an array copy/move/set is
629 /// converted to a sequence of store operations. It's use helps to ensure that
630 /// such replacements don't generate code that causes an alignment error
631 /// (trap) on the target machine.
632 /// @brief Determine if the target supports unaligned memory accesses.
633 bool allowsUnalignedMemoryAccesses() const {
634 return allowUnalignedMemoryAccesses;
637 /// This function returns true if the target would benefit from code placement
639 /// @brief Determine if the target should perform code placement optimization.
640 bool shouldOptimizeCodePlacement() const {
641 return benefitFromCodePlacementOpt;
644 /// getOptimalMemOpType - Returns the target specific optimal type for load
645 /// and store operations as a result of memset, memcpy, and memmove lowering.
646 /// It returns EVT::iAny if SelectionDAG should be responsible for
648 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
649 bool isSrcConst, bool isSrcStr,
650 SelectionDAG &DAG) const {
654 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
655 /// to implement llvm.setjmp.
656 bool usesUnderscoreSetJmp() const {
657 return UseUnderscoreSetJmp;
660 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
661 /// to implement llvm.longjmp.
662 bool usesUnderscoreLongJmp() const {
663 return UseUnderscoreLongJmp;
666 /// getStackPointerRegisterToSaveRestore - If a physical register, this
667 /// specifies the register that llvm.savestack/llvm.restorestack should save
669 unsigned getStackPointerRegisterToSaveRestore() const {
670 return StackPointerRegisterToSaveRestore;
673 /// getExceptionAddressRegister - If a physical register, this returns
674 /// the register that receives the exception address on entry to a landing
676 unsigned getExceptionAddressRegister() const {
677 return ExceptionPointerRegister;
680 /// getExceptionSelectorRegister - If a physical register, this returns
681 /// the register that receives the exception typeid on entry to a landing
683 unsigned getExceptionSelectorRegister() const {
684 return ExceptionSelectorRegister;
687 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
688 /// set, the default is 200)
689 unsigned getJumpBufSize() const {
693 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
694 /// (if never set, the default is 0)
695 unsigned getJumpBufAlignment() const {
696 return JumpBufAlignment;
699 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
700 /// limit. Any block whose size is greater should not be predicated.
701 unsigned getIfCvtBlockSizeLimit() const {
702 return IfCvtBlockSizeLimit;
705 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
706 /// block to be considered for duplication. Any block whose size is greater
707 /// should not be duplicated to facilitate its predication.
708 unsigned getIfCvtDupBlockSizeLimit() const {
709 return IfCvtDupBlockSizeLimit;
712 /// getPrefLoopAlignment - return the preferred loop alignment.
714 unsigned getPrefLoopAlignment() const {
715 return PrefLoopAlignment;
718 /// getPreIndexedAddressParts - returns true by value, base pointer and
719 /// offset pointer and addressing mode by reference if the node's address
720 /// can be legally represented as pre-indexed load / store address.
721 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
723 ISD::MemIndexedMode &AM,
724 SelectionDAG &DAG) const {
728 /// getPostIndexedAddressParts - returns true by value, base pointer and
729 /// offset pointer and addressing mode by reference if this node can be
730 /// combined with a load / store to form a post-indexed load / store.
731 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
732 SDValue &Base, SDValue &Offset,
733 ISD::MemIndexedMode &AM,
734 SelectionDAG &DAG) const {
738 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
740 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
741 SelectionDAG &DAG) const;
743 /// isOffsetFoldingLegal - Return true if folding a constant offset
744 /// with the given GlobalAddress is legal. It is frequently not legal in
745 /// PIC relocation models.
746 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
748 /// getFunctionAlignment - Return the Log2 alignment of this function.
749 virtual unsigned getFunctionAlignment(const Function *) const = 0;
751 //===--------------------------------------------------------------------===//
752 // TargetLowering Optimization Methods
755 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
756 /// SDValues for returning information from TargetLowering to its clients
757 /// that want to combine
758 struct TargetLoweringOpt {
763 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
765 bool CombineTo(SDValue O, SDValue N) {
771 /// ShrinkDemandedConstant - Check to see if the specified operand of the
772 /// specified instruction is a constant integer. If so, check to see if
773 /// there are any bits set in the constant that are not demanded. If so,
774 /// shrink the constant and return true.
775 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
777 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
778 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
779 /// cast, but it could be generalized for targets with other types of
780 /// implicit widening casts.
781 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
785 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
786 /// DemandedMask bits of the result of Op are ever used downstream. If we can
787 /// use this information to simplify Op, create a new simplified DAG node and
788 /// return true, returning the original and new nodes in Old and New.
789 /// Otherwise, analyze the expression and return a mask of KnownOne and
790 /// KnownZero bits for the expression (used to simplify the caller).
791 /// The KnownZero/One bits may only be accurate for those bits in the
793 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
794 APInt &KnownZero, APInt &KnownOne,
795 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
797 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
798 /// Mask are known to be either zero or one and return them in the
799 /// KnownZero/KnownOne bitsets.
800 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
804 const SelectionDAG &DAG,
805 unsigned Depth = 0) const;
807 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
808 /// targets that want to expose additional information about sign bits to the
810 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
811 unsigned Depth = 0) const;
813 struct DAGCombinerInfo {
814 void *DC; // The DAG Combiner object.
816 bool BeforeLegalizeOps;
817 bool CalledByLegalizer;
821 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
822 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
823 CalledByLegalizer(cl), DAG(dag) {}
825 bool isBeforeLegalize() const { return BeforeLegalize; }
826 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
827 bool isCalledByLegalizer() const { return CalledByLegalizer; }
829 void AddToWorklist(SDNode *N);
830 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
832 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
833 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
835 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
838 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
839 /// and cc. If it is unable to simplify it, return a null SDValue.
840 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
841 ISD::CondCode Cond, bool foldBooleans,
842 DAGCombinerInfo &DCI, DebugLoc dl) const;
844 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
845 /// node is a GlobalAddress + offset.
847 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
849 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
850 /// location that is 'Dist' units away from the location that the 'Base' load
852 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes,
853 int Dist, const MachineFrameInfo *MFI) const;
855 /// PerformDAGCombine - This method will be invoked for all target nodes and
856 /// for any target-independent nodes that the target has registered with
859 /// The semantics are as follows:
861 /// SDValue.Val == 0 - No change was made
862 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
863 /// otherwise - N should be replaced by the returned Operand.
865 /// In addition, methods provided by DAGCombinerInfo may be used to perform
866 /// more complex transformations.
868 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
870 //===--------------------------------------------------------------------===//
871 // TargetLowering Configuration Methods - These methods should be invoked by
872 // the derived class constructor to configure this object for the target.
876 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
877 /// GOT for PC-relative code.
878 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
880 /// setShiftAmountType - Describe the type that should be used for shift
881 /// amounts. This type defaults to the pointer type.
882 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
884 /// setBooleanContents - Specify how the target extends the result of a
885 /// boolean value from i1 to a wider type. See getBooleanContents.
886 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
888 /// setSchedulingPreference - Specify the target scheduling preference.
889 void setSchedulingPreference(SchedPreference Pref) {
890 SchedPreferenceInfo = Pref;
893 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
894 /// use _setjmp to implement llvm.setjmp or the non _ version.
895 /// Defaults to false.
896 void setUseUnderscoreSetJmp(bool Val) {
897 UseUnderscoreSetJmp = Val;
900 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
901 /// use _longjmp to implement llvm.longjmp or the non _ version.
902 /// Defaults to false.
903 void setUseUnderscoreLongJmp(bool Val) {
904 UseUnderscoreLongJmp = Val;
907 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
908 /// specifies the register that llvm.savestack/llvm.restorestack should save
910 void setStackPointerRegisterToSaveRestore(unsigned R) {
911 StackPointerRegisterToSaveRestore = R;
914 /// setExceptionPointerRegister - If set to a physical register, this sets
915 /// the register that receives the exception address on entry to a landing
917 void setExceptionPointerRegister(unsigned R) {
918 ExceptionPointerRegister = R;
921 /// setExceptionSelectorRegister - If set to a physical register, this sets
922 /// the register that receives the exception typeid on entry to a landing
924 void setExceptionSelectorRegister(unsigned R) {
925 ExceptionSelectorRegister = R;
928 /// SelectIsExpensive - Tells the code generator not to expand operations
929 /// into sequences that use the select operations if possible.
930 void setSelectIsExpensive() { SelectIsExpensive = true; }
932 /// setIntDivIsCheap - Tells the code generator that integer divide is
933 /// expensive, and if possible, should be replaced by an alternate sequence
934 /// of instructions not containing an integer divide.
935 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
937 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
938 /// srl/add/sra for a signed divide by power of two, and let the target handle
940 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
942 /// addRegisterClass - Add the specified register class as an available
943 /// regclass for the specified value type. This indicates the selector can
944 /// handle values of that class natively.
945 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
946 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
947 AvailableRegClasses.push_back(std::make_pair(VT, RC));
948 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
951 /// computeRegisterProperties - Once all of the register classes are added,
952 /// this allows us to compute derived properties we expose.
953 void computeRegisterProperties();
955 /// setOperationAction - Indicate that the specified operation does not work
956 /// with the specified type and indicate what to do about it.
957 void setOperationAction(unsigned Op, MVT VT,
958 LegalizeAction Action) {
959 unsigned I = (unsigned)VT.SimpleTy;
962 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
963 OpActions[I][Op] |= (uint64_t)Action << (J*2);
966 /// setLoadExtAction - Indicate that the specified load with extension does
967 /// not work with the with specified type and indicate what to do about it.
968 void setLoadExtAction(unsigned ExtType, MVT VT,
969 LegalizeAction Action) {
970 assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
971 ExtType < array_lengthof(LoadExtActions) &&
972 "Table isn't big enough!");
973 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
974 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
977 /// setTruncStoreAction - Indicate that the specified truncating store does
978 /// not work with the with specified type and indicate what to do about it.
979 void setTruncStoreAction(MVT ValVT, MVT MemVT,
980 LegalizeAction Action) {
981 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
982 (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 &&
983 "Table isn't big enough!");
984 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
985 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
988 /// setIndexedLoadAction - Indicate that the specified indexed load does or
989 /// does not work with the with specified type and indicate what to do abort
990 /// it. NOTE: All indexed mode loads are initialized to Expand in
991 /// TargetLowering.cpp
992 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
993 LegalizeAction Action) {
994 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
995 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
996 "Table isn't big enough!");
997 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1000 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1001 /// does not work with the with specified type and indicate what to do about
1002 /// it. NOTE: All indexed mode stores are initialized to Expand in
1003 /// TargetLowering.cpp
1004 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1005 LegalizeAction Action) {
1006 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1007 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1008 "Table isn't big enough!");
1009 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1012 /// setConvertAction - Indicate that the specified conversion does or does
1013 /// not work with the with specified type and indicate what to do about it.
1014 void setConvertAction(MVT FromVT, MVT ToVT,
1015 LegalizeAction Action) {
1016 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1017 (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 &&
1018 "Table isn't big enough!");
1019 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1020 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
1023 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1024 /// supported on the target and indicate what to do about it.
1025 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1026 LegalizeAction Action) {
1027 assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
1028 (unsigned)CC < array_lengthof(CondCodeActions) &&
1029 "Table isn't big enough!");
1030 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1031 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1034 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1035 /// promotion code defaults to trying a larger integer/fp until it can find
1036 /// one that works. If that default is insufficient, this method can be used
1037 /// by the target to override the default.
1038 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1039 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1042 /// addLegalFPImmediate - Indicate that this target can instruction select
1043 /// the specified FP immediate natively.
1044 void addLegalFPImmediate(const APFloat& Imm) {
1045 LegalFPImmediates.push_back(Imm);
1048 /// setTargetDAGCombine - Targets should invoke this method for each target
1049 /// independent node that they want to provide a custom DAG combiner for by
1050 /// implementing the PerformDAGCombine virtual method.
1051 void setTargetDAGCombine(ISD::NodeType NT) {
1052 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1053 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1056 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1057 /// bytes); default is 200
1058 void setJumpBufSize(unsigned Size) {
1062 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1063 /// alignment (in bytes); default is 0
1064 void setJumpBufAlignment(unsigned Align) {
1065 JumpBufAlignment = Align;
1068 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1069 /// limit (in number of instructions); default is 2.
1070 void setIfCvtBlockSizeLimit(unsigned Limit) {
1071 IfCvtBlockSizeLimit = Limit;
1074 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1075 /// of instructions) to be considered for code duplication during
1076 /// if-conversion; default is 2.
1077 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1078 IfCvtDupBlockSizeLimit = Limit;
1081 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1082 /// alignment is zero, it means the target does not care about loop alignment.
1083 void setPrefLoopAlignment(unsigned Align) {
1084 PrefLoopAlignment = Align;
1089 virtual const TargetSubtarget *getSubtarget() {
1090 assert(0 && "Not Implemented");
1091 return NULL; // this is here to silence compiler errors
1094 //===--------------------------------------------------------------------===//
1095 // Lowering methods - These methods must be implemented by targets so that
1096 // the SelectionDAGLowering code knows how to lower these.
1099 /// LowerFormalArguments - This hook must be implemented to lower the
1100 /// incoming (formal) arguments, described by the Ins array, into the
1101 /// specified DAG. The implementation should fill in the InVals array
1102 /// with legal-type argument values, and return the resulting token
1106 LowerFormalArguments(SDValue Chain,
1107 unsigned CallConv, bool isVarArg,
1108 const SmallVectorImpl<ISD::InputArg> &Ins,
1109 DebugLoc dl, SelectionDAG &DAG,
1110 SmallVectorImpl<SDValue> &InVals) {
1111 assert(0 && "Not Implemented");
1112 return SDValue(); // this is here to silence compiler errors
1115 /// LowerCallTo - This function lowers an abstract call to a function into an
1116 /// actual call. This returns a pair of operands. The first element is the
1117 /// return value for the function (if RetTy is not VoidTy). The second
1118 /// element is the outgoing token chain. It calls LowerCall to do the actual
1120 struct ArgListEntry {
1131 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1132 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1134 typedef std::vector<ArgListEntry> ArgListTy;
1135 std::pair<SDValue, SDValue>
1136 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1137 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1138 unsigned CallConv, bool isTailCall, bool isReturnValueUsed,
1139 SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
1141 /// LowerCall - This hook must be implemented to lower calls into the
1142 /// the specified DAG. The outgoing arguments to the call are described
1143 /// by the Outs array, and the values to be returned by the call are
1144 /// described by the Ins array. The implementation should fill in the
1145 /// InVals array with legal-type return values from the call, and return
1146 /// the resulting token chain value.
1148 /// The isTailCall flag here is normative. If it is true, the
1149 /// implementation must emit a tail call. The
1150 /// IsEligibleForTailCallOptimization hook should be used to catch
1151 /// cases that cannot be handled.
1154 LowerCall(SDValue Chain, SDValue Callee,
1155 unsigned CallConv, bool isVarArg, bool isTailCall,
1156 const SmallVectorImpl<ISD::OutputArg> &Outs,
1157 const SmallVectorImpl<ISD::InputArg> &Ins,
1158 DebugLoc dl, SelectionDAG &DAG,
1159 SmallVectorImpl<SDValue> &InVals) {
1160 assert(0 && "Not Implemented");
1161 return SDValue(); // this is here to silence compiler errors
1164 /// LowerReturn - This hook must be implemented to lower outgoing
1165 /// return values, described by the Outs array, into the specified
1166 /// DAG. The implementation should return the resulting token chain
1170 LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg,
1171 const SmallVectorImpl<ISD::OutputArg> &Outs,
1172 DebugLoc dl, SelectionDAG &DAG) {
1173 assert(0 && "Not Implemented");
1174 return SDValue(); // this is here to silence compiler errors
1177 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1178 /// memcpy. This can be used by targets to provide code sequences for cases
1179 /// that don't fit the target's parameters for simple loads/stores and can be
1180 /// more efficient than using a library call. This function can return a null
1181 /// SDValue if the target declines to use custom code and a different
1182 /// lowering strategy should be used.
1184 /// If AlwaysInline is true, the size is constant and the target should not
1185 /// emit any calls and is strongly encouraged to attempt to emit inline code
1186 /// even if it is beyond the usual threshold because this intrinsic is being
1187 /// expanded in a place where calls are not feasible (e.g. within the prologue
1188 /// for another call). If the target chooses to decline an AlwaysInline
1189 /// request here, legalize will resort to using simple loads and stores.
1191 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1193 SDValue Op1, SDValue Op2,
1194 SDValue Op3, unsigned Align,
1196 const Value *DstSV, uint64_t DstOff,
1197 const Value *SrcSV, uint64_t SrcOff) {
1201 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1202 /// memmove. This can be used by targets to provide code sequences for cases
1203 /// that don't fit the target's parameters for simple loads/stores and can be
1204 /// more efficient than using a library call. This function can return a null
1205 /// SDValue if the target declines to use custom code and a different
1206 /// lowering strategy should be used.
1208 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1210 SDValue Op1, SDValue Op2,
1211 SDValue Op3, unsigned Align,
1212 const Value *DstSV, uint64_t DstOff,
1213 const Value *SrcSV, uint64_t SrcOff) {
1217 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1218 /// memset. This can be used by targets to provide code sequences for cases
1219 /// that don't fit the target's parameters for simple stores and can be more
1220 /// efficient than using a library call. This function can return a null
1221 /// SDValue if the target declines to use custom code and a different
1222 /// lowering strategy should be used.
1224 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1226 SDValue Op1, SDValue Op2,
1227 SDValue Op3, unsigned Align,
1228 const Value *DstSV, uint64_t DstOff) {
1232 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1233 /// to legalize nodes with an illegal operand type but legal result types.
1234 /// It replaces the LowerOperation callback in the type Legalizer.
1235 /// The reason we can not do away with LowerOperation entirely is that
1236 /// LegalizeDAG isn't yet ready to use this callback.
1237 /// TODO: Consider merging with ReplaceNodeResults.
1239 /// The target places new result values for the node in Results (their number
1240 /// and types must exactly match those of the original return values of
1241 /// the node), or leaves Results empty, which indicates that the node is not
1242 /// to be custom lowered after all.
1243 /// The default implementation calls LowerOperation.
1244 virtual void LowerOperationWrapper(SDNode *N,
1245 SmallVectorImpl<SDValue> &Results,
1248 /// LowerOperation - This callback is invoked for operations that are
1249 /// unsupported by the target, which are registered to use 'custom' lowering,
1250 /// and whose defined values are all legal.
1251 /// If the target has no operations that require custom lowering, it need not
1252 /// implement this. The default implementation of this aborts.
1253 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1255 /// ReplaceNodeResults - This callback is invoked when a node result type is
1256 /// illegal for the target, and the operation was registered to use 'custom'
1257 /// lowering for that result type. The target places new result values for
1258 /// the node in Results (their number and types must exactly match those of
1259 /// the original return values of the node), or leaves Results empty, which
1260 /// indicates that the node is not to be custom lowered after all.
1262 /// If the target has no operations that require custom lowering, it need not
1263 /// implement this. The default implementation aborts.
1264 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1265 SelectionDAG &DAG) {
1266 assert(0 && "ReplaceNodeResults not implemented for this target!");
1269 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1270 /// tail call optimization. Targets which want to do tail call optimization
1271 /// should override this function.
1273 IsEligibleForTailCallOptimization(SDValue Callee,
1276 const SmallVectorImpl<ISD::InputArg> &Ins,
1277 SelectionDAG& DAG) const {
1278 // Conservative default: no calls are eligible.
1282 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1283 /// it exists. Skip a possible ISD::TokenFactor.
1284 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1285 unsigned TailCallNodeOpCode) {
1286 if (Chain.getOpcode() == TailCallNodeOpCode) {
1288 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1289 if (Chain.getNumOperands() &&
1290 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1291 return Chain.getOperand(0);
1296 /// getTargetNodeName() - This method returns the name of a target specific
1298 virtual const char *getTargetNodeName(unsigned Opcode) const;
1300 /// createFastISel - This method returns a target specific FastISel object,
1301 /// or null if the target does not support "fast" ISel.
1303 createFastISel(MachineFunction &,
1304 MachineModuleInfo *, DwarfWriter *,
1305 DenseMap<const Value *, unsigned> &,
1306 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1307 DenseMap<const AllocaInst *, int> &
1309 , SmallSet<Instruction*, 8> &CatchInfoLost
1315 //===--------------------------------------------------------------------===//
1316 // Inline Asm Support hooks
1319 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1320 /// call to be explicit llvm code if it wants to. This is useful for
1321 /// turning simple inline asms into LLVM intrinsics, which gives the
1322 /// compiler more information about the behavior of the code.
1323 virtual bool ExpandInlineAsm(CallInst *CI) const {
1327 enum ConstraintType {
1328 C_Register, // Constraint represents specific register(s).
1329 C_RegisterClass, // Constraint represents any of register(s) in class.
1330 C_Memory, // Memory constraint.
1331 C_Other, // Something else.
1332 C_Unknown // Unsupported constraint.
1335 /// AsmOperandInfo - This contains information for each constraint that we are
1337 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1338 /// ConstraintCode - This contains the actual string for the code, like "m".
1339 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1340 /// most closely matches the operand.
1341 std::string ConstraintCode;
1343 /// ConstraintType - Information about the constraint code, e.g. Register,
1344 /// RegisterClass, Memory, Other, Unknown.
1345 TargetLowering::ConstraintType ConstraintType;
1347 /// CallOperandval - If this is the result output operand or a
1348 /// clobber, this is null, otherwise it is the incoming operand to the
1349 /// CallInst. This gets modified as the asm is processed.
1350 Value *CallOperandVal;
1352 /// ConstraintVT - The ValueType for the operand value.
1355 /// isMatchingInputConstraint - Return true of this is an input operand that
1356 /// is a matching constraint like "4".
1357 bool isMatchingInputConstraint() const;
1359 /// getMatchedOperand - If this is an input matching constraint, this method
1360 /// returns the output operand it matches.
1361 unsigned getMatchedOperand() const;
1363 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1364 : InlineAsm::ConstraintInfo(info),
1365 ConstraintType(TargetLowering::C_Unknown),
1366 CallOperandVal(0), ConstraintVT(MVT::Other) {
1370 /// ComputeConstraintToUse - Determines the constraint code and constraint
1371 /// type to use for the specific AsmOperandInfo, setting
1372 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1373 /// being passed in is available, it can be passed in as Op, otherwise an
1374 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1375 /// constraint of the inline asm instruction being processed is 'm'.
1376 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1379 SelectionDAG *DAG = 0) const;
1381 /// getConstraintType - Given a constraint, return the type of constraint it
1382 /// is for this target.
1383 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1385 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1386 /// return a list of registers that can be used to satisfy the constraint.
1387 /// This should only be used for C_RegisterClass constraints.
1388 virtual std::vector<unsigned>
1389 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1392 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1393 /// {edx}), return the register number and the register class for the
1396 /// Given a register class constraint, like 'r', if this corresponds directly
1397 /// to an LLVM register class, return a register of 0 and the register class
1400 /// This should only be used for C_Register constraints. On error,
1401 /// this returns a register number of 0 and a null register class pointer..
1402 virtual std::pair<unsigned, const TargetRegisterClass*>
1403 getRegForInlineAsmConstraint(const std::string &Constraint,
1406 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1407 /// with another that has more specific requirements based on the type of the
1408 /// corresponding operand. This returns null if there is no replacement to
1410 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1412 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1413 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1414 /// it means one of the asm constraint of the inline asm instruction being
1415 /// processed is 'm'.
1416 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1418 std::vector<SDValue> &Ops,
1419 SelectionDAG &DAG) const;
1421 //===--------------------------------------------------------------------===//
1425 // EmitInstrWithCustomInserter - This method should be implemented by targets
1426 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1427 // instructions are special in various ways, which require special support to
1428 // insert. The specified MachineInstr is created but not inserted into any
1429 // basic blocks, and the scheduler passes ownership of it to this method.
1430 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1431 MachineBasicBlock *MBB) const;
1433 //===--------------------------------------------------------------------===//
1434 // Addressing mode description hooks (used by LSR etc).
1437 /// AddrMode - This represents an addressing mode of:
1438 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1439 /// If BaseGV is null, there is no BaseGV.
1440 /// If BaseOffs is zero, there is no base offset.
1441 /// If HasBaseReg is false, there is no base register.
1442 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1446 GlobalValue *BaseGV;
1450 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1453 /// isLegalAddressingMode - Return true if the addressing mode represented by
1454 /// AM is legal for this target, for a load/store of the specified type.
1455 /// The type may be VoidTy, in which case only return true if the addressing
1456 /// mode is legal for a load/store of any legal type.
1457 /// TODO: Handle pre/postinc as well.
1458 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1460 /// isTruncateFree - Return true if it's free to truncate a value of
1461 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1462 /// register EAX to i16 by referencing its sub-register AX.
1463 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1467 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1471 /// isZExtFree - Return true if any actual instruction that defines a
1472 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1473 /// register. This does not necessarily include registers defined in
1474 /// unknown ways, such as incoming arguments, or copies from unknown
1475 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1476 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1477 /// all instructions that define 32-bit values implicit zero-extend the
1478 /// result out to 64 bits.
1479 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1483 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1487 /// isNarrowingProfitable - Return true if it's profitable to narrow
1488 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1489 /// from i32 to i8 but not from i32 to i16.
1490 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1494 //===--------------------------------------------------------------------===//
1495 // Div utility functions
1497 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1498 std::vector<SDNode*>* Created) const;
1499 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1500 std::vector<SDNode*>* Created) const;
1503 //===--------------------------------------------------------------------===//
1504 // Runtime Library hooks
1507 /// setLibcallName - Rename the default libcall routine name for the specified
1509 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1510 LibcallRoutineNames[Call] = Name;
1513 /// getLibcallName - Get the libcall routine name for the specified libcall.
1515 const char *getLibcallName(RTLIB::Libcall Call) const {
1516 return LibcallRoutineNames[Call];
1519 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1520 /// result of the comparison libcall against zero.
1521 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1522 CmpLibcallCCs[Call] = CC;
1525 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1526 /// the comparison libcall against zero.
1527 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1528 return CmpLibcallCCs[Call];
1533 const TargetData *TD;
1534 TargetLoweringObjectFile &TLOF;
1536 /// PointerTy - The type to use for pointers, usually i32 or i64.
1540 /// IsLittleEndian - True if this is a little endian target.
1542 bool IsLittleEndian;
1544 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1546 bool UsesGlobalOffsetTable;
1548 /// SelectIsExpensive - Tells the code generator not to expand operations
1549 /// into sequences that use the select operations if possible.
1550 bool SelectIsExpensive;
1552 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1553 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1554 /// a real cost model is in place. If we ever optimize for size, this will be
1555 /// set to true unconditionally.
1558 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1559 /// srl/add/sra for a signed divide by power of two, and let the target handle
1561 bool Pow2DivIsCheap;
1563 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1564 /// llvm.setjmp. Defaults to false.
1565 bool UseUnderscoreSetJmp;
1567 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1568 /// llvm.longjmp. Defaults to false.
1569 bool UseUnderscoreLongJmp;
1571 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1575 /// BooleanContents - Information about the contents of the high-bits in
1576 /// boolean values held in a type wider than i1. See getBooleanContents.
1577 BooleanContent BooleanContents;
1579 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1580 /// total cycles or lowest register usage.
1581 SchedPreference SchedPreferenceInfo;
1583 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1584 unsigned JumpBufSize;
1586 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1588 unsigned JumpBufAlignment;
1590 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1592 unsigned IfCvtBlockSizeLimit;
1594 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1595 /// duplicated during if-conversion.
1596 unsigned IfCvtDupBlockSizeLimit;
1598 /// PrefLoopAlignment - The perferred loop alignment.
1600 unsigned PrefLoopAlignment;
1602 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1603 /// specifies the register that llvm.savestack/llvm.restorestack should save
1605 unsigned StackPointerRegisterToSaveRestore;
1607 /// ExceptionPointerRegister - If set to a physical register, this specifies
1608 /// the register that receives the exception address on entry to a landing
1610 unsigned ExceptionPointerRegister;
1612 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1613 /// the register that receives the exception typeid on entry to a landing
1615 unsigned ExceptionSelectorRegister;
1617 /// RegClassForVT - This indicates the default register class to use for
1618 /// each ValueType the target supports natively.
1619 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1620 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1621 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1623 /// TransformToType - For any value types we are promoting or expanding, this
1624 /// contains the value type that we are changing to. For Expanded types, this
1625 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1626 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1627 /// by the system, this holds the same type (e.g. i32 -> i32).
1628 EVT TransformToType[MVT::LAST_VALUETYPE];
1630 /// OpActions - For each operation and each value type, keep a LegalizeAction
1631 /// that indicates how instruction selection should deal with the operation.
1632 /// Most operations are Legal (aka, supported natively by the target), but
1633 /// operations that are not should be described. Note that operations on
1634 /// non-legal value types are not described here.
1635 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1636 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1637 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1639 /// LoadExtActions - For each load of load extension type and each value type,
1640 /// keep a LegalizeAction that indicates how instruction selection should deal
1642 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1644 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1645 /// indicates how instruction selection should deal with the store.
1646 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1648 /// IndexedModeActions - For each indexed mode and each value type,
1649 /// keep a pair of LegalizeAction that indicates how instruction
1650 /// selection should deal with the load / store. The first
1651 /// dimension is now the value_type for the reference. The second
1652 /// dimension is the load [0] vs. store[1]. The third dimension
1653 /// represents the various modes for load store.
1654 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1656 /// ConvertActions - For each conversion from source type to destination type,
1657 /// keep a LegalizeAction that indicates how instruction selection should
1658 /// deal with the conversion.
1659 /// Currently, this is used only for floating->floating conversions
1660 /// (FP_EXTEND and FP_ROUND).
1661 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1663 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1664 /// LegalizeAction that indicates how instruction selection should
1665 /// deal with the condition code.
1666 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1668 ValueTypeActionImpl ValueTypeActions;
1670 std::vector<APFloat> LegalFPImmediates;
1672 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1674 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1675 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1676 /// which sets a bit in this array.
1678 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1680 /// PromoteToType - For operations that must be promoted to a specific type,
1681 /// this holds the destination type. This map should be sparse, so don't hold
1684 /// Targets add entries to this map with AddPromotedToType(..), clients access
1685 /// this with getTypeToPromoteTo(..).
1686 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1689 /// LibcallRoutineNames - Stores the name each libcall.
1691 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1693 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1694 /// of each of the comparison libcall against zero.
1695 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1698 /// When lowering \@llvm.memset this field specifies the maximum number of
1699 /// store operations that may be substituted for the call to memset. Targets
1700 /// must set this value based on the cost threshold for that target. Targets
1701 /// should assume that the memset will be done using as many of the largest
1702 /// store operations first, followed by smaller ones, if necessary, per
1703 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1704 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1705 /// store. This only applies to setting a constant array of a constant size.
1706 /// @brief Specify maximum number of store instructions per memset call.
1707 unsigned maxStoresPerMemset;
1709 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1710 /// store operations that may be substituted for a call to memcpy. Targets
1711 /// must set this value based on the cost threshold for that target. Targets
1712 /// should assume that the memcpy will be done using as many of the largest
1713 /// store operations first, followed by smaller ones, if necessary, per
1714 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1715 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1716 /// and one 1-byte store. This only applies to copying a constant array of
1718 /// @brief Specify maximum bytes of store instructions per memcpy call.
1719 unsigned maxStoresPerMemcpy;
1721 /// When lowering \@llvm.memmove this field specifies the maximum number of
1722 /// store instructions that may be substituted for a call to memmove. Targets
1723 /// must set this value based on the cost threshold for that target. Targets
1724 /// should assume that the memmove will be done using as many of the largest
1725 /// store operations first, followed by smaller ones, if necessary, per
1726 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1727 /// with 8-bit alignment would result in nine 1-byte stores. This only
1728 /// applies to copying a constant array of constant size.
1729 /// @brief Specify maximum bytes of store instructions per memmove call.
1730 unsigned maxStoresPerMemmove;
1732 /// This field specifies whether the target machine permits unaligned memory
1733 /// accesses. This is used, for example, to determine the size of store
1734 /// operations when copying small arrays and other similar tasks.
1735 /// @brief Indicate whether the target permits unaligned memory accesses.
1736 bool allowUnalignedMemoryAccesses;
1738 /// This field specifies whether the target can benefit from code placement
1740 bool benefitFromCodePlacementOpt;
1742 } // end llvm namespace