1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/Support/DebugLoc.h"
32 #include "llvm/Target/TargetCallingConv.h"
33 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
46 class MachineBasicBlock;
47 class MachineFunction;
48 class MachineFrameInfo;
50 class MachineJumpTableInfo;
56 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLoweringObjectFile;
63 // FIXME: should this be here?
72 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
75 //===----------------------------------------------------------------------===//
76 /// TargetLowering - This class defines information used to lower LLVM code to
77 /// legal SelectionDAG operators that the target instruction selector can accept
80 /// This class also defines callbacks that targets must implement to lower
81 /// target-specific constructs to SelectionDAG operators.
83 class TargetLowering {
84 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
85 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
87 /// LegalizeAction - This enum indicates whether operations are valid for a
88 /// target, and if not, what action should be used to make them valid.
90 Legal, // The target natively supports this operation.
91 Promote, // This operation should be executed in a larger type.
92 Expand, // Try to expand this to other ops, otherwise use a libcall.
93 Custom // Use the LowerOperation hook to implement custom lowering.
96 enum BooleanContent { // How the target represents true/false values.
97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
98 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
102 /// NOTE: The constructor takes ownership of TLOF.
103 explicit TargetLowering(const TargetMachine &TM,
104 const TargetLoweringObjectFile *TLOF);
105 virtual ~TargetLowering();
107 const TargetMachine &getTargetMachine() const { return TM; }
108 const TargetData *getTargetData() const { return TD; }
109 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
111 bool isBigEndian() const { return !IsLittleEndian; }
112 bool isLittleEndian() const { return IsLittleEndian; }
113 MVT getPointerTy() const { return PointerTy; }
114 virtual MVT getShiftAmountTy(EVT LHSTy) const;
116 /// isSelectExpensive - Return true if the select operation is expensive for
118 bool isSelectExpensive() const { return SelectIsExpensive; }
120 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
121 /// a sequence of several shifts, adds, and multiplies for this target.
122 bool isIntDivCheap() const { return IntDivIsCheap; }
124 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
126 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
128 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
129 /// that should be avoided.
130 bool isJumpExpensive() const { return JumpIsExpensive; }
132 /// getSetCCResultType - Return the ValueType of the result of SETCC
133 /// operations. Also used to obtain the target's preferred type for
134 /// the condition operand of SELECT and BRCOND nodes. In the case of
135 /// BRCOND the argument passed is MVT::Other since there are no other
136 /// operands to get a type hint from.
138 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
140 /// getCmpLibcallReturnType - Return the ValueType for comparison
141 /// libcalls. Comparions libcalls include floating point comparion calls,
142 /// and Ordered/Unordered check calls on floating point numbers.
144 MVT::SimpleValueType getCmpLibcallReturnType() const;
146 /// getBooleanContents - For targets without i1 registers, this gives the
147 /// nature of the high-bits of boolean values held in types wider than i1.
148 /// "Boolean values" are special true/false values produced by nodes like
149 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
150 /// Not to be confused with general values promoted from i1.
151 BooleanContent getBooleanContents() const { return BooleanContents;}
153 /// getSchedulingPreference - Return target scheduling preference.
154 Sched::Preference getSchedulingPreference() const {
155 return SchedPreferenceInfo;
158 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
159 /// different scheduling heuristics for different nodes. This function returns
160 /// the preference (or none) for the given node.
161 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
165 /// getRegClassFor - Return the register class that should be used for the
166 /// specified value type.
167 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
168 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
169 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
170 assert(RC && "This value type is not natively supported!");
174 /// getRepRegClassFor - Return the 'representative' register class for the
175 /// specified value type. The 'representative' register class is the largest
176 /// legal super-reg register class for the register class of the value type.
177 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
178 /// while the rep register class is GR64 on x86_64.
179 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
180 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
181 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
185 /// getRepRegClassCostFor - Return the cost of the 'representative' register
186 /// class for the specified value type.
187 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
188 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
189 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
192 /// getRegPressureLimit - Return the register pressure "high water mark" for
193 /// the specific register class. The scheduler is in high register pressure
194 /// mode (for the specific register class) if it goes over the limit.
195 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
196 MachineFunction &MF) const {
200 /// isTypeLegal - Return true if the target has native support for the
201 /// specified value type. This means that it has a register that directly
202 /// holds it without promotions or expansions.
203 bool isTypeLegal(EVT VT) const {
204 assert(!VT.isSimple() ||
205 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
206 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
209 class ValueTypeActionImpl {
210 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
211 /// that indicates how instruction selection should deal with the type.
212 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
214 LegalizeAction getExtendedTypeAction(EVT VT) const {
215 // Handle non-vector integers.
216 if (!VT.isVector()) {
217 assert(VT.isInteger() && "Unsupported extended type!");
218 unsigned BitSize = VT.getSizeInBits();
219 // First promote to a power-of-two size, then expand if necessary.
220 if (BitSize < 8 || !isPowerOf2_32(BitSize))
225 // Vectors with only one element are always scalarized.
226 if (VT.getVectorNumElements() == 1)
229 // Vectors with a number of elements that is not a power of two are always
230 // widened, for example <3 x float> -> <4 x float>.
231 if (!VT.isPow2VectorType())
234 // Vectors with a crazy element type are always expanded, for example
235 // <4 x i2> is expanded into two vectors of type <2 x i2>.
236 if (!VT.getVectorElementType().isSimple())
239 // If this type is smaller than a legal vector type then widen it,
240 // otherwise expand it. E.g. <2 x float> -> <4 x float>.
241 MVT EltType = VT.getVectorElementType().getSimpleVT();
242 unsigned NumElts = VT.getVectorNumElements();
244 // Round up to the next power of 2.
245 NumElts = (unsigned)NextPowerOf2(NumElts);
247 // If there is no simple vector type with this many elements then there
248 // cannot be a larger legal vector type. Note that this assumes that
249 // there are no skipped intermediate vector types in the simple types.
250 MVT LargerVector = MVT::getVectorVT(EltType, NumElts);
251 if (LargerVector == MVT())
254 // If this type is legal then widen the vector.
255 if (getTypeAction(LargerVector) == Legal)
260 ValueTypeActionImpl() {
261 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
264 LegalizeAction getTypeAction(EVT VT) const {
265 if (!VT.isExtended())
266 return getTypeAction(VT.getSimpleVT());
267 return getExtendedTypeAction(VT);
270 LegalizeAction getTypeAction(MVT VT) const {
271 return (LegalizeAction)ValueTypeActions[VT.SimpleTy];
274 void setTypeAction(EVT VT, LegalizeAction Action) {
275 unsigned I = VT.getSimpleVT().SimpleTy;
276 ValueTypeActions[I] = Action;
280 const ValueTypeActionImpl &getValueTypeActions() const {
281 return ValueTypeActions;
284 /// getTypeAction - Return how we should legalize values of this type, either
285 /// it is already legal (return 'Legal') or we need to promote it to a larger
286 /// type (return 'Promote'), or we need to expand it into multiple registers
287 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
288 LegalizeAction getTypeAction(EVT VT) const {
289 return ValueTypeActions.getTypeAction(VT);
291 LegalizeAction getTypeAction(MVT VT) const {
292 return ValueTypeActions.getTypeAction(VT);
295 /// getTypeToTransformTo - For types supported by the target, this is an
296 /// identity function. For types that must be promoted to larger types, this
297 /// returns the larger type to promote to. For integer types that are larger
298 /// than the largest integer register, this contains one step in the expansion
299 /// to get to the smaller register. For illegal floating point types, this
300 /// returns the integer type to transform to.
301 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
303 assert((unsigned)VT.getSimpleVT().SimpleTy <
304 array_lengthof(TransformToType));
305 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
306 assert(getTypeAction(NVT) != Promote &&
307 "Promote may not follow Expand or Promote");
312 EVT NVT = VT.getPow2VectorType(Context);
314 // Vector length is a power of 2 - split to half the size.
315 unsigned NumElts = VT.getVectorNumElements();
316 EVT EltVT = VT.getVectorElementType();
317 return (NumElts == 1) ?
318 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
320 // Promote to a power of two size, avoiding multi-step promotion.
321 return getTypeAction(NVT) == Promote ?
322 getTypeToTransformTo(Context, NVT) : NVT;
323 } else if (VT.isInteger()) {
324 EVT NVT = VT.getRoundIntegerType(Context);
325 if (NVT == VT) // Size is a power of two - expand to half the size.
326 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
328 // Promote to a power of two size, avoiding multi-step promotion.
329 return getTypeAction(NVT) == Promote ?
330 getTypeToTransformTo(Context, NVT) : NVT;
332 assert(0 && "Unsupported extended type!");
333 return MVT(MVT::Other); // Not reached
336 /// getTypeToExpandTo - For types supported by the target, this is an
337 /// identity function. For types that must be expanded (i.e. integer types
338 /// that are larger than the largest integer register or illegal floating
339 /// point types), this returns the largest legal type it will be expanded to.
340 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
341 assert(!VT.isVector());
343 switch (getTypeAction(VT)) {
347 VT = getTypeToTransformTo(Context, VT);
350 assert(false && "Type is not legal nor is it to be expanded!");
357 /// getVectorTypeBreakdown - Vector types are broken down into some number of
358 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
359 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
360 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
362 /// This method returns the number of registers needed, and the VT for each
363 /// register. It also returns the VT and quantity of the intermediate values
364 /// before they are promoted/expanded.
366 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
368 unsigned &NumIntermediates,
369 EVT &RegisterVT) const;
371 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
372 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
373 /// this is the case, it returns true and store the intrinsic
374 /// information into the IntrinsicInfo that was passed to the function.
375 struct IntrinsicInfo {
376 unsigned opc; // target opcode
377 EVT memVT; // memory VT
378 const Value* ptrVal; // value representing memory location
379 int offset; // offset off of ptrVal
380 unsigned align; // alignment
381 bool vol; // is volatile?
382 bool readMem; // reads memory?
383 bool writeMem; // writes memory?
386 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
387 const CallInst &I, unsigned Intrinsic) const {
391 /// isFPImmLegal - Returns true if the target can instruction select the
392 /// specified FP immediate natively. If false, the legalizer will materialize
393 /// the FP immediate as a load from a constant pool.
394 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
398 /// isShuffleMaskLegal - Targets can use this to indicate that they only
399 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
400 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
401 /// are assumed to be legal.
402 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
407 /// canOpTrap - Returns true if the operation can trap for the value type.
408 /// VT must be a legal type. By default, we optimistically assume most
409 /// operations don't trap except for divide and remainder.
410 virtual bool canOpTrap(unsigned Op, EVT VT) const;
412 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
413 /// used by Targets can use this to indicate if there is a suitable
414 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
416 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
421 /// getOperationAction - Return how this operation should be treated: either
422 /// it is legal, needs to be promoted to a larger size, needs to be
423 /// expanded to some other code sequence, or the target has a custom expander
425 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
426 if (VT.isExtended()) return Expand;
427 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
428 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
429 return (LegalizeAction)OpActions[I][Op];
432 /// isOperationLegalOrCustom - Return true if the specified operation is
433 /// legal on this target or can be made legal with custom lowering. This
434 /// is used to help guide high-level lowering decisions.
435 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
436 return (VT == MVT::Other || isTypeLegal(VT)) &&
437 (getOperationAction(Op, VT) == Legal ||
438 getOperationAction(Op, VT) == Custom);
441 /// isOperationLegal - Return true if the specified operation is legal on this
443 bool isOperationLegal(unsigned Op, EVT VT) const {
444 return (VT == MVT::Other || isTypeLegal(VT)) &&
445 getOperationAction(Op, VT) == Legal;
448 /// getLoadExtAction - Return how this load with extension should be treated:
449 /// either it is legal, needs to be promoted to a larger size, needs to be
450 /// expanded to some other code sequence, or the target has a custom expander
452 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
453 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
454 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
455 "Table isn't big enough!");
456 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
459 /// isLoadExtLegal - Return true if the specified load with extension is legal
461 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
462 return VT.isSimple() &&
463 (getLoadExtAction(ExtType, VT) == Legal ||
464 getLoadExtAction(ExtType, VT) == Custom);
467 /// getTruncStoreAction - Return how this store with truncation should be
468 /// treated: either it is legal, needs to be promoted to a larger size, needs
469 /// to be expanded to some other code sequence, or the target has a custom
471 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
472 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
473 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
474 "Table isn't big enough!");
475 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
476 [MemVT.getSimpleVT().SimpleTy];
479 /// isTruncStoreLegal - Return true if the specified store with truncation is
480 /// legal on this target.
481 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
482 return isTypeLegal(ValVT) && MemVT.isSimple() &&
483 (getTruncStoreAction(ValVT, MemVT) == Legal ||
484 getTruncStoreAction(ValVT, MemVT) == Custom);
487 /// getIndexedLoadAction - Return how the indexed load should be treated:
488 /// either it is legal, needs to be promoted to a larger size, needs to be
489 /// expanded to some other code sequence, or the target has a custom expander
492 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
493 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
494 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
495 "Table isn't big enough!");
496 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
497 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
500 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
502 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
503 return VT.isSimple() &&
504 (getIndexedLoadAction(IdxMode, VT) == Legal ||
505 getIndexedLoadAction(IdxMode, VT) == Custom);
508 /// getIndexedStoreAction - Return how the indexed store should be treated:
509 /// either it is legal, needs to be promoted to a larger size, needs to be
510 /// expanded to some other code sequence, or the target has a custom expander
513 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
514 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
515 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
516 "Table isn't big enough!");
517 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
518 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
521 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
523 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
524 return VT.isSimple() &&
525 (getIndexedStoreAction(IdxMode, VT) == Legal ||
526 getIndexedStoreAction(IdxMode, VT) == Custom);
529 /// getCondCodeAction - Return how the condition code should be treated:
530 /// either it is legal, needs to be expanded to some other code sequence,
531 /// or the target has a custom expander for it.
533 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
534 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
535 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
536 "Table isn't big enough!");
537 LegalizeAction Action = (LegalizeAction)
538 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
539 assert(Action != Promote && "Can't promote condition code!");
543 /// isCondCodeLegal - Return true if the specified condition code is legal
545 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
546 return getCondCodeAction(CC, VT) == Legal ||
547 getCondCodeAction(CC, VT) == Custom;
551 /// getTypeToPromoteTo - If the action for this operation is to promote, this
552 /// method returns the ValueType to promote to.
553 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
554 assert(getOperationAction(Op, VT) == Promote &&
555 "This operation isn't promoted!");
557 // See if this has an explicit type specified.
558 std::map<std::pair<unsigned, MVT::SimpleValueType>,
559 MVT::SimpleValueType>::const_iterator PTTI =
560 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
561 if (PTTI != PromoteToType.end()) return PTTI->second;
563 assert((VT.isInteger() || VT.isFloatingPoint()) &&
564 "Cannot autopromote this type, add it with AddPromotedToType.");
568 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
569 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
570 "Didn't find type to promote to!");
571 } while (!isTypeLegal(NVT) ||
572 getOperationAction(Op, NVT) == Promote);
576 /// getValueType - Return the EVT corresponding to this LLVM type.
577 /// This is fixed by the LLVM operations except for the pointer size. If
578 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
579 /// counterpart (e.g. structs), otherwise it will assert.
580 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
581 EVT VT = EVT::getEVT(Ty, AllowUnknown);
582 return VT == MVT::iPTR ? PointerTy : VT;
585 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
586 /// function arguments in the caller parameter area. This is the actual
587 /// alignment, not its logarithm.
588 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
590 /// getRegisterType - Return the type of registers that this ValueType will
591 /// eventually require.
592 EVT getRegisterType(MVT VT) const {
593 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
594 return RegisterTypeForVT[VT.SimpleTy];
597 /// getRegisterType - Return the type of registers that this ValueType will
598 /// eventually require.
599 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
601 assert((unsigned)VT.getSimpleVT().SimpleTy <
602 array_lengthof(RegisterTypeForVT));
603 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
607 unsigned NumIntermediates;
608 (void)getVectorTypeBreakdown(Context, VT, VT1,
609 NumIntermediates, RegisterVT);
612 if (VT.isInteger()) {
613 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
615 assert(0 && "Unsupported extended type!");
616 return EVT(MVT::Other); // Not reached
619 /// getNumRegisters - Return the number of registers that this ValueType will
620 /// eventually require. This is one for any types promoted to live in larger
621 /// registers, but may be more than one for types (like i64) that are split
622 /// into pieces. For types like i140, which are first promoted then expanded,
623 /// it is the number of registers needed to hold all the bits of the original
624 /// type. For an i140 on a 32 bit machine this means 5 registers.
625 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
627 assert((unsigned)VT.getSimpleVT().SimpleTy <
628 array_lengthof(NumRegistersForVT));
629 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
633 unsigned NumIntermediates;
634 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
636 if (VT.isInteger()) {
637 unsigned BitWidth = VT.getSizeInBits();
638 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
639 return (BitWidth + RegWidth - 1) / RegWidth;
641 assert(0 && "Unsupported extended type!");
642 return 0; // Not reached
645 /// ShouldShrinkFPConstant - If true, then instruction selection should
646 /// seek to shrink the FP constant of the specified type to a smaller type
647 /// in order to save space and / or reduce runtime.
648 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
650 /// hasTargetDAGCombine - If true, the target has custom DAG combine
651 /// transformations that it can perform for the specified node.
652 bool hasTargetDAGCombine(ISD::NodeType NT) const {
653 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
654 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
657 /// This function returns the maximum number of store operations permitted
658 /// to replace a call to llvm.memset. The value is set by the target at the
659 /// performance threshold for such a replacement. If OptSize is true,
660 /// return the limit for functions that have OptSize attribute.
661 /// @brief Get maximum # of store operations permitted for llvm.memset
662 unsigned getMaxStoresPerMemset(bool OptSize) const {
663 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset;
666 /// This function returns the maximum number of store operations permitted
667 /// to replace a call to llvm.memcpy. The value is set by the target at the
668 /// performance threshold for such a replacement. If OptSize is true,
669 /// return the limit for functions that have OptSize attribute.
670 /// @brief Get maximum # of store operations permitted for llvm.memcpy
671 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
672 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy;
675 /// This function returns the maximum number of store operations permitted
676 /// to replace a call to llvm.memmove. The value is set by the target at the
677 /// performance threshold for such a replacement. If OptSize is true,
678 /// return the limit for functions that have OptSize attribute.
679 /// @brief Get maximum # of store operations permitted for llvm.memmove
680 unsigned getMaxStoresPerMemmove(bool OptSize) const {
681 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove;
684 /// This function returns true if the target allows unaligned memory accesses.
685 /// of the specified type. This is used, for example, in situations where an
686 /// array copy/move/set is converted to a sequence of store operations. It's
687 /// use helps to ensure that such replacements don't generate code that causes
688 /// an alignment error (trap) on the target machine.
689 /// @brief Determine if the target supports unaligned memory accesses.
690 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
694 /// This function returns true if the target would benefit from code placement
696 /// @brief Determine if the target should perform code placement optimization.
697 bool shouldOptimizeCodePlacement() const {
698 return benefitFromCodePlacementOpt;
701 /// getOptimalMemOpType - Returns the target specific optimal type for load
702 /// and store operations as a result of memset, memcpy, and memmove
703 /// lowering. If DstAlign is zero that means it's safe to destination
704 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
705 /// means there isn't a need to check it against alignment requirement,
706 /// probably because the source does not need to be loaded. If
707 /// 'NonScalarIntSafe' is true, that means it's safe to return a
708 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
709 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
710 /// constant so it does not need to be loaded.
711 /// It returns EVT::Other if the type should be determined using generic
712 /// target-independent logic.
713 virtual EVT getOptimalMemOpType(uint64_t Size,
714 unsigned DstAlign, unsigned SrcAlign,
715 bool NonScalarIntSafe, bool MemcpyStrSrc,
716 MachineFunction &MF) const {
720 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
721 /// to implement llvm.setjmp.
722 bool usesUnderscoreSetJmp() const {
723 return UseUnderscoreSetJmp;
726 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
727 /// to implement llvm.longjmp.
728 bool usesUnderscoreLongJmp() const {
729 return UseUnderscoreLongJmp;
732 /// getStackPointerRegisterToSaveRestore - If a physical register, this
733 /// specifies the register that llvm.savestack/llvm.restorestack should save
735 unsigned getStackPointerRegisterToSaveRestore() const {
736 return StackPointerRegisterToSaveRestore;
739 /// getExceptionAddressRegister - If a physical register, this returns
740 /// the register that receives the exception address on entry to a landing
742 unsigned getExceptionAddressRegister() const {
743 return ExceptionPointerRegister;
746 /// getExceptionSelectorRegister - If a physical register, this returns
747 /// the register that receives the exception typeid on entry to a landing
749 unsigned getExceptionSelectorRegister() const {
750 return ExceptionSelectorRegister;
753 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
754 /// set, the default is 200)
755 unsigned getJumpBufSize() const {
759 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
760 /// (if never set, the default is 0)
761 unsigned getJumpBufAlignment() const {
762 return JumpBufAlignment;
765 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
767 unsigned getMinStackArgumentAlignment() const {
768 return MinStackArgumentAlignment;
771 /// getPrefLoopAlignment - return the preferred loop alignment.
773 unsigned getPrefLoopAlignment() const {
774 return PrefLoopAlignment;
777 /// getShouldFoldAtomicFences - return whether the combiner should fold
778 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
780 bool getShouldFoldAtomicFences() const {
781 return ShouldFoldAtomicFences;
784 /// getPreIndexedAddressParts - returns true by value, base pointer and
785 /// offset pointer and addressing mode by reference if the node's address
786 /// can be legally represented as pre-indexed load / store address.
787 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
789 ISD::MemIndexedMode &AM,
790 SelectionDAG &DAG) const {
794 /// getPostIndexedAddressParts - returns true by value, base pointer and
795 /// offset pointer and addressing mode by reference if this node can be
796 /// combined with a load / store to form a post-indexed load / store.
797 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
798 SDValue &Base, SDValue &Offset,
799 ISD::MemIndexedMode &AM,
800 SelectionDAG &DAG) const {
804 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
805 /// current function. The returned value is a member of the
806 /// MachineJumpTableInfo::JTEntryKind enum.
807 virtual unsigned getJumpTableEncoding() const;
809 virtual const MCExpr *
810 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
811 const MachineBasicBlock *MBB, unsigned uid,
812 MCContext &Ctx) const {
813 assert(0 && "Need to implement this hook if target has custom JTIs");
817 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
819 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
820 SelectionDAG &DAG) const;
822 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
823 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
825 virtual const MCExpr *
826 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
827 unsigned JTI, MCContext &Ctx) const;
829 /// isOffsetFoldingLegal - Return true if folding a constant offset
830 /// with the given GlobalAddress is legal. It is frequently not legal in
831 /// PIC relocation models.
832 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
834 /// getFunctionAlignment - Return the Log2 alignment of this function.
835 virtual unsigned getFunctionAlignment(const Function *) const = 0;
837 /// getStackCookieLocation - Return true if the target stores stack
838 /// protector cookies at a fixed offset in some non-standard address
839 /// space, and populates the address space and offset as
841 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
845 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
846 /// used for loads / stores from the global.
847 virtual unsigned getMaximalGlobalOffset() const {
851 //===--------------------------------------------------------------------===//
852 // TargetLowering Optimization Methods
855 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
856 /// SDValues for returning information from TargetLowering to its clients
857 /// that want to combine
858 struct TargetLoweringOpt {
865 explicit TargetLoweringOpt(SelectionDAG &InDAG,
867 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
869 bool LegalTypes() const { return LegalTys; }
870 bool LegalOperations() const { return LegalOps; }
872 bool CombineTo(SDValue O, SDValue N) {
878 /// ShrinkDemandedConstant - Check to see if the specified operand of the
879 /// specified instruction is a constant integer. If so, check to see if
880 /// there are any bits set in the constant that are not demanded. If so,
881 /// shrink the constant and return true.
882 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
884 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
885 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
886 /// cast, but it could be generalized for targets with other types of
887 /// implicit widening casts.
888 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
892 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
893 /// DemandedMask bits of the result of Op are ever used downstream. If we can
894 /// use this information to simplify Op, create a new simplified DAG node and
895 /// return true, returning the original and new nodes in Old and New.
896 /// Otherwise, analyze the expression and return a mask of KnownOne and
897 /// KnownZero bits for the expression (used to simplify the caller).
898 /// The KnownZero/One bits may only be accurate for those bits in the
900 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
901 APInt &KnownZero, APInt &KnownOne,
902 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
904 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
905 /// Mask are known to be either zero or one and return them in the
906 /// KnownZero/KnownOne bitsets.
907 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
911 const SelectionDAG &DAG,
912 unsigned Depth = 0) const;
914 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
915 /// targets that want to expose additional information about sign bits to the
917 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
918 unsigned Depth = 0) const;
920 struct DAGCombinerInfo {
921 void *DC; // The DAG Combiner object.
923 bool BeforeLegalizeOps;
924 bool CalledByLegalizer;
928 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
929 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
930 CalledByLegalizer(cl), DAG(dag) {}
932 bool isBeforeLegalize() const { return BeforeLegalize; }
933 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
934 bool isCalledByLegalizer() const { return CalledByLegalizer; }
936 void AddToWorklist(SDNode *N);
937 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
939 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
940 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
942 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
945 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
946 /// and cc. If it is unable to simplify it, return a null SDValue.
947 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
948 ISD::CondCode Cond, bool foldBooleans,
949 DAGCombinerInfo &DCI, DebugLoc dl) const;
951 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
952 /// node is a GlobalAddress + offset.
954 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
956 /// PerformDAGCombine - This method will be invoked for all target nodes and
957 /// for any target-independent nodes that the target has registered with
960 /// The semantics are as follows:
962 /// SDValue.Val == 0 - No change was made
963 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
964 /// otherwise - N should be replaced by the returned Operand.
966 /// In addition, methods provided by DAGCombinerInfo may be used to perform
967 /// more complex transformations.
969 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
971 /// isTypeDesirableForOp - Return true if the target has native support for
972 /// the specified value type and it is 'desirable' to use the type for the
973 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
974 /// instruction encodings are longer and some i16 instructions are slow.
975 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
976 // By default, assume all legal types are desirable.
977 return isTypeLegal(VT);
980 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
981 /// to transform a floating point op of specified opcode to a equivalent op of
982 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
983 virtual bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const {
987 /// IsDesirableToPromoteOp - This method query the target whether it is
988 /// beneficial for dag combiner to promote the specified node. If true, it
989 /// should return the desired promotion type by reference.
990 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
994 //===--------------------------------------------------------------------===//
995 // TargetLowering Configuration Methods - These methods should be invoked by
996 // the derived class constructor to configure this object for the target.
1000 /// setBooleanContents - Specify how the target extends the result of a
1001 /// boolean value from i1 to a wider type. See getBooleanContents.
1002 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
1004 /// setSchedulingPreference - Specify the target scheduling preference.
1005 void setSchedulingPreference(Sched::Preference Pref) {
1006 SchedPreferenceInfo = Pref;
1009 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
1010 /// use _setjmp to implement llvm.setjmp or the non _ version.
1011 /// Defaults to false.
1012 void setUseUnderscoreSetJmp(bool Val) {
1013 UseUnderscoreSetJmp = Val;
1016 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
1017 /// use _longjmp to implement llvm.longjmp or the non _ version.
1018 /// Defaults to false.
1019 void setUseUnderscoreLongJmp(bool Val) {
1020 UseUnderscoreLongJmp = Val;
1023 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
1024 /// specifies the register that llvm.savestack/llvm.restorestack should save
1026 void setStackPointerRegisterToSaveRestore(unsigned R) {
1027 StackPointerRegisterToSaveRestore = R;
1030 /// setExceptionPointerRegister - If set to a physical register, this sets
1031 /// the register that receives the exception address on entry to a landing
1033 void setExceptionPointerRegister(unsigned R) {
1034 ExceptionPointerRegister = R;
1037 /// setExceptionSelectorRegister - If set to a physical register, this sets
1038 /// the register that receives the exception typeid on entry to a landing
1040 void setExceptionSelectorRegister(unsigned R) {
1041 ExceptionSelectorRegister = R;
1044 /// SelectIsExpensive - Tells the code generator not to expand operations
1045 /// into sequences that use the select operations if possible.
1046 void setSelectIsExpensive(bool isExpensive = true) {
1047 SelectIsExpensive = isExpensive;
1050 /// JumpIsExpensive - Tells the code generator not to expand sequence of
1051 /// operations into a seperate sequences that increases the amount of
1053 void setJumpIsExpensive(bool isExpensive = true) {
1054 JumpIsExpensive = isExpensive;
1057 /// setIntDivIsCheap - Tells the code generator that integer divide is
1058 /// expensive, and if possible, should be replaced by an alternate sequence
1059 /// of instructions not containing an integer divide.
1060 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1062 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1063 /// srl/add/sra for a signed divide by power of two, and let the target handle
1065 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1067 /// addRegisterClass - Add the specified register class as an available
1068 /// regclass for the specified value type. This indicates the selector can
1069 /// handle values of that class natively.
1070 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
1071 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1072 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1073 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1076 /// findRepresentativeClass - Return the largest legal super-reg register class
1077 /// of the register class for the specified type and its associated "cost".
1078 virtual std::pair<const TargetRegisterClass*, uint8_t>
1079 findRepresentativeClass(EVT VT) const;
1081 /// computeRegisterProperties - Once all of the register classes are added,
1082 /// this allows us to compute derived properties we expose.
1083 void computeRegisterProperties();
1085 /// setOperationAction - Indicate that the specified operation does not work
1086 /// with the specified type and indicate what to do about it.
1087 void setOperationAction(unsigned Op, MVT VT,
1088 LegalizeAction Action) {
1089 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1090 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1093 /// setLoadExtAction - Indicate that the specified load with extension does
1094 /// not work with the specified type and indicate what to do about it.
1095 void setLoadExtAction(unsigned ExtType, MVT VT,
1096 LegalizeAction Action) {
1097 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1098 "Table isn't big enough!");
1099 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1102 /// setTruncStoreAction - Indicate that the specified truncating store does
1103 /// not work with the specified type and indicate what to do about it.
1104 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1105 LegalizeAction Action) {
1106 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1107 "Table isn't big enough!");
1108 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1111 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1112 /// does not work with the specified type and indicate what to do abort
1113 /// it. NOTE: All indexed mode loads are initialized to Expand in
1114 /// TargetLowering.cpp
1115 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1116 LegalizeAction Action) {
1117 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1118 (unsigned)Action < 0xf && "Table isn't big enough!");
1119 // Load action are kept in the upper half.
1120 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1121 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1124 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1125 /// does not work with the specified type and indicate what to do about
1126 /// it. NOTE: All indexed mode stores are initialized to Expand in
1127 /// TargetLowering.cpp
1128 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1129 LegalizeAction Action) {
1130 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1131 (unsigned)Action < 0xf && "Table isn't big enough!");
1132 // Store action are kept in the lower half.
1133 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1134 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1137 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1138 /// supported on the target and indicate what to do about it.
1139 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1140 LegalizeAction Action) {
1141 assert(VT < MVT::LAST_VALUETYPE &&
1142 (unsigned)CC < array_lengthof(CondCodeActions) &&
1143 "Table isn't big enough!");
1144 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1145 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1148 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1149 /// promotion code defaults to trying a larger integer/fp until it can find
1150 /// one that works. If that default is insufficient, this method can be used
1151 /// by the target to override the default.
1152 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1153 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1156 /// setTargetDAGCombine - Targets should invoke this method for each target
1157 /// independent node that they want to provide a custom DAG combiner for by
1158 /// implementing the PerformDAGCombine virtual method.
1159 void setTargetDAGCombine(ISD::NodeType NT) {
1160 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1161 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1164 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1165 /// bytes); default is 200
1166 void setJumpBufSize(unsigned Size) {
1170 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1171 /// alignment (in bytes); default is 0
1172 void setJumpBufAlignment(unsigned Align) {
1173 JumpBufAlignment = Align;
1176 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1177 /// alignment is zero, it means the target does not care about loop alignment.
1178 void setPrefLoopAlignment(unsigned Align) {
1179 PrefLoopAlignment = Align;
1182 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1184 void setMinStackArgumentAlignment(unsigned Align) {
1185 MinStackArgumentAlignment = Align;
1188 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1189 /// atomic operation intrinsics includes locking. Default is false.
1190 void setShouldFoldAtomicFences(bool fold) {
1191 ShouldFoldAtomicFences = fold;
1195 //===--------------------------------------------------------------------===//
1196 // Lowering methods - These methods must be implemented by targets so that
1197 // the SelectionDAGLowering code knows how to lower these.
1200 /// LowerFormalArguments - This hook must be implemented to lower the
1201 /// incoming (formal) arguments, described by the Ins array, into the
1202 /// specified DAG. The implementation should fill in the InVals array
1203 /// with legal-type argument values, and return the resulting token
1207 LowerFormalArguments(SDValue Chain,
1208 CallingConv::ID CallConv, bool isVarArg,
1209 const SmallVectorImpl<ISD::InputArg> &Ins,
1210 DebugLoc dl, SelectionDAG &DAG,
1211 SmallVectorImpl<SDValue> &InVals) const {
1212 assert(0 && "Not Implemented");
1213 return SDValue(); // this is here to silence compiler errors
1216 /// LowerCallTo - This function lowers an abstract call to a function into an
1217 /// actual call. This returns a pair of operands. The first element is the
1218 /// return value for the function (if RetTy is not VoidTy). The second
1219 /// element is the outgoing token chain. It calls LowerCall to do the actual
1221 struct ArgListEntry {
1232 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1233 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1235 typedef std::vector<ArgListEntry> ArgListTy;
1236 std::pair<SDValue, SDValue>
1237 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1238 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1239 CallingConv::ID CallConv, bool isTailCall,
1240 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1241 SelectionDAG &DAG, DebugLoc dl) const;
1243 /// LowerCall - This hook must be implemented to lower calls into the
1244 /// the specified DAG. The outgoing arguments to the call are described
1245 /// by the Outs array, and the values to be returned by the call are
1246 /// described by the Ins array. The implementation should fill in the
1247 /// InVals array with legal-type return values from the call, and return
1248 /// the resulting token chain value.
1250 LowerCall(SDValue Chain, SDValue Callee,
1251 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1252 const SmallVectorImpl<ISD::OutputArg> &Outs,
1253 const SmallVectorImpl<SDValue> &OutVals,
1254 const SmallVectorImpl<ISD::InputArg> &Ins,
1255 DebugLoc dl, SelectionDAG &DAG,
1256 SmallVectorImpl<SDValue> &InVals) const {
1257 assert(0 && "Not Implemented");
1258 return SDValue(); // this is here to silence compiler errors
1261 /// CanLowerReturn - This hook should be implemented to check whether the
1262 /// return values described by the Outs array can fit into the return
1263 /// registers. If false is returned, an sret-demotion is performed.
1265 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1266 const SmallVectorImpl<ISD::OutputArg> &Outs,
1267 LLVMContext &Context) const
1269 // Return true by default to get preexisting behavior.
1273 /// LowerReturn - This hook must be implemented to lower outgoing
1274 /// return values, described by the Outs array, into the specified
1275 /// DAG. The implementation should return the resulting token chain
1279 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1280 const SmallVectorImpl<ISD::OutputArg> &Outs,
1281 const SmallVectorImpl<SDValue> &OutVals,
1282 DebugLoc dl, SelectionDAG &DAG) const {
1283 assert(0 && "Not Implemented");
1284 return SDValue(); // this is here to silence compiler errors
1287 /// isUsedByReturnOnly - Return true if result of the specified node is used
1288 /// by a return node only. This is used to determine whether it is possible
1289 /// to codegen a libcall as tail call at legalization time.
1290 virtual bool isUsedByReturnOnly(SDNode *N) const {
1294 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1295 /// to legalize nodes with an illegal operand type but legal result types.
1296 /// It replaces the LowerOperation callback in the type Legalizer.
1297 /// The reason we can not do away with LowerOperation entirely is that
1298 /// LegalizeDAG isn't yet ready to use this callback.
1299 /// TODO: Consider merging with ReplaceNodeResults.
1301 /// The target places new result values for the node in Results (their number
1302 /// and types must exactly match those of the original return values of
1303 /// the node), or leaves Results empty, which indicates that the node is not
1304 /// to be custom lowered after all.
1305 /// The default implementation calls LowerOperation.
1306 virtual void LowerOperationWrapper(SDNode *N,
1307 SmallVectorImpl<SDValue> &Results,
1308 SelectionDAG &DAG) const;
1310 /// LowerOperation - This callback is invoked for operations that are
1311 /// unsupported by the target, which are registered to use 'custom' lowering,
1312 /// and whose defined values are all legal.
1313 /// If the target has no operations that require custom lowering, it need not
1314 /// implement this. The default implementation of this aborts.
1315 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1317 /// ReplaceNodeResults - This callback is invoked when a node result type is
1318 /// illegal for the target, and the operation was registered to use 'custom'
1319 /// lowering for that result type. The target places new result values for
1320 /// the node in Results (their number and types must exactly match those of
1321 /// the original return values of the node), or leaves Results empty, which
1322 /// indicates that the node is not to be custom lowered after all.
1324 /// If the target has no operations that require custom lowering, it need not
1325 /// implement this. The default implementation aborts.
1326 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1327 SelectionDAG &DAG) const {
1328 assert(0 && "ReplaceNodeResults not implemented for this target!");
1331 /// getTargetNodeName() - This method returns the name of a target specific
1333 virtual const char *getTargetNodeName(unsigned Opcode) const;
1335 /// createFastISel - This method returns a target specific FastISel object,
1336 /// or null if the target does not support "fast" ISel.
1337 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1341 //===--------------------------------------------------------------------===//
1342 // Inline Asm Support hooks
1345 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1346 /// call to be explicit llvm code if it wants to. This is useful for
1347 /// turning simple inline asms into LLVM intrinsics, which gives the
1348 /// compiler more information about the behavior of the code.
1349 virtual bool ExpandInlineAsm(CallInst *CI) const {
1353 enum ConstraintType {
1354 C_Register, // Constraint represents specific register(s).
1355 C_RegisterClass, // Constraint represents any of register(s) in class.
1356 C_Memory, // Memory constraint.
1357 C_Other, // Something else.
1358 C_Unknown // Unsupported constraint.
1361 enum ConstraintWeight {
1363 CW_Invalid = -1, // No match.
1364 CW_Okay = 0, // Acceptable.
1365 CW_Good = 1, // Good weight.
1366 CW_Better = 2, // Better weight.
1367 CW_Best = 3, // Best weight.
1369 // Well-known weights.
1370 CW_SpecificReg = CW_Okay, // Specific register operands.
1371 CW_Register = CW_Good, // Register operands.
1372 CW_Memory = CW_Better, // Memory operands.
1373 CW_Constant = CW_Best, // Constant operand.
1374 CW_Default = CW_Okay // Default or don't know type.
1377 /// AsmOperandInfo - This contains information for each constraint that we are
1379 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1380 /// ConstraintCode - This contains the actual string for the code, like "m".
1381 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1382 /// most closely matches the operand.
1383 std::string ConstraintCode;
1385 /// ConstraintType - Information about the constraint code, e.g. Register,
1386 /// RegisterClass, Memory, Other, Unknown.
1387 TargetLowering::ConstraintType ConstraintType;
1389 /// CallOperandval - If this is the result output operand or a
1390 /// clobber, this is null, otherwise it is the incoming operand to the
1391 /// CallInst. This gets modified as the asm is processed.
1392 Value *CallOperandVal;
1394 /// ConstraintVT - The ValueType for the operand value.
1397 /// isMatchingInputConstraint - Return true of this is an input operand that
1398 /// is a matching constraint like "4".
1399 bool isMatchingInputConstraint() const;
1401 /// getMatchedOperand - If this is an input matching constraint, this method
1402 /// returns the output operand it matches.
1403 unsigned getMatchedOperand() const;
1405 /// Copy constructor for copying from an AsmOperandInfo.
1406 AsmOperandInfo(const AsmOperandInfo &info)
1407 : InlineAsm::ConstraintInfo(info),
1408 ConstraintCode(info.ConstraintCode),
1409 ConstraintType(info.ConstraintType),
1410 CallOperandVal(info.CallOperandVal),
1411 ConstraintVT(info.ConstraintVT) {
1414 /// Copy constructor for copying from a ConstraintInfo.
1415 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1416 : InlineAsm::ConstraintInfo(info),
1417 ConstraintType(TargetLowering::C_Unknown),
1418 CallOperandVal(0), ConstraintVT(MVT::Other) {
1422 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
1424 /// ParseConstraints - Split up the constraint string from the inline
1425 /// assembly value into the specific constraints and their prefixes,
1426 /// and also tie in the associated operand values.
1427 /// If this returns an empty vector, and if the constraint string itself
1428 /// isn't empty, there was an error parsing.
1429 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
1431 /// Examine constraint type and operand type and determine a weight value.
1432 /// The operand object must already have been set up with the operand type.
1433 virtual ConstraintWeight getMultipleConstraintMatchWeight(
1434 AsmOperandInfo &info, int maIndex) const;
1436 /// Examine constraint string and operand type and determine a weight value.
1437 /// The operand object must already have been set up with the operand type.
1438 virtual ConstraintWeight getSingleConstraintMatchWeight(
1439 AsmOperandInfo &info, const char *constraint) const;
1441 /// ComputeConstraintToUse - Determines the constraint code and constraint
1442 /// type to use for the specific AsmOperandInfo, setting
1443 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1444 /// being passed in is available, it can be passed in as Op, otherwise an
1445 /// empty SDValue can be passed.
1446 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1448 SelectionDAG *DAG = 0) const;
1450 /// getConstraintType - Given a constraint, return the type of constraint it
1451 /// is for this target.
1452 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1454 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1455 /// return a list of registers that can be used to satisfy the constraint.
1456 /// This should only be used for C_RegisterClass constraints.
1457 virtual std::vector<unsigned>
1458 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1461 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1462 /// {edx}), return the register number and the register class for the
1465 /// Given a register class constraint, like 'r', if this corresponds directly
1466 /// to an LLVM register class, return a register of 0 and the register class
1469 /// This should only be used for C_Register constraints. On error,
1470 /// this returns a register number of 0 and a null register class pointer..
1471 virtual std::pair<unsigned, const TargetRegisterClass*>
1472 getRegForInlineAsmConstraint(const std::string &Constraint,
1475 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1476 /// with another that has more specific requirements based on the type of the
1477 /// corresponding operand. This returns null if there is no replacement to
1479 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1481 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1482 /// vector. If it is invalid, don't add anything to Ops.
1483 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1484 std::vector<SDValue> &Ops,
1485 SelectionDAG &DAG) const;
1487 //===--------------------------------------------------------------------===//
1488 // Instruction Emitting Hooks
1491 // EmitInstrWithCustomInserter - This method should be implemented by targets
1492 // that mark instructions with the 'usesCustomInserter' flag. These
1493 // instructions are special in various ways, which require special support to
1494 // insert. The specified MachineInstr is created but not inserted into any
1495 // basic blocks, and this method is called to expand it into a sequence of
1496 // instructions, potentially also creating new basic blocks and control flow.
1497 virtual MachineBasicBlock *
1498 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1500 //===--------------------------------------------------------------------===//
1501 // Addressing mode description hooks (used by LSR etc).
1504 /// AddrMode - This represents an addressing mode of:
1505 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1506 /// If BaseGV is null, there is no BaseGV.
1507 /// If BaseOffs is zero, there is no base offset.
1508 /// If HasBaseReg is false, there is no base register.
1509 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1513 GlobalValue *BaseGV;
1517 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1520 /// isLegalAddressingMode - Return true if the addressing mode represented by
1521 /// AM is legal for this target, for a load/store of the specified type.
1522 /// The type may be VoidTy, in which case only return true if the addressing
1523 /// mode is legal for a load/store of any legal type.
1524 /// TODO: Handle pre/postinc as well.
1525 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1527 /// isTruncateFree - Return true if it's free to truncate a value of
1528 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1529 /// register EAX to i16 by referencing its sub-register AX.
1530 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1534 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1538 /// isZExtFree - Return true if any actual instruction that defines a
1539 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1540 /// register. This does not necessarily include registers defined in
1541 /// unknown ways, such as incoming arguments, or copies from unknown
1542 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1543 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1544 /// all instructions that define 32-bit values implicit zero-extend the
1545 /// result out to 64 bits.
1546 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1550 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1554 /// isNarrowingProfitable - Return true if it's profitable to narrow
1555 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1556 /// from i32 to i8 but not from i32 to i16.
1557 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1561 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1562 /// icmp immediate, that is the target has icmp instructions which can compare
1563 /// a register against the immediate without having to materialize the
1564 /// immediate into a register.
1565 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1569 //===--------------------------------------------------------------------===//
1570 // Div utility functions
1572 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1573 std::vector<SDNode*>* Created) const;
1574 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1575 std::vector<SDNode*>* Created) const;
1578 //===--------------------------------------------------------------------===//
1579 // Runtime Library hooks
1582 /// setLibcallName - Rename the default libcall routine name for the specified
1584 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1585 LibcallRoutineNames[Call] = Name;
1588 /// getLibcallName - Get the libcall routine name for the specified libcall.
1590 const char *getLibcallName(RTLIB::Libcall Call) const {
1591 return LibcallRoutineNames[Call];
1594 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1595 /// result of the comparison libcall against zero.
1596 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1597 CmpLibcallCCs[Call] = CC;
1600 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1601 /// the comparison libcall against zero.
1602 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1603 return CmpLibcallCCs[Call];
1606 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1607 /// specified libcall.
1608 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1609 LibcallCallingConvs[Call] = CC;
1612 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1613 /// specified libcall.
1614 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1615 return LibcallCallingConvs[Call];
1619 const TargetMachine &TM;
1620 const TargetData *TD;
1621 const TargetLoweringObjectFile &TLOF;
1623 /// PointerTy - The type to use for pointers, usually i32 or i64.
1627 /// IsLittleEndian - True if this is a little endian target.
1629 bool IsLittleEndian;
1631 /// SelectIsExpensive - Tells the code generator not to expand operations
1632 /// into sequences that use the select operations if possible.
1633 bool SelectIsExpensive;
1635 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1636 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1637 /// a real cost model is in place. If we ever optimize for size, this will be
1638 /// set to true unconditionally.
1641 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1642 /// srl/add/sra for a signed divide by power of two, and let the target handle
1644 bool Pow2DivIsCheap;
1646 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1647 /// extra flow control instructions and should attempt to combine flow
1648 /// control instructions via predication.
1649 bool JumpIsExpensive;
1651 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1652 /// llvm.setjmp. Defaults to false.
1653 bool UseUnderscoreSetJmp;
1655 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1656 /// llvm.longjmp. Defaults to false.
1657 bool UseUnderscoreLongJmp;
1659 /// BooleanContents - Information about the contents of the high-bits in
1660 /// boolean values held in a type wider than i1. See getBooleanContents.
1661 BooleanContent BooleanContents;
1663 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1664 /// total cycles or lowest register usage.
1665 Sched::Preference SchedPreferenceInfo;
1667 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1668 unsigned JumpBufSize;
1670 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1672 unsigned JumpBufAlignment;
1674 /// MinStackArgumentAlignment - The minimum alignment that any argument
1675 /// on the stack needs to have.
1677 unsigned MinStackArgumentAlignment;
1679 /// PrefLoopAlignment - The perferred loop alignment.
1681 unsigned PrefLoopAlignment;
1683 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1684 /// be folded into the enclosed atomic intrinsic instruction by the
1686 bool ShouldFoldAtomicFences;
1688 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1689 /// specifies the register that llvm.savestack/llvm.restorestack should save
1691 unsigned StackPointerRegisterToSaveRestore;
1693 /// ExceptionPointerRegister - If set to a physical register, this specifies
1694 /// the register that receives the exception address on entry to a landing
1696 unsigned ExceptionPointerRegister;
1698 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1699 /// the register that receives the exception typeid on entry to a landing
1701 unsigned ExceptionSelectorRegister;
1703 /// RegClassForVT - This indicates the default register class to use for
1704 /// each ValueType the target supports natively.
1705 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1706 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1707 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1709 /// RepRegClassForVT - This indicates the "representative" register class to
1710 /// use for each ValueType the target supports natively. This information is
1711 /// used by the scheduler to track register pressure. By default, the
1712 /// representative register class is the largest legal super-reg register
1713 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1714 /// and i32's representative class would be GR32.
1715 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1717 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1718 /// register class for each ValueType. The cost is used by the scheduler to
1719 /// approximate register pressure.
1720 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1722 /// TransformToType - For any value types we are promoting or expanding, this
1723 /// contains the value type that we are changing to. For Expanded types, this
1724 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1725 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1726 /// by the system, this holds the same type (e.g. i32 -> i32).
1727 EVT TransformToType[MVT::LAST_VALUETYPE];
1729 /// OpActions - For each operation and each value type, keep a LegalizeAction
1730 /// that indicates how instruction selection should deal with the operation.
1731 /// Most operations are Legal (aka, supported natively by the target), but
1732 /// operations that are not should be described. Note that operations on
1733 /// non-legal value types are not described here.
1734 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1736 /// LoadExtActions - For each load extension type and each value type,
1737 /// keep a LegalizeAction that indicates how instruction selection should deal
1738 /// with a load of a specific value type and extension type.
1739 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1741 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1742 /// indicates whether a truncating store of a specific value type and
1743 /// truncating type is legal.
1744 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1746 /// IndexedModeActions - For each indexed mode and each value type,
1747 /// keep a pair of LegalizeAction that indicates how instruction
1748 /// selection should deal with the load / store. The first dimension is the
1749 /// value_type for the reference. The second dimension represents the various
1750 /// modes for load store.
1751 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1753 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1754 /// LegalizeAction that indicates how instruction selection should
1755 /// deal with the condition code.
1756 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1758 ValueTypeActionImpl ValueTypeActions;
1760 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1762 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1763 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1764 /// which sets a bit in this array.
1766 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1768 /// PromoteToType - For operations that must be promoted to a specific type,
1769 /// this holds the destination type. This map should be sparse, so don't hold
1772 /// Targets add entries to this map with AddPromotedToType(..), clients access
1773 /// this with getTypeToPromoteTo(..).
1774 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1777 /// LibcallRoutineNames - Stores the name each libcall.
1779 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1781 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1782 /// of each of the comparison libcall against zero.
1783 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1785 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1787 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1790 /// When lowering \@llvm.memset this field specifies the maximum number of
1791 /// store operations that may be substituted for the call to memset. Targets
1792 /// must set this value based on the cost threshold for that target. Targets
1793 /// should assume that the memset will be done using as many of the largest
1794 /// store operations first, followed by smaller ones, if necessary, per
1795 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1796 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1797 /// store. This only applies to setting a constant array of a constant size.
1798 /// @brief Specify maximum number of store instructions per memset call.
1799 unsigned maxStoresPerMemset;
1801 /// Maximum number of stores operations that may be substituted for the call
1802 /// to memset, used for functions with OptSize attribute.
1803 unsigned maxStoresPerMemsetOptSize;
1805 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1806 /// store operations that may be substituted for a call to memcpy. Targets
1807 /// must set this value based on the cost threshold for that target. Targets
1808 /// should assume that the memcpy will be done using as many of the largest
1809 /// store operations first, followed by smaller ones, if necessary, per
1810 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1811 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1812 /// and one 1-byte store. This only applies to copying a constant array of
1814 /// @brief Specify maximum bytes of store instructions per memcpy call.
1815 unsigned maxStoresPerMemcpy;
1817 /// Maximum number of store operations that may be substituted for a call
1818 /// to memcpy, used for functions with OptSize attribute.
1819 unsigned maxStoresPerMemcpyOptSize;
1821 /// When lowering \@llvm.memmove this field specifies the maximum number of
1822 /// store instructions that may be substituted for a call to memmove. Targets
1823 /// must set this value based on the cost threshold for that target. Targets
1824 /// should assume that the memmove will be done using as many of the largest
1825 /// store operations first, followed by smaller ones, if necessary, per
1826 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1827 /// with 8-bit alignment would result in nine 1-byte stores. This only
1828 /// applies to copying a constant array of constant size.
1829 /// @brief Specify maximum bytes of store instructions per memmove call.
1830 unsigned maxStoresPerMemmove;
1832 /// Maximum number of store instructions that may be substituted for a call
1833 /// to memmove, used for functions with OpSize attribute.
1834 unsigned maxStoresPerMemmoveOptSize;
1836 /// This field specifies whether the target can benefit from code placement
1838 bool benefitFromCodePlacementOpt;
1841 /// isLegalRC - Return true if the value types that can be represented by the
1842 /// specified register class are all legal.
1843 bool isLegalRC(const TargetRegisterClass *RC) const;
1845 /// hasLegalSuperRegRegClasses - Return true if the specified register class
1846 /// has one or more super-reg register classes that are legal.
1847 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
1850 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1851 /// compute the return value EVTs and flags, and optionally also
1852 /// the offsets, if the return value is being lowered to memory.
1853 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1854 SmallVectorImpl<ISD::OutputArg> &Outs,
1855 const TargetLowering &TLI,
1856 SmallVectorImpl<uint64_t> *Offsets = 0);
1858 } // end llvm namespace